18f1e5bf9SLi Xu /* 28f1e5bf9SLi Xu * ALSA SoC CS43130 codec driver 38f1e5bf9SLi Xu * 48f1e5bf9SLi Xu * Copyright 2017 Cirrus Logic, Inc. 58f1e5bf9SLi Xu * 68f1e5bf9SLi Xu * Author: Li Xu <li.xu@cirrus.com> 78f1e5bf9SLi Xu * 88f1e5bf9SLi Xu * This program is free software; you can redistribute it and/or 98f1e5bf9SLi Xu * modify it under the terms of the GNU General Public License 108f1e5bf9SLi Xu * version 2 as published by the Free Software Foundation. 118f1e5bf9SLi Xu * 128f1e5bf9SLi Xu * This program is distributed in the hope that it will be useful, but 138f1e5bf9SLi Xu * WITHOUT ANY WARRANTY; without even the implied warranty of 148f1e5bf9SLi Xu * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 158f1e5bf9SLi Xu * General Public License for more details. 168f1e5bf9SLi Xu * 178f1e5bf9SLi Xu */ 188f1e5bf9SLi Xu 198f1e5bf9SLi Xu #ifndef __CS43130_H__ 208f1e5bf9SLi Xu #define __CS43130_H__ 218f1e5bf9SLi Xu 228f1e5bf9SLi Xu /* CS43130 registers addresses */ 238f1e5bf9SLi Xu /* all reg address is shifted by a byte for control byte to be LSB */ 248f1e5bf9SLi Xu #define CS43130_FIRSTREG 0x010000 258f1e5bf9SLi Xu #define CS43130_LASTREG 0x190000 268f1e5bf9SLi Xu #define CS43130_CHIP_ID 0x00043130 278f1e5bf9SLi Xu #define CS4399_CHIP_ID 0x00043990 288f1e5bf9SLi Xu #define CS43131_CHIP_ID 0x00043131 298f1e5bf9SLi Xu #define CS43198_CHIP_ID 0x00043198 308f1e5bf9SLi Xu #define CS43130_DEVID_AB 0x010000 /* Device ID A & B [RO] */ 318f1e5bf9SLi Xu #define CS43130_DEVID_CD 0x010001 /* Device ID C & D [RO] */ 328f1e5bf9SLi Xu #define CS43130_DEVID_E 0x010002 /* Device ID E [RO] */ 338f1e5bf9SLi Xu #define CS43130_FAB_ID 0x010003 /* Fab ID [RO] */ 348f1e5bf9SLi Xu #define CS43130_REV_ID 0x010004 /* Revision ID [RO] */ 358f1e5bf9SLi Xu #define CS43130_SUBREV_ID 0x010005 /* Subrevision ID */ 368f1e5bf9SLi Xu #define CS43130_SYS_CLK_CTL_1 0x010006 /* System Clocking Ctl 1 */ 378f1e5bf9SLi Xu #define CS43130_SP_SRATE 0x01000B /* Serial Port Sample Rate */ 388f1e5bf9SLi Xu #define CS43130_SP_BITSIZE 0x01000C /* Serial Port Bit Size */ 398f1e5bf9SLi Xu #define CS43130_PAD_INT_CFG 0x01000D /* Pad Interface Config */ 408f1e5bf9SLi Xu #define CS43130_DXD1 0x010010 /* DXD1 */ 418f1e5bf9SLi Xu #define CS43130_DXD7 0x010025 /* DXD7 */ 428f1e5bf9SLi Xu #define CS43130_DXD19 0x010026 /* DXD19 */ 438f1e5bf9SLi Xu #define CS43130_DXD17 0x010027 /* DXD17 */ 448f1e5bf9SLi Xu #define CS43130_DXD18 0x010028 /* DXD18 */ 458f1e5bf9SLi Xu #define CS43130_DXD12 0x01002C /* DXD12 */ 468f1e5bf9SLi Xu #define CS43130_DXD8 0x01002E /* DXD8 */ 478f1e5bf9SLi Xu #define CS43130_PWDN_CTL 0x020000 /* Power Down Ctl */ 488f1e5bf9SLi Xu #define CS43130_DXD2 0x020019 /* DXD2 */ 498f1e5bf9SLi Xu #define CS43130_CRYSTAL_SET 0x020052 /* Crystal Setting */ 508f1e5bf9SLi Xu #define CS43130_PLL_SET_1 0x030001 /* PLL Setting 1 */ 518f1e5bf9SLi Xu #define CS43130_PLL_SET_2 0x030002 /* PLL Setting 2 */ 528f1e5bf9SLi Xu #define CS43130_PLL_SET_3 0x030003 /* PLL Setting 3 */ 538f1e5bf9SLi Xu #define CS43130_PLL_SET_4 0x030004 /* PLL Setting 4 */ 548f1e5bf9SLi Xu #define CS43130_PLL_SET_5 0x030005 /* PLL Setting 5 */ 558f1e5bf9SLi Xu #define CS43130_PLL_SET_6 0x030008 /* PLL Setting 6 */ 568f1e5bf9SLi Xu #define CS43130_PLL_SET_7 0x03000A /* PLL Setting 7 */ 578f1e5bf9SLi Xu #define CS43130_PLL_SET_8 0x03001B /* PLL Setting 8 */ 588f1e5bf9SLi Xu #define CS43130_PLL_SET_9 0x040002 /* PLL Setting 9 */ 598f1e5bf9SLi Xu #define CS43130_PLL_SET_10 0x040003 /* PLL Setting 10 */ 608f1e5bf9SLi Xu #define CS43130_CLKOUT_CTL 0x040004 /* CLKOUT Ctl */ 618f1e5bf9SLi Xu #define CS43130_ASP_NUM_1 0x040010 /* ASP Numerator 1 */ 628f1e5bf9SLi Xu #define CS43130_ASP_NUM_2 0x040011 /* ASP Numerator 2 */ 638f1e5bf9SLi Xu #define CS43130_ASP_DEN_1 0x040012 /* ASP Denominator 1 */ 648f1e5bf9SLi Xu #define CS43130_ASP_DEN_2 0x040013 /* ASP Denominator 2 */ 658f1e5bf9SLi Xu #define CS43130_ASP_LRCK_HI_TIME_1 0x040014 /* ASP LRCK High Time 1 */ 668f1e5bf9SLi Xu #define CS43130_ASP_LRCK_HI_TIME_2 0x040015 /* ASP LRCK High Time 2 */ 678f1e5bf9SLi Xu #define CS43130_ASP_LRCK_PERIOD_1 0x040016 /* ASP LRCK Period 1 */ 688f1e5bf9SLi Xu #define CS43130_ASP_LRCK_PERIOD_2 0x040017 /* ASP LRCK Period 2 */ 698f1e5bf9SLi Xu #define CS43130_ASP_CLOCK_CONF 0x040018 /* ASP Clock Config */ 708f1e5bf9SLi Xu #define CS43130_ASP_FRAME_CONF 0x040019 /* ASP Frame Config */ 718f1e5bf9SLi Xu #define CS43130_XSP_NUM_1 0x040020 /* XSP Numerator 1 */ 728f1e5bf9SLi Xu #define CS43130_XSP_NUM_2 0x040021 /* XSP Numerator 2 */ 738f1e5bf9SLi Xu #define CS43130_XSP_DEN_1 0x040022 /* XSP Denominator 1 */ 748f1e5bf9SLi Xu #define CS43130_XSP_DEN_2 0x040023 /* XSP Denominator 2 */ 758f1e5bf9SLi Xu #define CS43130_XSP_LRCK_HI_TIME_1 0x040024 /* XSP LRCK High Time 1 */ 768f1e5bf9SLi Xu #define CS43130_XSP_LRCK_HI_TIME_2 0x040025 /* XSP LRCK High Time 2 */ 778f1e5bf9SLi Xu #define CS43130_XSP_LRCK_PERIOD_1 0x040026 /* XSP LRCK Period 1 */ 788f1e5bf9SLi Xu #define CS43130_XSP_LRCK_PERIOD_2 0x040027 /* XSP LRCK Period 2 */ 798f1e5bf9SLi Xu #define CS43130_XSP_CLOCK_CONF 0x040028 /* XSP Clock Config */ 808f1e5bf9SLi Xu #define CS43130_XSP_FRAME_CONF 0x040029 /* XSP Frame Config */ 818f1e5bf9SLi Xu #define CS43130_ASP_CH_1_LOC 0x050000 /* ASP Chan 1 Location */ 828f1e5bf9SLi Xu #define CS43130_ASP_CH_2_LOC 0x050001 /* ASP Chan 2 Location */ 838f1e5bf9SLi Xu #define CS43130_ASP_CH_1_SZ_EN 0x05000A /* ASP Chan 1 Size, Enable */ 848f1e5bf9SLi Xu #define CS43130_ASP_CH_2_SZ_EN 0x05000B /* ASP Chan 2 Size, Enable */ 858f1e5bf9SLi Xu #define CS43130_XSP_CH_1_LOC 0x060000 /* XSP Chan 1 Location */ 868f1e5bf9SLi Xu #define CS43130_XSP_CH_2_LOC 0x060001 /* XSP Chan 2 Location */ 878f1e5bf9SLi Xu #define CS43130_XSP_CH_1_SZ_EN 0x06000A /* XSP Chan 1 Size, Enable */ 888f1e5bf9SLi Xu #define CS43130_XSP_CH_2_SZ_EN 0x06000B /* XSP Chan 2 Size, Enable */ 898f1e5bf9SLi Xu #define CS43130_DSD_VOL_B 0x070000 /* DSD Volume B */ 908f1e5bf9SLi Xu #define CS43130_DSD_VOL_A 0x070001 /* DSD Volume A */ 918f1e5bf9SLi Xu #define CS43130_DSD_PATH_CTL_1 0x070002 /* DSD Proc Path Sig Ctl 1 */ 928f1e5bf9SLi Xu #define CS43130_DSD_INT_CFG 0x070003 /* DSD Interface Config */ 938f1e5bf9SLi Xu #define CS43130_DSD_PATH_CTL_2 0x070004 /* DSD Proc Path Sig Ctl 2 */ 948f1e5bf9SLi Xu #define CS43130_DSD_PCM_MIX_CTL 0x070005 /* DSD and PCM Mixing Ctl */ 958f1e5bf9SLi Xu #define CS43130_DSD_PATH_CTL_3 0x070006 /* DSD Proc Path Sig Ctl 3 */ 968f1e5bf9SLi Xu #define CS43130_HP_OUT_CTL_1 0x080000 /* HP Output Ctl 1 */ 978f1e5bf9SLi Xu #define CS43130_DXD16 0x080024 /* DXD16 */ 988f1e5bf9SLi Xu #define CS43130_DXD13 0x080032 /* DXD13 */ 998f1e5bf9SLi Xu #define CS43130_PCM_FILT_OPT 0x090000 /* PCM Filter Option */ 1008f1e5bf9SLi Xu #define CS43130_PCM_VOL_B 0x090001 /* PCM Volume B */ 1018f1e5bf9SLi Xu #define CS43130_PCM_VOL_A 0x090002 /* PCM Volume A */ 1028f1e5bf9SLi Xu #define CS43130_PCM_PATH_CTL_1 0x090003 /* PCM Path Signal Ctl 1 */ 1038f1e5bf9SLi Xu #define CS43130_PCM_PATH_CTL_2 0x090004 /* PCM Path Signal Ctl 2 */ 1048f1e5bf9SLi Xu #define CS43130_DXD6 0x090097 /* DXD6 */ 1058f1e5bf9SLi Xu #define CS43130_CLASS_H_CTL 0x0B0000 /* Class H Ctl */ 1068f1e5bf9SLi Xu #define CS43130_DXD15 0x0B0005 /* DXD15 */ 1078f1e5bf9SLi Xu #define CS43130_DXD14 0x0B0006 /* DXD14 */ 1088f1e5bf9SLi Xu #define CS43130_DXD3 0x0C0002 /* DXD3 */ 1098f1e5bf9SLi Xu #define CS43130_DXD10 0x0C0003 /* DXD10 */ 1108f1e5bf9SLi Xu #define CS43130_DXD11 0x0C0005 /* DXD11 */ 1118f1e5bf9SLi Xu #define CS43130_DXD9 0x0C0006 /* DXD9 */ 1128f1e5bf9SLi Xu #define CS43130_DXD4 0x0C0009 /* DXD4 */ 1138f1e5bf9SLi Xu #define CS43130_DXD5 0x0C000E /* DXD5 */ 1148f1e5bf9SLi Xu #define CS43130_HP_DETECT 0x0D0000 /* HP Detect */ 1158f1e5bf9SLi Xu #define CS43130_HP_STATUS 0x0D0001 /* HP Status [RO] */ 1168f1e5bf9SLi Xu #define CS43130_HP_LOAD_1 0x0E0000 /* HP Load 1 */ 1178f1e5bf9SLi Xu #define CS43130_HP_MEAS_LOAD_1 0x0E0003 /* HP Load Measurement 1 */ 1188f1e5bf9SLi Xu #define CS43130_HP_MEAS_LOAD_2 0x0E0004 /* HP Load Measurement 2 */ 1198f1e5bf9SLi Xu #define CS43130_HP_DC_STAT_1 0x0E000D /* HP DC Load Status 0 [RO] */ 1208f1e5bf9SLi Xu #define CS43130_HP_DC_STAT_2 0x0E000E /* HP DC Load Status 1 [RO] */ 1218f1e5bf9SLi Xu #define CS43130_HP_AC_STAT_1 0x0E0010 /* HP AC Load Status 0 [RO] */ 1228f1e5bf9SLi Xu #define CS43130_HP_AC_STAT_2 0x0E0011 /* HP AC Load Status 1 [RO] */ 1238f1e5bf9SLi Xu #define CS43130_HP_LOAD_STAT 0x0E001A /* HP Load Status [RO] */ 1248f1e5bf9SLi Xu #define CS43130_INT_STATUS_1 0x0F0000 /* Interrupt Status 1 */ 1258f1e5bf9SLi Xu #define CS43130_INT_STATUS_2 0x0F0001 /* Interrupt Status 2 */ 1268f1e5bf9SLi Xu #define CS43130_INT_STATUS_3 0x0F0002 /* Interrupt Status 3 */ 1278f1e5bf9SLi Xu #define CS43130_INT_STATUS_4 0x0F0003 /* Interrupt Status 4 */ 1288f1e5bf9SLi Xu #define CS43130_INT_STATUS_5 0x0F0004 /* Interrupt Status 5 */ 1298f1e5bf9SLi Xu #define CS43130_INT_MASK_1 0x0F0010 /* Interrupt Mask 1 */ 1308f1e5bf9SLi Xu #define CS43130_INT_MASK_2 0x0F0011 /* Interrupt Mask 2 */ 1318f1e5bf9SLi Xu #define CS43130_INT_MASK_3 0x0F0012 /* Interrupt Mask 3 */ 1328f1e5bf9SLi Xu #define CS43130_INT_MASK_4 0x0F0013 /* Interrupt Mask 4 */ 1338f1e5bf9SLi Xu #define CS43130_INT_MASK_5 0x0F0014 /* Interrupt Mask 5 */ 1348f1e5bf9SLi Xu 1358f1e5bf9SLi Xu #define CS43130_MCLK_SRC_SEL_MASK 0x03 1368f1e5bf9SLi Xu #define CS43130_MCLK_SRC_SEL_SHIFT 0 1378f1e5bf9SLi Xu #define CS43130_MCLK_INT_MASK 0x04 1388f1e5bf9SLi Xu #define CS43130_MCLK_INT_SHIFT 2 1398f1e5bf9SLi Xu #define CS43130_CH_BITSIZE_MASK 0x03 1408f1e5bf9SLi Xu #define CS43130_CH_EN_MASK 0x04 1418f1e5bf9SLi Xu #define CS43130_CH_EN_SHIFT 2 1428f1e5bf9SLi Xu #define CS43130_ASP_BITSIZE_MASK 0x03 1438f1e5bf9SLi Xu #define CS43130_XSP_BITSIZE_MASK 0x0C 1448f1e5bf9SLi Xu #define CS43130_XSP_BITSIZE_SHIFT 2 1458f1e5bf9SLi Xu #define CS43130_SP_BITSIZE_ASP_SHIFT 0 1468f1e5bf9SLi Xu #define CS43130_HP_DETECT_CTRL_SHIFT 6 1478f1e5bf9SLi Xu #define CS43130_HP_DETECT_CTRL_MASK (0x03 << CS43130_HP_DETECT_CTRL_SHIFT) 1488f1e5bf9SLi Xu #define CS43130_HP_DETECT_INV_SHIFT 5 1498f1e5bf9SLi Xu #define CS43130_HP_DETECT_INV_MASK (1 << CS43130_HP_DETECT_INV_SHIFT) 1508f1e5bf9SLi Xu 1518f1e5bf9SLi Xu /* CS43130_INT_MASK_1 */ 1528f1e5bf9SLi Xu #define CS43130_HP_PLUG_INT_SHIFT 6 1538f1e5bf9SLi Xu #define CS43130_HP_PLUG_INT (1 << CS43130_HP_PLUG_INT_SHIFT) 1548f1e5bf9SLi Xu #define CS43130_HP_UNPLUG_INT_SHIFT 5 1558f1e5bf9SLi Xu #define CS43130_HP_UNPLUG_INT (1 << CS43130_HP_UNPLUG_INT_SHIFT) 1568f1e5bf9SLi Xu #define CS43130_XTAL_RDY_INT_SHIFT 4 1578f1e5bf9SLi Xu #define CS43130_XTAL_RDY_INT_MASK 0x10 1588f1e5bf9SLi Xu #define CS43130_XTAL_RDY_INT (1 << CS43130_XTAL_RDY_INT_SHIFT) 1598f1e5bf9SLi Xu #define CS43130_XTAL_ERR_INT_SHIFT 3 1608f1e5bf9SLi Xu #define CS43130_XTAL_ERR_INT (1 << CS43130_XTAL_ERR_INT_SHIFT) 1618f1e5bf9SLi Xu #define CS43130_PLL_RDY_INT_MASK 0x04 1628f1e5bf9SLi Xu #define CS43130_PLL_RDY_INT_SHIFT 2 1638f1e5bf9SLi Xu #define CS43130_PLL_RDY_INT (1 << CS43130_PLL_RDY_INT_SHIFT) 1648f1e5bf9SLi Xu 1658f1e5bf9SLi Xu /* CS43130_INT_MASK_4 */ 1668f1e5bf9SLi Xu #define CS43130_INT_MASK_ALL 0xFF 1678f1e5bf9SLi Xu #define CS43130_HPLOAD_NO_DC_INT_SHIFT 7 1688f1e5bf9SLi Xu #define CS43130_HPLOAD_NO_DC_INT (1 << CS43130_HPLOAD_NO_DC_INT_SHIFT) 1698f1e5bf9SLi Xu #define CS43130_HPLOAD_UNPLUG_INT_SHIFT 6 1708f1e5bf9SLi Xu #define CS43130_HPLOAD_UNPLUG_INT (1 << CS43130_HPLOAD_UNPLUG_INT_SHIFT) 1718f1e5bf9SLi Xu #define CS43130_HPLOAD_OOR_INT_SHIFT 4 1728f1e5bf9SLi Xu #define CS43130_HPLOAD_OOR_INT (1 << CS43130_HPLOAD_OOR_INT_SHIFT) 1738f1e5bf9SLi Xu #define CS43130_HPLOAD_AC_INT_SHIFT 3 1748f1e5bf9SLi Xu #define CS43130_HPLOAD_AC_INT (1 << CS43130_HPLOAD_AC_INT_SHIFT) 1758f1e5bf9SLi Xu #define CS43130_HPLOAD_DC_INT_SHIFT 2 1768f1e5bf9SLi Xu #define CS43130_HPLOAD_DC_INT (1 << CS43130_HPLOAD_DC_INT_SHIFT) 1778f1e5bf9SLi Xu #define CS43130_HPLOAD_OFF_INT_SHIFT 1 1788f1e5bf9SLi Xu #define CS43130_HPLOAD_OFF_INT (1 << CS43130_HPLOAD_OFF_INT_SHIFT) 1798f1e5bf9SLi Xu #define CS43130_HPLOAD_ON_INT 1 1808f1e5bf9SLi Xu 1818f1e5bf9SLi Xu /* CS43130_HP_LOAD_1 */ 1828f1e5bf9SLi Xu #define CS43130_HPLOAD_EN_SHIFT 7 1838f1e5bf9SLi Xu #define CS43130_HPLOAD_EN (1 << CS43130_HPLOAD_EN_SHIFT) 1848f1e5bf9SLi Xu #define CS43130_HPLOAD_CHN_SEL_SHIFT 4 1858f1e5bf9SLi Xu #define CS43130_HPLOAD_CHN_SEL (1 << CS43130_HPLOAD_CHN_SEL_SHIFT) 1868f1e5bf9SLi Xu #define CS43130_HPLOAD_AC_START_SHIFT 1 1878f1e5bf9SLi Xu #define CS43130_HPLOAD_AC_START (1 << CS43130_HPLOAD_AC_START_SHIFT) 1888f1e5bf9SLi Xu #define CS43130_HPLOAD_DC_START 1 1898f1e5bf9SLi Xu 1908f1e5bf9SLi Xu /* Reg CS43130_SP_BITSIZE */ 1918f1e5bf9SLi Xu #define CS43130_SP_BIT_SIZE_8 0x03 1928f1e5bf9SLi Xu #define CS43130_SP_BIT_SIZE_16 0x02 1938f1e5bf9SLi Xu #define CS43130_SP_BIT_SIZE_24 0x01 1948f1e5bf9SLi Xu #define CS43130_SP_BIT_SIZE_32 0x00 1958f1e5bf9SLi Xu 1968f1e5bf9SLi Xu /* Reg CS43130_SP_CH_SZ_EN */ 1978f1e5bf9SLi Xu #define CS43130_CH_BIT_SIZE_8 0x00 1988f1e5bf9SLi Xu #define CS43130_CH_BIT_SIZE_16 0x01 1998f1e5bf9SLi Xu #define CS43130_CH_BIT_SIZE_24 0x02 2008f1e5bf9SLi Xu #define CS43130_CH_BIT_SIZE_32 0x03 2018f1e5bf9SLi Xu 2028f1e5bf9SLi Xu /* PLL */ 2038f1e5bf9SLi Xu #define CS43130_PLL_START_MASK 0x01 2048f1e5bf9SLi Xu #define CS43130_PLL_MODE_MASK 0x02 2058f1e5bf9SLi Xu #define CS43130_PLL_MODE_SHIFT 1 2068f1e5bf9SLi Xu 2078f1e5bf9SLi Xu #define CS43130_PLL_REF_PREDIV_MASK 0x3 2088f1e5bf9SLi Xu 2098f1e5bf9SLi Xu #define CS43130_SP_STP_MASK 0x10 2108f1e5bf9SLi Xu #define CS43130_SP_STP_SHIFT 4 2118f1e5bf9SLi Xu #define CS43130_SP_5050_MASK 0x08 2128f1e5bf9SLi Xu #define CS43130_SP_5050_SHIFT 3 2138f1e5bf9SLi Xu #define CS43130_SP_FSD_MASK 0x07 2148f1e5bf9SLi Xu 2158f1e5bf9SLi Xu #define CS43130_SP_MODE_MASK 0x10 2168f1e5bf9SLi Xu #define CS43130_SP_MODE_SHIFT 4 2178f1e5bf9SLi Xu #define CS43130_SP_SCPOL_OUT_MASK 0x08 2188f1e5bf9SLi Xu #define CS43130_SP_SCPOL_OUT_SHIFT 3 2198f1e5bf9SLi Xu #define CS43130_SP_SCPOL_IN_MASK 0x04 2208f1e5bf9SLi Xu #define CS43130_SP_SCPOL_IN_SHIFT 2 2218f1e5bf9SLi Xu #define CS43130_SP_LCPOL_OUT_MASK 0x02 2228f1e5bf9SLi Xu #define CS43130_SP_LCPOL_OUT_SHIFT 1 2238f1e5bf9SLi Xu #define CS43130_SP_LCPOL_IN_MASK 0x01 2248f1e5bf9SLi Xu #define CS43130_SP_LCPOL_IN_SHIFT 0 2258f1e5bf9SLi Xu 2268f1e5bf9SLi Xu /* Reg CS43130_PWDN_CTL */ 2278f1e5bf9SLi Xu #define CS43130_PDN_XSP_MASK 0x80 2288f1e5bf9SLi Xu #define CS43130_PDN_XSP_SHIFT 7 2298f1e5bf9SLi Xu #define CS43130_PDN_ASP_MASK 0x40 2308f1e5bf9SLi Xu #define CS43130_PDN_ASP_SHIFT 6 2318f1e5bf9SLi Xu #define CS43130_PDN_DSPIF_MASK 0x20 2328f1e5bf9SLi Xu #define CS43130_PDN_DSDIF_SHIFT 5 2338f1e5bf9SLi Xu #define CS43130_PDN_HP_MASK 0x10 2348f1e5bf9SLi Xu #define CS43130_PDN_HP_SHIFT 4 2358f1e5bf9SLi Xu #define CS43130_PDN_XTAL_MASK 0x08 2368f1e5bf9SLi Xu #define CS43130_PDN_XTAL_SHIFT 3 2378f1e5bf9SLi Xu #define CS43130_PDN_PLL_MASK 0x04 2388f1e5bf9SLi Xu #define CS43130_PDN_PLL_SHIFT 2 2398f1e5bf9SLi Xu #define CS43130_PDN_CLKOUT_MASK 0x02 2408f1e5bf9SLi Xu #define CS43130_PDN_CLKOUT_SHIFT 1 2418f1e5bf9SLi Xu 2428f1e5bf9SLi Xu /* Reg CS43130_HP_OUT_CTL_1 */ 2438f1e5bf9SLi Xu #define CS43130_HP_IN_EN_SHIFT 3 2448f1e5bf9SLi Xu #define CS43130_HP_IN_EN_MASK 0x08 2458f1e5bf9SLi Xu 2468f1e5bf9SLi Xu /* Reg CS43130_PAD_INT_CFG */ 2478f1e5bf9SLi Xu #define CS43130_ASP_3ST_MASK 0x01 2488f1e5bf9SLi Xu #define CS43130_XSP_3ST_MASK 0x02 2498f1e5bf9SLi Xu 2508f1e5bf9SLi Xu /* Reg CS43130_PLL_SET_2 */ 2518f1e5bf9SLi Xu #define CS43130_PLL_DIV_DATA_MASK 0x000000FF 2528f1e5bf9SLi Xu #define CS43130_PLL_DIV_FRAC_0_DATA_SHIFT 0 2538f1e5bf9SLi Xu 2548f1e5bf9SLi Xu /* Reg CS43130_PLL_SET_3 */ 2558f1e5bf9SLi Xu #define CS43130_PLL_DIV_FRAC_1_DATA_SHIFT 8 2568f1e5bf9SLi Xu 2578f1e5bf9SLi Xu /* Reg CS43130_PLL_SET_4 */ 2588f1e5bf9SLi Xu #define CS43130_PLL_DIV_FRAC_2_DATA_SHIFT 16 2598f1e5bf9SLi Xu 2608f1e5bf9SLi Xu /* Reg CS43130_SP_DEN_1 */ 2618f1e5bf9SLi Xu #define CS43130_SP_M_LSB_DATA_MASK 0x00FF 2628f1e5bf9SLi Xu #define CS43130_SP_M_LSB_DATA_SHIFT 0 2638f1e5bf9SLi Xu 2648f1e5bf9SLi Xu /* Reg CS43130_SP_DEN_2 */ 2658f1e5bf9SLi Xu #define CS43130_SP_M_MSB_DATA_MASK 0xFF00 2668f1e5bf9SLi Xu #define CS43130_SP_M_MSB_DATA_SHIFT 8 2678f1e5bf9SLi Xu 2688f1e5bf9SLi Xu /* Reg CS43130_SP_NUM_1 */ 2698f1e5bf9SLi Xu #define CS43130_SP_N_LSB_DATA_MASK 0x00FF 2708f1e5bf9SLi Xu #define CS43130_SP_N_LSB_DATA_SHIFT 0 2718f1e5bf9SLi Xu 2728f1e5bf9SLi Xu /* Reg CS43130_SP_NUM_2 */ 2738f1e5bf9SLi Xu #define CS43130_SP_N_MSB_DATA_MASK 0xFF00 2748f1e5bf9SLi Xu #define CS43130_SP_N_MSB_DATA_SHIFT 8 2758f1e5bf9SLi Xu 2768f1e5bf9SLi Xu /* Reg CS43130_SP_LRCK_HI_TIME_1 */ 2778f1e5bf9SLi Xu #define CS43130_SP_LCHI_DATA_MASK 0x00FF 2788f1e5bf9SLi Xu #define CS43130_SP_LCHI_LSB_DATA_SHIFT 0 2798f1e5bf9SLi Xu 2808f1e5bf9SLi Xu /* Reg CS43130_SP_LRCK_HI_TIME_2 */ 2818f1e5bf9SLi Xu #define CS43130_SP_LCHI_MSB_DATA_SHIFT 8 2828f1e5bf9SLi Xu 2838f1e5bf9SLi Xu /* Reg CS43130_SP_LRCK_PERIOD_1 */ 2848f1e5bf9SLi Xu #define CS43130_SP_LCPR_DATA_MASK 0x00FF 2858f1e5bf9SLi Xu #define CS43130_SP_LCPR_LSB_DATA_SHIFT 0 2868f1e5bf9SLi Xu 2878f1e5bf9SLi Xu /* Reg CS43130_SP_LRCK_PERIOD_2 */ 2888f1e5bf9SLi Xu #define CS43130_SP_LCPR_MSB_DATA_SHIFT 8 2898f1e5bf9SLi Xu 2908f1e5bf9SLi Xu #define CS43130_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 2918f1e5bf9SLi Xu SNDRV_PCM_FMTBIT_S16_LE | \ 2928f1e5bf9SLi Xu SNDRV_PCM_FMTBIT_S24_LE | \ 2938f1e5bf9SLi Xu SNDRV_PCM_FMTBIT_S32_LE) 2948f1e5bf9SLi Xu 2958f1e5bf9SLi Xu #define CS43130_DOP_FORMATS (SNDRV_PCM_FMTBIT_DSD_U16_LE | \ 2968f1e5bf9SLi Xu SNDRV_PCM_FMTBIT_DSD_U16_BE | \ 2978f1e5bf9SLi Xu SNDRV_PCM_FMTBIT_S24_LE) 2988f1e5bf9SLi Xu 2998f1e5bf9SLi Xu /* Reg CS43130_CRYSTAL_SET */ 3008f1e5bf9SLi Xu #define CS43130_XTAL_IBIAS_MASK 0x07 3018f1e5bf9SLi Xu 3028f1e5bf9SLi Xu /* Reg CS43130_PATH_CTL_1 */ 3038f1e5bf9SLi Xu #define CS43130_MUTE_MASK 0x03 3048f1e5bf9SLi Xu #define CS43130_MUTE_EN 0x03 3058f1e5bf9SLi Xu 3068f1e5bf9SLi Xu /* Reg CS43130_DSD_INT_CFG */ 3078f1e5bf9SLi Xu #define CS43130_DSD_MASTER 0x04 3088f1e5bf9SLi Xu 3098f1e5bf9SLi Xu /* Reg CS43130_DSD_PATH_CTL_2 */ 3108f1e5bf9SLi Xu #define CS43130_DSD_SRC_MASK 0x60 3118f1e5bf9SLi Xu #define CS43130_DSD_SRC_SHIFT 5 3128f1e5bf9SLi Xu #define CS43130_DSD_EN_SHIFT 4 3138f1e5bf9SLi Xu #define CS43130_DSD_SPEED_MASK 0x04 3148f1e5bf9SLi Xu #define CS43130_DSD_SPEED_SHIFT 2 3158f1e5bf9SLi Xu 3168f1e5bf9SLi Xu /* Reg CS43130_DSD_PCM_MIX_CTL */ 3178f1e5bf9SLi Xu #define CS43130_MIX_PCM_PREP_SHIFT 1 3188f1e5bf9SLi Xu #define CS43130_MIX_PCM_PREP_MASK 0x02 3198f1e5bf9SLi Xu 3208f1e5bf9SLi Xu #define CS43130_MIX_PCM_DSD_SHIFT 0 3218f1e5bf9SLi Xu #define CS43130_MIX_PCM_DSD_MASK 0x01 3228f1e5bf9SLi Xu 3238f1e5bf9SLi Xu /* Reg CS43130_HP_MEAS_LOAD */ 3248f1e5bf9SLi Xu #define CS43130_HP_MEAS_LOAD_MASK 0x000000FF 3258f1e5bf9SLi Xu #define CS43130_HP_MEAS_LOAD_1_SHIFT 0 3268f1e5bf9SLi Xu #define CS43130_HP_MEAS_LOAD_2_SHIFT 8 3278f1e5bf9SLi Xu 3288f1e5bf9SLi Xu #define CS43130_MCLK_22M 22579200 3298f1e5bf9SLi Xu #define CS43130_MCLK_24M 24576000 3308f1e5bf9SLi Xu 3318f1e5bf9SLi Xu #define CS43130_LINEOUT_LOAD 5000 3328f1e5bf9SLi Xu #define CS43130_JACK_LINEOUT (SND_JACK_MECHANICAL | SND_JACK_LINEOUT) 3338f1e5bf9SLi Xu #define CS43130_JACK_HEADPHONE (SND_JACK_MECHANICAL | \ 3348f1e5bf9SLi Xu SND_JACK_HEADPHONE) 3358f1e5bf9SLi Xu #define CS43130_JACK_MASK (SND_JACK_MECHANICAL | \ 3368f1e5bf9SLi Xu SND_JACK_LINEOUT | \ 3378f1e5bf9SLi Xu SND_JACK_HEADPHONE) 3388f1e5bf9SLi Xu 3398f1e5bf9SLi Xu enum cs43130_dsd_src { 3408f1e5bf9SLi Xu CS43130_DSD_SRC_DSD = 0, 3418f1e5bf9SLi Xu CS43130_DSD_SRC_ASP = 2, 3428f1e5bf9SLi Xu CS43130_DSD_SRC_XSP = 3, 3438f1e5bf9SLi Xu }; 3448f1e5bf9SLi Xu 3458f1e5bf9SLi Xu enum cs43130_asp_rate { 3468f1e5bf9SLi Xu CS43130_ASP_SPRATE_32K = 0, 3478f1e5bf9SLi Xu CS43130_ASP_SPRATE_44_1K, 3488f1e5bf9SLi Xu CS43130_ASP_SPRATE_48K, 3498f1e5bf9SLi Xu CS43130_ASP_SPRATE_88_2K, 3508f1e5bf9SLi Xu CS43130_ASP_SPRATE_96K, 3518f1e5bf9SLi Xu CS43130_ASP_SPRATE_176_4K, 3528f1e5bf9SLi Xu CS43130_ASP_SPRATE_192K, 3538f1e5bf9SLi Xu CS43130_ASP_SPRATE_352_8K, 3548f1e5bf9SLi Xu CS43130_ASP_SPRATE_384K, 3558f1e5bf9SLi Xu }; 3568f1e5bf9SLi Xu 3578f1e5bf9SLi Xu enum cs43130_mclk_src_sel { 3588f1e5bf9SLi Xu CS43130_MCLK_SRC_EXT = 0, 3598f1e5bf9SLi Xu CS43130_MCLK_SRC_PLL, 3608f1e5bf9SLi Xu CS43130_MCLK_SRC_RCO 3618f1e5bf9SLi Xu }; 3628f1e5bf9SLi Xu 3638f1e5bf9SLi Xu enum cs43130_mclk_int_freq { 3648f1e5bf9SLi Xu CS43130_MCLK_24P5 = 0, 3658f1e5bf9SLi Xu CS43130_MCLK_22P5, 3668f1e5bf9SLi Xu }; 3678f1e5bf9SLi Xu 3688f1e5bf9SLi Xu enum cs43130_xtal_ibias { 3698f1e5bf9SLi Xu CS43130_XTAL_UNUSED = -1, 3708f1e5bf9SLi Xu CS43130_XTAL_IBIAS_15UA = 2, 3718f1e5bf9SLi Xu CS43130_XTAL_IBIAS_12_5UA = 4, 3728f1e5bf9SLi Xu CS43130_XTAL_IBIAS_7_5UA = 6, 3738f1e5bf9SLi Xu }; 3748f1e5bf9SLi Xu 3758f1e5bf9SLi Xu enum cs43130_dai_id { 3768f1e5bf9SLi Xu CS43130_ASP_PCM_DAI = 0, 3778f1e5bf9SLi Xu CS43130_ASP_DOP_DAI, 3788f1e5bf9SLi Xu CS43130_XSP_DOP_DAI, 3798f1e5bf9SLi Xu CS43130_XSP_DSD_DAI, 3808f1e5bf9SLi Xu CS43130_DAI_ID_MAX, 3818f1e5bf9SLi Xu }; 3828f1e5bf9SLi Xu 3838f1e5bf9SLi Xu struct cs43130_clk_gen { 3848f1e5bf9SLi Xu unsigned int mclk_int; 3858f1e5bf9SLi Xu int fs; 3868f1e5bf9SLi Xu u16 den; 3878f1e5bf9SLi Xu u16 num; 3888f1e5bf9SLi Xu }; 3898f1e5bf9SLi Xu 3908f1e5bf9SLi Xu /* frm_size = 16 */ 3918f1e5bf9SLi Xu static const struct cs43130_clk_gen cs43130_16_clk_gen[] = { 3928f1e5bf9SLi Xu {22579200, 32000, 441, 10,}, 3938f1e5bf9SLi Xu {22579200, 44100, 32, 1,}, 3948f1e5bf9SLi Xu {22579200, 48000, 147, 5,}, 3958f1e5bf9SLi Xu {22579200, 88200, 16, 1,}, 3968f1e5bf9SLi Xu {22579200, 96000, 147, 10,}, 3978f1e5bf9SLi Xu {22579200, 176400, 8, 1,}, 3988f1e5bf9SLi Xu {22579200, 192000, 147, 20,}, 3998f1e5bf9SLi Xu {22579200, 352800, 4, 1,}, 4008f1e5bf9SLi Xu {22579200, 384000, 147, 40,}, 4018f1e5bf9SLi Xu {24576000, 32000, 48, 1,}, 4028f1e5bf9SLi Xu {24576000, 44100, 5120, 147,}, 4038f1e5bf9SLi Xu {24576000, 48000, 32, 1,}, 4048f1e5bf9SLi Xu {24576000, 88200, 2560, 147,}, 4058f1e5bf9SLi Xu {24576000, 96000, 16, 1,}, 4068f1e5bf9SLi Xu {24576000, 176400, 1280, 147,}, 4078f1e5bf9SLi Xu {24576000, 192000, 8, 1,}, 4088f1e5bf9SLi Xu {24576000, 352800, 640, 147,}, 4098f1e5bf9SLi Xu {24576000, 384000, 4, 1,}, 4108f1e5bf9SLi Xu }; 4118f1e5bf9SLi Xu 4128f1e5bf9SLi Xu /* frm_size = 32 */ 4138f1e5bf9SLi Xu static const struct cs43130_clk_gen cs43130_32_clk_gen[] = { 4148f1e5bf9SLi Xu {22579200, 32000, 441, 20,}, 4158f1e5bf9SLi Xu {22579200, 44100, 16, 1,}, 4168f1e5bf9SLi Xu {22579200, 48000, 147, 10,}, 4178f1e5bf9SLi Xu {22579200, 88200, 8, 1,}, 4188f1e5bf9SLi Xu {22579200, 96000, 147, 20,}, 4198f1e5bf9SLi Xu {22579200, 176400, 4, 1,}, 4208f1e5bf9SLi Xu {22579200, 192000, 147, 40,}, 4218f1e5bf9SLi Xu {22579200, 352800, 2, 1,}, 4228f1e5bf9SLi Xu {22579200, 384000, 147, 80,}, 4238f1e5bf9SLi Xu {24576000, 32000, 24, 1,}, 4248f1e5bf9SLi Xu {24576000, 44100, 2560, 147,}, 4258f1e5bf9SLi Xu {24576000, 48000, 16, 1,}, 4268f1e5bf9SLi Xu {24576000, 88200, 1280, 147,}, 4278f1e5bf9SLi Xu {24576000, 96000, 8, 1,}, 4288f1e5bf9SLi Xu {24576000, 176400, 640, 147,}, 4298f1e5bf9SLi Xu {24576000, 192000, 4, 1,}, 4308f1e5bf9SLi Xu {24576000, 352800, 320, 147,}, 4318f1e5bf9SLi Xu {24576000, 384000, 2, 1,}, 4328f1e5bf9SLi Xu }; 4338f1e5bf9SLi Xu 4348f1e5bf9SLi Xu /* frm_size = 48 */ 4358f1e5bf9SLi Xu static const struct cs43130_clk_gen cs43130_48_clk_gen[] = { 4368f1e5bf9SLi Xu {22579200, 32000, 147, 100,}, 4378f1e5bf9SLi Xu {22579200, 44100, 32, 3,}, 4388f1e5bf9SLi Xu {22579200, 48000, 49, 5,}, 4398f1e5bf9SLi Xu {22579200, 88200, 16, 3,}, 4408f1e5bf9SLi Xu {22579200, 96000, 49, 10,}, 4418f1e5bf9SLi Xu {22579200, 176400, 8, 3,}, 4428f1e5bf9SLi Xu {22579200, 192000, 49, 20,}, 4438f1e5bf9SLi Xu {22579200, 352800, 4, 3,}, 4448f1e5bf9SLi Xu {22579200, 384000, 49, 40,}, 4458f1e5bf9SLi Xu {24576000, 32000, 16, 1,}, 4468f1e5bf9SLi Xu {24576000, 44100, 5120, 441,}, 4478f1e5bf9SLi Xu {24576000, 48000, 32, 3,}, 4488f1e5bf9SLi Xu {24576000, 88200, 2560, 441,}, 4498f1e5bf9SLi Xu {24576000, 96000, 16, 3,}, 4508f1e5bf9SLi Xu {24576000, 176400, 1280, 441,}, 4518f1e5bf9SLi Xu {24576000, 192000, 8, 3,}, 4528f1e5bf9SLi Xu {24576000, 352800, 640, 441,}, 4538f1e5bf9SLi Xu {24576000, 384000, 4, 3,}, 4548f1e5bf9SLi Xu }; 4558f1e5bf9SLi Xu 4568f1e5bf9SLi Xu /* frm_size = 64 */ 4578f1e5bf9SLi Xu static const struct cs43130_clk_gen cs43130_64_clk_gen[] = { 4588f1e5bf9SLi Xu {22579200, 32000, 441, 40,}, 4598f1e5bf9SLi Xu {22579200, 44100, 8, 1,}, 4608f1e5bf9SLi Xu {22579200, 48000, 147, 20,}, 4618f1e5bf9SLi Xu {22579200, 88200, 4, 1,}, 4628f1e5bf9SLi Xu {22579200, 96000, 147, 40,}, 4638f1e5bf9SLi Xu {22579200, 176400, 2, 1,}, 4648f1e5bf9SLi Xu {22579200, 192000, 147, 80,}, 4658f1e5bf9SLi Xu {22579200, 352800, 1, 1,}, 4668f1e5bf9SLi Xu {24576000, 32000, 12, 1,}, 4678f1e5bf9SLi Xu {24576000, 44100, 1280, 147,}, 4688f1e5bf9SLi Xu {24576000, 48000, 8, 1,}, 4698f1e5bf9SLi Xu {24576000, 88200, 640, 147,}, 4708f1e5bf9SLi Xu {24576000, 96000, 4, 1,}, 4718f1e5bf9SLi Xu {24576000, 176400, 320, 147,}, 4728f1e5bf9SLi Xu {24576000, 192000, 2, 1,}, 4738f1e5bf9SLi Xu {24576000, 352800, 160, 147,}, 4748f1e5bf9SLi Xu {24576000, 384000, 1, 1,}, 4758f1e5bf9SLi Xu }; 4768f1e5bf9SLi Xu 4778f1e5bf9SLi Xu struct cs43130_bitwidth_map { 4788f1e5bf9SLi Xu unsigned int bitwidth; 4798f1e5bf9SLi Xu u8 sp_bit; 4808f1e5bf9SLi Xu u8 ch_bit; 4818f1e5bf9SLi Xu }; 4828f1e5bf9SLi Xu 4838f1e5bf9SLi Xu struct cs43130_rate_map { 4848f1e5bf9SLi Xu int fs; 4858f1e5bf9SLi Xu int val; 4868f1e5bf9SLi Xu }; 4878f1e5bf9SLi Xu 4888f1e5bf9SLi Xu #define HP_LEFT 0 4898f1e5bf9SLi Xu #define HP_RIGHT 1 4908f1e5bf9SLi Xu #define CS43130_AC_FREQ 10 4918f1e5bf9SLi Xu #define CS43130_DC_THRESHOLD 2 4928f1e5bf9SLi Xu 4938f1e5bf9SLi Xu #define CS43130_NUM_SUPPLIES 5 4948f1e5bf9SLi Xu static const char *const cs43130_supply_names[CS43130_NUM_SUPPLIES] = { 4958f1e5bf9SLi Xu "VA", 4968f1e5bf9SLi Xu "VP", 4978f1e5bf9SLi Xu "VCP", 4988f1e5bf9SLi Xu "VD", 4998f1e5bf9SLi Xu "VL", 5008f1e5bf9SLi Xu }; 5018f1e5bf9SLi Xu 5028f1e5bf9SLi Xu #define CS43130_NUM_INT 5 /* number of interrupt status reg */ 5038f1e5bf9SLi Xu 5048f1e5bf9SLi Xu struct cs43130_dai { 5058f1e5bf9SLi Xu unsigned int sclk; 5068f1e5bf9SLi Xu unsigned int dai_format; 5078f1e5bf9SLi Xu unsigned int dai_mode; 5088f1e5bf9SLi Xu }; 5098f1e5bf9SLi Xu 5108f1e5bf9SLi Xu struct cs43130_private { 5118f1e5bf9SLi Xu struct snd_soc_codec *codec; 5128f1e5bf9SLi Xu struct regmap *regmap; 5138f1e5bf9SLi Xu struct regulator_bulk_data supplies[CS43130_NUM_SUPPLIES]; 5148f1e5bf9SLi Xu struct gpio_desc *reset_gpio; 5158f1e5bf9SLi Xu unsigned int dev_id; /* codec device ID */ 5168f1e5bf9SLi Xu int xtal_ibias; 5178f1e5bf9SLi Xu 5188f1e5bf9SLi Xu /* shared by both DAIs */ 5198f1e5bf9SLi Xu struct mutex clk_mutex; 5208f1e5bf9SLi Xu int clk_req; 5218f1e5bf9SLi Xu bool pll_bypass; 5228f1e5bf9SLi Xu struct completion xtal_rdy; 5238f1e5bf9SLi Xu struct completion pll_rdy; 5248f1e5bf9SLi Xu unsigned int mclk; 5258f1e5bf9SLi Xu unsigned int mclk_int; 5268f1e5bf9SLi Xu int mclk_int_src; 5278f1e5bf9SLi Xu 5288f1e5bf9SLi Xu /* DAI specific */ 5298f1e5bf9SLi Xu struct cs43130_dai dais[CS43130_DAI_ID_MAX]; 5308f1e5bf9SLi Xu 5318f1e5bf9SLi Xu /* HP load specific */ 5328f1e5bf9SLi Xu bool dc_meas; 5338f1e5bf9SLi Xu bool ac_meas; 5348f1e5bf9SLi Xu bool hpload_done; 5358f1e5bf9SLi Xu struct completion hpload_evt; 5368f1e5bf9SLi Xu unsigned int hpload_stat; 5378f1e5bf9SLi Xu u16 hpload_dc[2]; 5388f1e5bf9SLi Xu u16 dc_threshold[CS43130_DC_THRESHOLD]; 5398f1e5bf9SLi Xu u16 ac_freq[CS43130_AC_FREQ]; 5408f1e5bf9SLi Xu u16 hpload_ac[CS43130_AC_FREQ][2]; 5418f1e5bf9SLi Xu struct workqueue_struct *wq; 5428f1e5bf9SLi Xu struct work_struct work; 5438f1e5bf9SLi Xu struct snd_soc_jack jack; 5448f1e5bf9SLi Xu }; 5458f1e5bf9SLi Xu 5468f1e5bf9SLi Xu #endif /* __CS43130_H__ */ 547