1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs43130.c -- CS43130 ALSA Soc Audio driver 4 * 5 * Copyright 2017 Cirrus Logic, Inc. 6 * 7 * Authors: Li Xu <li.xu@cirrus.com> 8 */ 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/gpio.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/i2c.h> 19 #include <linux/of_device.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <linux/of_gpio.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/of_irq.h> 33 #include <linux/completion.h> 34 #include <linux/mutex.h> 35 #include <linux/workqueue.h> 36 #include <sound/jack.h> 37 38 #include "cs43130.h" 39 #include "cirrus_legacy.h" 40 41 static const struct reg_default cs43130_reg_defaults[] = { 42 {CS43130_SYS_CLK_CTL_1, 0x06}, 43 {CS43130_SP_SRATE, 0x01}, 44 {CS43130_SP_BITSIZE, 0x05}, 45 {CS43130_PAD_INT_CFG, 0x03}, 46 {CS43130_PWDN_CTL, 0xFE}, 47 {CS43130_CRYSTAL_SET, 0x04}, 48 {CS43130_PLL_SET_1, 0x00}, 49 {CS43130_PLL_SET_2, 0x00}, 50 {CS43130_PLL_SET_3, 0x00}, 51 {CS43130_PLL_SET_4, 0x00}, 52 {CS43130_PLL_SET_5, 0x40}, 53 {CS43130_PLL_SET_6, 0x10}, 54 {CS43130_PLL_SET_7, 0x80}, 55 {CS43130_PLL_SET_8, 0x03}, 56 {CS43130_PLL_SET_9, 0x02}, 57 {CS43130_PLL_SET_10, 0x02}, 58 {CS43130_CLKOUT_CTL, 0x00}, 59 {CS43130_ASP_NUM_1, 0x01}, 60 {CS43130_ASP_NUM_2, 0x00}, 61 {CS43130_ASP_DEN_1, 0x08}, 62 {CS43130_ASP_DEN_2, 0x00}, 63 {CS43130_ASP_LRCK_HI_TIME_1, 0x1F}, 64 {CS43130_ASP_LRCK_HI_TIME_2, 0x00}, 65 {CS43130_ASP_LRCK_PERIOD_1, 0x3F}, 66 {CS43130_ASP_LRCK_PERIOD_2, 0x00}, 67 {CS43130_ASP_CLOCK_CONF, 0x0C}, 68 {CS43130_ASP_FRAME_CONF, 0x0A}, 69 {CS43130_XSP_NUM_1, 0x01}, 70 {CS43130_XSP_NUM_2, 0x00}, 71 {CS43130_XSP_DEN_1, 0x02}, 72 {CS43130_XSP_DEN_2, 0x00}, 73 {CS43130_XSP_LRCK_HI_TIME_1, 0x1F}, 74 {CS43130_XSP_LRCK_HI_TIME_2, 0x00}, 75 {CS43130_XSP_LRCK_PERIOD_1, 0x3F}, 76 {CS43130_XSP_LRCK_PERIOD_2, 0x00}, 77 {CS43130_XSP_CLOCK_CONF, 0x0C}, 78 {CS43130_XSP_FRAME_CONF, 0x0A}, 79 {CS43130_ASP_CH_1_LOC, 0x00}, 80 {CS43130_ASP_CH_2_LOC, 0x00}, 81 {CS43130_ASP_CH_1_SZ_EN, 0x06}, 82 {CS43130_ASP_CH_2_SZ_EN, 0x0E}, 83 {CS43130_XSP_CH_1_LOC, 0x00}, 84 {CS43130_XSP_CH_2_LOC, 0x00}, 85 {CS43130_XSP_CH_1_SZ_EN, 0x06}, 86 {CS43130_XSP_CH_2_SZ_EN, 0x0E}, 87 {CS43130_DSD_VOL_B, 0x78}, 88 {CS43130_DSD_VOL_A, 0x78}, 89 {CS43130_DSD_PATH_CTL_1, 0xA8}, 90 {CS43130_DSD_INT_CFG, 0x00}, 91 {CS43130_DSD_PATH_CTL_2, 0x02}, 92 {CS43130_DSD_PCM_MIX_CTL, 0x00}, 93 {CS43130_DSD_PATH_CTL_3, 0x40}, 94 {CS43130_HP_OUT_CTL_1, 0x30}, 95 {CS43130_PCM_FILT_OPT, 0x02}, 96 {CS43130_PCM_VOL_B, 0x78}, 97 {CS43130_PCM_VOL_A, 0x78}, 98 {CS43130_PCM_PATH_CTL_1, 0xA8}, 99 {CS43130_PCM_PATH_CTL_2, 0x00}, 100 {CS43130_CLASS_H_CTL, 0x1E}, 101 {CS43130_HP_DETECT, 0x04}, 102 {CS43130_HP_LOAD_1, 0x00}, 103 {CS43130_HP_MEAS_LOAD_1, 0x00}, 104 {CS43130_HP_MEAS_LOAD_2, 0x00}, 105 {CS43130_INT_MASK_1, 0xFF}, 106 {CS43130_INT_MASK_2, 0xFF}, 107 {CS43130_INT_MASK_3, 0xFF}, 108 {CS43130_INT_MASK_4, 0xFF}, 109 {CS43130_INT_MASK_5, 0xFF}, 110 }; 111 112 static bool cs43130_volatile_register(struct device *dev, unsigned int reg) 113 { 114 switch (reg) { 115 case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5: 116 case CS43130_HP_DC_STAT_1 ... CS43130_HP_DC_STAT_2: 117 case CS43130_HP_AC_STAT_1 ... CS43130_HP_AC_STAT_2: 118 return true; 119 default: 120 return false; 121 } 122 } 123 124 static bool cs43130_readable_register(struct device *dev, unsigned int reg) 125 { 126 switch (reg) { 127 case CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1: 128 case CS43130_SP_SRATE ... CS43130_PAD_INT_CFG: 129 case CS43130_PWDN_CTL: 130 case CS43130_CRYSTAL_SET: 131 case CS43130_PLL_SET_1 ... CS43130_PLL_SET_5: 132 case CS43130_PLL_SET_6: 133 case CS43130_PLL_SET_7: 134 case CS43130_PLL_SET_8: 135 case CS43130_PLL_SET_9: 136 case CS43130_PLL_SET_10: 137 case CS43130_CLKOUT_CTL: 138 case CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF: 139 case CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF: 140 case CS43130_ASP_CH_1_LOC: 141 case CS43130_ASP_CH_2_LOC: 142 case CS43130_ASP_CH_1_SZ_EN: 143 case CS43130_ASP_CH_2_SZ_EN: 144 case CS43130_XSP_CH_1_LOC: 145 case CS43130_XSP_CH_2_LOC: 146 case CS43130_XSP_CH_1_SZ_EN: 147 case CS43130_XSP_CH_2_SZ_EN: 148 case CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3: 149 case CS43130_HP_OUT_CTL_1: 150 case CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2: 151 case CS43130_CLASS_H_CTL: 152 case CS43130_HP_DETECT: 153 case CS43130_HP_STATUS: 154 case CS43130_HP_LOAD_1: 155 case CS43130_HP_MEAS_LOAD_1: 156 case CS43130_HP_MEAS_LOAD_2: 157 case CS43130_HP_DC_STAT_1: 158 case CS43130_HP_DC_STAT_2: 159 case CS43130_HP_AC_STAT_1: 160 case CS43130_HP_AC_STAT_2: 161 case CS43130_HP_LOAD_STAT: 162 case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5: 163 case CS43130_INT_MASK_1 ... CS43130_INT_MASK_5: 164 return true; 165 default: 166 return false; 167 } 168 } 169 170 static bool cs43130_precious_register(struct device *dev, unsigned int reg) 171 { 172 switch (reg) { 173 case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5: 174 return true; 175 default: 176 return false; 177 } 178 } 179 180 struct cs43130_pll_params { 181 unsigned int pll_in; 182 u8 sclk_prediv; 183 u8 pll_div_int; 184 u32 pll_div_frac; 185 u8 pll_mode; 186 u8 pll_divout; 187 unsigned int pll_out; 188 u8 pll_cal_ratio; 189 }; 190 191 static const struct cs43130_pll_params pll_ratio_table[] = { 192 {9600000, 0x02, 0x49, 0x800000, 0x00, 0x08, 22579200, 151}, 193 {9600000, 0x02, 0x50, 0x000000, 0x00, 0x08, 24576000, 164}, 194 195 {11289600, 0x02, 0X40, 0, 0x01, 0x08, 22579200, 128}, 196 {11289600, 0x02, 0x44, 0x06F700, 0x0, 0x08, 24576000, 139}, 197 198 {12000000, 0x02, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120}, 199 {12000000, 0x02, 0x40, 0x000000, 0x00, 0x08, 24576000, 131}, 200 201 {12288000, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118}, 202 {12288000, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128}, 203 204 {13000000, 0x02, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111}, 205 {13000000, 0x02, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121}, 206 207 {19200000, 0x03, 0x49, 0x800000, 0x00, 0x08, 22579200, 151}, 208 {19200000, 0x03, 0x50, 0x000000, 0x00, 0x08, 24576000, 164}, 209 210 {22579200, 0, 0, 0, 0, 0, 22579200, 0}, 211 {22579200, 0x03, 0x44, 0x06F700, 0x00, 0x08, 24576000, 139}, 212 213 {24000000, 0x03, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120}, 214 {24000000, 0x03, 0x40, 0x000000, 0x00, 0x08, 24576000, 131}, 215 216 {24576000, 0x03, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118}, 217 {24576000, 0, 0, 0, 0, 0, 24576000, 0}, 218 219 {26000000, 0x03, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111}, 220 {26000000, 0x03, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121}, 221 }; 222 223 static const struct cs43130_pll_params *cs43130_get_pll_table( 224 unsigned int freq_in, unsigned int freq_out) 225 { 226 int i; 227 228 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 229 if (pll_ratio_table[i].pll_in == freq_in && 230 pll_ratio_table[i].pll_out == freq_out) 231 return &pll_ratio_table[i]; 232 } 233 234 return NULL; 235 } 236 237 static int cs43130_pll_config(struct snd_soc_component *component) 238 { 239 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 240 const struct cs43130_pll_params *pll_entry; 241 242 dev_dbg(component->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n", 243 cs43130->mclk, cs43130->mclk_int); 244 245 pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int); 246 if (!pll_entry) 247 return -EINVAL; 248 249 if (pll_entry->pll_cal_ratio == 0) { 250 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1, 251 CS43130_PLL_START_MASK, 0); 252 253 cs43130->pll_bypass = true; 254 return 0; 255 } 256 257 cs43130->pll_bypass = false; 258 259 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_2, 260 CS43130_PLL_DIV_DATA_MASK, 261 pll_entry->pll_div_frac >> 262 CS43130_PLL_DIV_FRAC_0_DATA_SHIFT); 263 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_3, 264 CS43130_PLL_DIV_DATA_MASK, 265 pll_entry->pll_div_frac >> 266 CS43130_PLL_DIV_FRAC_1_DATA_SHIFT); 267 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_4, 268 CS43130_PLL_DIV_DATA_MASK, 269 pll_entry->pll_div_frac >> 270 CS43130_PLL_DIV_FRAC_2_DATA_SHIFT); 271 regmap_write(cs43130->regmap, CS43130_PLL_SET_5, 272 pll_entry->pll_div_int); 273 regmap_write(cs43130->regmap, CS43130_PLL_SET_6, pll_entry->pll_divout); 274 regmap_write(cs43130->regmap, CS43130_PLL_SET_7, 275 pll_entry->pll_cal_ratio); 276 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8, 277 CS43130_PLL_MODE_MASK, 278 pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT); 279 regmap_write(cs43130->regmap, CS43130_PLL_SET_9, 280 pll_entry->sclk_prediv); 281 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1, 282 CS43130_PLL_START_MASK, 1); 283 284 return 0; 285 } 286 287 static int cs43130_set_pll(struct snd_soc_component *component, int pll_id, int source, 288 unsigned int freq_in, unsigned int freq_out) 289 { 290 int ret = 0; 291 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 292 293 switch (freq_in) { 294 case 9600000: 295 case 11289600: 296 case 12000000: 297 case 12288000: 298 case 13000000: 299 case 19200000: 300 case 22579200: 301 case 24000000: 302 case 24576000: 303 case 26000000: 304 cs43130->mclk = freq_in; 305 break; 306 default: 307 dev_err(component->dev, 308 "unsupported pll input reference clock:%d\n", freq_in); 309 return -EINVAL; 310 } 311 312 switch (freq_out) { 313 case 22579200: 314 cs43130->mclk_int = freq_out; 315 break; 316 case 24576000: 317 cs43130->mclk_int = freq_out; 318 break; 319 default: 320 dev_err(component->dev, 321 "unsupported pll output ref clock: %u\n", freq_out); 322 return -EINVAL; 323 } 324 325 ret = cs43130_pll_config(component); 326 dev_dbg(component->dev, "cs43130->pll_bypass = %d", cs43130->pll_bypass); 327 return ret; 328 } 329 330 static int cs43130_change_clksrc(struct snd_soc_component *component, 331 enum cs43130_mclk_src_sel src) 332 { 333 int ret; 334 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 335 int mclk_int_decoded; 336 337 if (src == cs43130->mclk_int_src) { 338 /* clk source has not changed */ 339 return 0; 340 } 341 342 switch (cs43130->mclk_int) { 343 case CS43130_MCLK_22M: 344 mclk_int_decoded = CS43130_MCLK_22P5; 345 break; 346 case CS43130_MCLK_24M: 347 mclk_int_decoded = CS43130_MCLK_24P5; 348 break; 349 default: 350 dev_err(component->dev, "Invalid MCLK INT freq: %u\n", cs43130->mclk_int); 351 return -EINVAL; 352 } 353 354 switch (src) { 355 case CS43130_MCLK_SRC_EXT: 356 cs43130->pll_bypass = true; 357 cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT; 358 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) { 359 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 360 CS43130_PDN_XTAL_MASK, 361 1 << CS43130_PDN_XTAL_SHIFT); 362 } else { 363 reinit_completion(&cs43130->xtal_rdy); 364 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 365 CS43130_XTAL_RDY_INT_MASK, 0); 366 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 367 CS43130_PDN_XTAL_MASK, 0); 368 ret = wait_for_completion_timeout(&cs43130->xtal_rdy, 369 msecs_to_jiffies(100)); 370 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 371 CS43130_XTAL_RDY_INT_MASK, 372 1 << CS43130_XTAL_RDY_INT_SHIFT); 373 if (ret == 0) { 374 dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n"); 375 return -ETIMEDOUT; 376 } 377 } 378 379 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 380 CS43130_MCLK_SRC_SEL_MASK, 381 src << CS43130_MCLK_SRC_SEL_SHIFT); 382 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 383 CS43130_MCLK_INT_MASK, 384 mclk_int_decoded << CS43130_MCLK_INT_SHIFT); 385 usleep_range(150, 200); 386 387 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 388 CS43130_PDN_PLL_MASK, 389 1 << CS43130_PDN_PLL_SHIFT); 390 break; 391 case CS43130_MCLK_SRC_PLL: 392 cs43130->pll_bypass = false; 393 cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL; 394 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) { 395 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 396 CS43130_PDN_XTAL_MASK, 397 1 << CS43130_PDN_XTAL_SHIFT); 398 } else { 399 reinit_completion(&cs43130->xtal_rdy); 400 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 401 CS43130_XTAL_RDY_INT_MASK, 0); 402 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 403 CS43130_PDN_XTAL_MASK, 0); 404 ret = wait_for_completion_timeout(&cs43130->xtal_rdy, 405 msecs_to_jiffies(100)); 406 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 407 CS43130_XTAL_RDY_INT_MASK, 408 1 << CS43130_XTAL_RDY_INT_SHIFT); 409 if (ret == 0) { 410 dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n"); 411 return -ETIMEDOUT; 412 } 413 } 414 415 reinit_completion(&cs43130->pll_rdy); 416 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 417 CS43130_PLL_RDY_INT_MASK, 0); 418 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 419 CS43130_PDN_PLL_MASK, 0); 420 ret = wait_for_completion_timeout(&cs43130->pll_rdy, 421 msecs_to_jiffies(100)); 422 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 423 CS43130_PLL_RDY_INT_MASK, 424 1 << CS43130_PLL_RDY_INT_SHIFT); 425 if (ret == 0) { 426 dev_err(component->dev, "Timeout waiting for PLL_READY interrupt\n"); 427 return -ETIMEDOUT; 428 } 429 430 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 431 CS43130_MCLK_SRC_SEL_MASK, 432 src << CS43130_MCLK_SRC_SEL_SHIFT); 433 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 434 CS43130_MCLK_INT_MASK, 435 mclk_int_decoded << CS43130_MCLK_INT_SHIFT); 436 usleep_range(150, 200); 437 break; 438 case CS43130_MCLK_SRC_RCO: 439 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO; 440 441 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 442 CS43130_MCLK_SRC_SEL_MASK, 443 src << CS43130_MCLK_SRC_SEL_SHIFT); 444 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 445 CS43130_MCLK_INT_MASK, 446 CS43130_MCLK_22P5 << CS43130_MCLK_INT_SHIFT); 447 usleep_range(150, 200); 448 449 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 450 CS43130_PDN_XTAL_MASK, 451 1 << CS43130_PDN_XTAL_SHIFT); 452 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 453 CS43130_PDN_PLL_MASK, 454 1 << CS43130_PDN_PLL_SHIFT); 455 break; 456 default: 457 dev_err(component->dev, "Invalid MCLK source value\n"); 458 return -EINVAL; 459 } 460 461 return 0; 462 } 463 464 static const struct cs43130_bitwidth_map cs43130_bitwidth_table[] = { 465 {8, CS43130_SP_BIT_SIZE_8, CS43130_CH_BIT_SIZE_8}, 466 {16, CS43130_SP_BIT_SIZE_16, CS43130_CH_BIT_SIZE_16}, 467 {24, CS43130_SP_BIT_SIZE_24, CS43130_CH_BIT_SIZE_24}, 468 {32, CS43130_SP_BIT_SIZE_32, CS43130_CH_BIT_SIZE_32}, 469 }; 470 471 static const struct cs43130_bitwidth_map *cs43130_get_bitwidth_table( 472 unsigned int bitwidth) 473 { 474 int i; 475 476 for (i = 0; i < ARRAY_SIZE(cs43130_bitwidth_table); i++) { 477 if (cs43130_bitwidth_table[i].bitwidth == bitwidth) 478 return &cs43130_bitwidth_table[i]; 479 } 480 481 return NULL; 482 } 483 484 static int cs43130_set_bitwidth(int dai_id, unsigned int bitwidth_dai, 485 struct regmap *regmap) 486 { 487 const struct cs43130_bitwidth_map *bw_map; 488 489 bw_map = cs43130_get_bitwidth_table(bitwidth_dai); 490 if (!bw_map) 491 return -EINVAL; 492 493 switch (dai_id) { 494 case CS43130_ASP_PCM_DAI: 495 case CS43130_ASP_DOP_DAI: 496 regmap_update_bits(regmap, CS43130_ASP_CH_1_SZ_EN, 497 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); 498 regmap_update_bits(regmap, CS43130_ASP_CH_2_SZ_EN, 499 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); 500 regmap_update_bits(regmap, CS43130_SP_BITSIZE, 501 CS43130_ASP_BITSIZE_MASK, bw_map->sp_bit); 502 break; 503 case CS43130_XSP_DOP_DAI: 504 regmap_update_bits(regmap, CS43130_XSP_CH_1_SZ_EN, 505 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); 506 regmap_update_bits(regmap, CS43130_XSP_CH_2_SZ_EN, 507 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); 508 regmap_update_bits(regmap, CS43130_SP_BITSIZE, 509 CS43130_XSP_BITSIZE_MASK, bw_map->sp_bit << 510 CS43130_XSP_BITSIZE_SHIFT); 511 break; 512 default: 513 return -EINVAL; 514 } 515 516 return 0; 517 } 518 519 static const struct cs43130_rate_map cs43130_rate_table[] = { 520 {32000, CS43130_ASP_SPRATE_32K}, 521 {44100, CS43130_ASP_SPRATE_44_1K}, 522 {48000, CS43130_ASP_SPRATE_48K}, 523 {88200, CS43130_ASP_SPRATE_88_2K}, 524 {96000, CS43130_ASP_SPRATE_96K}, 525 {176400, CS43130_ASP_SPRATE_176_4K}, 526 {192000, CS43130_ASP_SPRATE_192K}, 527 {352800, CS43130_ASP_SPRATE_352_8K}, 528 {384000, CS43130_ASP_SPRATE_384K}, 529 }; 530 531 static const struct cs43130_rate_map *cs43130_get_rate_table(int fs) 532 { 533 int i; 534 535 for (i = 0; i < ARRAY_SIZE(cs43130_rate_table); i++) { 536 if (cs43130_rate_table[i].fs == fs) 537 return &cs43130_rate_table[i]; 538 } 539 540 return NULL; 541 } 542 543 static const struct cs43130_clk_gen *cs43130_get_clk_gen(int mclk_int, int fs, 544 const struct cs43130_clk_gen *clk_gen_table, int len_clk_gen_table) 545 { 546 int i; 547 548 for (i = 0; i < len_clk_gen_table; i++) { 549 if (clk_gen_table[i].mclk_int == mclk_int && 550 clk_gen_table[i].fs == fs) 551 return &clk_gen_table[i]; 552 } 553 554 return NULL; 555 } 556 557 static int cs43130_set_sp_fmt(int dai_id, unsigned int bitwidth_sclk, 558 struct snd_pcm_hw_params *params, 559 struct cs43130_private *cs43130) 560 { 561 u16 frm_size; 562 u16 hi_size; 563 u8 frm_delay; 564 u8 frm_phase; 565 u8 frm_data; 566 u8 sclk_edge; 567 u8 lrck_edge; 568 u8 clk_data; 569 u8 loc_ch1; 570 u8 loc_ch2; 571 u8 dai_mode_val; 572 const struct cs43130_clk_gen *clk_gen; 573 574 switch (cs43130->dais[dai_id].dai_format) { 575 case SND_SOC_DAIFMT_I2S: 576 hi_size = bitwidth_sclk; 577 frm_delay = 2; 578 frm_phase = 0; 579 break; 580 case SND_SOC_DAIFMT_LEFT_J: 581 hi_size = bitwidth_sclk; 582 frm_delay = 2; 583 frm_phase = 1; 584 break; 585 case SND_SOC_DAIFMT_DSP_A: 586 hi_size = 1; 587 frm_delay = 2; 588 frm_phase = 1; 589 break; 590 case SND_SOC_DAIFMT_DSP_B: 591 hi_size = 1; 592 frm_delay = 0; 593 frm_phase = 1; 594 break; 595 default: 596 return -EINVAL; 597 } 598 599 switch (cs43130->dais[dai_id].dai_mode) { 600 case SND_SOC_DAIFMT_CBS_CFS: 601 dai_mode_val = 0; 602 break; 603 case SND_SOC_DAIFMT_CBM_CFM: 604 dai_mode_val = 1; 605 break; 606 default: 607 return -EINVAL; 608 } 609 610 frm_size = bitwidth_sclk * params_channels(params); 611 sclk_edge = 1; 612 lrck_edge = 0; 613 loc_ch1 = 0; 614 loc_ch2 = bitwidth_sclk * (params_channels(params) - 1); 615 616 frm_data = frm_delay & CS43130_SP_FSD_MASK; 617 frm_data |= (frm_phase << CS43130_SP_STP_SHIFT) & CS43130_SP_STP_MASK; 618 619 clk_data = lrck_edge & CS43130_SP_LCPOL_IN_MASK; 620 clk_data |= (lrck_edge << CS43130_SP_LCPOL_OUT_SHIFT) & 621 CS43130_SP_LCPOL_OUT_MASK; 622 clk_data |= (sclk_edge << CS43130_SP_SCPOL_IN_SHIFT) & 623 CS43130_SP_SCPOL_IN_MASK; 624 clk_data |= (sclk_edge << CS43130_SP_SCPOL_OUT_SHIFT) & 625 CS43130_SP_SCPOL_OUT_MASK; 626 clk_data |= (dai_mode_val << CS43130_SP_MODE_SHIFT) & 627 CS43130_SP_MODE_MASK; 628 629 switch (dai_id) { 630 case CS43130_ASP_PCM_DAI: 631 case CS43130_ASP_DOP_DAI: 632 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1, 633 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> 634 CS43130_SP_LCPR_LSB_DATA_SHIFT); 635 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2, 636 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> 637 CS43130_SP_LCPR_MSB_DATA_SHIFT); 638 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1, 639 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> 640 CS43130_SP_LCHI_LSB_DATA_SHIFT); 641 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2, 642 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> 643 CS43130_SP_LCHI_MSB_DATA_SHIFT); 644 regmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data); 645 regmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1); 646 regmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2); 647 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN, 648 CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT); 649 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN, 650 CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT); 651 regmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data); 652 break; 653 case CS43130_XSP_DOP_DAI: 654 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1, 655 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> 656 CS43130_SP_LCPR_LSB_DATA_SHIFT); 657 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2, 658 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> 659 CS43130_SP_LCPR_MSB_DATA_SHIFT); 660 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1, 661 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> 662 CS43130_SP_LCHI_LSB_DATA_SHIFT); 663 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2, 664 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> 665 CS43130_SP_LCHI_MSB_DATA_SHIFT); 666 regmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data); 667 regmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1); 668 regmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2); 669 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN, 670 CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT); 671 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN, 672 CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT); 673 regmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data); 674 break; 675 default: 676 return -EINVAL; 677 } 678 679 switch (frm_size) { 680 case 16: 681 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, 682 params_rate(params), 683 cs43130_16_clk_gen, 684 ARRAY_SIZE(cs43130_16_clk_gen)); 685 break; 686 case 32: 687 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, 688 params_rate(params), 689 cs43130_32_clk_gen, 690 ARRAY_SIZE(cs43130_32_clk_gen)); 691 break; 692 case 48: 693 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, 694 params_rate(params), 695 cs43130_48_clk_gen, 696 ARRAY_SIZE(cs43130_48_clk_gen)); 697 break; 698 case 64: 699 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, 700 params_rate(params), 701 cs43130_64_clk_gen, 702 ARRAY_SIZE(cs43130_64_clk_gen)); 703 break; 704 default: 705 return -EINVAL; 706 } 707 708 if (!clk_gen) 709 return -EINVAL; 710 711 switch (dai_id) { 712 case CS43130_ASP_PCM_DAI: 713 case CS43130_ASP_DOP_DAI: 714 regmap_write(cs43130->regmap, CS43130_ASP_DEN_1, 715 (clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >> 716 CS43130_SP_M_LSB_DATA_SHIFT); 717 regmap_write(cs43130->regmap, CS43130_ASP_DEN_2, 718 (clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >> 719 CS43130_SP_M_MSB_DATA_SHIFT); 720 regmap_write(cs43130->regmap, CS43130_ASP_NUM_1, 721 (clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >> 722 CS43130_SP_N_LSB_DATA_SHIFT); 723 regmap_write(cs43130->regmap, CS43130_ASP_NUM_2, 724 (clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >> 725 CS43130_SP_N_MSB_DATA_SHIFT); 726 break; 727 case CS43130_XSP_DOP_DAI: 728 regmap_write(cs43130->regmap, CS43130_XSP_DEN_1, 729 (clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >> 730 CS43130_SP_M_LSB_DATA_SHIFT); 731 regmap_write(cs43130->regmap, CS43130_XSP_DEN_2, 732 (clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >> 733 CS43130_SP_M_MSB_DATA_SHIFT); 734 regmap_write(cs43130->regmap, CS43130_XSP_NUM_1, 735 (clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >> 736 CS43130_SP_N_LSB_DATA_SHIFT); 737 regmap_write(cs43130->regmap, CS43130_XSP_NUM_2, 738 (clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >> 739 CS43130_SP_N_MSB_DATA_SHIFT); 740 break; 741 default: 742 return -EINVAL; 743 } 744 745 return 0; 746 } 747 748 static int cs43130_pcm_dsd_mix(bool en, struct regmap *regmap) 749 { 750 if (en) { 751 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL, 752 CS43130_MIX_PCM_PREP_MASK, 753 1 << CS43130_MIX_PCM_PREP_SHIFT); 754 usleep_range(6000, 6050); 755 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL, 756 CS43130_MIX_PCM_DSD_MASK, 757 1 << CS43130_MIX_PCM_DSD_SHIFT); 758 } else { 759 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL, 760 CS43130_MIX_PCM_DSD_MASK, 761 0 << CS43130_MIX_PCM_DSD_SHIFT); 762 usleep_range(1600, 1650); 763 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL, 764 CS43130_MIX_PCM_PREP_MASK, 765 0 << CS43130_MIX_PCM_PREP_SHIFT); 766 } 767 768 return 0; 769 } 770 771 static int cs43130_dsd_hw_params(struct snd_pcm_substream *substream, 772 struct snd_pcm_hw_params *params, 773 struct snd_soc_dai *dai) 774 { 775 struct snd_soc_component *component = dai->component; 776 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 777 unsigned int required_clk; 778 u8 dsd_speed; 779 780 mutex_lock(&cs43130->clk_mutex); 781 if (!cs43130->clk_req) { 782 /* no DAI is currently using clk */ 783 if (!(CS43130_MCLK_22M % params_rate(params))) 784 required_clk = CS43130_MCLK_22M; 785 else 786 required_clk = CS43130_MCLK_24M; 787 788 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk); 789 if (cs43130->pll_bypass) 790 cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT); 791 else 792 cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL); 793 } 794 795 cs43130->clk_req++; 796 if (cs43130->clk_req == 2) 797 cs43130_pcm_dsd_mix(true, cs43130->regmap); 798 mutex_unlock(&cs43130->clk_mutex); 799 800 switch (params_rate(params)) { 801 case 176400: 802 dsd_speed = 0; 803 break; 804 case 352800: 805 dsd_speed = 1; 806 break; 807 default: 808 dev_err(component->dev, "Rate(%u) not supported\n", 809 params_rate(params)); 810 return -EINVAL; 811 } 812 813 if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) 814 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG, 815 CS43130_DSD_MASTER, CS43130_DSD_MASTER); 816 else 817 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG, 818 CS43130_DSD_MASTER, 0); 819 820 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 821 CS43130_DSD_SPEED_MASK, 822 dsd_speed << CS43130_DSD_SPEED_SHIFT); 823 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 824 CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_DSD << 825 CS43130_DSD_SRC_SHIFT); 826 827 return 0; 828 } 829 830 static int cs43130_hw_params(struct snd_pcm_substream *substream, 831 struct snd_pcm_hw_params *params, 832 struct snd_soc_dai *dai) 833 { 834 struct snd_soc_component *component = dai->component; 835 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 836 const struct cs43130_rate_map *rate_map; 837 unsigned int sclk = cs43130->dais[dai->id].sclk; 838 unsigned int bitwidth_sclk; 839 unsigned int bitwidth_dai = (unsigned int)(params_width(params)); 840 unsigned int required_clk; 841 u8 dsd_speed; 842 843 mutex_lock(&cs43130->clk_mutex); 844 if (!cs43130->clk_req) { 845 /* no DAI is currently using clk */ 846 if (!(CS43130_MCLK_22M % params_rate(params))) 847 required_clk = CS43130_MCLK_22M; 848 else 849 required_clk = CS43130_MCLK_24M; 850 851 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk); 852 if (cs43130->pll_bypass) 853 cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT); 854 else 855 cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL); 856 } 857 858 cs43130->clk_req++; 859 if (cs43130->clk_req == 2) 860 cs43130_pcm_dsd_mix(true, cs43130->regmap); 861 mutex_unlock(&cs43130->clk_mutex); 862 863 switch (dai->id) { 864 case CS43130_ASP_DOP_DAI: 865 case CS43130_XSP_DOP_DAI: 866 /* DoP bitwidth is always 24-bit */ 867 bitwidth_dai = 24; 868 sclk = params_rate(params) * bitwidth_dai * 869 params_channels(params); 870 871 switch (params_rate(params)) { 872 case 176400: 873 dsd_speed = 0; 874 break; 875 case 352800: 876 dsd_speed = 1; 877 break; 878 default: 879 dev_err(component->dev, "Rate(%u) not supported\n", 880 params_rate(params)); 881 return -EINVAL; 882 } 883 884 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 885 CS43130_DSD_SPEED_MASK, 886 dsd_speed << CS43130_DSD_SPEED_SHIFT); 887 break; 888 case CS43130_ASP_PCM_DAI: 889 rate_map = cs43130_get_rate_table(params_rate(params)); 890 if (!rate_map) 891 return -EINVAL; 892 893 regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val); 894 break; 895 default: 896 dev_err(component->dev, "Invalid DAI (%d)\n", dai->id); 897 return -EINVAL; 898 } 899 900 switch (dai->id) { 901 case CS43130_ASP_DOP_DAI: 902 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 903 CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_ASP << 904 CS43130_DSD_SRC_SHIFT); 905 break; 906 case CS43130_XSP_DOP_DAI: 907 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 908 CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_XSP << 909 CS43130_DSD_SRC_SHIFT); 910 break; 911 } 912 913 if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) 914 /* Calculate SCLK in master mode if unassigned */ 915 sclk = params_rate(params) * bitwidth_dai * 916 params_channels(params); 917 918 if (!sclk) { 919 /* at this point, SCLK must be set */ 920 dev_err(component->dev, "SCLK freq is not set\n"); 921 return -EINVAL; 922 } 923 924 bitwidth_sclk = (sclk / params_rate(params)) / params_channels(params); 925 if (bitwidth_sclk < bitwidth_dai) { 926 dev_err(component->dev, "Format not supported: SCLK freq is too low\n"); 927 return -EINVAL; 928 } 929 930 dev_dbg(component->dev, 931 "sclk = %u, fs = %d, bitwidth_dai = %u\n", 932 sclk, params_rate(params), bitwidth_dai); 933 934 dev_dbg(component->dev, 935 "bitwidth_sclk = %u, num_ch = %u\n", 936 bitwidth_sclk, params_channels(params)); 937 938 cs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap); 939 cs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130); 940 941 return 0; 942 } 943 944 static int cs43130_hw_free(struct snd_pcm_substream *substream, 945 struct snd_soc_dai *dai) 946 { 947 struct snd_soc_component *component = dai->component; 948 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 949 950 mutex_lock(&cs43130->clk_mutex); 951 cs43130->clk_req--; 952 if (!cs43130->clk_req) { 953 /* no DAI is currently using clk */ 954 cs43130_change_clksrc(component, CS43130_MCLK_SRC_RCO); 955 cs43130_pcm_dsd_mix(false, cs43130->regmap); 956 } 957 mutex_unlock(&cs43130->clk_mutex); 958 959 return 0; 960 } 961 962 static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1); 963 964 static const char * const pcm_ch_text[] = { 965 "Left-Right Ch", 966 "Left-Left Ch", 967 "Right-Left Ch", 968 "Right-Right Ch", 969 }; 970 971 static const struct reg_sequence pcm_ch_en_seq[] = { 972 {CS43130_DXD1, 0x99}, 973 {0x180005, 0x8C}, 974 {0x180007, 0xAB}, 975 {0x180015, 0x31}, 976 {0x180017, 0xB2}, 977 {0x180025, 0x30}, 978 {0x180027, 0x84}, 979 {0x180035, 0x9C}, 980 {0x180037, 0xAE}, 981 {0x18000D, 0x24}, 982 {0x18000F, 0xA3}, 983 {0x18001D, 0x05}, 984 {0x18001F, 0xD4}, 985 {0x18002D, 0x0B}, 986 {0x18002F, 0xC7}, 987 {0x18003D, 0x71}, 988 {0x18003F, 0xE7}, 989 {CS43130_DXD1, 0}, 990 }; 991 992 static const struct reg_sequence pcm_ch_dis_seq[] = { 993 {CS43130_DXD1, 0x99}, 994 {0x180005, 0x24}, 995 {0x180007, 0xA3}, 996 {0x180015, 0x05}, 997 {0x180017, 0xD4}, 998 {0x180025, 0x0B}, 999 {0x180027, 0xC7}, 1000 {0x180035, 0x71}, 1001 {0x180037, 0xE7}, 1002 {0x18000D, 0x8C}, 1003 {0x18000F, 0xAB}, 1004 {0x18001D, 0x31}, 1005 {0x18001F, 0xB2}, 1006 {0x18002D, 0x30}, 1007 {0x18002F, 0x84}, 1008 {0x18003D, 0x9C}, 1009 {0x18003F, 0xAE}, 1010 {CS43130_DXD1, 0}, 1011 }; 1012 1013 static int cs43130_pcm_ch_get(struct snd_kcontrol *kcontrol, 1014 struct snd_ctl_elem_value *ucontrol) 1015 { 1016 return snd_soc_get_enum_double(kcontrol, ucontrol); 1017 } 1018 1019 static int cs43130_pcm_ch_put(struct snd_kcontrol *kcontrol, 1020 struct snd_ctl_elem_value *ucontrol) 1021 { 1022 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1023 unsigned int *item = ucontrol->value.enumerated.item; 1024 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1025 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 1026 unsigned int val; 1027 1028 if (item[0] >= e->items) 1029 return -EINVAL; 1030 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 1031 1032 switch (cs43130->dev_id) { 1033 case CS43131_CHIP_ID: 1034 case CS43198_CHIP_ID: 1035 if (val >= 2) 1036 regmap_multi_reg_write(cs43130->regmap, pcm_ch_en_seq, 1037 ARRAY_SIZE(pcm_ch_en_seq)); 1038 else 1039 regmap_multi_reg_write(cs43130->regmap, pcm_ch_dis_seq, 1040 ARRAY_SIZE(pcm_ch_dis_seq)); 1041 break; 1042 } 1043 1044 return snd_soc_put_enum_double(kcontrol, ucontrol); 1045 } 1046 1047 static SOC_ENUM_SINGLE_DECL(pcm_ch_enum, CS43130_PCM_PATH_CTL_2, 0, 1048 pcm_ch_text); 1049 1050 static const char * const pcm_spd_texts[] = { 1051 "Fast", 1052 "Slow", 1053 }; 1054 1055 static SOC_ENUM_SINGLE_DECL(pcm_spd_enum, CS43130_PCM_FILT_OPT, 7, 1056 pcm_spd_texts); 1057 1058 static const char * const dsd_texts[] = { 1059 "Off", 1060 "BCKA Mode", 1061 "BCKD Mode", 1062 }; 1063 1064 static const unsigned int dsd_values[] = { 1065 CS43130_DSD_SRC_DSD, 1066 CS43130_DSD_SRC_ASP, 1067 CS43130_DSD_SRC_XSP, 1068 }; 1069 1070 static SOC_VALUE_ENUM_SINGLE_DECL(dsd_enum, CS43130_DSD_INT_CFG, 0, 0x03, 1071 dsd_texts, dsd_values); 1072 1073 static const struct snd_kcontrol_new cs43130_snd_controls[] = { 1074 SOC_DOUBLE_R_TLV("Master Playback Volume", 1075 CS43130_PCM_VOL_A, CS43130_PCM_VOL_B, 0, 0xFF, 1, 1076 pcm_vol_tlv), 1077 SOC_DOUBLE_R_TLV("Master DSD Playback Volume", 1078 CS43130_DSD_VOL_A, CS43130_DSD_VOL_B, 0, 0xFF, 1, 1079 pcm_vol_tlv), 1080 SOC_ENUM_EXT("PCM Ch Select", pcm_ch_enum, cs43130_pcm_ch_get, 1081 cs43130_pcm_ch_put), 1082 SOC_ENUM("PCM Filter Speed", pcm_spd_enum), 1083 SOC_SINGLE("PCM Phase Compensation", CS43130_PCM_FILT_OPT, 6, 1, 0), 1084 SOC_SINGLE("PCM Nonoversample Emulate", CS43130_PCM_FILT_OPT, 5, 1, 0), 1085 SOC_SINGLE("PCM High-pass Filter", CS43130_PCM_FILT_OPT, 1, 1, 0), 1086 SOC_SINGLE("PCM De-emphasis Filter", CS43130_PCM_FILT_OPT, 0, 1, 0), 1087 SOC_ENUM("DSD Phase Modulation", dsd_enum), 1088 }; 1089 1090 static const struct reg_sequence pcm_seq[] = { 1091 {CS43130_DXD1, 0x99}, 1092 {CS43130_DXD7, 0x01}, 1093 {CS43130_DXD8, 0}, 1094 {CS43130_DXD9, 0x01}, 1095 {CS43130_DXD3, 0x12}, 1096 {CS43130_DXD4, 0}, 1097 {CS43130_DXD10, 0x28}, 1098 {CS43130_DXD11, 0x28}, 1099 {CS43130_DXD1, 0}, 1100 }; 1101 1102 static const struct reg_sequence dsd_seq[] = { 1103 {CS43130_DXD1, 0x99}, 1104 {CS43130_DXD7, 0x01}, 1105 {CS43130_DXD8, 0}, 1106 {CS43130_DXD9, 0x01}, 1107 {CS43130_DXD3, 0x12}, 1108 {CS43130_DXD4, 0}, 1109 {CS43130_DXD10, 0x1E}, 1110 {CS43130_DXD11, 0x20}, 1111 {CS43130_DXD1, 0}, 1112 }; 1113 1114 static const struct reg_sequence pop_free_seq[] = { 1115 {CS43130_DXD1, 0x99}, 1116 {CS43130_DXD12, 0x0A}, 1117 {CS43130_DXD1, 0}, 1118 }; 1119 1120 static const struct reg_sequence pop_free_seq2[] = { 1121 {CS43130_DXD1, 0x99}, 1122 {CS43130_DXD13, 0x20}, 1123 {CS43130_DXD1, 0}, 1124 }; 1125 1126 static const struct reg_sequence mute_seq[] = { 1127 {CS43130_DXD1, 0x99}, 1128 {CS43130_DXD3, 0x12}, 1129 {CS43130_DXD5, 0x02}, 1130 {CS43130_DXD4, 0x12}, 1131 {CS43130_DXD1, 0}, 1132 }; 1133 1134 static const struct reg_sequence unmute_seq[] = { 1135 {CS43130_DXD1, 0x99}, 1136 {CS43130_DXD3, 0x10}, 1137 {CS43130_DXD5, 0}, 1138 {CS43130_DXD4, 0x16}, 1139 {CS43130_DXD1, 0}, 1140 }; 1141 1142 static int cs43130_dsd_event(struct snd_soc_dapm_widget *w, 1143 struct snd_kcontrol *kcontrol, int event) 1144 { 1145 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1146 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 1147 1148 switch (event) { 1149 case SND_SOC_DAPM_PRE_PMU: 1150 switch (cs43130->dev_id) { 1151 case CS43130_CHIP_ID: 1152 case CS4399_CHIP_ID: 1153 regmap_multi_reg_write(cs43130->regmap, dsd_seq, 1154 ARRAY_SIZE(dsd_seq)); 1155 break; 1156 } 1157 break; 1158 case SND_SOC_DAPM_POST_PMU: 1159 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_1, 1160 CS43130_MUTE_MASK, 0); 1161 switch (cs43130->dev_id) { 1162 case CS43130_CHIP_ID: 1163 case CS4399_CHIP_ID: 1164 regmap_multi_reg_write(cs43130->regmap, unmute_seq, 1165 ARRAY_SIZE(unmute_seq)); 1166 break; 1167 } 1168 break; 1169 case SND_SOC_DAPM_PRE_PMD: 1170 switch (cs43130->dev_id) { 1171 case CS43130_CHIP_ID: 1172 case CS4399_CHIP_ID: 1173 regmap_multi_reg_write(cs43130->regmap, mute_seq, 1174 ARRAY_SIZE(mute_seq)); 1175 regmap_update_bits(cs43130->regmap, 1176 CS43130_DSD_PATH_CTL_1, 1177 CS43130_MUTE_MASK, CS43130_MUTE_EN); 1178 /* 1179 * DSD Power Down Sequence 1180 * According to Design, 130ms is preferred. 1181 */ 1182 msleep(130); 1183 break; 1184 case CS43131_CHIP_ID: 1185 case CS43198_CHIP_ID: 1186 regmap_update_bits(cs43130->regmap, 1187 CS43130_DSD_PATH_CTL_1, 1188 CS43130_MUTE_MASK, CS43130_MUTE_EN); 1189 break; 1190 } 1191 break; 1192 default: 1193 dev_err(component->dev, "Invalid event = 0x%x\n", event); 1194 return -EINVAL; 1195 } 1196 return 0; 1197 } 1198 1199 static int cs43130_pcm_event(struct snd_soc_dapm_widget *w, 1200 struct snd_kcontrol *kcontrol, int event) 1201 { 1202 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1203 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 1204 1205 switch (event) { 1206 case SND_SOC_DAPM_PRE_PMU: 1207 switch (cs43130->dev_id) { 1208 case CS43130_CHIP_ID: 1209 case CS4399_CHIP_ID: 1210 regmap_multi_reg_write(cs43130->regmap, pcm_seq, 1211 ARRAY_SIZE(pcm_seq)); 1212 break; 1213 } 1214 break; 1215 case SND_SOC_DAPM_POST_PMU: 1216 regmap_update_bits(cs43130->regmap, CS43130_PCM_PATH_CTL_1, 1217 CS43130_MUTE_MASK, 0); 1218 switch (cs43130->dev_id) { 1219 case CS43130_CHIP_ID: 1220 case CS4399_CHIP_ID: 1221 regmap_multi_reg_write(cs43130->regmap, unmute_seq, 1222 ARRAY_SIZE(unmute_seq)); 1223 break; 1224 } 1225 break; 1226 case SND_SOC_DAPM_PRE_PMD: 1227 switch (cs43130->dev_id) { 1228 case CS43130_CHIP_ID: 1229 case CS4399_CHIP_ID: 1230 regmap_multi_reg_write(cs43130->regmap, mute_seq, 1231 ARRAY_SIZE(mute_seq)); 1232 regmap_update_bits(cs43130->regmap, 1233 CS43130_PCM_PATH_CTL_1, 1234 CS43130_MUTE_MASK, CS43130_MUTE_EN); 1235 /* 1236 * PCM Power Down Sequence 1237 * According to Design, 130ms is preferred. 1238 */ 1239 msleep(130); 1240 break; 1241 case CS43131_CHIP_ID: 1242 case CS43198_CHIP_ID: 1243 regmap_update_bits(cs43130->regmap, 1244 CS43130_PCM_PATH_CTL_1, 1245 CS43130_MUTE_MASK, CS43130_MUTE_EN); 1246 break; 1247 } 1248 break; 1249 default: 1250 dev_err(component->dev, "Invalid event = 0x%x\n", event); 1251 return -EINVAL; 1252 } 1253 return 0; 1254 } 1255 1256 static const struct reg_sequence dac_postpmu_seq[] = { 1257 {CS43130_DXD9, 0x0C}, 1258 {CS43130_DXD3, 0x10}, 1259 {CS43130_DXD4, 0x20}, 1260 }; 1261 1262 static const struct reg_sequence dac_postpmd_seq[] = { 1263 {CS43130_DXD1, 0x99}, 1264 {CS43130_DXD6, 0x01}, 1265 {CS43130_DXD1, 0}, 1266 }; 1267 1268 static int cs43130_dac_event(struct snd_soc_dapm_widget *w, 1269 struct snd_kcontrol *kcontrol, int event) 1270 { 1271 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1272 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 1273 1274 switch (event) { 1275 case SND_SOC_DAPM_PRE_PMU: 1276 switch (cs43130->dev_id) { 1277 case CS43130_CHIP_ID: 1278 case CS4399_CHIP_ID: 1279 regmap_multi_reg_write(cs43130->regmap, pop_free_seq, 1280 ARRAY_SIZE(pop_free_seq)); 1281 break; 1282 case CS43131_CHIP_ID: 1283 case CS43198_CHIP_ID: 1284 regmap_multi_reg_write(cs43130->regmap, pop_free_seq2, 1285 ARRAY_SIZE(pop_free_seq2)); 1286 break; 1287 } 1288 break; 1289 case SND_SOC_DAPM_POST_PMU: 1290 usleep_range(10000, 10050); 1291 1292 regmap_write(cs43130->regmap, CS43130_DXD1, 0x99); 1293 1294 switch (cs43130->dev_id) { 1295 case CS43130_CHIP_ID: 1296 case CS4399_CHIP_ID: 1297 regmap_multi_reg_write(cs43130->regmap, dac_postpmu_seq, 1298 ARRAY_SIZE(dac_postpmu_seq)); 1299 /* 1300 * Per datasheet, Sec. PCM Power-Up Sequence. 1301 * According to Design, CS43130_DXD12 must be 0 to meet 1302 * THDN and Dynamic Range spec. 1303 */ 1304 msleep(1000); 1305 regmap_write(cs43130->regmap, CS43130_DXD12, 0); 1306 break; 1307 case CS43131_CHIP_ID: 1308 case CS43198_CHIP_ID: 1309 usleep_range(12000, 12010); 1310 regmap_write(cs43130->regmap, CS43130_DXD13, 0); 1311 break; 1312 } 1313 1314 regmap_write(cs43130->regmap, CS43130_DXD1, 0); 1315 break; 1316 case SND_SOC_DAPM_POST_PMD: 1317 switch (cs43130->dev_id) { 1318 case CS43130_CHIP_ID: 1319 case CS4399_CHIP_ID: 1320 regmap_multi_reg_write(cs43130->regmap, dac_postpmd_seq, 1321 ARRAY_SIZE(dac_postpmd_seq)); 1322 break; 1323 } 1324 break; 1325 default: 1326 dev_err(component->dev, "Invalid DAC event = 0x%x\n", event); 1327 return -EINVAL; 1328 } 1329 return 0; 1330 } 1331 1332 static const struct reg_sequence hpin_prepmd_seq[] = { 1333 {CS43130_DXD1, 0x99}, 1334 {CS43130_DXD15, 0x64}, 1335 {CS43130_DXD14, 0}, 1336 {CS43130_DXD2, 0}, 1337 {CS43130_DXD1, 0}, 1338 }; 1339 1340 static const struct reg_sequence hpin_postpmu_seq[] = { 1341 {CS43130_DXD1, 0x99}, 1342 {CS43130_DXD2, 1}, 1343 {CS43130_DXD14, 0xDC}, 1344 {CS43130_DXD15, 0xE4}, 1345 {CS43130_DXD1, 0}, 1346 }; 1347 1348 static int cs43130_hpin_event(struct snd_soc_dapm_widget *w, 1349 struct snd_kcontrol *kcontrol, int event) 1350 { 1351 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1352 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 1353 1354 switch (event) { 1355 case SND_SOC_DAPM_POST_PMD: 1356 regmap_multi_reg_write(cs43130->regmap, hpin_prepmd_seq, 1357 ARRAY_SIZE(hpin_prepmd_seq)); 1358 break; 1359 case SND_SOC_DAPM_PRE_PMU: 1360 regmap_multi_reg_write(cs43130->regmap, hpin_postpmu_seq, 1361 ARRAY_SIZE(hpin_postpmu_seq)); 1362 break; 1363 default: 1364 dev_err(component->dev, "Invalid HPIN event = 0x%x\n", event); 1365 return -EINVAL; 1366 } 1367 return 0; 1368 } 1369 1370 static const struct snd_soc_dapm_widget digital_hp_widgets[] = { 1371 SND_SOC_DAPM_OUTPUT("HPOUTA"), 1372 SND_SOC_DAPM_OUTPUT("HPOUTB"), 1373 1374 SND_SOC_DAPM_AIF_IN_E("ASPIN PCM", NULL, 0, CS43130_PWDN_CTL, 1375 CS43130_PDN_ASP_SHIFT, 1, cs43130_pcm_event, 1376 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1377 SND_SOC_DAPM_PRE_PMD)), 1378 1379 SND_SOC_DAPM_AIF_IN_E("ASPIN DoP", NULL, 0, CS43130_PWDN_CTL, 1380 CS43130_PDN_ASP_SHIFT, 1, cs43130_dsd_event, 1381 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1382 SND_SOC_DAPM_PRE_PMD)), 1383 1384 SND_SOC_DAPM_AIF_IN_E("XSPIN DoP", NULL, 0, CS43130_PWDN_CTL, 1385 CS43130_PDN_XSP_SHIFT, 1, cs43130_dsd_event, 1386 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1387 SND_SOC_DAPM_PRE_PMD)), 1388 1389 SND_SOC_DAPM_AIF_IN_E("XSPIN DSD", NULL, 0, CS43130_PWDN_CTL, 1390 CS43130_PDN_DSDIF_SHIFT, 1, cs43130_dsd_event, 1391 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1392 SND_SOC_DAPM_PRE_PMD)), 1393 1394 SND_SOC_DAPM_DAC("DSD", NULL, CS43130_DSD_PATH_CTL_2, 1395 CS43130_DSD_EN_SHIFT, 0), 1396 1397 SND_SOC_DAPM_DAC_E("HiFi DAC", NULL, CS43130_PWDN_CTL, 1398 CS43130_PDN_HP_SHIFT, 1, cs43130_dac_event, 1399 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1400 SND_SOC_DAPM_POST_PMD)), 1401 }; 1402 1403 static const struct snd_soc_dapm_widget analog_hp_widgets[] = { 1404 SND_SOC_DAPM_DAC_E("Analog Playback", NULL, CS43130_HP_OUT_CTL_1, 1405 CS43130_HP_IN_EN_SHIFT, 0, cs43130_hpin_event, 1406 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)), 1407 }; 1408 1409 static struct snd_soc_dapm_widget all_hp_widgets[ 1410 ARRAY_SIZE(digital_hp_widgets) + 1411 ARRAY_SIZE(analog_hp_widgets)]; 1412 1413 static const struct snd_soc_dapm_route digital_hp_routes[] = { 1414 {"ASPIN PCM", NULL, "ASP PCM Playback"}, 1415 {"ASPIN DoP", NULL, "ASP DoP Playback"}, 1416 {"XSPIN DoP", NULL, "XSP DoP Playback"}, 1417 {"XSPIN DSD", NULL, "XSP DSD Playback"}, 1418 {"DSD", NULL, "ASPIN DoP"}, 1419 {"DSD", NULL, "XSPIN DoP"}, 1420 {"DSD", NULL, "XSPIN DSD"}, 1421 {"HiFi DAC", NULL, "ASPIN PCM"}, 1422 {"HiFi DAC", NULL, "DSD"}, 1423 {"HPOUTA", NULL, "HiFi DAC"}, 1424 {"HPOUTB", NULL, "HiFi DAC"}, 1425 }; 1426 1427 static const struct snd_soc_dapm_route analog_hp_routes[] = { 1428 {"HPOUTA", NULL, "Analog Playback"}, 1429 {"HPOUTB", NULL, "Analog Playback"}, 1430 }; 1431 1432 static struct snd_soc_dapm_route all_hp_routes[ 1433 ARRAY_SIZE(digital_hp_routes) + 1434 ARRAY_SIZE(analog_hp_routes)]; 1435 1436 static const unsigned int cs43130_asp_src_rates[] = { 1437 32000, 44100, 48000, 88200, 96000, 176400, 192000, 352800, 384000 1438 }; 1439 1440 static const struct snd_pcm_hw_constraint_list cs43130_asp_constraints = { 1441 .count = ARRAY_SIZE(cs43130_asp_src_rates), 1442 .list = cs43130_asp_src_rates, 1443 }; 1444 1445 static int cs43130_pcm_startup(struct snd_pcm_substream *substream, 1446 struct snd_soc_dai *dai) 1447 { 1448 return snd_pcm_hw_constraint_list(substream->runtime, 0, 1449 SNDRV_PCM_HW_PARAM_RATE, 1450 &cs43130_asp_constraints); 1451 } 1452 1453 static const unsigned int cs43130_dop_src_rates[] = { 1454 176400, 352800, 1455 }; 1456 1457 static const struct snd_pcm_hw_constraint_list cs43130_dop_constraints = { 1458 .count = ARRAY_SIZE(cs43130_dop_src_rates), 1459 .list = cs43130_dop_src_rates, 1460 }; 1461 1462 static int cs43130_dop_startup(struct snd_pcm_substream *substream, 1463 struct snd_soc_dai *dai) 1464 { 1465 return snd_pcm_hw_constraint_list(substream->runtime, 0, 1466 SNDRV_PCM_HW_PARAM_RATE, 1467 &cs43130_dop_constraints); 1468 } 1469 1470 static int cs43130_pcm_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1471 { 1472 struct snd_soc_component *component = codec_dai->component; 1473 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 1474 1475 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1476 case SND_SOC_DAIFMT_CBS_CFS: 1477 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS; 1478 break; 1479 case SND_SOC_DAIFMT_CBM_CFM: 1480 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM; 1481 break; 1482 default: 1483 dev_err(component->dev, "unsupported mode\n"); 1484 return -EINVAL; 1485 } 1486 1487 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1488 case SND_SOC_DAIFMT_I2S: 1489 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S; 1490 break; 1491 case SND_SOC_DAIFMT_LEFT_J: 1492 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J; 1493 break; 1494 case SND_SOC_DAIFMT_DSP_A: 1495 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_A; 1496 break; 1497 case SND_SOC_DAIFMT_DSP_B: 1498 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_B; 1499 break; 1500 default: 1501 dev_err(component->dev, 1502 "unsupported audio format\n"); 1503 return -EINVAL; 1504 } 1505 1506 dev_dbg(component->dev, "dai_id = %d, dai_mode = %u, dai_format = %u\n", 1507 codec_dai->id, 1508 cs43130->dais[codec_dai->id].dai_mode, 1509 cs43130->dais[codec_dai->id].dai_format); 1510 1511 return 0; 1512 } 1513 1514 static int cs43130_dsd_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1515 { 1516 struct snd_soc_component *component = codec_dai->component; 1517 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 1518 1519 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1520 case SND_SOC_DAIFMT_CBS_CFS: 1521 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS; 1522 break; 1523 case SND_SOC_DAIFMT_CBM_CFM: 1524 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM; 1525 break; 1526 default: 1527 dev_err(component->dev, "Unsupported DAI format.\n"); 1528 return -EINVAL; 1529 } 1530 1531 dev_dbg(component->dev, "dai_mode = 0x%x\n", 1532 cs43130->dais[codec_dai->id].dai_mode); 1533 1534 return 0; 1535 } 1536 1537 static int cs43130_set_sysclk(struct snd_soc_dai *codec_dai, 1538 int clk_id, unsigned int freq, int dir) 1539 { 1540 struct snd_soc_component *component = codec_dai->component; 1541 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 1542 1543 cs43130->dais[codec_dai->id].sclk = freq; 1544 dev_dbg(component->dev, "dai_id = %d, sclk = %u\n", codec_dai->id, 1545 cs43130->dais[codec_dai->id].sclk); 1546 1547 return 0; 1548 } 1549 1550 static const struct snd_soc_dai_ops cs43130_pcm_ops = { 1551 .startup = cs43130_pcm_startup, 1552 .hw_params = cs43130_hw_params, 1553 .hw_free = cs43130_hw_free, 1554 .set_sysclk = cs43130_set_sysclk, 1555 .set_fmt = cs43130_pcm_set_fmt, 1556 }; 1557 1558 static const struct snd_soc_dai_ops cs43130_dop_ops = { 1559 .startup = cs43130_dop_startup, 1560 .hw_params = cs43130_hw_params, 1561 .hw_free = cs43130_hw_free, 1562 .set_sysclk = cs43130_set_sysclk, 1563 .set_fmt = cs43130_pcm_set_fmt, 1564 }; 1565 1566 static const struct snd_soc_dai_ops cs43130_dsd_ops = { 1567 .startup = cs43130_dop_startup, 1568 .hw_params = cs43130_dsd_hw_params, 1569 .hw_free = cs43130_hw_free, 1570 .set_fmt = cs43130_dsd_set_fmt, 1571 }; 1572 1573 static struct snd_soc_dai_driver cs43130_dai[] = { 1574 { 1575 .name = "cs43130-asp-pcm", 1576 .id = CS43130_ASP_PCM_DAI, 1577 .playback = { 1578 .stream_name = "ASP PCM Playback", 1579 .channels_min = 1, 1580 .channels_max = 2, 1581 .rates = SNDRV_PCM_RATE_KNOT, 1582 .formats = CS43130_PCM_FORMATS, 1583 }, 1584 .ops = &cs43130_pcm_ops, 1585 .symmetric_rate = 1, 1586 }, 1587 { 1588 .name = "cs43130-asp-dop", 1589 .id = CS43130_ASP_DOP_DAI, 1590 .playback = { 1591 .stream_name = "ASP DoP Playback", 1592 .channels_min = 1, 1593 .channels_max = 2, 1594 .rates = SNDRV_PCM_RATE_KNOT, 1595 .formats = CS43130_DOP_FORMATS, 1596 }, 1597 .ops = &cs43130_dop_ops, 1598 .symmetric_rate = 1, 1599 }, 1600 { 1601 .name = "cs43130-xsp-dop", 1602 .id = CS43130_XSP_DOP_DAI, 1603 .playback = { 1604 .stream_name = "XSP DoP Playback", 1605 .channels_min = 1, 1606 .channels_max = 2, 1607 .rates = SNDRV_PCM_RATE_KNOT, 1608 .formats = CS43130_DOP_FORMATS, 1609 }, 1610 .ops = &cs43130_dop_ops, 1611 .symmetric_rate = 1, 1612 }, 1613 { 1614 .name = "cs43130-xsp-dsd", 1615 .id = CS43130_XSP_DSD_DAI, 1616 .playback = { 1617 .stream_name = "XSP DSD Playback", 1618 .channels_min = 1, 1619 .channels_max = 2, 1620 .rates = SNDRV_PCM_RATE_KNOT, 1621 .formats = CS43130_DOP_FORMATS, 1622 }, 1623 .ops = &cs43130_dsd_ops, 1624 }, 1625 1626 }; 1627 1628 static int cs43130_component_set_sysclk(struct snd_soc_component *component, 1629 int clk_id, int source, unsigned int freq, 1630 int dir) 1631 { 1632 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 1633 1634 dev_dbg(component->dev, "clk_id = %d, source = %d, freq = %d, dir = %d\n", 1635 clk_id, source, freq, dir); 1636 1637 switch (freq) { 1638 case CS43130_MCLK_22M: 1639 case CS43130_MCLK_24M: 1640 cs43130->mclk = freq; 1641 break; 1642 default: 1643 dev_err(component->dev, "Invalid MCLK INT freq: %u\n", freq); 1644 return -EINVAL; 1645 } 1646 1647 if (source == CS43130_MCLK_SRC_EXT) { 1648 cs43130->pll_bypass = true; 1649 } else { 1650 dev_err(component->dev, "Invalid MCLK source\n"); 1651 return -EINVAL; 1652 } 1653 1654 return 0; 1655 } 1656 1657 static inline u16 cs43130_get_ac_reg_val(u16 ac_freq) 1658 { 1659 /* AC freq is counted in 5.94Hz step. */ 1660 return ac_freq / 6; 1661 } 1662 1663 static int cs43130_show_dc(struct device *dev, char *buf, u8 ch) 1664 { 1665 struct i2c_client *client = to_i2c_client(dev); 1666 struct cs43130_private *cs43130 = i2c_get_clientdata(client); 1667 1668 if (!cs43130->hpload_done) 1669 return scnprintf(buf, PAGE_SIZE, "NO_HPLOAD\n"); 1670 else 1671 return scnprintf(buf, PAGE_SIZE, "%u\n", 1672 cs43130->hpload_dc[ch]); 1673 } 1674 1675 static ssize_t hpload_dc_l_show(struct device *dev, 1676 struct device_attribute *attr, char *buf) 1677 { 1678 return cs43130_show_dc(dev, buf, HP_LEFT); 1679 } 1680 1681 static ssize_t hpload_dc_r_show(struct device *dev, 1682 struct device_attribute *attr, char *buf) 1683 { 1684 return cs43130_show_dc(dev, buf, HP_RIGHT); 1685 } 1686 1687 static u16 const cs43130_ac_freq[CS43130_AC_FREQ] = { 1688 24, 1689 43, 1690 93, 1691 200, 1692 431, 1693 928, 1694 2000, 1695 4309, 1696 9283, 1697 20000, 1698 }; 1699 1700 static int cs43130_show_ac(struct device *dev, char *buf, u8 ch) 1701 { 1702 int i, j = 0, tmp; 1703 struct i2c_client *client = to_i2c_client(dev); 1704 struct cs43130_private *cs43130 = i2c_get_clientdata(client); 1705 1706 if (cs43130->hpload_done && cs43130->ac_meas) { 1707 for (i = 0; i < ARRAY_SIZE(cs43130_ac_freq); i++) { 1708 tmp = scnprintf(buf + j, PAGE_SIZE - j, "%u\n", 1709 cs43130->hpload_ac[i][ch]); 1710 if (!tmp) 1711 break; 1712 1713 j += tmp; 1714 } 1715 1716 return j; 1717 } else { 1718 return scnprintf(buf, PAGE_SIZE, "NO_HPLOAD\n"); 1719 } 1720 } 1721 1722 static ssize_t hpload_ac_l_show(struct device *dev, 1723 struct device_attribute *attr, char *buf) 1724 { 1725 return cs43130_show_ac(dev, buf, HP_LEFT); 1726 } 1727 1728 static ssize_t hpload_ac_r_show(struct device *dev, 1729 struct device_attribute *attr, char *buf) 1730 { 1731 return cs43130_show_ac(dev, buf, HP_RIGHT); 1732 } 1733 1734 static DEVICE_ATTR_RO(hpload_dc_l); 1735 static DEVICE_ATTR_RO(hpload_dc_r); 1736 static DEVICE_ATTR_RO(hpload_ac_l); 1737 static DEVICE_ATTR_RO(hpload_ac_r); 1738 1739 static struct attribute *hpload_attrs[] = { 1740 &dev_attr_hpload_dc_l.attr, 1741 &dev_attr_hpload_dc_r.attr, 1742 &dev_attr_hpload_ac_l.attr, 1743 &dev_attr_hpload_ac_r.attr, 1744 }; 1745 ATTRIBUTE_GROUPS(hpload); 1746 1747 static struct reg_sequence hp_en_cal_seq[] = { 1748 {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL}, 1749 {CS43130_HP_MEAS_LOAD_1, 0}, 1750 {CS43130_HP_MEAS_LOAD_2, 0}, 1751 {CS43130_INT_MASK_4, 0}, 1752 {CS43130_DXD1, 0x99}, 1753 {CS43130_DXD16, 0xBB}, 1754 {CS43130_DXD12, 0x01}, 1755 {CS43130_DXD19, 0xCB}, 1756 {CS43130_DXD17, 0x95}, 1757 {CS43130_DXD18, 0x0B}, 1758 {CS43130_DXD1, 0}, 1759 {CS43130_HP_LOAD_1, 0x80}, 1760 }; 1761 1762 static struct reg_sequence hp_en_cal_seq2[] = { 1763 {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL}, 1764 {CS43130_HP_MEAS_LOAD_1, 0}, 1765 {CS43130_HP_MEAS_LOAD_2, 0}, 1766 {CS43130_INT_MASK_4, 0}, 1767 {CS43130_HP_LOAD_1, 0x80}, 1768 }; 1769 1770 static struct reg_sequence hp_dis_cal_seq[] = { 1771 {CS43130_HP_LOAD_1, 0x80}, 1772 {CS43130_DXD1, 0x99}, 1773 {CS43130_DXD12, 0}, 1774 {CS43130_DXD1, 0}, 1775 {CS43130_HP_LOAD_1, 0}, 1776 }; 1777 1778 static struct reg_sequence hp_dis_cal_seq2[] = { 1779 {CS43130_HP_LOAD_1, 0x80}, 1780 {CS43130_HP_LOAD_1, 0}, 1781 }; 1782 1783 static struct reg_sequence hp_dc_ch_l_seq[] = { 1784 {CS43130_DXD1, 0x99}, 1785 {CS43130_DXD19, 0x0A}, 1786 {CS43130_DXD17, 0x93}, 1787 {CS43130_DXD18, 0x0A}, 1788 {CS43130_DXD1, 0}, 1789 {CS43130_HP_LOAD_1, 0x80}, 1790 {CS43130_HP_LOAD_1, 0x81}, 1791 }; 1792 1793 static struct reg_sequence hp_dc_ch_l_seq2[] = { 1794 {CS43130_HP_LOAD_1, 0x80}, 1795 {CS43130_HP_LOAD_1, 0x81}, 1796 }; 1797 1798 static struct reg_sequence hp_dc_ch_r_seq[] = { 1799 {CS43130_DXD1, 0x99}, 1800 {CS43130_DXD19, 0x8A}, 1801 {CS43130_DXD17, 0x15}, 1802 {CS43130_DXD18, 0x06}, 1803 {CS43130_DXD1, 0}, 1804 {CS43130_HP_LOAD_1, 0x90}, 1805 {CS43130_HP_LOAD_1, 0x91}, 1806 }; 1807 1808 static struct reg_sequence hp_dc_ch_r_seq2[] = { 1809 {CS43130_HP_LOAD_1, 0x90}, 1810 {CS43130_HP_LOAD_1, 0x91}, 1811 }; 1812 1813 static struct reg_sequence hp_ac_ch_l_seq[] = { 1814 {CS43130_DXD1, 0x99}, 1815 {CS43130_DXD19, 0x0A}, 1816 {CS43130_DXD17, 0x93}, 1817 {CS43130_DXD18, 0x0A}, 1818 {CS43130_DXD1, 0}, 1819 {CS43130_HP_LOAD_1, 0x80}, 1820 {CS43130_HP_LOAD_1, 0x82}, 1821 }; 1822 1823 static struct reg_sequence hp_ac_ch_l_seq2[] = { 1824 {CS43130_HP_LOAD_1, 0x80}, 1825 {CS43130_HP_LOAD_1, 0x82}, 1826 }; 1827 1828 static struct reg_sequence hp_ac_ch_r_seq[] = { 1829 {CS43130_DXD1, 0x99}, 1830 {CS43130_DXD19, 0x8A}, 1831 {CS43130_DXD17, 0x15}, 1832 {CS43130_DXD18, 0x06}, 1833 {CS43130_DXD1, 0}, 1834 {CS43130_HP_LOAD_1, 0x90}, 1835 {CS43130_HP_LOAD_1, 0x92}, 1836 }; 1837 1838 static struct reg_sequence hp_ac_ch_r_seq2[] = { 1839 {CS43130_HP_LOAD_1, 0x90}, 1840 {CS43130_HP_LOAD_1, 0x92}, 1841 }; 1842 1843 static struct reg_sequence hp_cln_seq[] = { 1844 {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL}, 1845 {CS43130_HP_MEAS_LOAD_1, 0}, 1846 {CS43130_HP_MEAS_LOAD_2, 0}, 1847 }; 1848 1849 struct reg_sequences { 1850 struct reg_sequence *seq; 1851 int size; 1852 unsigned int msk; 1853 }; 1854 1855 static struct reg_sequences hpload_seq1[] = { 1856 { 1857 .seq = hp_en_cal_seq, 1858 .size = ARRAY_SIZE(hp_en_cal_seq), 1859 .msk = CS43130_HPLOAD_ON_INT, 1860 }, 1861 { 1862 .seq = hp_dc_ch_l_seq, 1863 .size = ARRAY_SIZE(hp_dc_ch_l_seq), 1864 .msk = CS43130_HPLOAD_DC_INT, 1865 }, 1866 { 1867 .seq = hp_ac_ch_l_seq, 1868 .size = ARRAY_SIZE(hp_ac_ch_l_seq), 1869 .msk = CS43130_HPLOAD_AC_INT, 1870 }, 1871 { 1872 .seq = hp_dis_cal_seq, 1873 .size = ARRAY_SIZE(hp_dis_cal_seq), 1874 .msk = CS43130_HPLOAD_OFF_INT, 1875 }, 1876 { 1877 .seq = hp_en_cal_seq, 1878 .size = ARRAY_SIZE(hp_en_cal_seq), 1879 .msk = CS43130_HPLOAD_ON_INT, 1880 }, 1881 { 1882 .seq = hp_dc_ch_r_seq, 1883 .size = ARRAY_SIZE(hp_dc_ch_r_seq), 1884 .msk = CS43130_HPLOAD_DC_INT, 1885 }, 1886 { 1887 .seq = hp_ac_ch_r_seq, 1888 .size = ARRAY_SIZE(hp_ac_ch_r_seq), 1889 .msk = CS43130_HPLOAD_AC_INT, 1890 }, 1891 }; 1892 1893 static struct reg_sequences hpload_seq2[] = { 1894 { 1895 .seq = hp_en_cal_seq2, 1896 .size = ARRAY_SIZE(hp_en_cal_seq2), 1897 .msk = CS43130_HPLOAD_ON_INT, 1898 }, 1899 { 1900 .seq = hp_dc_ch_l_seq2, 1901 .size = ARRAY_SIZE(hp_dc_ch_l_seq2), 1902 .msk = CS43130_HPLOAD_DC_INT, 1903 }, 1904 { 1905 .seq = hp_ac_ch_l_seq2, 1906 .size = ARRAY_SIZE(hp_ac_ch_l_seq2), 1907 .msk = CS43130_HPLOAD_AC_INT, 1908 }, 1909 { 1910 .seq = hp_dis_cal_seq2, 1911 .size = ARRAY_SIZE(hp_dis_cal_seq2), 1912 .msk = CS43130_HPLOAD_OFF_INT, 1913 }, 1914 { 1915 .seq = hp_en_cal_seq2, 1916 .size = ARRAY_SIZE(hp_en_cal_seq2), 1917 .msk = CS43130_HPLOAD_ON_INT, 1918 }, 1919 { 1920 .seq = hp_dc_ch_r_seq2, 1921 .size = ARRAY_SIZE(hp_dc_ch_r_seq2), 1922 .msk = CS43130_HPLOAD_DC_INT, 1923 }, 1924 { 1925 .seq = hp_ac_ch_r_seq2, 1926 .size = ARRAY_SIZE(hp_ac_ch_r_seq2), 1927 .msk = CS43130_HPLOAD_AC_INT, 1928 }, 1929 }; 1930 1931 static int cs43130_update_hpload(unsigned int msk, int ac_idx, 1932 struct cs43130_private *cs43130) 1933 { 1934 bool left_ch = true; 1935 unsigned int reg; 1936 u32 addr; 1937 u16 impedance; 1938 struct snd_soc_component *component = cs43130->component; 1939 1940 switch (msk) { 1941 case CS43130_HPLOAD_DC_INT: 1942 case CS43130_HPLOAD_AC_INT: 1943 break; 1944 default: 1945 return 0; 1946 } 1947 1948 regmap_read(cs43130->regmap, CS43130_HP_LOAD_1, ®); 1949 if (reg & CS43130_HPLOAD_CHN_SEL) 1950 left_ch = false; 1951 1952 if (msk == CS43130_HPLOAD_DC_INT) 1953 addr = CS43130_HP_DC_STAT_1; 1954 else 1955 addr = CS43130_HP_AC_STAT_1; 1956 1957 regmap_read(cs43130->regmap, addr, ®); 1958 impedance = reg >> 3; 1959 regmap_read(cs43130->regmap, addr + 1, ®); 1960 impedance |= reg << 5; 1961 1962 if (msk == CS43130_HPLOAD_DC_INT) { 1963 if (left_ch) 1964 cs43130->hpload_dc[HP_LEFT] = impedance; 1965 else 1966 cs43130->hpload_dc[HP_RIGHT] = impedance; 1967 1968 dev_dbg(component->dev, "HP DC impedance (Ch %u): %u\n", !left_ch, 1969 impedance); 1970 } else { 1971 if (left_ch) 1972 cs43130->hpload_ac[ac_idx][HP_LEFT] = impedance; 1973 else 1974 cs43130->hpload_ac[ac_idx][HP_RIGHT] = impedance; 1975 1976 dev_dbg(component->dev, "HP AC (%u Hz) impedance (Ch %u): %u\n", 1977 cs43130->ac_freq[ac_idx], !left_ch, impedance); 1978 } 1979 1980 return 0; 1981 } 1982 1983 static int cs43130_hpload_proc(struct cs43130_private *cs43130, 1984 struct reg_sequence *seq, int seq_size, 1985 unsigned int rslt_msk, int ac_idx) 1986 { 1987 int ret; 1988 unsigned int msk; 1989 u16 ac_reg_val; 1990 struct snd_soc_component *component = cs43130->component; 1991 1992 reinit_completion(&cs43130->hpload_evt); 1993 1994 if (rslt_msk == CS43130_HPLOAD_AC_INT) { 1995 ac_reg_val = cs43130_get_ac_reg_val(cs43130->ac_freq[ac_idx]); 1996 regmap_update_bits(cs43130->regmap, CS43130_HP_LOAD_1, 1997 CS43130_HPLOAD_AC_START, 0); 1998 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_1, 1999 CS43130_HP_MEAS_LOAD_MASK, 2000 ac_reg_val >> CS43130_HP_MEAS_LOAD_1_SHIFT); 2001 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_2, 2002 CS43130_HP_MEAS_LOAD_MASK, 2003 ac_reg_val >> CS43130_HP_MEAS_LOAD_2_SHIFT); 2004 } 2005 2006 regmap_multi_reg_write(cs43130->regmap, seq, 2007 seq_size); 2008 2009 ret = wait_for_completion_timeout(&cs43130->hpload_evt, 2010 msecs_to_jiffies(1000)); 2011 regmap_read(cs43130->regmap, CS43130_INT_MASK_4, &msk); 2012 if (!ret) { 2013 dev_err(component->dev, "Timeout waiting for HPLOAD interrupt\n"); 2014 return -1; 2015 } 2016 2017 dev_dbg(component->dev, "HP load stat: %x, INT_MASK_4: %x\n", 2018 cs43130->hpload_stat, msk); 2019 if ((cs43130->hpload_stat & (CS43130_HPLOAD_NO_DC_INT | 2020 CS43130_HPLOAD_UNPLUG_INT | 2021 CS43130_HPLOAD_OOR_INT)) || 2022 !(cs43130->hpload_stat & rslt_msk)) { 2023 dev_dbg(component->dev, "HP load measure failed\n"); 2024 return -1; 2025 } 2026 2027 return 0; 2028 } 2029 2030 static const struct reg_sequence hv_seq[][2] = { 2031 { 2032 {CS43130_CLASS_H_CTL, 0x1C}, 2033 {CS43130_HP_OUT_CTL_1, 0x10}, 2034 }, 2035 { 2036 {CS43130_CLASS_H_CTL, 0x1E}, 2037 {CS43130_HP_OUT_CTL_1, 0x20}, 2038 }, 2039 { 2040 {CS43130_CLASS_H_CTL, 0x1E}, 2041 {CS43130_HP_OUT_CTL_1, 0x30}, 2042 }, 2043 }; 2044 2045 static int cs43130_set_hv(struct regmap *regmap, u16 hpload_dc, 2046 const u16 *dc_threshold) 2047 { 2048 int i; 2049 2050 for (i = 0; i < CS43130_DC_THRESHOLD; i++) { 2051 if (hpload_dc <= dc_threshold[i]) 2052 break; 2053 } 2054 2055 regmap_multi_reg_write(regmap, hv_seq[i], ARRAY_SIZE(hv_seq[i])); 2056 2057 return 0; 2058 } 2059 2060 static void cs43130_imp_meas(struct work_struct *wk) 2061 { 2062 unsigned int reg, seq_size; 2063 int i, ret, ac_idx; 2064 struct cs43130_private *cs43130; 2065 struct snd_soc_component *component; 2066 struct reg_sequences *hpload_seq; 2067 2068 cs43130 = container_of(wk, struct cs43130_private, work); 2069 component = cs43130->component; 2070 2071 if (!cs43130->mclk) 2072 return; 2073 2074 cs43130->hpload_done = false; 2075 2076 mutex_lock(&cs43130->clk_mutex); 2077 if (!cs43130->clk_req) { 2078 /* clk not in use */ 2079 cs43130_set_pll(component, 0, 0, cs43130->mclk, CS43130_MCLK_22M); 2080 if (cs43130->pll_bypass) 2081 cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT); 2082 else 2083 cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL); 2084 } 2085 2086 cs43130->clk_req++; 2087 mutex_unlock(&cs43130->clk_mutex); 2088 2089 regmap_read(cs43130->regmap, CS43130_INT_STATUS_4, ®); 2090 2091 switch (cs43130->dev_id) { 2092 case CS43130_CHIP_ID: 2093 hpload_seq = hpload_seq1; 2094 seq_size = ARRAY_SIZE(hpload_seq1); 2095 break; 2096 case CS43131_CHIP_ID: 2097 hpload_seq = hpload_seq2; 2098 seq_size = ARRAY_SIZE(hpload_seq2); 2099 break; 2100 default: 2101 WARN(1, "Invalid dev_id for meas: %d", cs43130->dev_id); 2102 return; 2103 } 2104 2105 i = 0; 2106 ac_idx = 0; 2107 while (i < seq_size) { 2108 ret = cs43130_hpload_proc(cs43130, hpload_seq[i].seq, 2109 hpload_seq[i].size, 2110 hpload_seq[i].msk, ac_idx); 2111 if (ret < 0) 2112 goto exit; 2113 2114 cs43130_update_hpload(hpload_seq[i].msk, ac_idx, cs43130); 2115 2116 if (cs43130->ac_meas && 2117 hpload_seq[i].msk == CS43130_HPLOAD_AC_INT && 2118 ac_idx < CS43130_AC_FREQ - 1) { 2119 ac_idx++; 2120 } else { 2121 ac_idx = 0; 2122 i++; 2123 } 2124 } 2125 cs43130->hpload_done = true; 2126 2127 if (cs43130->hpload_dc[HP_LEFT] >= CS43130_LINEOUT_LOAD) 2128 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_LINEOUT, 2129 CS43130_JACK_MASK); 2130 else 2131 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_HEADPHONE, 2132 CS43130_JACK_MASK); 2133 2134 dev_dbg(component->dev, "Set HP output control. DC threshold\n"); 2135 for (i = 0; i < CS43130_DC_THRESHOLD; i++) 2136 dev_dbg(component->dev, "DC threshold[%d]: %u.\n", i, 2137 cs43130->dc_threshold[i]); 2138 2139 cs43130_set_hv(cs43130->regmap, cs43130->hpload_dc[HP_LEFT], 2140 cs43130->dc_threshold); 2141 2142 exit: 2143 switch (cs43130->dev_id) { 2144 case CS43130_CHIP_ID: 2145 cs43130_hpload_proc(cs43130, hp_dis_cal_seq, 2146 ARRAY_SIZE(hp_dis_cal_seq), 2147 CS43130_HPLOAD_OFF_INT, ac_idx); 2148 break; 2149 case CS43131_CHIP_ID: 2150 cs43130_hpload_proc(cs43130, hp_dis_cal_seq2, 2151 ARRAY_SIZE(hp_dis_cal_seq2), 2152 CS43130_HPLOAD_OFF_INT, ac_idx); 2153 break; 2154 } 2155 2156 regmap_multi_reg_write(cs43130->regmap, hp_cln_seq, 2157 ARRAY_SIZE(hp_cln_seq)); 2158 2159 mutex_lock(&cs43130->clk_mutex); 2160 cs43130->clk_req--; 2161 /* clk not in use */ 2162 if (!cs43130->clk_req) 2163 cs43130_change_clksrc(component, CS43130_MCLK_SRC_RCO); 2164 mutex_unlock(&cs43130->clk_mutex); 2165 } 2166 2167 static irqreturn_t cs43130_irq_thread(int irq, void *data) 2168 { 2169 struct cs43130_private *cs43130 = (struct cs43130_private *)data; 2170 struct snd_soc_component *component = cs43130->component; 2171 unsigned int stickies[CS43130_NUM_INT]; 2172 unsigned int irq_occurrence = 0; 2173 unsigned int masks[CS43130_NUM_INT]; 2174 int i, j; 2175 2176 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 2177 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1 + i, 2178 &stickies[i]); 2179 regmap_read(cs43130->regmap, CS43130_INT_MASK_1 + i, 2180 &masks[i]); 2181 } 2182 2183 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 2184 stickies[i] = stickies[i] & (~masks[i]); 2185 for (j = 0; j < 8; j++) 2186 irq_occurrence += (stickies[i] >> j) & 1; 2187 } 2188 dev_dbg(component->dev, "number of interrupts occurred (%u)\n", 2189 irq_occurrence); 2190 2191 if (!irq_occurrence) 2192 return IRQ_NONE; 2193 2194 if (stickies[0] & CS43130_XTAL_RDY_INT) { 2195 complete(&cs43130->xtal_rdy); 2196 return IRQ_HANDLED; 2197 } 2198 2199 if (stickies[0] & CS43130_PLL_RDY_INT) { 2200 complete(&cs43130->pll_rdy); 2201 return IRQ_HANDLED; 2202 } 2203 2204 if (stickies[3] & CS43130_HPLOAD_NO_DC_INT) { 2205 cs43130->hpload_stat = stickies[3]; 2206 dev_err(component->dev, 2207 "DC load has not completed before AC load (%x)\n", 2208 cs43130->hpload_stat); 2209 complete(&cs43130->hpload_evt); 2210 return IRQ_HANDLED; 2211 } 2212 2213 if (stickies[3] & CS43130_HPLOAD_UNPLUG_INT) { 2214 cs43130->hpload_stat = stickies[3]; 2215 dev_err(component->dev, "HP unplugged during measurement (%x)\n", 2216 cs43130->hpload_stat); 2217 complete(&cs43130->hpload_evt); 2218 return IRQ_HANDLED; 2219 } 2220 2221 if (stickies[3] & CS43130_HPLOAD_OOR_INT) { 2222 cs43130->hpload_stat = stickies[3]; 2223 dev_err(component->dev, "HP load out of range (%x)\n", 2224 cs43130->hpload_stat); 2225 complete(&cs43130->hpload_evt); 2226 return IRQ_HANDLED; 2227 } 2228 2229 if (stickies[3] & CS43130_HPLOAD_AC_INT) { 2230 cs43130->hpload_stat = stickies[3]; 2231 dev_dbg(component->dev, "HP AC load measurement done (%x)\n", 2232 cs43130->hpload_stat); 2233 complete(&cs43130->hpload_evt); 2234 return IRQ_HANDLED; 2235 } 2236 2237 if (stickies[3] & CS43130_HPLOAD_DC_INT) { 2238 cs43130->hpload_stat = stickies[3]; 2239 dev_dbg(component->dev, "HP DC load measurement done (%x)\n", 2240 cs43130->hpload_stat); 2241 complete(&cs43130->hpload_evt); 2242 return IRQ_HANDLED; 2243 } 2244 2245 if (stickies[3] & CS43130_HPLOAD_ON_INT) { 2246 cs43130->hpload_stat = stickies[3]; 2247 dev_dbg(component->dev, "HP load state machine on done (%x)\n", 2248 cs43130->hpload_stat); 2249 complete(&cs43130->hpload_evt); 2250 return IRQ_HANDLED; 2251 } 2252 2253 if (stickies[3] & CS43130_HPLOAD_OFF_INT) { 2254 cs43130->hpload_stat = stickies[3]; 2255 dev_dbg(component->dev, "HP load state machine off done (%x)\n", 2256 cs43130->hpload_stat); 2257 complete(&cs43130->hpload_evt); 2258 return IRQ_HANDLED; 2259 } 2260 2261 if (stickies[0] & CS43130_XTAL_ERR_INT) { 2262 dev_err(component->dev, "Crystal err: clock is not running\n"); 2263 return IRQ_HANDLED; 2264 } 2265 2266 if (stickies[0] & CS43130_HP_UNPLUG_INT) { 2267 dev_dbg(component->dev, "HP unplugged\n"); 2268 cs43130->hpload_done = false; 2269 snd_soc_jack_report(&cs43130->jack, 0, CS43130_JACK_MASK); 2270 return IRQ_HANDLED; 2271 } 2272 2273 if (stickies[0] & CS43130_HP_PLUG_INT) { 2274 if (cs43130->dc_meas && !cs43130->hpload_done && 2275 !work_busy(&cs43130->work)) { 2276 dev_dbg(component->dev, "HP load queue work\n"); 2277 queue_work(cs43130->wq, &cs43130->work); 2278 } 2279 2280 snd_soc_jack_report(&cs43130->jack, SND_JACK_MECHANICAL, 2281 CS43130_JACK_MASK); 2282 return IRQ_HANDLED; 2283 } 2284 2285 return IRQ_NONE; 2286 } 2287 2288 static int cs43130_probe(struct snd_soc_component *component) 2289 { 2290 int ret; 2291 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component); 2292 struct snd_soc_card *card = component->card; 2293 unsigned int reg; 2294 2295 cs43130->component = component; 2296 2297 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) { 2298 regmap_update_bits(cs43130->regmap, CS43130_CRYSTAL_SET, 2299 CS43130_XTAL_IBIAS_MASK, 2300 cs43130->xtal_ibias); 2301 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2302 CS43130_XTAL_ERR_INT, 0); 2303 } 2304 2305 ret = snd_soc_card_jack_new(card, "Headphone", CS43130_JACK_MASK, 2306 &cs43130->jack); 2307 if (ret < 0) { 2308 dev_err(component->dev, "Cannot create jack\n"); 2309 return ret; 2310 } 2311 2312 cs43130->hpload_done = false; 2313 if (cs43130->dc_meas) { 2314 ret = sysfs_create_groups(&component->dev->kobj, hpload_groups); 2315 if (ret) 2316 return ret; 2317 2318 cs43130->wq = create_singlethread_workqueue("cs43130_hp"); 2319 if (!cs43130->wq) { 2320 sysfs_remove_groups(&component->dev->kobj, hpload_groups); 2321 return -ENOMEM; 2322 } 2323 INIT_WORK(&cs43130->work, cs43130_imp_meas); 2324 } 2325 2326 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, ®); 2327 regmap_read(cs43130->regmap, CS43130_HP_STATUS, ®); 2328 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2329 CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, 0); 2330 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT, 2331 CS43130_HP_DETECT_CTRL_MASK, 0); 2332 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT, 2333 CS43130_HP_DETECT_CTRL_MASK, 2334 CS43130_HP_DETECT_CTRL_MASK); 2335 2336 return 0; 2337 } 2338 2339 static struct snd_soc_component_driver soc_component_dev_cs43130 = { 2340 .probe = cs43130_probe, 2341 .controls = cs43130_snd_controls, 2342 .num_controls = ARRAY_SIZE(cs43130_snd_controls), 2343 .set_sysclk = cs43130_component_set_sysclk, 2344 .set_pll = cs43130_set_pll, 2345 .idle_bias_on = 1, 2346 .use_pmdown_time = 1, 2347 .endianness = 1, 2348 }; 2349 2350 static const struct regmap_config cs43130_regmap = { 2351 .reg_bits = 24, 2352 .pad_bits = 8, 2353 .val_bits = 8, 2354 2355 .max_register = CS43130_LASTREG, 2356 .reg_defaults = cs43130_reg_defaults, 2357 .num_reg_defaults = ARRAY_SIZE(cs43130_reg_defaults), 2358 .readable_reg = cs43130_readable_register, 2359 .precious_reg = cs43130_precious_register, 2360 .volatile_reg = cs43130_volatile_register, 2361 .cache_type = REGCACHE_RBTREE, 2362 /* needed for regcache_sync */ 2363 .use_single_read = true, 2364 .use_single_write = true, 2365 }; 2366 2367 static u16 const cs43130_dc_threshold[CS43130_DC_THRESHOLD] = { 2368 50, 2369 120, 2370 }; 2371 2372 static int cs43130_handle_device_data(struct i2c_client *i2c_client, 2373 struct cs43130_private *cs43130) 2374 { 2375 struct device_node *np = i2c_client->dev.of_node; 2376 unsigned int val; 2377 int i; 2378 2379 if (of_property_read_u32(np, "cirrus,xtal-ibias", &val) < 0) { 2380 /* Crystal is unused. System clock is used for external MCLK */ 2381 cs43130->xtal_ibias = CS43130_XTAL_UNUSED; 2382 return 0; 2383 } 2384 2385 switch (val) { 2386 case 1: 2387 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA; 2388 break; 2389 case 2: 2390 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA; 2391 break; 2392 case 3: 2393 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA; 2394 break; 2395 default: 2396 dev_err(&i2c_client->dev, 2397 "Invalid cirrus,xtal-ibias value: %d\n", val); 2398 return -EINVAL; 2399 } 2400 2401 cs43130->dc_meas = of_property_read_bool(np, "cirrus,dc-measure"); 2402 cs43130->ac_meas = of_property_read_bool(np, "cirrus,ac-measure"); 2403 2404 if (of_property_read_u16_array(np, "cirrus,ac-freq", cs43130->ac_freq, 2405 CS43130_AC_FREQ) < 0) { 2406 for (i = 0; i < CS43130_AC_FREQ; i++) 2407 cs43130->ac_freq[i] = cs43130_ac_freq[i]; 2408 } 2409 2410 if (of_property_read_u16_array(np, "cirrus,dc-threshold", 2411 cs43130->dc_threshold, 2412 CS43130_DC_THRESHOLD) < 0) { 2413 for (i = 0; i < CS43130_DC_THRESHOLD; i++) 2414 cs43130->dc_threshold[i] = cs43130_dc_threshold[i]; 2415 } 2416 2417 return 0; 2418 } 2419 2420 static int cs43130_i2c_probe(struct i2c_client *client) 2421 { 2422 struct cs43130_private *cs43130; 2423 int ret; 2424 unsigned int reg; 2425 int i, devid; 2426 2427 cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL); 2428 if (!cs43130) 2429 return -ENOMEM; 2430 2431 i2c_set_clientdata(client, cs43130); 2432 2433 cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap); 2434 if (IS_ERR(cs43130->regmap)) { 2435 ret = PTR_ERR(cs43130->regmap); 2436 return ret; 2437 } 2438 2439 if (client->dev.of_node) { 2440 ret = cs43130_handle_device_data(client, cs43130); 2441 if (ret != 0) 2442 return ret; 2443 } 2444 for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++) 2445 cs43130->supplies[i].supply = cs43130_supply_names[i]; 2446 2447 ret = devm_regulator_bulk_get(&client->dev, 2448 ARRAY_SIZE(cs43130->supplies), 2449 cs43130->supplies); 2450 if (ret != 0) { 2451 dev_err(&client->dev, "Failed to request supplies: %d\n", ret); 2452 return ret; 2453 } 2454 ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies), 2455 cs43130->supplies); 2456 if (ret != 0) { 2457 dev_err(&client->dev, "Failed to enable supplies: %d\n", ret); 2458 return ret; 2459 } 2460 2461 cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev, 2462 "reset", GPIOD_OUT_LOW); 2463 if (IS_ERR(cs43130->reset_gpio)) { 2464 ret = PTR_ERR(cs43130->reset_gpio); 2465 goto err_supplies; 2466 } 2467 2468 gpiod_set_value_cansleep(cs43130->reset_gpio, 1); 2469 2470 usleep_range(2000, 2050); 2471 2472 devid = cirrus_read_device_id(cs43130->regmap, CS43130_DEVID_AB); 2473 if (devid < 0) { 2474 ret = devid; 2475 dev_err(&client->dev, "Failed to read device ID: %d\n", ret); 2476 goto err; 2477 } 2478 2479 switch (devid) { 2480 case CS43130_CHIP_ID: 2481 case CS4399_CHIP_ID: 2482 case CS43131_CHIP_ID: 2483 case CS43198_CHIP_ID: 2484 break; 2485 default: 2486 dev_err(&client->dev, 2487 "CS43130 Device ID %X. Expected ID %X, %X, %X or %X\n", 2488 devid, CS43130_CHIP_ID, CS4399_CHIP_ID, 2489 CS43131_CHIP_ID, CS43198_CHIP_ID); 2490 ret = -ENODEV; 2491 goto err; 2492 } 2493 2494 cs43130->dev_id = devid; 2495 ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®); 2496 if (ret < 0) { 2497 dev_err(&client->dev, "Get Revision ID failed\n"); 2498 goto err; 2499 } 2500 2501 dev_info(&client->dev, 2502 "Cirrus Logic CS43130 (%x), Revision: %02X\n", devid, 2503 reg & 0xFF); 2504 2505 mutex_init(&cs43130->clk_mutex); 2506 2507 init_completion(&cs43130->xtal_rdy); 2508 init_completion(&cs43130->pll_rdy); 2509 init_completion(&cs43130->hpload_evt); 2510 2511 ret = devm_request_threaded_irq(&client->dev, client->irq, 2512 NULL, cs43130_irq_thread, 2513 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 2514 "cs43130", cs43130); 2515 if (ret != 0) { 2516 dev_err(&client->dev, "Failed to request IRQ: %d\n", ret); 2517 goto err; 2518 } 2519 2520 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO; 2521 2522 pm_runtime_set_autosuspend_delay(&client->dev, 100); 2523 pm_runtime_use_autosuspend(&client->dev); 2524 pm_runtime_set_active(&client->dev); 2525 pm_runtime_enable(&client->dev); 2526 2527 switch (cs43130->dev_id) { 2528 case CS43130_CHIP_ID: 2529 case CS43131_CHIP_ID: 2530 memcpy(all_hp_widgets, digital_hp_widgets, 2531 sizeof(digital_hp_widgets)); 2532 memcpy(all_hp_widgets + ARRAY_SIZE(digital_hp_widgets), 2533 analog_hp_widgets, sizeof(analog_hp_widgets)); 2534 memcpy(all_hp_routes, digital_hp_routes, 2535 sizeof(digital_hp_routes)); 2536 memcpy(all_hp_routes + ARRAY_SIZE(digital_hp_routes), 2537 analog_hp_routes, sizeof(analog_hp_routes)); 2538 2539 soc_component_dev_cs43130.dapm_widgets = 2540 all_hp_widgets; 2541 soc_component_dev_cs43130.num_dapm_widgets = 2542 ARRAY_SIZE(all_hp_widgets); 2543 soc_component_dev_cs43130.dapm_routes = 2544 all_hp_routes; 2545 soc_component_dev_cs43130.num_dapm_routes = 2546 ARRAY_SIZE(all_hp_routes); 2547 break; 2548 case CS43198_CHIP_ID: 2549 case CS4399_CHIP_ID: 2550 soc_component_dev_cs43130.dapm_widgets = 2551 digital_hp_widgets; 2552 soc_component_dev_cs43130.num_dapm_widgets = 2553 ARRAY_SIZE(digital_hp_widgets); 2554 soc_component_dev_cs43130.dapm_routes = 2555 digital_hp_routes; 2556 soc_component_dev_cs43130.num_dapm_routes = 2557 ARRAY_SIZE(digital_hp_routes); 2558 break; 2559 } 2560 2561 ret = devm_snd_soc_register_component(&client->dev, 2562 &soc_component_dev_cs43130, 2563 cs43130_dai, ARRAY_SIZE(cs43130_dai)); 2564 if (ret < 0) { 2565 dev_err(&client->dev, 2566 "snd_soc_register_component failed with ret = %d\n", ret); 2567 goto err; 2568 } 2569 2570 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG, 2571 CS43130_ASP_3ST_MASK, 0); 2572 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG, 2573 CS43130_XSP_3ST_MASK, 0); 2574 2575 return 0; 2576 2577 err: 2578 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); 2579 err_supplies: 2580 regulator_bulk_disable(ARRAY_SIZE(cs43130->supplies), 2581 cs43130->supplies); 2582 2583 return ret; 2584 } 2585 2586 static int cs43130_i2c_remove(struct i2c_client *client) 2587 { 2588 struct cs43130_private *cs43130 = i2c_get_clientdata(client); 2589 2590 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) 2591 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2592 CS43130_XTAL_ERR_INT, 2593 1 << CS43130_XTAL_ERR_INT_SHIFT); 2594 2595 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2596 CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, 2597 CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT); 2598 2599 if (cs43130->dc_meas) { 2600 cancel_work_sync(&cs43130->work); 2601 flush_workqueue(cs43130->wq); 2602 2603 device_remove_file(&client->dev, &dev_attr_hpload_dc_l); 2604 device_remove_file(&client->dev, &dev_attr_hpload_dc_r); 2605 device_remove_file(&client->dev, &dev_attr_hpload_ac_l); 2606 device_remove_file(&client->dev, &dev_attr_hpload_ac_r); 2607 } 2608 2609 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); 2610 2611 pm_runtime_disable(&client->dev); 2612 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); 2613 2614 return 0; 2615 } 2616 2617 static int __maybe_unused cs43130_runtime_suspend(struct device *dev) 2618 { 2619 struct cs43130_private *cs43130 = dev_get_drvdata(dev); 2620 2621 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) 2622 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2623 CS43130_XTAL_ERR_INT, 2624 1 << CS43130_XTAL_ERR_INT_SHIFT); 2625 2626 regcache_cache_only(cs43130->regmap, true); 2627 regcache_mark_dirty(cs43130->regmap); 2628 2629 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); 2630 2631 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); 2632 2633 return 0; 2634 } 2635 2636 static int __maybe_unused cs43130_runtime_resume(struct device *dev) 2637 { 2638 struct cs43130_private *cs43130 = dev_get_drvdata(dev); 2639 int ret; 2640 2641 ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES, cs43130->supplies); 2642 if (ret != 0) { 2643 dev_err(dev, "Failed to enable supplies: %d\n", ret); 2644 return ret; 2645 } 2646 2647 regcache_cache_only(cs43130->regmap, false); 2648 2649 gpiod_set_value_cansleep(cs43130->reset_gpio, 1); 2650 2651 usleep_range(2000, 2050); 2652 2653 ret = regcache_sync(cs43130->regmap); 2654 if (ret != 0) { 2655 dev_err(dev, "Failed to restore register cache\n"); 2656 goto err; 2657 } 2658 2659 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) 2660 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2661 CS43130_XTAL_ERR_INT, 0); 2662 2663 return 0; 2664 err: 2665 regcache_cache_only(cs43130->regmap, true); 2666 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); 2667 2668 return ret; 2669 } 2670 2671 static const struct dev_pm_ops cs43130_runtime_pm = { 2672 SET_RUNTIME_PM_OPS(cs43130_runtime_suspend, cs43130_runtime_resume, 2673 NULL) 2674 }; 2675 2676 static const struct of_device_id cs43130_of_match[] = { 2677 {.compatible = "cirrus,cs43130",}, 2678 {.compatible = "cirrus,cs4399",}, 2679 {.compatible = "cirrus,cs43131",}, 2680 {.compatible = "cirrus,cs43198",}, 2681 {}, 2682 }; 2683 2684 MODULE_DEVICE_TABLE(of, cs43130_of_match); 2685 2686 static const struct i2c_device_id cs43130_i2c_id[] = { 2687 {"cs43130", 0}, 2688 {"cs4399", 0}, 2689 {"cs43131", 0}, 2690 {"cs43198", 0}, 2691 {} 2692 }; 2693 2694 MODULE_DEVICE_TABLE(i2c, cs43130_i2c_id); 2695 2696 static struct i2c_driver cs43130_i2c_driver = { 2697 .driver = { 2698 .name = "cs43130", 2699 .of_match_table = cs43130_of_match, 2700 .pm = &cs43130_runtime_pm, 2701 }, 2702 .id_table = cs43130_i2c_id, 2703 .probe_new = cs43130_i2c_probe, 2704 .remove = cs43130_i2c_remove, 2705 }; 2706 2707 module_i2c_driver(cs43130_i2c_driver); 2708 2709 MODULE_AUTHOR("Li Xu <li.xu@cirrus.com>"); 2710 MODULE_DESCRIPTION("Cirrus Logic CS43130 ALSA SoC Codec Driver"); 2711 MODULE_LICENSE("GPL"); 2712