1 /* 2 * cs43130.c -- CS43130 ALSA Soc Audio driver 3 * 4 * Copyright 2017 Cirrus Logic, Inc. 5 * 6 * Authors: Li Xu <li.xu@cirrus.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/i2c.h> 22 #include <linux/of_device.h> 23 #include <linux/regmap.h> 24 #include <linux/slab.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/soc-dapm.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 #include <linux/of_gpio.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/of_irq.h> 36 #include <linux/completion.h> 37 #include <linux/mutex.h> 38 #include <linux/workqueue.h> 39 #include <sound/jack.h> 40 41 #include "cs43130.h" 42 43 static const struct reg_default cs43130_reg_defaults[] = { 44 {CS43130_SYS_CLK_CTL_1, 0x06}, 45 {CS43130_SP_SRATE, 0x01}, 46 {CS43130_SP_BITSIZE, 0x05}, 47 {CS43130_PAD_INT_CFG, 0x03}, 48 {CS43130_PWDN_CTL, 0xFE}, 49 {CS43130_CRYSTAL_SET, 0x04}, 50 {CS43130_PLL_SET_1, 0x00}, 51 {CS43130_PLL_SET_2, 0x00}, 52 {CS43130_PLL_SET_3, 0x00}, 53 {CS43130_PLL_SET_4, 0x00}, 54 {CS43130_PLL_SET_5, 0x40}, 55 {CS43130_PLL_SET_6, 0x10}, 56 {CS43130_PLL_SET_7, 0x80}, 57 {CS43130_PLL_SET_8, 0x03}, 58 {CS43130_PLL_SET_9, 0x02}, 59 {CS43130_PLL_SET_10, 0x02}, 60 {CS43130_CLKOUT_CTL, 0x00}, 61 {CS43130_ASP_NUM_1, 0x01}, 62 {CS43130_ASP_NUM_2, 0x00}, 63 {CS43130_ASP_DEN_1, 0x08}, 64 {CS43130_ASP_DEN_2, 0x00}, 65 {CS43130_ASP_LRCK_HI_TIME_1, 0x1F}, 66 {CS43130_ASP_LRCK_HI_TIME_2, 0x00}, 67 {CS43130_ASP_LRCK_PERIOD_1, 0x3F}, 68 {CS43130_ASP_LRCK_PERIOD_2, 0x00}, 69 {CS43130_ASP_CLOCK_CONF, 0x0C}, 70 {CS43130_ASP_FRAME_CONF, 0x0A}, 71 {CS43130_XSP_NUM_1, 0x01}, 72 {CS43130_XSP_NUM_2, 0x00}, 73 {CS43130_XSP_DEN_1, 0x02}, 74 {CS43130_XSP_DEN_2, 0x00}, 75 {CS43130_XSP_LRCK_HI_TIME_1, 0x1F}, 76 {CS43130_XSP_LRCK_HI_TIME_2, 0x00}, 77 {CS43130_XSP_LRCK_PERIOD_1, 0x3F}, 78 {CS43130_XSP_LRCK_PERIOD_2, 0x00}, 79 {CS43130_XSP_CLOCK_CONF, 0x0C}, 80 {CS43130_XSP_FRAME_CONF, 0x0A}, 81 {CS43130_ASP_CH_1_LOC, 0x00}, 82 {CS43130_ASP_CH_2_LOC, 0x00}, 83 {CS43130_ASP_CH_1_SZ_EN, 0x06}, 84 {CS43130_ASP_CH_2_SZ_EN, 0x0E}, 85 {CS43130_XSP_CH_1_LOC, 0x00}, 86 {CS43130_XSP_CH_2_LOC, 0x00}, 87 {CS43130_XSP_CH_1_SZ_EN, 0x06}, 88 {CS43130_XSP_CH_2_SZ_EN, 0x0E}, 89 {CS43130_DSD_VOL_B, 0x78}, 90 {CS43130_DSD_VOL_A, 0x78}, 91 {CS43130_DSD_PATH_CTL_1, 0xA8}, 92 {CS43130_DSD_INT_CFG, 0x00}, 93 {CS43130_DSD_PATH_CTL_2, 0x02}, 94 {CS43130_DSD_PCM_MIX_CTL, 0x00}, 95 {CS43130_DSD_PATH_CTL_3, 0x40}, 96 {CS43130_HP_OUT_CTL_1, 0x30}, 97 {CS43130_PCM_FILT_OPT, 0x02}, 98 {CS43130_PCM_VOL_B, 0x78}, 99 {CS43130_PCM_VOL_A, 0x78}, 100 {CS43130_PCM_PATH_CTL_1, 0xA8}, 101 {CS43130_PCM_PATH_CTL_2, 0x00}, 102 {CS43130_CLASS_H_CTL, 0x1E}, 103 {CS43130_HP_DETECT, 0x04}, 104 {CS43130_HP_LOAD_1, 0x00}, 105 {CS43130_HP_MEAS_LOAD_1, 0x00}, 106 {CS43130_HP_MEAS_LOAD_2, 0x00}, 107 {CS43130_INT_MASK_1, 0xFF}, 108 {CS43130_INT_MASK_2, 0xFF}, 109 {CS43130_INT_MASK_3, 0xFF}, 110 {CS43130_INT_MASK_4, 0xFF}, 111 {CS43130_INT_MASK_5, 0xFF}, 112 }; 113 114 static bool cs43130_volatile_register(struct device *dev, unsigned int reg) 115 { 116 switch (reg) { 117 case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5: 118 case CS43130_HP_DC_STAT_1 ... CS43130_HP_DC_STAT_2: 119 case CS43130_HP_AC_STAT_1 ... CS43130_HP_AC_STAT_2: 120 return true; 121 default: 122 return false; 123 } 124 } 125 126 static bool cs43130_readable_register(struct device *dev, unsigned int reg) 127 { 128 switch (reg) { 129 case CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1: 130 case CS43130_SP_SRATE ... CS43130_PAD_INT_CFG: 131 case CS43130_PWDN_CTL: 132 case CS43130_CRYSTAL_SET: 133 case CS43130_PLL_SET_1 ... CS43130_PLL_SET_5: 134 case CS43130_PLL_SET_6: 135 case CS43130_PLL_SET_7: 136 case CS43130_PLL_SET_8: 137 case CS43130_PLL_SET_9: 138 case CS43130_PLL_SET_10: 139 case CS43130_CLKOUT_CTL: 140 case CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF: 141 case CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF: 142 case CS43130_ASP_CH_1_LOC: 143 case CS43130_ASP_CH_2_LOC: 144 case CS43130_ASP_CH_1_SZ_EN: 145 case CS43130_ASP_CH_2_SZ_EN: 146 case CS43130_XSP_CH_1_LOC: 147 case CS43130_XSP_CH_2_LOC: 148 case CS43130_XSP_CH_1_SZ_EN: 149 case CS43130_XSP_CH_2_SZ_EN: 150 case CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3: 151 case CS43130_HP_OUT_CTL_1: 152 case CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2: 153 case CS43130_CLASS_H_CTL: 154 case CS43130_HP_DETECT: 155 case CS43130_HP_STATUS: 156 case CS43130_HP_LOAD_1: 157 case CS43130_HP_MEAS_LOAD_1: 158 case CS43130_HP_MEAS_LOAD_2: 159 case CS43130_HP_DC_STAT_1: 160 case CS43130_HP_DC_STAT_2: 161 case CS43130_HP_AC_STAT_1: 162 case CS43130_HP_AC_STAT_2: 163 case CS43130_HP_LOAD_STAT: 164 case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5: 165 case CS43130_INT_MASK_1 ... CS43130_INT_MASK_5: 166 return true; 167 default: 168 return false; 169 } 170 } 171 172 static bool cs43130_precious_register(struct device *dev, unsigned int reg) 173 { 174 switch (reg) { 175 case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5: 176 return true; 177 default: 178 return false; 179 } 180 } 181 182 struct cs43130_pll_params { 183 unsigned int pll_in; 184 u8 sclk_prediv; 185 u8 pll_div_int; 186 u32 pll_div_frac; 187 u8 pll_mode; 188 u8 pll_divout; 189 unsigned int pll_out; 190 u8 pll_cal_ratio; 191 }; 192 193 static const struct cs43130_pll_params pll_ratio_table[] = { 194 {9600000, 0x02, 0x49, 0x800000, 0x00, 0x08, 22579200, 151}, 195 {9600000, 0x02, 0x50, 0x000000, 0x00, 0x08, 24576000, 164}, 196 197 {11289600, 0x02, 0X40, 0, 0x01, 0x08, 22579200, 128}, 198 {11289600, 0x02, 0x44, 0x06F700, 0x0, 0x08, 24576000, 139}, 199 200 {12000000, 0x02, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120}, 201 {12000000, 0x02, 0x40, 0x000000, 0x00, 0x08, 24576000, 131}, 202 203 {12288000, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118}, 204 {12288000, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128}, 205 206 {13000000, 0x02, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111}, 207 {13000000, 0x02, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121}, 208 209 {19200000, 0x03, 0x49, 0x800000, 0x00, 0x08, 22579200, 151}, 210 {19200000, 0x03, 0x50, 0x000000, 0x00, 0x08, 24576000, 164}, 211 212 {22579200, 0, 0, 0, 0, 0, 22579200, 0}, 213 {22579200, 0x03, 0x44, 0x06F700, 0x00, 0x08, 24576000, 139}, 214 215 {24000000, 0x03, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120}, 216 {24000000, 0x03, 0x40, 0x000000, 0x00, 0x08, 24576000, 131}, 217 218 {24576000, 0x03, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118}, 219 {24576000, 0, 0, 0, 0, 0, 24576000, 0}, 220 221 {26000000, 0x03, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111}, 222 {26000000, 0x03, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121}, 223 }; 224 225 static const struct cs43130_pll_params *cs43130_get_pll_table( 226 unsigned int freq_in, unsigned int freq_out) 227 { 228 int i; 229 230 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 231 if (pll_ratio_table[i].pll_in == freq_in && 232 pll_ratio_table[i].pll_out == freq_out) 233 return &pll_ratio_table[i]; 234 } 235 236 return NULL; 237 } 238 239 static int cs43130_pll_config(struct snd_soc_codec *codec) 240 { 241 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 242 const struct cs43130_pll_params *pll_entry; 243 244 dev_dbg(codec->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n", 245 cs43130->mclk, cs43130->mclk_int); 246 247 pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int); 248 if (!pll_entry) 249 return -EINVAL; 250 251 if (pll_entry->pll_cal_ratio == 0) { 252 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1, 253 CS43130_PLL_START_MASK, 0); 254 255 cs43130->pll_bypass = true; 256 return 0; 257 } 258 259 cs43130->pll_bypass = false; 260 261 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_2, 262 CS43130_PLL_DIV_DATA_MASK, 263 pll_entry->pll_div_frac >> 264 CS43130_PLL_DIV_FRAC_0_DATA_SHIFT); 265 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_3, 266 CS43130_PLL_DIV_DATA_MASK, 267 pll_entry->pll_div_frac >> 268 CS43130_PLL_DIV_FRAC_1_DATA_SHIFT); 269 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_4, 270 CS43130_PLL_DIV_DATA_MASK, 271 pll_entry->pll_div_frac >> 272 CS43130_PLL_DIV_FRAC_2_DATA_SHIFT); 273 regmap_write(cs43130->regmap, CS43130_PLL_SET_5, 274 pll_entry->pll_div_int); 275 regmap_write(cs43130->regmap, CS43130_PLL_SET_6, pll_entry->pll_divout); 276 regmap_write(cs43130->regmap, CS43130_PLL_SET_7, 277 pll_entry->pll_cal_ratio); 278 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8, 279 CS43130_PLL_MODE_MASK, 280 pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT); 281 regmap_write(cs43130->regmap, CS43130_PLL_SET_9, 282 pll_entry->sclk_prediv); 283 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1, 284 CS43130_PLL_START_MASK, 1); 285 286 return 0; 287 } 288 289 static int cs43130_set_pll(struct snd_soc_codec *codec, int pll_id, int source, 290 unsigned int freq_in, unsigned int freq_out) 291 { 292 int ret = 0; 293 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 294 295 switch (freq_in) { 296 case 9600000: 297 case 11289600: 298 case 12000000: 299 case 12288000: 300 case 13000000: 301 case 19200000: 302 case 22579200: 303 case 24000000: 304 case 24576000: 305 case 26000000: 306 cs43130->mclk = freq_in; 307 break; 308 default: 309 dev_err(codec->dev, 310 "unsupported pll input reference clock:%d\n", freq_in); 311 return -EINVAL; 312 } 313 314 switch (freq_out) { 315 case 22579200: 316 cs43130->mclk_int = freq_out; 317 break; 318 case 24576000: 319 cs43130->mclk_int = freq_out; 320 break; 321 default: 322 dev_err(codec->dev, 323 "unsupported pll output ref clock: %u\n", freq_out); 324 return -EINVAL; 325 } 326 327 ret = cs43130_pll_config(codec); 328 dev_dbg(codec->dev, "cs43130->pll_bypass = %d", cs43130->pll_bypass); 329 return ret; 330 } 331 332 static int cs43130_change_clksrc(struct snd_soc_codec *codec, 333 enum cs43130_mclk_src_sel src) 334 { 335 int ret; 336 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 337 int mclk_int_decoded; 338 339 if (src == cs43130->mclk_int_src) { 340 /* clk source has not changed */ 341 return 0; 342 } 343 344 switch (cs43130->mclk_int) { 345 case CS43130_MCLK_22M: 346 mclk_int_decoded = CS43130_MCLK_22P5; 347 break; 348 case CS43130_MCLK_24M: 349 mclk_int_decoded = CS43130_MCLK_24P5; 350 break; 351 default: 352 dev_err(codec->dev, "Invalid MCLK INT freq: %u\n", cs43130->mclk_int); 353 return -EINVAL; 354 } 355 356 switch (src) { 357 case CS43130_MCLK_SRC_EXT: 358 cs43130->pll_bypass = true; 359 cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT; 360 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) { 361 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 362 CS43130_PDN_XTAL_MASK, 363 1 << CS43130_PDN_XTAL_SHIFT); 364 } else { 365 reinit_completion(&cs43130->xtal_rdy); 366 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 367 CS43130_XTAL_RDY_INT_MASK, 0); 368 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 369 CS43130_PDN_XTAL_MASK, 0); 370 ret = wait_for_completion_timeout(&cs43130->xtal_rdy, 371 msecs_to_jiffies(100)); 372 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 373 CS43130_XTAL_RDY_INT_MASK, 374 1 << CS43130_XTAL_RDY_INT_SHIFT); 375 if (ret == 0) { 376 dev_err(codec->dev, "Timeout waiting for XTAL_READY interrupt\n"); 377 return -ETIMEDOUT; 378 } 379 } 380 381 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 382 CS43130_MCLK_SRC_SEL_MASK, 383 src << CS43130_MCLK_SRC_SEL_SHIFT); 384 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 385 CS43130_MCLK_INT_MASK, 386 mclk_int_decoded << CS43130_MCLK_INT_SHIFT); 387 usleep_range(150, 200); 388 389 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 390 CS43130_PDN_PLL_MASK, 391 1 << CS43130_PDN_PLL_SHIFT); 392 break; 393 case CS43130_MCLK_SRC_PLL: 394 cs43130->pll_bypass = false; 395 cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL; 396 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) { 397 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 398 CS43130_PDN_XTAL_MASK, 399 1 << CS43130_PDN_XTAL_SHIFT); 400 } else { 401 reinit_completion(&cs43130->xtal_rdy); 402 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 403 CS43130_XTAL_RDY_INT_MASK, 0); 404 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 405 CS43130_PDN_XTAL_MASK, 0); 406 ret = wait_for_completion_timeout(&cs43130->xtal_rdy, 407 msecs_to_jiffies(100)); 408 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 409 CS43130_XTAL_RDY_INT_MASK, 410 1 << CS43130_XTAL_RDY_INT_SHIFT); 411 if (ret == 0) { 412 dev_err(codec->dev, "Timeout waiting for XTAL_READY interrupt\n"); 413 return -ETIMEDOUT; 414 } 415 } 416 417 reinit_completion(&cs43130->pll_rdy); 418 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 419 CS43130_PLL_RDY_INT_MASK, 0); 420 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 421 CS43130_PDN_PLL_MASK, 0); 422 ret = wait_for_completion_timeout(&cs43130->pll_rdy, 423 msecs_to_jiffies(100)); 424 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 425 CS43130_PLL_RDY_INT_MASK, 426 1 << CS43130_PLL_RDY_INT_SHIFT); 427 if (ret == 0) { 428 dev_err(codec->dev, "Timeout waiting for PLL_READY interrupt\n"); 429 return -ETIMEDOUT; 430 } 431 432 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 433 CS43130_MCLK_SRC_SEL_MASK, 434 src << CS43130_MCLK_SRC_SEL_SHIFT); 435 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 436 CS43130_MCLK_INT_MASK, 437 mclk_int_decoded << CS43130_MCLK_INT_SHIFT); 438 usleep_range(150, 200); 439 break; 440 case CS43130_MCLK_SRC_RCO: 441 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO; 442 443 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 444 CS43130_MCLK_SRC_SEL_MASK, 445 src << CS43130_MCLK_SRC_SEL_SHIFT); 446 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, 447 CS43130_MCLK_INT_MASK, 448 CS43130_MCLK_22P5 << CS43130_MCLK_INT_SHIFT); 449 usleep_range(150, 200); 450 451 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 452 CS43130_PDN_XTAL_MASK, 453 1 << CS43130_PDN_XTAL_SHIFT); 454 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, 455 CS43130_PDN_PLL_MASK, 456 1 << CS43130_PDN_PLL_SHIFT); 457 break; 458 default: 459 dev_err(codec->dev, "Invalid MCLK source value\n"); 460 return -EINVAL; 461 } 462 463 return 0; 464 } 465 466 static const struct cs43130_bitwidth_map cs43130_bitwidth_table[] = { 467 {8, CS43130_SP_BIT_SIZE_8, CS43130_CH_BIT_SIZE_8}, 468 {16, CS43130_SP_BIT_SIZE_16, CS43130_CH_BIT_SIZE_16}, 469 {24, CS43130_SP_BIT_SIZE_24, CS43130_CH_BIT_SIZE_24}, 470 {32, CS43130_SP_BIT_SIZE_32, CS43130_CH_BIT_SIZE_32}, 471 }; 472 473 static const struct cs43130_bitwidth_map *cs43130_get_bitwidth_table( 474 unsigned int bitwidth) 475 { 476 int i; 477 478 for (i = 0; i < ARRAY_SIZE(cs43130_bitwidth_table); i++) { 479 if (cs43130_bitwidth_table[i].bitwidth == bitwidth) 480 return &cs43130_bitwidth_table[i]; 481 } 482 483 return NULL; 484 } 485 486 static int cs43130_set_bitwidth(int dai_id, unsigned int bitwidth_dai, 487 struct regmap *regmap) 488 { 489 const struct cs43130_bitwidth_map *bw_map; 490 491 bw_map = cs43130_get_bitwidth_table(bitwidth_dai); 492 if (!bw_map) 493 return -EINVAL; 494 495 switch (dai_id) { 496 case CS43130_ASP_PCM_DAI: 497 case CS43130_ASP_DOP_DAI: 498 regmap_update_bits(regmap, CS43130_ASP_CH_1_SZ_EN, 499 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); 500 regmap_update_bits(regmap, CS43130_ASP_CH_2_SZ_EN, 501 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); 502 regmap_update_bits(regmap, CS43130_SP_BITSIZE, 503 CS43130_ASP_BITSIZE_MASK, bw_map->sp_bit); 504 break; 505 case CS43130_XSP_DOP_DAI: 506 regmap_update_bits(regmap, CS43130_XSP_CH_1_SZ_EN, 507 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); 508 regmap_update_bits(regmap, CS43130_XSP_CH_2_SZ_EN, 509 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); 510 regmap_update_bits(regmap, CS43130_SP_BITSIZE, 511 CS43130_XSP_BITSIZE_MASK, bw_map->sp_bit << 512 CS43130_XSP_BITSIZE_SHIFT); 513 break; 514 default: 515 return -EINVAL; 516 } 517 518 return 0; 519 } 520 521 static const struct cs43130_rate_map cs43130_rate_table[] = { 522 {32000, CS43130_ASP_SPRATE_32K}, 523 {44100, CS43130_ASP_SPRATE_44_1K}, 524 {48000, CS43130_ASP_SPRATE_48K}, 525 {88200, CS43130_ASP_SPRATE_88_2K}, 526 {96000, CS43130_ASP_SPRATE_96K}, 527 {176400, CS43130_ASP_SPRATE_176_4K}, 528 {192000, CS43130_ASP_SPRATE_192K}, 529 {352800, CS43130_ASP_SPRATE_352_8K}, 530 {384000, CS43130_ASP_SPRATE_384K}, 531 }; 532 533 static const struct cs43130_rate_map *cs43130_get_rate_table(int fs) 534 { 535 int i; 536 537 for (i = 0; i < ARRAY_SIZE(cs43130_rate_table); i++) { 538 if (cs43130_rate_table[i].fs == fs) 539 return &cs43130_rate_table[i]; 540 } 541 542 return NULL; 543 } 544 545 static const struct cs43130_clk_gen *cs43130_get_clk_gen(int mclk_int, int fs, 546 const struct cs43130_clk_gen *clk_gen_table, int len_clk_gen_table) 547 { 548 int i; 549 550 for (i = 0; i < len_clk_gen_table; i++) { 551 if (clk_gen_table[i].mclk_int == mclk_int && 552 clk_gen_table[i].fs == fs) 553 return &clk_gen_table[i]; 554 } 555 556 return NULL; 557 } 558 559 static int cs43130_set_sp_fmt(int dai_id, unsigned int bitwidth_sclk, 560 struct snd_pcm_hw_params *params, 561 struct cs43130_private *cs43130) 562 { 563 u16 frm_size; 564 u16 hi_size; 565 u8 frm_delay; 566 u8 frm_phase; 567 u8 frm_data; 568 u8 sclk_edge; 569 u8 lrck_edge; 570 u8 clk_data; 571 u8 loc_ch1; 572 u8 loc_ch2; 573 u8 dai_mode_val; 574 const struct cs43130_clk_gen *clk_gen; 575 576 switch (cs43130->dais[dai_id].dai_format) { 577 case SND_SOC_DAIFMT_I2S: 578 hi_size = bitwidth_sclk; 579 frm_delay = 2; 580 frm_phase = 0; 581 break; 582 case SND_SOC_DAIFMT_LEFT_J: 583 hi_size = bitwidth_sclk; 584 frm_delay = 2; 585 frm_phase = 1; 586 break; 587 case SND_SOC_DAIFMT_DSP_A: 588 hi_size = 1; 589 frm_delay = 2; 590 frm_phase = 1; 591 break; 592 case SND_SOC_DAIFMT_DSP_B: 593 hi_size = 1; 594 frm_delay = 0; 595 frm_phase = 1; 596 break; 597 default: 598 return -EINVAL; 599 } 600 601 switch (cs43130->dais[dai_id].dai_mode) { 602 case SND_SOC_DAIFMT_CBS_CFS: 603 dai_mode_val = 0; 604 break; 605 case SND_SOC_DAIFMT_CBM_CFM: 606 dai_mode_val = 1; 607 break; 608 default: 609 return -EINVAL; 610 } 611 612 frm_size = bitwidth_sclk * params_channels(params); 613 sclk_edge = 1; 614 lrck_edge = 0; 615 loc_ch1 = 0; 616 loc_ch2 = bitwidth_sclk * (params_channels(params) - 1); 617 618 frm_data = frm_delay & CS43130_SP_FSD_MASK; 619 frm_data |= (frm_phase << CS43130_SP_STP_SHIFT) & CS43130_SP_STP_MASK; 620 621 clk_data = lrck_edge & CS43130_SP_LCPOL_IN_MASK; 622 clk_data |= (lrck_edge << CS43130_SP_LCPOL_OUT_SHIFT) & 623 CS43130_SP_LCPOL_OUT_MASK; 624 clk_data |= (sclk_edge << CS43130_SP_SCPOL_IN_SHIFT) & 625 CS43130_SP_SCPOL_IN_MASK; 626 clk_data |= (sclk_edge << CS43130_SP_SCPOL_OUT_SHIFT) & 627 CS43130_SP_SCPOL_OUT_MASK; 628 clk_data |= (dai_mode_val << CS43130_SP_MODE_SHIFT) & 629 CS43130_SP_MODE_MASK; 630 631 switch (dai_id) { 632 case CS43130_ASP_PCM_DAI: 633 case CS43130_ASP_DOP_DAI: 634 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1, 635 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> 636 CS43130_SP_LCPR_LSB_DATA_SHIFT); 637 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2, 638 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> 639 CS43130_SP_LCPR_MSB_DATA_SHIFT); 640 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1, 641 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> 642 CS43130_SP_LCHI_LSB_DATA_SHIFT); 643 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2, 644 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> 645 CS43130_SP_LCHI_MSB_DATA_SHIFT); 646 regmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data); 647 regmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1); 648 regmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2); 649 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN, 650 CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT); 651 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN, 652 CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT); 653 regmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data); 654 break; 655 case CS43130_XSP_DOP_DAI: 656 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1, 657 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> 658 CS43130_SP_LCPR_LSB_DATA_SHIFT); 659 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2, 660 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> 661 CS43130_SP_LCPR_MSB_DATA_SHIFT); 662 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1, 663 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> 664 CS43130_SP_LCHI_LSB_DATA_SHIFT); 665 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2, 666 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> 667 CS43130_SP_LCHI_MSB_DATA_SHIFT); 668 regmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data); 669 regmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1); 670 regmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2); 671 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN, 672 CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT); 673 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN, 674 CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT); 675 regmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data); 676 break; 677 default: 678 return -EINVAL; 679 } 680 681 switch (frm_size) { 682 case 16: 683 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, 684 params_rate(params), 685 cs43130_16_clk_gen, 686 ARRAY_SIZE(cs43130_16_clk_gen)); 687 break; 688 case 32: 689 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, 690 params_rate(params), 691 cs43130_32_clk_gen, 692 ARRAY_SIZE(cs43130_32_clk_gen)); 693 break; 694 case 48: 695 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, 696 params_rate(params), 697 cs43130_48_clk_gen, 698 ARRAY_SIZE(cs43130_48_clk_gen)); 699 break; 700 case 64: 701 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, 702 params_rate(params), 703 cs43130_64_clk_gen, 704 ARRAY_SIZE(cs43130_64_clk_gen)); 705 break; 706 default: 707 return -EINVAL; 708 } 709 710 if (!clk_gen) 711 return -EINVAL; 712 713 switch (dai_id) { 714 case CS43130_ASP_PCM_DAI: 715 case CS43130_ASP_DOP_DAI: 716 regmap_write(cs43130->regmap, CS43130_ASP_DEN_1, 717 (clk_gen->den & CS43130_SP_M_LSB_DATA_MASK) >> 718 CS43130_SP_M_LSB_DATA_SHIFT); 719 regmap_write(cs43130->regmap, CS43130_ASP_DEN_2, 720 (clk_gen->den & CS43130_SP_M_MSB_DATA_MASK) >> 721 CS43130_SP_M_MSB_DATA_SHIFT); 722 regmap_write(cs43130->regmap, CS43130_ASP_NUM_1, 723 (clk_gen->num & CS43130_SP_N_LSB_DATA_MASK) >> 724 CS43130_SP_N_LSB_DATA_SHIFT); 725 regmap_write(cs43130->regmap, CS43130_ASP_NUM_2, 726 (clk_gen->num & CS43130_SP_N_MSB_DATA_MASK) >> 727 CS43130_SP_N_MSB_DATA_SHIFT); 728 break; 729 case CS43130_XSP_DOP_DAI: 730 regmap_write(cs43130->regmap, CS43130_XSP_DEN_1, 731 (clk_gen->den & CS43130_SP_M_LSB_DATA_MASK) >> 732 CS43130_SP_M_LSB_DATA_SHIFT); 733 regmap_write(cs43130->regmap, CS43130_XSP_DEN_2, 734 (clk_gen->den & CS43130_SP_M_MSB_DATA_MASK) >> 735 CS43130_SP_M_MSB_DATA_SHIFT); 736 regmap_write(cs43130->regmap, CS43130_XSP_NUM_1, 737 (clk_gen->num & CS43130_SP_N_LSB_DATA_MASK) >> 738 CS43130_SP_N_LSB_DATA_SHIFT); 739 regmap_write(cs43130->regmap, CS43130_XSP_NUM_2, 740 (clk_gen->num & CS43130_SP_N_MSB_DATA_MASK) >> 741 CS43130_SP_N_MSB_DATA_SHIFT); 742 break; 743 default: 744 return -EINVAL; 745 } 746 747 return 0; 748 } 749 750 static int cs43130_pcm_dsd_mix(bool en, struct regmap *regmap) 751 { 752 if (en) { 753 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL, 754 CS43130_MIX_PCM_PREP_MASK, 755 1 << CS43130_MIX_PCM_PREP_SHIFT); 756 usleep_range(6000, 6050); 757 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL, 758 CS43130_MIX_PCM_DSD_MASK, 759 1 << CS43130_MIX_PCM_DSD_SHIFT); 760 } else { 761 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL, 762 CS43130_MIX_PCM_DSD_MASK, 763 0 << CS43130_MIX_PCM_DSD_SHIFT); 764 usleep_range(1600, 1650); 765 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL, 766 CS43130_MIX_PCM_PREP_MASK, 767 0 << CS43130_MIX_PCM_PREP_SHIFT); 768 } 769 770 return 0; 771 } 772 773 static int cs43130_dsd_hw_params(struct snd_pcm_substream *substream, 774 struct snd_pcm_hw_params *params, 775 struct snd_soc_dai *dai) 776 { 777 struct snd_soc_codec *codec = dai->codec; 778 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 779 unsigned int required_clk; 780 u8 dsd_speed; 781 782 mutex_lock(&cs43130->clk_mutex); 783 if (!cs43130->clk_req) { 784 /* no DAI is currently using clk */ 785 if (!(CS43130_MCLK_22M % params_rate(params))) 786 required_clk = CS43130_MCLK_22M; 787 else 788 required_clk = CS43130_MCLK_24M; 789 790 cs43130_set_pll(codec, 0, 0, cs43130->mclk, required_clk); 791 if (cs43130->pll_bypass) 792 cs43130_change_clksrc(codec, CS43130_MCLK_SRC_EXT); 793 else 794 cs43130_change_clksrc(codec, CS43130_MCLK_SRC_PLL); 795 } 796 797 cs43130->clk_req++; 798 if (cs43130->clk_req == 2) 799 cs43130_pcm_dsd_mix(true, cs43130->regmap); 800 mutex_unlock(&cs43130->clk_mutex); 801 802 switch (params_rate(params)) { 803 case 176400: 804 dsd_speed = 0; 805 break; 806 case 352800: 807 dsd_speed = 1; 808 break; 809 default: 810 dev_err(codec->dev, "Rate(%u) not supported\n", 811 params_rate(params)); 812 return -EINVAL; 813 } 814 815 if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) 816 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG, 817 CS43130_DSD_MASTER, CS43130_DSD_MASTER); 818 else 819 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG, 820 CS43130_DSD_MASTER, 0); 821 822 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 823 CS43130_DSD_SPEED_MASK, 824 dsd_speed << CS43130_DSD_SPEED_SHIFT); 825 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 826 CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_DSD << 827 CS43130_DSD_SRC_SHIFT); 828 829 return 0; 830 } 831 832 static int cs43130_hw_params(struct snd_pcm_substream *substream, 833 struct snd_pcm_hw_params *params, 834 struct snd_soc_dai *dai) 835 { 836 struct snd_soc_codec *codec = dai->codec; 837 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 838 const struct cs43130_rate_map *rate_map; 839 unsigned int sclk = cs43130->dais[dai->id].sclk; 840 unsigned int bitwidth_sclk; 841 unsigned int bitwidth_dai = (unsigned int)(params_width(params)); 842 unsigned int required_clk; 843 u8 dsd_speed; 844 845 mutex_lock(&cs43130->clk_mutex); 846 if (!cs43130->clk_req) { 847 /* no DAI is currently using clk */ 848 if (!(CS43130_MCLK_22M % params_rate(params))) 849 required_clk = CS43130_MCLK_22M; 850 else 851 required_clk = CS43130_MCLK_24M; 852 853 cs43130_set_pll(codec, 0, 0, cs43130->mclk, required_clk); 854 if (cs43130->pll_bypass) 855 cs43130_change_clksrc(codec, CS43130_MCLK_SRC_EXT); 856 else 857 cs43130_change_clksrc(codec, CS43130_MCLK_SRC_PLL); 858 } 859 860 cs43130->clk_req++; 861 if (cs43130->clk_req == 2) 862 cs43130_pcm_dsd_mix(true, cs43130->regmap); 863 mutex_unlock(&cs43130->clk_mutex); 864 865 switch (dai->id) { 866 case CS43130_ASP_DOP_DAI: 867 case CS43130_XSP_DOP_DAI: 868 /* DoP bitwidth is always 24-bit */ 869 bitwidth_dai = 24; 870 sclk = params_rate(params) * bitwidth_dai * 871 params_channels(params); 872 873 switch (params_rate(params)) { 874 case 176400: 875 dsd_speed = 0; 876 break; 877 case 352800: 878 dsd_speed = 1; 879 break; 880 default: 881 dev_err(codec->dev, "Rate(%u) not supported\n", 882 params_rate(params)); 883 return -EINVAL; 884 } 885 886 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 887 CS43130_DSD_SPEED_MASK, 888 dsd_speed << CS43130_DSD_SPEED_SHIFT); 889 break; 890 case CS43130_ASP_PCM_DAI: 891 rate_map = cs43130_get_rate_table(params_rate(params)); 892 if (!rate_map) 893 return -EINVAL; 894 895 regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val); 896 break; 897 default: 898 dev_err(codec->dev, "Invalid DAI (%d)\n", dai->id); 899 return -EINVAL; 900 } 901 902 switch (dai->id) { 903 case CS43130_ASP_DOP_DAI: 904 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 905 CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_ASP << 906 CS43130_DSD_SRC_SHIFT); 907 break; 908 case CS43130_XSP_DOP_DAI: 909 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 910 CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_XSP << 911 CS43130_DSD_SRC_SHIFT); 912 break; 913 } 914 915 if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) 916 /* Calculate SCLK in master mode if unassigned */ 917 sclk = params_rate(params) * bitwidth_dai * 918 params_channels(params); 919 920 if (!sclk) { 921 /* at this point, SCLK must be set */ 922 dev_err(codec->dev, "SCLK freq is not set\n"); 923 return -EINVAL; 924 } 925 926 bitwidth_sclk = (sclk / params_rate(params)) / params_channels(params); 927 if (bitwidth_sclk < bitwidth_dai) { 928 dev_err(codec->dev, "Format not supported: SCLK freq is too low\n"); 929 return -EINVAL; 930 } 931 932 dev_dbg(codec->dev, 933 "sclk = %u, fs = %d, bitwidth_dai = %u\n", 934 sclk, params_rate(params), bitwidth_dai); 935 936 dev_dbg(codec->dev, 937 "bitwidth_sclk = %u, num_ch = %u\n", 938 bitwidth_sclk, params_channels(params)); 939 940 cs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap); 941 cs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130); 942 943 return 0; 944 } 945 946 static int cs43130_hw_free(struct snd_pcm_substream *substream, 947 struct snd_soc_dai *dai) 948 { 949 struct snd_soc_codec *codec = dai->codec; 950 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 951 952 mutex_lock(&cs43130->clk_mutex); 953 cs43130->clk_req--; 954 if (!cs43130->clk_req) { 955 /* no DAI is currently using clk */ 956 cs43130_change_clksrc(codec, CS43130_MCLK_SRC_RCO); 957 cs43130_pcm_dsd_mix(false, cs43130->regmap); 958 } 959 mutex_unlock(&cs43130->clk_mutex); 960 961 return 0; 962 } 963 964 static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1); 965 966 static const char * const pcm_ch_text[] = { 967 "Left-Right Ch", 968 "Left-Left Ch", 969 "Right-Left Ch", 970 "Right-Right Ch", 971 }; 972 973 static const struct reg_sequence pcm_ch_en_seq[] = { 974 {CS43130_DXD1, 0x99}, 975 {0x180005, 0x8C}, 976 {0x180007, 0xAB}, 977 {0x180015, 0x31}, 978 {0x180017, 0xB2}, 979 {0x180025, 0x30}, 980 {0x180027, 0x84}, 981 {0x180035, 0x9C}, 982 {0x180037, 0xAE}, 983 {0x18000D, 0x24}, 984 {0x18000F, 0xA3}, 985 {0x18001D, 0x05}, 986 {0x18001F, 0xD4}, 987 {0x18002D, 0x0B}, 988 {0x18002F, 0xC7}, 989 {0x18003D, 0x71}, 990 {0x18003F, 0xE7}, 991 {CS43130_DXD1, 0}, 992 }; 993 994 static const struct reg_sequence pcm_ch_dis_seq[] = { 995 {CS43130_DXD1, 0x99}, 996 {0x180005, 0x24}, 997 {0x180007, 0xA3}, 998 {0x180015, 0x05}, 999 {0x180017, 0xD4}, 1000 {0x180025, 0x0B}, 1001 {0x180027, 0xC7}, 1002 {0x180035, 0x71}, 1003 {0x180037, 0xE7}, 1004 {0x18000D, 0x8C}, 1005 {0x18000F, 0xAB}, 1006 {0x18001D, 0x31}, 1007 {0x18001F, 0xB2}, 1008 {0x18002D, 0x30}, 1009 {0x18002F, 0x84}, 1010 {0x18003D, 0x9C}, 1011 {0x18003F, 0xAE}, 1012 {CS43130_DXD1, 0}, 1013 }; 1014 1015 static int cs43130_pcm_ch_get(struct snd_kcontrol *kcontrol, 1016 struct snd_ctl_elem_value *ucontrol) 1017 { 1018 return snd_soc_get_enum_double(kcontrol, ucontrol); 1019 } 1020 1021 static int cs43130_pcm_ch_put(struct snd_kcontrol *kcontrol, 1022 struct snd_ctl_elem_value *ucontrol) 1023 { 1024 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1025 unsigned int *item = ucontrol->value.enumerated.item; 1026 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1027 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 1028 unsigned int val; 1029 1030 if (item[0] >= e->items) 1031 return -EINVAL; 1032 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 1033 1034 switch (cs43130->dev_id) { 1035 case CS43131_CHIP_ID: 1036 case CS43198_CHIP_ID: 1037 if (val >= 2) 1038 regmap_multi_reg_write(cs43130->regmap, pcm_ch_en_seq, 1039 ARRAY_SIZE(pcm_ch_en_seq)); 1040 else 1041 regmap_multi_reg_write(cs43130->regmap, pcm_ch_dis_seq, 1042 ARRAY_SIZE(pcm_ch_dis_seq)); 1043 break; 1044 } 1045 1046 return snd_soc_put_enum_double(kcontrol, ucontrol); 1047 } 1048 1049 static SOC_ENUM_SINGLE_DECL(pcm_ch_enum, CS43130_PCM_PATH_CTL_2, 0, 1050 pcm_ch_text); 1051 1052 static const char * const pcm_spd_texts[] = { 1053 "Fast", 1054 "Slow", 1055 }; 1056 1057 static SOC_ENUM_SINGLE_DECL(pcm_spd_enum, CS43130_PCM_FILT_OPT, 7, 1058 pcm_spd_texts); 1059 1060 static const char * const dsd_texts[] = { 1061 "Off", 1062 "BCKA Mode", 1063 "BCKD Mode", 1064 }; 1065 1066 static const unsigned int dsd_values[] = { 1067 CS43130_DSD_SRC_DSD, 1068 CS43130_DSD_SRC_ASP, 1069 CS43130_DSD_SRC_XSP, 1070 }; 1071 1072 static SOC_VALUE_ENUM_SINGLE_DECL(dsd_enum, CS43130_DSD_INT_CFG, 0, 0x03, 1073 dsd_texts, dsd_values); 1074 1075 static const struct snd_kcontrol_new cs43130_snd_controls[] = { 1076 SOC_DOUBLE_R_TLV("Master Playback Volume", 1077 CS43130_PCM_VOL_A, CS43130_PCM_VOL_B, 0, 0xFF, 1, 1078 pcm_vol_tlv), 1079 SOC_DOUBLE_R_TLV("Master DSD Playback Volume", 1080 CS43130_DSD_VOL_A, CS43130_DSD_VOL_B, 0, 0xFF, 1, 1081 pcm_vol_tlv), 1082 SOC_ENUM_EXT("PCM Ch Select", pcm_ch_enum, cs43130_pcm_ch_get, 1083 cs43130_pcm_ch_put), 1084 SOC_ENUM("PCM Filter Speed", pcm_spd_enum), 1085 SOC_SINGLE("PCM Phase Compensation", CS43130_PCM_FILT_OPT, 6, 1, 0), 1086 SOC_SINGLE("PCM Nonoversample Emulate", CS43130_PCM_FILT_OPT, 5, 1, 0), 1087 SOC_SINGLE("PCM High-pass Filter", CS43130_PCM_FILT_OPT, 1, 1, 0), 1088 SOC_SINGLE("PCM De-emphasis Filter", CS43130_PCM_FILT_OPT, 0, 1, 0), 1089 SOC_ENUM("DSD Phase Modulation", dsd_enum), 1090 }; 1091 1092 static const struct reg_sequence pcm_seq[] = { 1093 {CS43130_DXD1, 0x99}, 1094 {CS43130_DXD7, 0x01}, 1095 {CS43130_DXD8, 0}, 1096 {CS43130_DXD9, 0x01}, 1097 {CS43130_DXD3, 0x12}, 1098 {CS43130_DXD4, 0}, 1099 {CS43130_DXD10, 0x28}, 1100 {CS43130_DXD11, 0x28}, 1101 {CS43130_DXD1, 0}, 1102 }; 1103 1104 static const struct reg_sequence dsd_seq[] = { 1105 {CS43130_DXD1, 0x99}, 1106 {CS43130_DXD7, 0x01}, 1107 {CS43130_DXD8, 0}, 1108 {CS43130_DXD9, 0x01}, 1109 {CS43130_DXD3, 0x12}, 1110 {CS43130_DXD4, 0}, 1111 {CS43130_DXD10, 0x1E}, 1112 {CS43130_DXD11, 0x20}, 1113 {CS43130_DXD1, 0}, 1114 }; 1115 1116 static const struct reg_sequence pop_free_seq[] = { 1117 {CS43130_DXD1, 0x99}, 1118 {CS43130_DXD12, 0x0A}, 1119 {CS43130_DXD1, 0}, 1120 }; 1121 1122 static const struct reg_sequence pop_free_seq2[] = { 1123 {CS43130_DXD1, 0x99}, 1124 {CS43130_DXD13, 0x20}, 1125 {CS43130_DXD1, 0}, 1126 }; 1127 1128 static const struct reg_sequence mute_seq[] = { 1129 {CS43130_DXD1, 0x99}, 1130 {CS43130_DXD3, 0x12}, 1131 {CS43130_DXD5, 0x02}, 1132 {CS43130_DXD4, 0x12}, 1133 {CS43130_DXD1, 0}, 1134 }; 1135 1136 static const struct reg_sequence unmute_seq[] = { 1137 {CS43130_DXD1, 0x99}, 1138 {CS43130_DXD3, 0x10}, 1139 {CS43130_DXD5, 0}, 1140 {CS43130_DXD4, 0x16}, 1141 {CS43130_DXD1, 0}, 1142 }; 1143 1144 static int cs43130_dsd_event(struct snd_soc_dapm_widget *w, 1145 struct snd_kcontrol *kcontrol, int event) 1146 { 1147 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1148 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 1149 1150 switch (event) { 1151 case SND_SOC_DAPM_PRE_PMU: 1152 switch (cs43130->dev_id) { 1153 case CS43130_CHIP_ID: 1154 case CS4399_CHIP_ID: 1155 regmap_multi_reg_write(cs43130->regmap, dsd_seq, 1156 ARRAY_SIZE(dsd_seq)); 1157 break; 1158 } 1159 break; 1160 case SND_SOC_DAPM_POST_PMU: 1161 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_1, 1162 CS43130_MUTE_MASK, 0); 1163 switch (cs43130->dev_id) { 1164 case CS43130_CHIP_ID: 1165 case CS4399_CHIP_ID: 1166 regmap_multi_reg_write(cs43130->regmap, unmute_seq, 1167 ARRAY_SIZE(unmute_seq)); 1168 break; 1169 } 1170 break; 1171 case SND_SOC_DAPM_PRE_PMD: 1172 switch (cs43130->dev_id) { 1173 case CS43130_CHIP_ID: 1174 case CS4399_CHIP_ID: 1175 regmap_multi_reg_write(cs43130->regmap, mute_seq, 1176 ARRAY_SIZE(mute_seq)); 1177 regmap_update_bits(cs43130->regmap, 1178 CS43130_DSD_PATH_CTL_1, 1179 CS43130_MUTE_MASK, CS43130_MUTE_EN); 1180 /* 1181 * DSD Power Down Sequence 1182 * According to Design, 130ms is preferred. 1183 */ 1184 msleep(130); 1185 break; 1186 case CS43131_CHIP_ID: 1187 case CS43198_CHIP_ID: 1188 regmap_update_bits(cs43130->regmap, 1189 CS43130_DSD_PATH_CTL_1, 1190 CS43130_MUTE_MASK, CS43130_MUTE_EN); 1191 break; 1192 } 1193 break; 1194 default: 1195 dev_err(codec->dev, "Invalid event = 0x%x\n", event); 1196 return -EINVAL; 1197 } 1198 return 0; 1199 } 1200 1201 static int cs43130_pcm_event(struct snd_soc_dapm_widget *w, 1202 struct snd_kcontrol *kcontrol, int event) 1203 { 1204 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1205 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 1206 1207 switch (event) { 1208 case SND_SOC_DAPM_PRE_PMU: 1209 switch (cs43130->dev_id) { 1210 case CS43130_CHIP_ID: 1211 case CS4399_CHIP_ID: 1212 regmap_multi_reg_write(cs43130->regmap, pcm_seq, 1213 ARRAY_SIZE(pcm_seq)); 1214 break; 1215 } 1216 break; 1217 case SND_SOC_DAPM_POST_PMU: 1218 regmap_update_bits(cs43130->regmap, CS43130_PCM_PATH_CTL_1, 1219 CS43130_MUTE_MASK, 0); 1220 switch (cs43130->dev_id) { 1221 case CS43130_CHIP_ID: 1222 case CS4399_CHIP_ID: 1223 regmap_multi_reg_write(cs43130->regmap, unmute_seq, 1224 ARRAY_SIZE(unmute_seq)); 1225 break; 1226 } 1227 break; 1228 case SND_SOC_DAPM_PRE_PMD: 1229 switch (cs43130->dev_id) { 1230 case CS43130_CHIP_ID: 1231 case CS4399_CHIP_ID: 1232 regmap_multi_reg_write(cs43130->regmap, mute_seq, 1233 ARRAY_SIZE(mute_seq)); 1234 regmap_update_bits(cs43130->regmap, 1235 CS43130_PCM_PATH_CTL_1, 1236 CS43130_MUTE_MASK, CS43130_MUTE_EN); 1237 /* 1238 * PCM Power Down Sequence 1239 * According to Design, 130ms is preferred. 1240 */ 1241 msleep(130); 1242 break; 1243 case CS43131_CHIP_ID: 1244 case CS43198_CHIP_ID: 1245 regmap_update_bits(cs43130->regmap, 1246 CS43130_PCM_PATH_CTL_1, 1247 CS43130_MUTE_MASK, CS43130_MUTE_EN); 1248 break; 1249 } 1250 break; 1251 default: 1252 dev_err(codec->dev, "Invalid event = 0x%x\n", event); 1253 return -EINVAL; 1254 } 1255 return 0; 1256 } 1257 1258 static const struct reg_sequence dac_postpmu_seq[] = { 1259 {CS43130_DXD9, 0x0C}, 1260 {CS43130_DXD3, 0x10}, 1261 {CS43130_DXD4, 0x20}, 1262 }; 1263 1264 static const struct reg_sequence dac_postpmd_seq[] = { 1265 {CS43130_DXD1, 0x99}, 1266 {CS43130_DXD6, 0x01}, 1267 {CS43130_DXD1, 0}, 1268 }; 1269 1270 static int cs43130_dac_event(struct snd_soc_dapm_widget *w, 1271 struct snd_kcontrol *kcontrol, int event) 1272 { 1273 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1274 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 1275 1276 switch (event) { 1277 case SND_SOC_DAPM_PRE_PMU: 1278 switch (cs43130->dev_id) { 1279 case CS43130_CHIP_ID: 1280 case CS4399_CHIP_ID: 1281 regmap_multi_reg_write(cs43130->regmap, pop_free_seq, 1282 ARRAY_SIZE(pop_free_seq)); 1283 break; 1284 case CS43131_CHIP_ID: 1285 case CS43198_CHIP_ID: 1286 regmap_multi_reg_write(cs43130->regmap, pop_free_seq2, 1287 ARRAY_SIZE(pop_free_seq2)); 1288 break; 1289 } 1290 break; 1291 case SND_SOC_DAPM_POST_PMU: 1292 usleep_range(10000, 10050); 1293 1294 regmap_write(cs43130->regmap, CS43130_DXD1, 0x99); 1295 1296 switch (cs43130->dev_id) { 1297 case CS43130_CHIP_ID: 1298 case CS4399_CHIP_ID: 1299 regmap_multi_reg_write(cs43130->regmap, dac_postpmu_seq, 1300 ARRAY_SIZE(dac_postpmu_seq)); 1301 /* 1302 * Per datasheet, Sec. PCM Power-Up Sequence. 1303 * According to Design, CS43130_DXD12 must be 0 to meet 1304 * THDN and Dynamic Range spec. 1305 */ 1306 msleep(1000); 1307 regmap_write(cs43130->regmap, CS43130_DXD12, 0); 1308 break; 1309 case CS43131_CHIP_ID: 1310 case CS43198_CHIP_ID: 1311 usleep_range(12000, 12010); 1312 regmap_write(cs43130->regmap, CS43130_DXD13, 0); 1313 break; 1314 } 1315 1316 regmap_write(cs43130->regmap, CS43130_DXD1, 0); 1317 break; 1318 case SND_SOC_DAPM_POST_PMD: 1319 switch (cs43130->dev_id) { 1320 case CS43130_CHIP_ID: 1321 case CS4399_CHIP_ID: 1322 regmap_multi_reg_write(cs43130->regmap, dac_postpmd_seq, 1323 ARRAY_SIZE(dac_postpmd_seq)); 1324 break; 1325 } 1326 break; 1327 default: 1328 dev_err(codec->dev, "Invalid DAC event = 0x%x\n", event); 1329 return -EINVAL; 1330 } 1331 return 0; 1332 } 1333 1334 static const struct reg_sequence hpin_prepmd_seq[] = { 1335 {CS43130_DXD1, 0x99}, 1336 {CS43130_DXD15, 0x64}, 1337 {CS43130_DXD14, 0}, 1338 {CS43130_DXD2, 0}, 1339 {CS43130_DXD1, 0}, 1340 }; 1341 1342 static const struct reg_sequence hpin_postpmu_seq[] = { 1343 {CS43130_DXD1, 0x99}, 1344 {CS43130_DXD2, 1}, 1345 {CS43130_DXD14, 0xDC}, 1346 {CS43130_DXD15, 0xE4}, 1347 {CS43130_DXD1, 0}, 1348 }; 1349 1350 static int cs43130_hpin_event(struct snd_soc_dapm_widget *w, 1351 struct snd_kcontrol *kcontrol, int event) 1352 { 1353 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1354 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 1355 1356 switch (event) { 1357 case SND_SOC_DAPM_POST_PMD: 1358 regmap_multi_reg_write(cs43130->regmap, hpin_prepmd_seq, 1359 ARRAY_SIZE(hpin_prepmd_seq)); 1360 break; 1361 case SND_SOC_DAPM_PRE_PMU: 1362 regmap_multi_reg_write(cs43130->regmap, hpin_postpmu_seq, 1363 ARRAY_SIZE(hpin_postpmu_seq)); 1364 break; 1365 default: 1366 dev_err(codec->dev, "Invalid HPIN event = 0x%x\n", event); 1367 return -EINVAL; 1368 } 1369 return 0; 1370 } 1371 1372 static const struct snd_soc_dapm_widget digital_hp_widgets[] = { 1373 SND_SOC_DAPM_OUTPUT("HPOUTA"), 1374 SND_SOC_DAPM_OUTPUT("HPOUTB"), 1375 1376 SND_SOC_DAPM_AIF_IN_E("ASPIN PCM", NULL, 0, CS43130_PWDN_CTL, 1377 CS43130_PDN_ASP_SHIFT, 1, cs43130_pcm_event, 1378 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1379 SND_SOC_DAPM_PRE_PMD)), 1380 1381 SND_SOC_DAPM_AIF_IN_E("ASPIN DoP", NULL, 0, CS43130_PWDN_CTL, 1382 CS43130_PDN_ASP_SHIFT, 1, cs43130_dsd_event, 1383 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1384 SND_SOC_DAPM_PRE_PMD)), 1385 1386 SND_SOC_DAPM_AIF_IN_E("XSPIN DoP", NULL, 0, CS43130_PWDN_CTL, 1387 CS43130_PDN_XSP_SHIFT, 1, cs43130_dsd_event, 1388 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1389 SND_SOC_DAPM_PRE_PMD)), 1390 1391 SND_SOC_DAPM_AIF_IN_E("XSPIN DSD", NULL, 0, CS43130_PWDN_CTL, 1392 CS43130_PDN_DSDIF_SHIFT, 1, cs43130_dsd_event, 1393 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1394 SND_SOC_DAPM_PRE_PMD)), 1395 1396 SND_SOC_DAPM_DAC("DSD", NULL, CS43130_DSD_PATH_CTL_2, 1397 CS43130_DSD_EN_SHIFT, 0), 1398 1399 SND_SOC_DAPM_DAC_E("HiFi DAC", NULL, CS43130_PWDN_CTL, 1400 CS43130_PDN_HP_SHIFT, 1, cs43130_dac_event, 1401 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1402 SND_SOC_DAPM_POST_PMD)), 1403 }; 1404 1405 static const struct snd_soc_dapm_widget analog_hp_widgets[] = { 1406 SND_SOC_DAPM_DAC_E("Analog Playback", NULL, CS43130_HP_OUT_CTL_1, 1407 CS43130_HP_IN_EN_SHIFT, 0, cs43130_hpin_event, 1408 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)), 1409 }; 1410 1411 static struct snd_soc_dapm_widget all_hp_widgets[ 1412 ARRAY_SIZE(digital_hp_widgets) + 1413 ARRAY_SIZE(analog_hp_widgets)]; 1414 1415 static const struct snd_soc_dapm_route digital_hp_routes[] = { 1416 {"ASPIN PCM", NULL, "ASP PCM Playback"}, 1417 {"ASPIN DoP", NULL, "ASP DoP Playback"}, 1418 {"XSPIN DoP", NULL, "XSP DoP Playback"}, 1419 {"XSPIN DSD", NULL, "XSP DSD Playback"}, 1420 {"DSD", NULL, "ASPIN DoP"}, 1421 {"DSD", NULL, "XSPIN DoP"}, 1422 {"DSD", NULL, "XSPIN DSD"}, 1423 {"HiFi DAC", NULL, "ASPIN PCM"}, 1424 {"HiFi DAC", NULL, "DSD"}, 1425 {"HPOUTA", NULL, "HiFi DAC"}, 1426 {"HPOUTB", NULL, "HiFi DAC"}, 1427 }; 1428 1429 static const struct snd_soc_dapm_route analog_hp_routes[] = { 1430 {"HPOUTA", NULL, "Analog Playback"}, 1431 {"HPOUTB", NULL, "Analog Playback"}, 1432 }; 1433 1434 static struct snd_soc_dapm_route all_hp_routes[ 1435 ARRAY_SIZE(digital_hp_routes) + 1436 ARRAY_SIZE(analog_hp_routes)]; 1437 1438 static const unsigned int cs43130_asp_src_rates[] = { 1439 32000, 44100, 48000, 88200, 96000, 176400, 192000, 352800, 384000 1440 }; 1441 1442 static const struct snd_pcm_hw_constraint_list cs43130_asp_constraints = { 1443 .count = ARRAY_SIZE(cs43130_asp_src_rates), 1444 .list = cs43130_asp_src_rates, 1445 }; 1446 1447 static int cs43130_pcm_startup(struct snd_pcm_substream *substream, 1448 struct snd_soc_dai *dai) 1449 { 1450 return snd_pcm_hw_constraint_list(substream->runtime, 0, 1451 SNDRV_PCM_HW_PARAM_RATE, 1452 &cs43130_asp_constraints); 1453 } 1454 1455 static const unsigned int cs43130_dop_src_rates[] = { 1456 176400, 352800, 1457 }; 1458 1459 static const struct snd_pcm_hw_constraint_list cs43130_dop_constraints = { 1460 .count = ARRAY_SIZE(cs43130_dop_src_rates), 1461 .list = cs43130_dop_src_rates, 1462 }; 1463 1464 static int cs43130_dop_startup(struct snd_pcm_substream *substream, 1465 struct snd_soc_dai *dai) 1466 { 1467 return snd_pcm_hw_constraint_list(substream->runtime, 0, 1468 SNDRV_PCM_HW_PARAM_RATE, 1469 &cs43130_dop_constraints); 1470 } 1471 1472 static int cs43130_pcm_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1473 { 1474 struct snd_soc_codec *codec = codec_dai->codec; 1475 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 1476 1477 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1478 case SND_SOC_DAIFMT_CBS_CFS: 1479 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS; 1480 break; 1481 case SND_SOC_DAIFMT_CBM_CFM: 1482 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM; 1483 break; 1484 default: 1485 dev_err(codec->dev, "unsupported mode\n"); 1486 return -EINVAL; 1487 } 1488 1489 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1490 case SND_SOC_DAIFMT_I2S: 1491 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S; 1492 break; 1493 case SND_SOC_DAIFMT_LEFT_J: 1494 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J; 1495 break; 1496 case SND_SOC_DAIFMT_DSP_A: 1497 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_A; 1498 break; 1499 case SND_SOC_DAIFMT_DSP_B: 1500 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_B; 1501 break; 1502 default: 1503 dev_err(codec->dev, 1504 "unsupported audio format\n"); 1505 return -EINVAL; 1506 } 1507 1508 dev_dbg(codec->dev, "dai_id = %d, dai_mode = %u, dai_format = %u\n", 1509 codec_dai->id, 1510 cs43130->dais[codec_dai->id].dai_mode, 1511 cs43130->dais[codec_dai->id].dai_format); 1512 1513 return 0; 1514 } 1515 1516 static int cs43130_dsd_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1517 { 1518 struct snd_soc_codec *codec = codec_dai->codec; 1519 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 1520 1521 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1522 case SND_SOC_DAIFMT_CBS_CFS: 1523 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS; 1524 break; 1525 case SND_SOC_DAIFMT_CBM_CFM: 1526 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM; 1527 break; 1528 default: 1529 dev_err(codec->dev, "Unsupported DAI format.\n"); 1530 return -EINVAL; 1531 } 1532 1533 dev_dbg(codec->dev, "dai_mode = 0x%x\n", 1534 cs43130->dais[codec_dai->id].dai_mode); 1535 1536 return 0; 1537 } 1538 1539 static int cs43130_set_sysclk(struct snd_soc_dai *codec_dai, 1540 int clk_id, unsigned int freq, int dir) 1541 { 1542 struct snd_soc_codec *codec = codec_dai->codec; 1543 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 1544 1545 cs43130->dais[codec_dai->id].sclk = freq; 1546 dev_dbg(codec->dev, "dai_id = %d, sclk = %u\n", codec_dai->id, 1547 cs43130->dais[codec_dai->id].sclk); 1548 1549 return 0; 1550 } 1551 1552 static const struct snd_soc_dai_ops cs43130_pcm_ops = { 1553 .startup = cs43130_pcm_startup, 1554 .hw_params = cs43130_hw_params, 1555 .hw_free = cs43130_hw_free, 1556 .set_sysclk = cs43130_set_sysclk, 1557 .set_fmt = cs43130_pcm_set_fmt, 1558 }; 1559 1560 static const struct snd_soc_dai_ops cs43130_dop_ops = { 1561 .startup = cs43130_dop_startup, 1562 .hw_params = cs43130_hw_params, 1563 .hw_free = cs43130_hw_free, 1564 .set_sysclk = cs43130_set_sysclk, 1565 .set_fmt = cs43130_pcm_set_fmt, 1566 }; 1567 1568 static const struct snd_soc_dai_ops cs43130_dsd_ops = { 1569 .startup = cs43130_dop_startup, 1570 .hw_params = cs43130_dsd_hw_params, 1571 .hw_free = cs43130_hw_free, 1572 .set_fmt = cs43130_dsd_set_fmt, 1573 }; 1574 1575 static struct snd_soc_dai_driver cs43130_dai[] = { 1576 { 1577 .name = "cs43130-asp-pcm", 1578 .id = CS43130_ASP_PCM_DAI, 1579 .playback = { 1580 .stream_name = "ASP PCM Playback", 1581 .channels_min = 1, 1582 .channels_max = 2, 1583 .rates = SNDRV_PCM_RATE_KNOT, 1584 .formats = CS43130_PCM_FORMATS, 1585 }, 1586 .ops = &cs43130_pcm_ops, 1587 .symmetric_rates = 1, 1588 }, 1589 { 1590 .name = "cs43130-asp-dop", 1591 .id = CS43130_ASP_DOP_DAI, 1592 .playback = { 1593 .stream_name = "ASP DoP Playback", 1594 .channels_min = 1, 1595 .channels_max = 2, 1596 .rates = SNDRV_PCM_RATE_KNOT, 1597 .formats = CS43130_DOP_FORMATS, 1598 }, 1599 .ops = &cs43130_dop_ops, 1600 .symmetric_rates = 1, 1601 }, 1602 { 1603 .name = "cs43130-xsp-dop", 1604 .id = CS43130_XSP_DOP_DAI, 1605 .playback = { 1606 .stream_name = "XSP DoP Playback", 1607 .channels_min = 1, 1608 .channels_max = 2, 1609 .rates = SNDRV_PCM_RATE_KNOT, 1610 .formats = CS43130_DOP_FORMATS, 1611 }, 1612 .ops = &cs43130_dop_ops, 1613 .symmetric_rates = 1, 1614 }, 1615 { 1616 .name = "cs43130-xsp-dsd", 1617 .id = CS43130_XSP_DSD_DAI, 1618 .playback = { 1619 .stream_name = "XSP DSD Playback", 1620 .channels_min = 1, 1621 .channels_max = 2, 1622 .rates = SNDRV_PCM_RATE_KNOT, 1623 .formats = CS43130_DOP_FORMATS, 1624 }, 1625 .ops = &cs43130_dsd_ops, 1626 }, 1627 1628 }; 1629 1630 static int cs43130_codec_set_sysclk(struct snd_soc_codec *codec, 1631 int clk_id, int source, unsigned int freq, 1632 int dir) 1633 { 1634 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 1635 1636 dev_dbg(codec->dev, "clk_id = %d, source = %d, freq = %d, dir = %d\n", 1637 clk_id, source, freq, dir); 1638 1639 switch (freq) { 1640 case CS43130_MCLK_22M: 1641 case CS43130_MCLK_24M: 1642 cs43130->mclk = freq; 1643 break; 1644 default: 1645 dev_err(codec->dev, "Invalid MCLK INT freq: %u\n", freq); 1646 return -EINVAL; 1647 } 1648 1649 if (source == CS43130_MCLK_SRC_EXT) { 1650 cs43130->pll_bypass = true; 1651 } else { 1652 dev_err(codec->dev, "Invalid MCLK source\n"); 1653 return -EINVAL; 1654 } 1655 1656 return 0; 1657 } 1658 1659 static inline u16 cs43130_get_ac_reg_val(u16 ac_freq) 1660 { 1661 /* AC freq is counted in 5.94Hz step. */ 1662 return ac_freq / 6; 1663 } 1664 1665 static int cs43130_show_dc(struct device *dev, char *buf, u8 ch) 1666 { 1667 struct i2c_client *client = to_i2c_client(dev); 1668 struct cs43130_private *cs43130 = i2c_get_clientdata(client); 1669 1670 if (!cs43130->hpload_done) 1671 return scnprintf(buf, PAGE_SIZE, "NO_HPLOAD\n"); 1672 else 1673 return scnprintf(buf, PAGE_SIZE, "%u\n", 1674 cs43130->hpload_dc[ch]); 1675 } 1676 1677 static ssize_t cs43130_show_dc_l(struct device *dev, 1678 struct device_attribute *attr, char *buf) 1679 { 1680 return cs43130_show_dc(dev, buf, HP_LEFT); 1681 } 1682 1683 static ssize_t cs43130_show_dc_r(struct device *dev, 1684 struct device_attribute *attr, char *buf) 1685 { 1686 return cs43130_show_dc(dev, buf, HP_RIGHT); 1687 } 1688 1689 static u16 const cs43130_ac_freq[CS43130_AC_FREQ] = { 1690 24, 1691 43, 1692 93, 1693 200, 1694 431, 1695 928, 1696 2000, 1697 4309, 1698 9283, 1699 20000, 1700 }; 1701 1702 static int cs43130_show_ac(struct device *dev, char *buf, u8 ch) 1703 { 1704 int i, j = 0, tmp; 1705 struct i2c_client *client = to_i2c_client(dev); 1706 struct cs43130_private *cs43130 = i2c_get_clientdata(client); 1707 1708 if (cs43130->hpload_done && cs43130->ac_meas) { 1709 for (i = 0; i < ARRAY_SIZE(cs43130_ac_freq); i++) { 1710 tmp = scnprintf(buf + j, PAGE_SIZE - j, "%u\n", 1711 cs43130->hpload_ac[i][ch]); 1712 if (!tmp) 1713 break; 1714 1715 j += tmp; 1716 } 1717 1718 return j; 1719 } else { 1720 return scnprintf(buf, PAGE_SIZE, "NO_HPLOAD\n"); 1721 } 1722 } 1723 1724 static ssize_t cs43130_show_ac_l(struct device *dev, 1725 struct device_attribute *attr, char *buf) 1726 { 1727 return cs43130_show_ac(dev, buf, HP_LEFT); 1728 } 1729 1730 static ssize_t cs43130_show_ac_r(struct device *dev, 1731 struct device_attribute *attr, char *buf) 1732 { 1733 return cs43130_show_ac(dev, buf, HP_RIGHT); 1734 } 1735 1736 static DEVICE_ATTR(hpload_dc_l, S_IRUGO, cs43130_show_dc_l, NULL); 1737 static DEVICE_ATTR(hpload_dc_r, S_IRUGO, cs43130_show_dc_r, NULL); 1738 static DEVICE_ATTR(hpload_ac_l, S_IRUGO, cs43130_show_ac_l, NULL); 1739 static DEVICE_ATTR(hpload_ac_r, S_IRUGO, cs43130_show_ac_r, NULL); 1740 1741 static struct reg_sequence hp_en_cal_seq[] = { 1742 {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL}, 1743 {CS43130_HP_MEAS_LOAD_1, 0}, 1744 {CS43130_HP_MEAS_LOAD_2, 0}, 1745 {CS43130_INT_MASK_4, 0}, 1746 {CS43130_DXD1, 0x99}, 1747 {CS43130_DXD16, 0xBB}, 1748 {CS43130_DXD12, 0x01}, 1749 {CS43130_DXD19, 0xCB}, 1750 {CS43130_DXD17, 0x95}, 1751 {CS43130_DXD18, 0x0B}, 1752 {CS43130_DXD1, 0}, 1753 {CS43130_HP_LOAD_1, 0x80}, 1754 }; 1755 1756 static struct reg_sequence hp_en_cal_seq2[] = { 1757 {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL}, 1758 {CS43130_HP_MEAS_LOAD_1, 0}, 1759 {CS43130_HP_MEAS_LOAD_2, 0}, 1760 {CS43130_INT_MASK_4, 0}, 1761 {CS43130_HP_LOAD_1, 0x80}, 1762 }; 1763 1764 static struct reg_sequence hp_dis_cal_seq[] = { 1765 {CS43130_HP_LOAD_1, 0x80}, 1766 {CS43130_DXD1, 0x99}, 1767 {CS43130_DXD12, 0}, 1768 {CS43130_DXD1, 0}, 1769 {CS43130_HP_LOAD_1, 0}, 1770 }; 1771 1772 static struct reg_sequence hp_dis_cal_seq2[] = { 1773 {CS43130_HP_LOAD_1, 0x80}, 1774 {CS43130_HP_LOAD_1, 0}, 1775 }; 1776 1777 static struct reg_sequence hp_dc_ch_l_seq[] = { 1778 {CS43130_DXD1, 0x99}, 1779 {CS43130_DXD19, 0x0A}, 1780 {CS43130_DXD17, 0x93}, 1781 {CS43130_DXD18, 0x0A}, 1782 {CS43130_DXD1, 0}, 1783 {CS43130_HP_LOAD_1, 0x80}, 1784 {CS43130_HP_LOAD_1, 0x81}, 1785 }; 1786 1787 static struct reg_sequence hp_dc_ch_l_seq2[] = { 1788 {CS43130_HP_LOAD_1, 0x80}, 1789 {CS43130_HP_LOAD_1, 0x81}, 1790 }; 1791 1792 static struct reg_sequence hp_dc_ch_r_seq[] = { 1793 {CS43130_DXD1, 0x99}, 1794 {CS43130_DXD19, 0x8A}, 1795 {CS43130_DXD17, 0x15}, 1796 {CS43130_DXD18, 0x06}, 1797 {CS43130_DXD1, 0}, 1798 {CS43130_HP_LOAD_1, 0x90}, 1799 {CS43130_HP_LOAD_1, 0x91}, 1800 }; 1801 1802 static struct reg_sequence hp_dc_ch_r_seq2[] = { 1803 {CS43130_HP_LOAD_1, 0x90}, 1804 {CS43130_HP_LOAD_1, 0x91}, 1805 }; 1806 1807 static struct reg_sequence hp_ac_ch_l_seq[] = { 1808 {CS43130_DXD1, 0x99}, 1809 {CS43130_DXD19, 0x0A}, 1810 {CS43130_DXD17, 0x93}, 1811 {CS43130_DXD18, 0x0A}, 1812 {CS43130_DXD1, 0}, 1813 {CS43130_HP_LOAD_1, 0x80}, 1814 {CS43130_HP_LOAD_1, 0x82}, 1815 }; 1816 1817 static struct reg_sequence hp_ac_ch_l_seq2[] = { 1818 {CS43130_HP_LOAD_1, 0x80}, 1819 {CS43130_HP_LOAD_1, 0x82}, 1820 }; 1821 1822 static struct reg_sequence hp_ac_ch_r_seq[] = { 1823 {CS43130_DXD1, 0x99}, 1824 {CS43130_DXD19, 0x8A}, 1825 {CS43130_DXD17, 0x15}, 1826 {CS43130_DXD18, 0x06}, 1827 {CS43130_DXD1, 0}, 1828 {CS43130_HP_LOAD_1, 0x90}, 1829 {CS43130_HP_LOAD_1, 0x92}, 1830 }; 1831 1832 static struct reg_sequence hp_ac_ch_r_seq2[] = { 1833 {CS43130_HP_LOAD_1, 0x90}, 1834 {CS43130_HP_LOAD_1, 0x92}, 1835 }; 1836 1837 static struct reg_sequence hp_cln_seq[] = { 1838 {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL}, 1839 {CS43130_HP_MEAS_LOAD_1, 0}, 1840 {CS43130_HP_MEAS_LOAD_2, 0}, 1841 }; 1842 1843 struct reg_sequences { 1844 struct reg_sequence *seq; 1845 int size; 1846 unsigned int msk; 1847 }; 1848 1849 static struct reg_sequences hpload_seq1[] = { 1850 { 1851 .seq = hp_en_cal_seq, 1852 .size = ARRAY_SIZE(hp_en_cal_seq), 1853 .msk = CS43130_HPLOAD_ON_INT, 1854 }, 1855 { 1856 .seq = hp_dc_ch_l_seq, 1857 .size = ARRAY_SIZE(hp_dc_ch_l_seq), 1858 .msk = CS43130_HPLOAD_DC_INT, 1859 }, 1860 { 1861 .seq = hp_ac_ch_l_seq, 1862 .size = ARRAY_SIZE(hp_ac_ch_l_seq), 1863 .msk = CS43130_HPLOAD_AC_INT, 1864 }, 1865 { 1866 .seq = hp_dis_cal_seq, 1867 .size = ARRAY_SIZE(hp_dis_cal_seq), 1868 .msk = CS43130_HPLOAD_OFF_INT, 1869 }, 1870 { 1871 .seq = hp_en_cal_seq, 1872 .size = ARRAY_SIZE(hp_en_cal_seq), 1873 .msk = CS43130_HPLOAD_ON_INT, 1874 }, 1875 { 1876 .seq = hp_dc_ch_r_seq, 1877 .size = ARRAY_SIZE(hp_dc_ch_r_seq), 1878 .msk = CS43130_HPLOAD_DC_INT, 1879 }, 1880 { 1881 .seq = hp_ac_ch_r_seq, 1882 .size = ARRAY_SIZE(hp_ac_ch_r_seq), 1883 .msk = CS43130_HPLOAD_AC_INT, 1884 }, 1885 }; 1886 1887 static struct reg_sequences hpload_seq2[] = { 1888 { 1889 .seq = hp_en_cal_seq2, 1890 .size = ARRAY_SIZE(hp_en_cal_seq2), 1891 .msk = CS43130_HPLOAD_ON_INT, 1892 }, 1893 { 1894 .seq = hp_dc_ch_l_seq2, 1895 .size = ARRAY_SIZE(hp_dc_ch_l_seq2), 1896 .msk = CS43130_HPLOAD_DC_INT, 1897 }, 1898 { 1899 .seq = hp_ac_ch_l_seq2, 1900 .size = ARRAY_SIZE(hp_ac_ch_l_seq2), 1901 .msk = CS43130_HPLOAD_AC_INT, 1902 }, 1903 { 1904 .seq = hp_dis_cal_seq2, 1905 .size = ARRAY_SIZE(hp_dis_cal_seq2), 1906 .msk = CS43130_HPLOAD_OFF_INT, 1907 }, 1908 { 1909 .seq = hp_en_cal_seq2, 1910 .size = ARRAY_SIZE(hp_en_cal_seq2), 1911 .msk = CS43130_HPLOAD_ON_INT, 1912 }, 1913 { 1914 .seq = hp_dc_ch_r_seq2, 1915 .size = ARRAY_SIZE(hp_dc_ch_r_seq2), 1916 .msk = CS43130_HPLOAD_DC_INT, 1917 }, 1918 { 1919 .seq = hp_ac_ch_r_seq2, 1920 .size = ARRAY_SIZE(hp_ac_ch_r_seq2), 1921 .msk = CS43130_HPLOAD_AC_INT, 1922 }, 1923 }; 1924 1925 static int cs43130_update_hpload(unsigned int msk, int ac_idx, 1926 struct cs43130_private *cs43130) 1927 { 1928 bool left_ch = true; 1929 unsigned int reg; 1930 u32 addr; 1931 u16 impedance; 1932 struct snd_soc_codec *codec = cs43130->codec; 1933 1934 switch (msk) { 1935 case CS43130_HPLOAD_DC_INT: 1936 case CS43130_HPLOAD_AC_INT: 1937 break; 1938 default: 1939 return 0; 1940 } 1941 1942 regmap_read(cs43130->regmap, CS43130_HP_LOAD_1, ®); 1943 if (reg & CS43130_HPLOAD_CHN_SEL) 1944 left_ch = false; 1945 1946 if (msk == CS43130_HPLOAD_DC_INT) 1947 addr = CS43130_HP_DC_STAT_1; 1948 else 1949 addr = CS43130_HP_AC_STAT_1; 1950 1951 regmap_read(cs43130->regmap, addr, ®); 1952 impedance = reg >> 3; 1953 regmap_read(cs43130->regmap, addr + 1, ®); 1954 impedance |= reg << 5; 1955 1956 if (msk == CS43130_HPLOAD_DC_INT) { 1957 if (left_ch) 1958 cs43130->hpload_dc[HP_LEFT] = impedance; 1959 else 1960 cs43130->hpload_dc[HP_RIGHT] = impedance; 1961 1962 dev_dbg(codec->dev, "HP DC impedance (Ch %u): %u\n", !left_ch, 1963 impedance); 1964 } else { 1965 if (left_ch) 1966 cs43130->hpload_ac[ac_idx][HP_LEFT] = impedance; 1967 else 1968 cs43130->hpload_ac[ac_idx][HP_RIGHT] = impedance; 1969 1970 dev_dbg(codec->dev, "HP AC (%u Hz) impedance (Ch %u): %u\n", 1971 cs43130->ac_freq[ac_idx], !left_ch, impedance); 1972 } 1973 1974 return 0; 1975 } 1976 1977 static int cs43130_hpload_proc(struct cs43130_private *cs43130, 1978 struct reg_sequence *seq, int seq_size, 1979 unsigned int rslt_msk, int ac_idx) 1980 { 1981 int ret; 1982 unsigned int msk; 1983 u16 ac_reg_val; 1984 struct snd_soc_codec *codec = cs43130->codec; 1985 1986 reinit_completion(&cs43130->hpload_evt); 1987 1988 if (rslt_msk == CS43130_HPLOAD_AC_INT) { 1989 ac_reg_val = cs43130_get_ac_reg_val(cs43130->ac_freq[ac_idx]); 1990 regmap_update_bits(cs43130->regmap, CS43130_HP_LOAD_1, 1991 CS43130_HPLOAD_AC_START, 0); 1992 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_1, 1993 CS43130_HP_MEAS_LOAD_MASK, 1994 ac_reg_val >> CS43130_HP_MEAS_LOAD_1_SHIFT); 1995 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_2, 1996 CS43130_HP_MEAS_LOAD_MASK, 1997 ac_reg_val >> CS43130_HP_MEAS_LOAD_2_SHIFT); 1998 } 1999 2000 regmap_multi_reg_write(cs43130->regmap, seq, 2001 seq_size); 2002 2003 ret = wait_for_completion_timeout(&cs43130->hpload_evt, 2004 msecs_to_jiffies(1000)); 2005 regmap_read(cs43130->regmap, CS43130_INT_MASK_4, &msk); 2006 if (!ret) { 2007 dev_err(codec->dev, "Timeout waiting for HPLOAD interrupt\n"); 2008 return -1; 2009 } 2010 2011 dev_dbg(codec->dev, "HP load stat: %x, INT_MASK_4: %x\n", 2012 cs43130->hpload_stat, msk); 2013 if ((cs43130->hpload_stat & (CS43130_HPLOAD_NO_DC_INT | 2014 CS43130_HPLOAD_UNPLUG_INT | 2015 CS43130_HPLOAD_OOR_INT)) || 2016 !(cs43130->hpload_stat & rslt_msk)) { 2017 dev_dbg(codec->dev, "HP load measure failed\n"); 2018 return -1; 2019 } 2020 2021 return 0; 2022 } 2023 2024 static const struct reg_sequence hv_seq[][2] = { 2025 { 2026 {CS43130_CLASS_H_CTL, 0x1C}, 2027 {CS43130_HP_OUT_CTL_1, 0x10}, 2028 }, 2029 { 2030 {CS43130_CLASS_H_CTL, 0x1E}, 2031 {CS43130_HP_OUT_CTL_1, 0x20}, 2032 }, 2033 { 2034 {CS43130_CLASS_H_CTL, 0x1E}, 2035 {CS43130_HP_OUT_CTL_1, 0x30}, 2036 }, 2037 }; 2038 2039 static int cs43130_set_hv(struct regmap *regmap, u16 hpload_dc, 2040 const u16 *dc_threshold) 2041 { 2042 int i; 2043 2044 for (i = 0; i < CS43130_DC_THRESHOLD; i++) { 2045 if (hpload_dc <= dc_threshold[i]) 2046 break; 2047 } 2048 2049 regmap_multi_reg_write(regmap, hv_seq[i], ARRAY_SIZE(hv_seq[i])); 2050 2051 return 0; 2052 } 2053 2054 static void cs43130_imp_meas(struct work_struct *wk) 2055 { 2056 unsigned int reg, seq_size; 2057 int i, ret, ac_idx; 2058 struct cs43130_private *cs43130; 2059 struct snd_soc_codec *codec; 2060 struct reg_sequences *hpload_seq; 2061 2062 cs43130 = container_of(wk, struct cs43130_private, work); 2063 codec = cs43130->codec; 2064 2065 if (!cs43130->mclk) 2066 return; 2067 2068 cs43130->hpload_done = false; 2069 2070 mutex_lock(&cs43130->clk_mutex); 2071 if (!cs43130->clk_req) { 2072 /* clk not in use */ 2073 cs43130_set_pll(codec, 0, 0, cs43130->mclk, CS43130_MCLK_22M); 2074 if (cs43130->pll_bypass) 2075 cs43130_change_clksrc(codec, CS43130_MCLK_SRC_EXT); 2076 else 2077 cs43130_change_clksrc(codec, CS43130_MCLK_SRC_PLL); 2078 } 2079 2080 cs43130->clk_req++; 2081 mutex_unlock(&cs43130->clk_mutex); 2082 2083 regmap_read(cs43130->regmap, CS43130_INT_STATUS_4, ®); 2084 2085 switch (cs43130->dev_id) { 2086 case CS43130_CHIP_ID: 2087 hpload_seq = hpload_seq1; 2088 seq_size = ARRAY_SIZE(hpload_seq1); 2089 break; 2090 case CS43131_CHIP_ID: 2091 hpload_seq = hpload_seq2; 2092 seq_size = ARRAY_SIZE(hpload_seq2); 2093 break; 2094 default: 2095 WARN(1, "Invalid dev_id for meas: %d", cs43130->dev_id); 2096 return; 2097 } 2098 2099 i = 0; 2100 ac_idx = 0; 2101 while (i < seq_size) { 2102 ret = cs43130_hpload_proc(cs43130, hpload_seq[i].seq, 2103 hpload_seq[i].size, 2104 hpload_seq[i].msk, ac_idx); 2105 if (ret < 0) 2106 goto exit; 2107 2108 cs43130_update_hpload(hpload_seq[i].msk, ac_idx, cs43130); 2109 2110 if (cs43130->ac_meas && 2111 hpload_seq[i].msk == CS43130_HPLOAD_AC_INT && 2112 ac_idx < CS43130_AC_FREQ - 1) { 2113 ac_idx++; 2114 } else { 2115 ac_idx = 0; 2116 i++; 2117 } 2118 } 2119 cs43130->hpload_done = true; 2120 2121 if (cs43130->hpload_dc[HP_LEFT] >= CS43130_LINEOUT_LOAD) 2122 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_LINEOUT, 2123 CS43130_JACK_MASK); 2124 else 2125 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_HEADPHONE, 2126 CS43130_JACK_MASK); 2127 2128 dev_dbg(codec->dev, "Set HP output control. DC threshold\n"); 2129 for (i = 0; i < CS43130_DC_THRESHOLD; i++) 2130 dev_dbg(codec->dev, "DC threshold[%d]: %u.\n", i, 2131 cs43130->dc_threshold[i]); 2132 2133 cs43130_set_hv(cs43130->regmap, cs43130->hpload_dc[HP_LEFT], 2134 cs43130->dc_threshold); 2135 2136 exit: 2137 switch (cs43130->dev_id) { 2138 case CS43130_CHIP_ID: 2139 cs43130_hpload_proc(cs43130, hp_dis_cal_seq, 2140 ARRAY_SIZE(hp_dis_cal_seq), 2141 CS43130_HPLOAD_OFF_INT, ac_idx); 2142 break; 2143 case CS43131_CHIP_ID: 2144 cs43130_hpload_proc(cs43130, hp_dis_cal_seq2, 2145 ARRAY_SIZE(hp_dis_cal_seq2), 2146 CS43130_HPLOAD_OFF_INT, ac_idx); 2147 break; 2148 } 2149 2150 regmap_multi_reg_write(cs43130->regmap, hp_cln_seq, 2151 ARRAY_SIZE(hp_cln_seq)); 2152 2153 mutex_lock(&cs43130->clk_mutex); 2154 cs43130->clk_req--; 2155 /* clk not in use */ 2156 if (!cs43130->clk_req) 2157 cs43130_change_clksrc(codec, CS43130_MCLK_SRC_RCO); 2158 mutex_unlock(&cs43130->clk_mutex); 2159 } 2160 2161 static irqreturn_t cs43130_irq_thread(int irq, void *data) 2162 { 2163 struct cs43130_private *cs43130 = (struct cs43130_private *)data; 2164 struct snd_soc_codec *codec = cs43130->codec; 2165 unsigned int stickies[CS43130_NUM_INT]; 2166 unsigned int irq_occurrence = 0; 2167 unsigned int masks[CS43130_NUM_INT]; 2168 int i, j; 2169 2170 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 2171 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1 + i, 2172 &stickies[i]); 2173 regmap_read(cs43130->regmap, CS43130_INT_MASK_1 + i, 2174 &masks[i]); 2175 } 2176 2177 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 2178 stickies[i] = stickies[i] & (~masks[i]); 2179 for (j = 0; j < 8; j++) 2180 irq_occurrence += (stickies[i] >> j) & 1; 2181 } 2182 dev_dbg(codec->dev, "number of interrupts occurred (%u)\n", 2183 irq_occurrence); 2184 2185 if (!irq_occurrence) 2186 return IRQ_NONE; 2187 2188 if (stickies[0] & CS43130_XTAL_RDY_INT) { 2189 complete(&cs43130->xtal_rdy); 2190 return IRQ_HANDLED; 2191 } 2192 2193 if (stickies[0] & CS43130_PLL_RDY_INT) { 2194 complete(&cs43130->pll_rdy); 2195 return IRQ_HANDLED; 2196 } 2197 2198 if (stickies[3] & CS43130_HPLOAD_NO_DC_INT) { 2199 cs43130->hpload_stat = stickies[3]; 2200 dev_err(codec->dev, 2201 "DC load has not completed before AC load (%x)\n", 2202 cs43130->hpload_stat); 2203 complete(&cs43130->hpload_evt); 2204 return IRQ_HANDLED; 2205 } 2206 2207 if (stickies[3] & CS43130_HPLOAD_UNPLUG_INT) { 2208 cs43130->hpload_stat = stickies[3]; 2209 dev_err(codec->dev, "HP unplugged during measurement (%x)\n", 2210 cs43130->hpload_stat); 2211 complete(&cs43130->hpload_evt); 2212 return IRQ_HANDLED; 2213 } 2214 2215 if (stickies[3] & CS43130_HPLOAD_OOR_INT) { 2216 cs43130->hpload_stat = stickies[3]; 2217 dev_err(codec->dev, "HP load out of range (%x)\n", 2218 cs43130->hpload_stat); 2219 complete(&cs43130->hpload_evt); 2220 return IRQ_HANDLED; 2221 } 2222 2223 if (stickies[3] & CS43130_HPLOAD_AC_INT) { 2224 cs43130->hpload_stat = stickies[3]; 2225 dev_dbg(codec->dev, "HP AC load measurement done (%x)\n", 2226 cs43130->hpload_stat); 2227 complete(&cs43130->hpload_evt); 2228 return IRQ_HANDLED; 2229 } 2230 2231 if (stickies[3] & CS43130_HPLOAD_DC_INT) { 2232 cs43130->hpload_stat = stickies[3]; 2233 dev_dbg(codec->dev, "HP DC load measurement done (%x)\n", 2234 cs43130->hpload_stat); 2235 complete(&cs43130->hpload_evt); 2236 return IRQ_HANDLED; 2237 } 2238 2239 if (stickies[3] & CS43130_HPLOAD_ON_INT) { 2240 cs43130->hpload_stat = stickies[3]; 2241 dev_dbg(codec->dev, "HP load state machine on done (%x)\n", 2242 cs43130->hpload_stat); 2243 complete(&cs43130->hpload_evt); 2244 return IRQ_HANDLED; 2245 } 2246 2247 if (stickies[3] & CS43130_HPLOAD_OFF_INT) { 2248 cs43130->hpload_stat = stickies[3]; 2249 dev_dbg(codec->dev, "HP load state machine off done (%x)\n", 2250 cs43130->hpload_stat); 2251 complete(&cs43130->hpload_evt); 2252 return IRQ_HANDLED; 2253 } 2254 2255 if (stickies[0] & CS43130_XTAL_ERR_INT) { 2256 dev_err(codec->dev, "Crystal err: clock is not running\n"); 2257 return IRQ_HANDLED; 2258 } 2259 2260 if (stickies[0] & CS43130_HP_UNPLUG_INT) { 2261 dev_dbg(codec->dev, "HP unplugged\n"); 2262 cs43130->hpload_done = false; 2263 snd_soc_jack_report(&cs43130->jack, 0, CS43130_JACK_MASK); 2264 return IRQ_HANDLED; 2265 } 2266 2267 if (stickies[0] & CS43130_HP_PLUG_INT) { 2268 if (cs43130->dc_meas && !cs43130->hpload_done && 2269 !work_busy(&cs43130->work)) { 2270 dev_dbg(codec->dev, "HP load queue work\n"); 2271 queue_work(cs43130->wq, &cs43130->work); 2272 } 2273 2274 snd_soc_jack_report(&cs43130->jack, SND_JACK_MECHANICAL, 2275 CS43130_JACK_MASK); 2276 return IRQ_HANDLED; 2277 } 2278 2279 return IRQ_NONE; 2280 } 2281 2282 static int cs43130_probe(struct snd_soc_codec *codec) 2283 { 2284 int ret; 2285 struct cs43130_private *cs43130 = snd_soc_codec_get_drvdata(codec); 2286 struct snd_soc_card *card = codec->component.card; 2287 unsigned int reg; 2288 2289 cs43130->codec = codec; 2290 2291 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) { 2292 regmap_update_bits(cs43130->regmap, CS43130_CRYSTAL_SET, 2293 CS43130_XTAL_IBIAS_MASK, 2294 cs43130->xtal_ibias); 2295 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2296 CS43130_XTAL_ERR_INT, 0); 2297 } 2298 2299 ret = snd_soc_card_jack_new(card, "Headphone", CS43130_JACK_MASK, 2300 &cs43130->jack, NULL, 0); 2301 if (ret < 0) { 2302 dev_err(codec->dev, "Cannot create jack\n"); 2303 return ret; 2304 } 2305 2306 cs43130->hpload_done = false; 2307 if (cs43130->dc_meas) { 2308 ret = device_create_file(codec->dev, &dev_attr_hpload_dc_l); 2309 if (ret < 0) 2310 return ret; 2311 2312 ret = device_create_file(codec->dev, &dev_attr_hpload_dc_r); 2313 if (ret < 0) 2314 return ret; 2315 2316 ret = device_create_file(codec->dev, &dev_attr_hpload_ac_l); 2317 if (ret < 0) 2318 return ret; 2319 2320 ret = device_create_file(codec->dev, &dev_attr_hpload_ac_r); 2321 if (ret < 0) 2322 return ret; 2323 2324 cs43130->wq = create_singlethread_workqueue("cs43130_hp"); 2325 INIT_WORK(&cs43130->work, cs43130_imp_meas); 2326 } 2327 2328 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, ®); 2329 regmap_read(cs43130->regmap, CS43130_HP_STATUS, ®); 2330 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2331 CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, 0); 2332 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT, 2333 CS43130_HP_DETECT_CTRL_MASK, 0); 2334 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT, 2335 CS43130_HP_DETECT_CTRL_MASK, 2336 CS43130_HP_DETECT_CTRL_MASK); 2337 2338 return 0; 2339 } 2340 2341 static struct snd_soc_codec_driver soc_codec_dev_cs43130 = { 2342 .probe = cs43130_probe, 2343 .component_driver = { 2344 .controls = cs43130_snd_controls, 2345 .num_controls = ARRAY_SIZE(cs43130_snd_controls), 2346 }, 2347 .set_sysclk = cs43130_codec_set_sysclk, 2348 .set_pll = cs43130_set_pll, 2349 }; 2350 2351 static const struct regmap_config cs43130_regmap = { 2352 .reg_bits = 24, 2353 .pad_bits = 8, 2354 .val_bits = 8, 2355 2356 .max_register = CS43130_LASTREG, 2357 .reg_defaults = cs43130_reg_defaults, 2358 .num_reg_defaults = ARRAY_SIZE(cs43130_reg_defaults), 2359 .readable_reg = cs43130_readable_register, 2360 .precious_reg = cs43130_precious_register, 2361 .volatile_reg = cs43130_volatile_register, 2362 .cache_type = REGCACHE_RBTREE, 2363 .use_single_rw = true, /* needed for regcache_sync */ 2364 }; 2365 2366 static u16 const cs43130_dc_threshold[CS43130_DC_THRESHOLD] = { 2367 50, 2368 120, 2369 }; 2370 2371 static int cs43130_handle_device_data(struct i2c_client *i2c_client, 2372 struct cs43130_private *cs43130) 2373 { 2374 struct device_node *np = i2c_client->dev.of_node; 2375 unsigned int val; 2376 int i; 2377 2378 if (of_property_read_u32(np, "cirrus,xtal-ibias", &val) < 0) { 2379 /* Crystal is unused. System clock is used for external MCLK */ 2380 cs43130->xtal_ibias = CS43130_XTAL_UNUSED; 2381 return 0; 2382 } 2383 2384 switch (val) { 2385 case 1: 2386 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA; 2387 break; 2388 case 2: 2389 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA; 2390 break; 2391 case 3: 2392 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA; 2393 break; 2394 default: 2395 dev_err(&i2c_client->dev, 2396 "Invalid cirrus,xtal-ibias value: %d\n", val); 2397 return -EINVAL; 2398 } 2399 2400 cs43130->dc_meas = of_property_read_bool(np, "cirrus,dc-measure"); 2401 cs43130->ac_meas = of_property_read_bool(np, "cirrus,ac-measure"); 2402 2403 if (of_property_read_u16_array(np, "cirrus,ac-freq", cs43130->ac_freq, 2404 CS43130_AC_FREQ) < 0) { 2405 for (i = 0; i < CS43130_AC_FREQ; i++) 2406 cs43130->ac_freq[i] = cs43130_ac_freq[i]; 2407 } 2408 2409 if (of_property_read_u16_array(np, "cirrus,dc-threshold", 2410 cs43130->dc_threshold, 2411 CS43130_DC_THRESHOLD) < 0) { 2412 for (i = 0; i < CS43130_DC_THRESHOLD; i++) 2413 cs43130->dc_threshold[i] = cs43130_dc_threshold[i]; 2414 } 2415 2416 return 0; 2417 } 2418 2419 static int cs43130_i2c_probe(struct i2c_client *client, 2420 const struct i2c_device_id *id) 2421 { 2422 struct cs43130_private *cs43130; 2423 int ret; 2424 unsigned int devid = 0; 2425 unsigned int reg; 2426 int i; 2427 2428 cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL); 2429 if (!cs43130) 2430 return -ENOMEM; 2431 2432 i2c_set_clientdata(client, cs43130); 2433 2434 cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap); 2435 if (IS_ERR(cs43130->regmap)) { 2436 ret = PTR_ERR(cs43130->regmap); 2437 return ret; 2438 } 2439 2440 if (client->dev.of_node) { 2441 ret = cs43130_handle_device_data(client, cs43130); 2442 if (ret != 0) 2443 return ret; 2444 } 2445 for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++) 2446 cs43130->supplies[i].supply = cs43130_supply_names[i]; 2447 2448 ret = devm_regulator_bulk_get(&client->dev, 2449 ARRAY_SIZE(cs43130->supplies), 2450 cs43130->supplies); 2451 if (ret != 0) { 2452 dev_err(&client->dev, "Failed to request supplies: %d\n", ret); 2453 return ret; 2454 } 2455 ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies), 2456 cs43130->supplies); 2457 if (ret != 0) { 2458 dev_err(&client->dev, "Failed to enable supplies: %d\n", ret); 2459 return ret; 2460 } 2461 2462 cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev, 2463 "reset", GPIOD_OUT_LOW); 2464 if (IS_ERR(cs43130->reset_gpio)) 2465 return PTR_ERR(cs43130->reset_gpio); 2466 2467 gpiod_set_value_cansleep(cs43130->reset_gpio, 1); 2468 2469 usleep_range(2000, 2050); 2470 2471 ret = regmap_read(cs43130->regmap, CS43130_DEVID_AB, ®); 2472 2473 devid = (reg & 0xFF) << 12; 2474 ret = regmap_read(cs43130->regmap, CS43130_DEVID_CD, ®); 2475 devid |= (reg & 0xFF) << 4; 2476 ret = regmap_read(cs43130->regmap, CS43130_DEVID_E, ®); 2477 devid |= (reg & 0xF0) >> 4; 2478 2479 switch (devid) { 2480 case CS43130_CHIP_ID: 2481 case CS4399_CHIP_ID: 2482 case CS43131_CHIP_ID: 2483 case CS43198_CHIP_ID: 2484 break; 2485 default: 2486 dev_err(&client->dev, 2487 "CS43130 Device ID %X. Expected ID %X, %X, %X or %X\n", 2488 devid, CS43130_CHIP_ID, CS4399_CHIP_ID, 2489 CS43131_CHIP_ID, CS43198_CHIP_ID); 2490 ret = -ENODEV; 2491 goto err; 2492 } 2493 2494 cs43130->dev_id = devid; 2495 ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®); 2496 if (ret < 0) { 2497 dev_err(&client->dev, "Get Revision ID failed\n"); 2498 goto err; 2499 } 2500 2501 dev_info(&client->dev, 2502 "Cirrus Logic CS43130 (%x), Revision: %02X\n", devid, 2503 reg & 0xFF); 2504 2505 mutex_init(&cs43130->clk_mutex); 2506 2507 init_completion(&cs43130->xtal_rdy); 2508 init_completion(&cs43130->pll_rdy); 2509 init_completion(&cs43130->hpload_evt); 2510 2511 ret = devm_request_threaded_irq(&client->dev, client->irq, 2512 NULL, cs43130_irq_thread, 2513 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 2514 "cs43130", cs43130); 2515 if (ret != 0) { 2516 dev_err(&client->dev, "Failed to request IRQ: %d\n", ret); 2517 return ret; 2518 } 2519 2520 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO; 2521 2522 pm_runtime_set_autosuspend_delay(&client->dev, 100); 2523 pm_runtime_use_autosuspend(&client->dev); 2524 pm_runtime_set_active(&client->dev); 2525 pm_runtime_enable(&client->dev); 2526 2527 switch (cs43130->dev_id) { 2528 case CS43130_CHIP_ID: 2529 case CS43131_CHIP_ID: 2530 memcpy(all_hp_widgets, digital_hp_widgets, 2531 sizeof(digital_hp_widgets)); 2532 memcpy(all_hp_widgets + ARRAY_SIZE(digital_hp_widgets), 2533 analog_hp_widgets, sizeof(analog_hp_widgets)); 2534 memcpy(all_hp_routes, digital_hp_routes, 2535 sizeof(digital_hp_routes)); 2536 memcpy(all_hp_routes + ARRAY_SIZE(digital_hp_routes), 2537 analog_hp_routes, sizeof(analog_hp_routes)); 2538 2539 soc_codec_dev_cs43130.component_driver.dapm_widgets = 2540 all_hp_widgets; 2541 soc_codec_dev_cs43130.component_driver.num_dapm_widgets = 2542 ARRAY_SIZE(all_hp_widgets); 2543 soc_codec_dev_cs43130.component_driver.dapm_routes = 2544 all_hp_routes; 2545 soc_codec_dev_cs43130.component_driver.num_dapm_routes = 2546 ARRAY_SIZE(all_hp_routes); 2547 break; 2548 case CS43198_CHIP_ID: 2549 case CS4399_CHIP_ID: 2550 soc_codec_dev_cs43130.component_driver.dapm_widgets = 2551 digital_hp_widgets; 2552 soc_codec_dev_cs43130.component_driver.num_dapm_widgets = 2553 ARRAY_SIZE(digital_hp_widgets); 2554 soc_codec_dev_cs43130.component_driver.dapm_routes = 2555 digital_hp_routes; 2556 soc_codec_dev_cs43130.component_driver.num_dapm_routes = 2557 ARRAY_SIZE(digital_hp_routes); 2558 break; 2559 } 2560 2561 ret = snd_soc_register_codec(&client->dev, &soc_codec_dev_cs43130, 2562 cs43130_dai, ARRAY_SIZE(cs43130_dai)); 2563 if (ret < 0) { 2564 dev_err(&client->dev, 2565 "snd_soc_register_codec failed with ret = %d\n", ret); 2566 goto err; 2567 } 2568 2569 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG, 2570 CS43130_ASP_3ST_MASK, 0); 2571 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG, 2572 CS43130_XSP_3ST_MASK, 0); 2573 2574 return 0; 2575 err: 2576 return ret; 2577 } 2578 2579 static int cs43130_i2c_remove(struct i2c_client *client) 2580 { 2581 struct cs43130_private *cs43130 = i2c_get_clientdata(client); 2582 2583 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) 2584 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2585 CS43130_XTAL_ERR_INT, 2586 1 << CS43130_XTAL_ERR_INT_SHIFT); 2587 2588 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2589 CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, 2590 CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT); 2591 2592 if (cs43130->dc_meas) { 2593 cancel_work_sync(&cs43130->work); 2594 flush_workqueue(cs43130->wq); 2595 2596 device_remove_file(&client->dev, &dev_attr_hpload_dc_l); 2597 device_remove_file(&client->dev, &dev_attr_hpload_dc_r); 2598 device_remove_file(&client->dev, &dev_attr_hpload_ac_l); 2599 device_remove_file(&client->dev, &dev_attr_hpload_ac_r); 2600 } 2601 2602 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); 2603 2604 pm_runtime_disable(&client->dev); 2605 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); 2606 2607 snd_soc_unregister_codec(&client->dev); 2608 2609 return 0; 2610 } 2611 2612 static int __maybe_unused cs43130_runtime_suspend(struct device *dev) 2613 { 2614 struct cs43130_private *cs43130 = dev_get_drvdata(dev); 2615 2616 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) 2617 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2618 CS43130_XTAL_ERR_INT, 2619 1 << CS43130_XTAL_ERR_INT_SHIFT); 2620 2621 regcache_cache_only(cs43130->regmap, true); 2622 regcache_mark_dirty(cs43130->regmap); 2623 2624 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); 2625 2626 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); 2627 2628 return 0; 2629 } 2630 2631 static int __maybe_unused cs43130_runtime_resume(struct device *dev) 2632 { 2633 struct cs43130_private *cs43130 = dev_get_drvdata(dev); 2634 int ret; 2635 2636 ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES, cs43130->supplies); 2637 if (ret != 0) { 2638 dev_err(dev, "Failed to enable supplies: %d\n", ret); 2639 return ret; 2640 } 2641 2642 regcache_cache_only(cs43130->regmap, false); 2643 2644 gpiod_set_value_cansleep(cs43130->reset_gpio, 1); 2645 2646 usleep_range(2000, 2050); 2647 2648 ret = regcache_sync(cs43130->regmap); 2649 if (ret != 0) { 2650 dev_err(dev, "Failed to restore register cache\n"); 2651 goto err; 2652 } 2653 2654 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) 2655 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, 2656 CS43130_XTAL_ERR_INT, 0); 2657 2658 return 0; 2659 err: 2660 regcache_cache_only(cs43130->regmap, true); 2661 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); 2662 2663 return ret; 2664 } 2665 2666 static const struct dev_pm_ops cs43130_runtime_pm = { 2667 SET_RUNTIME_PM_OPS(cs43130_runtime_suspend, cs43130_runtime_resume, 2668 NULL) 2669 }; 2670 2671 static const struct of_device_id cs43130_of_match[] = { 2672 {.compatible = "cirrus,cs43130",}, 2673 {.compatible = "cirrus,cs4399",}, 2674 {.compatible = "cirrus,cs43131",}, 2675 {.compatible = "cirrus,cs43198",}, 2676 {}, 2677 }; 2678 2679 MODULE_DEVICE_TABLE(of, cs43130_of_match); 2680 2681 static const struct i2c_device_id cs43130_i2c_id[] = { 2682 {"cs43130", 0}, 2683 {"cs4399", 0}, 2684 {"cs43131", 0}, 2685 {"cs43198", 0}, 2686 {} 2687 }; 2688 2689 MODULE_DEVICE_TABLE(i2c, cs43130_i2c_id); 2690 2691 static struct i2c_driver cs43130_i2c_driver = { 2692 .driver = { 2693 .name = "cs43130", 2694 .of_match_table = cs43130_of_match, 2695 .pm = &cs43130_runtime_pm, 2696 }, 2697 .id_table = cs43130_i2c_id, 2698 .probe = cs43130_i2c_probe, 2699 .remove = cs43130_i2c_remove, 2700 }; 2701 2702 module_i2c_driver(cs43130_i2c_driver); 2703 2704 MODULE_AUTHOR("Li Xu <li.xu@cirrus.com>"); 2705 MODULE_DESCRIPTION("Cirrus Logic CS43130 ALSA SoC Codec Driver"); 2706 MODULE_LICENSE("GPL"); 2707