10c516b4fSNicolin Chen /* 20c516b4fSNicolin Chen * cs42xx8.h - Cirrus Logic CS42448/CS42888 Audio CODEC driver header file 30c516b4fSNicolin Chen * 40c516b4fSNicolin Chen * Copyright (C) 2014 Freescale Semiconductor, Inc. 50c516b4fSNicolin Chen * 60c516b4fSNicolin Chen * Author: Nicolin Chen <Guangyu.Chen@freescale.com> 70c516b4fSNicolin Chen * 80c516b4fSNicolin Chen * This file is licensed under the terms of the GNU General Public License 90c516b4fSNicolin Chen * version 2. This program is licensed "as is" without any warranty of any 100c516b4fSNicolin Chen * kind, whether express or implied. 110c516b4fSNicolin Chen */ 120c516b4fSNicolin Chen 130c516b4fSNicolin Chen #ifndef _CS42XX8_H 140c516b4fSNicolin Chen #define _CS42XX8_H 150c516b4fSNicolin Chen 160c516b4fSNicolin Chen struct cs42xx8_driver_data { 170c516b4fSNicolin Chen char name[32]; 180c516b4fSNicolin Chen int num_adcs; 190c516b4fSNicolin Chen }; 200c516b4fSNicolin Chen 210c516b4fSNicolin Chen extern const struct dev_pm_ops cs42xx8_pm; 220c516b4fSNicolin Chen extern const struct cs42xx8_driver_data cs42448_data; 230c516b4fSNicolin Chen extern const struct cs42xx8_driver_data cs42888_data; 240c516b4fSNicolin Chen extern const struct regmap_config cs42xx8_regmap_config; 25*e5afc867SPeter Bergin int cs42xx8_probe(struct device *dev, struct regmap *regmap, struct cs42xx8_driver_data *drvdata); 260c516b4fSNicolin Chen 270c516b4fSNicolin Chen /* CS42888 register map */ 280c516b4fSNicolin Chen #define CS42XX8_CHIPID 0x01 /* Chip ID */ 290c516b4fSNicolin Chen #define CS42XX8_PWRCTL 0x02 /* Power Control */ 300c516b4fSNicolin Chen #define CS42XX8_FUNCMOD 0x03 /* Functional Mode */ 310c516b4fSNicolin Chen #define CS42XX8_INTF 0x04 /* Interface Formats */ 320c516b4fSNicolin Chen #define CS42XX8_ADCCTL 0x05 /* ADC Control */ 330c516b4fSNicolin Chen #define CS42XX8_TXCTL 0x06 /* Transition Control */ 340c516b4fSNicolin Chen #define CS42XX8_DACMUTE 0x07 /* DAC Mute Control */ 350c516b4fSNicolin Chen #define CS42XX8_VOLAOUT1 0x08 /* Volume Control AOUT1 */ 360c516b4fSNicolin Chen #define CS42XX8_VOLAOUT2 0x09 /* Volume Control AOUT2 */ 370c516b4fSNicolin Chen #define CS42XX8_VOLAOUT3 0x0A /* Volume Control AOUT3 */ 380c516b4fSNicolin Chen #define CS42XX8_VOLAOUT4 0x0B /* Volume Control AOUT4 */ 390c516b4fSNicolin Chen #define CS42XX8_VOLAOUT5 0x0C /* Volume Control AOUT5 */ 400c516b4fSNicolin Chen #define CS42XX8_VOLAOUT6 0x0D /* Volume Control AOUT6 */ 410c516b4fSNicolin Chen #define CS42XX8_VOLAOUT7 0x0E /* Volume Control AOUT7 */ 420c516b4fSNicolin Chen #define CS42XX8_VOLAOUT8 0x0F /* Volume Control AOUT8 */ 430c516b4fSNicolin Chen #define CS42XX8_DACINV 0x10 /* DAC Channel Invert */ 440c516b4fSNicolin Chen #define CS42XX8_VOLAIN1 0x11 /* Volume Control AIN1 */ 450c516b4fSNicolin Chen #define CS42XX8_VOLAIN2 0x12 /* Volume Control AIN2 */ 460c516b4fSNicolin Chen #define CS42XX8_VOLAIN3 0x13 /* Volume Control AIN3 */ 470c516b4fSNicolin Chen #define CS42XX8_VOLAIN4 0x14 /* Volume Control AIN4 */ 480c516b4fSNicolin Chen #define CS42XX8_VOLAIN5 0x15 /* Volume Control AIN5 */ 490c516b4fSNicolin Chen #define CS42XX8_VOLAIN6 0x16 /* Volume Control AIN6 */ 500c516b4fSNicolin Chen #define CS42XX8_ADCINV 0x17 /* ADC Channel Invert */ 510c516b4fSNicolin Chen #define CS42XX8_STATUSCTL 0x18 /* Status Control */ 520c516b4fSNicolin Chen #define CS42XX8_STATUS 0x19 /* Status */ 530c516b4fSNicolin Chen #define CS42XX8_STATUSM 0x1A /* Status Mask */ 540c516b4fSNicolin Chen #define CS42XX8_MUTEC 0x1B /* MUTEC Pin Control */ 550c516b4fSNicolin Chen 560c516b4fSNicolin Chen #define CS42XX8_FIRSTREG CS42XX8_CHIPID 570c516b4fSNicolin Chen #define CS42XX8_LASTREG CS42XX8_MUTEC 580c516b4fSNicolin Chen #define CS42XX8_NUMREGS (CS42XX8_LASTREG - CS42XX8_FIRSTREG + 1) 590c516b4fSNicolin Chen #define CS42XX8_I2C_INCR 0x80 600c516b4fSNicolin Chen 610c516b4fSNicolin Chen /* Chip I.D. and Revision Register (Address 01h) */ 620c516b4fSNicolin Chen #define CS42XX8_CHIPID_CHIP_ID_MASK 0xF0 630c516b4fSNicolin Chen #define CS42XX8_CHIPID_REV_ID_MASK 0x0F 640c516b4fSNicolin Chen 650c516b4fSNicolin Chen /* Power Control (Address 02h) */ 660c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_ADC3_SHIFT 7 670c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_ADC3_MASK (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT) 680c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_ADC3 (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT) 690c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_ADC2_SHIFT 6 700c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_ADC2_MASK (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT) 710c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_ADC2 (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT) 720c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_ADC1_SHIFT 5 730c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_ADC1_MASK (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT) 740c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_ADC1 (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT) 750c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC4_SHIFT 4 760c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC4_MASK (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT) 770c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC4 (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT) 780c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC3_SHIFT 3 790c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC3_MASK (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT) 800c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC3 (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT) 810c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC2_SHIFT 2 820c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC2_MASK (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT) 830c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC2 (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT) 840c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC1_SHIFT 1 850c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC1_MASK (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT) 860c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_DAC1 (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT) 870c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_SHIFT 0 880c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN_MASK (1 << CS42XX8_PWRCTL_PDN_SHIFT) 890c516b4fSNicolin Chen #define CS42XX8_PWRCTL_PDN (1 << CS42XX8_PWRCTL_PDN_SHIFT) 900c516b4fSNicolin Chen 910c516b4fSNicolin Chen /* Functional Mode (Address 03h) */ 920c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_DAC_FM_SHIFT 6 930c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_DAC_FM_WIDTH 2 940c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_DAC_FM_MASK (((1 << CS42XX8_FUNCMOD_DAC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_DAC_FM_SHIFT) 950c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_DAC_FM(v) ((v) << CS42XX8_FUNCMOD_DAC_FM_SHIFT) 960c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_ADC_FM_SHIFT 4 970c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_ADC_FM_WIDTH 2 980c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_ADC_FM_MASK (((1 << CS42XX8_FUNCMOD_ADC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_ADC_FM_SHIFT) 990c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_ADC_FM(v) ((v) << CS42XX8_FUNCMOD_ADC_FM_SHIFT) 1000c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_xC_FM_MASK(x) ((x) ? CS42XX8_FUNCMOD_DAC_FM_MASK : CS42XX8_FUNCMOD_ADC_FM_MASK) 1010c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_xC_FM(x, v) ((x) ? CS42XX8_FUNCMOD_DAC_FM(v) : CS42XX8_FUNCMOD_ADC_FM(v)) 1020c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_MFREQ_SHIFT 1 1030c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_MFREQ_WIDTH 3 1040c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_MFREQ_MASK (((1 << CS42XX8_FUNCMOD_MFREQ_WIDTH) - 1) << CS42XX8_FUNCMOD_MFREQ_SHIFT) 1050c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_MFREQ_256(s) ((0 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1)) 1060c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_MFREQ_384(s) ((1 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1)) 1070c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_MFREQ_512(s) ((2 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1)) 1080c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_MFREQ_768(s) ((3 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1)) 1090c516b4fSNicolin Chen #define CS42XX8_FUNCMOD_MFREQ_1024(s) ((4 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1)) 1100c516b4fSNicolin Chen 1110c516b4fSNicolin Chen #define CS42XX8_FM_SINGLE 0 1120c516b4fSNicolin Chen #define CS42XX8_FM_DOUBLE 1 1130c516b4fSNicolin Chen #define CS42XX8_FM_QUAD 2 1140c516b4fSNicolin Chen #define CS42XX8_FM_AUTO 3 1150c516b4fSNicolin Chen 1160c516b4fSNicolin Chen /* Interface Formats (Address 04h) */ 1170c516b4fSNicolin Chen #define CS42XX8_INTF_FREEZE_SHIFT 7 1180c516b4fSNicolin Chen #define CS42XX8_INTF_FREEZE_MASK (1 << CS42XX8_INTF_FREEZE_SHIFT) 1190c516b4fSNicolin Chen #define CS42XX8_INTF_FREEZE (1 << CS42XX8_INTF_FREEZE_SHIFT) 1200c516b4fSNicolin Chen #define CS42XX8_INTF_AUX_DIF_SHIFT 6 1210c516b4fSNicolin Chen #define CS42XX8_INTF_AUX_DIF_MASK (1 << CS42XX8_INTF_AUX_DIF_SHIFT) 1220c516b4fSNicolin Chen #define CS42XX8_INTF_AUX_DIF (1 << CS42XX8_INTF_AUX_DIF_SHIFT) 1230c516b4fSNicolin Chen #define CS42XX8_INTF_DAC_DIF_SHIFT 3 1240c516b4fSNicolin Chen #define CS42XX8_INTF_DAC_DIF_WIDTH 3 1250c516b4fSNicolin Chen #define CS42XX8_INTF_DAC_DIF_MASK (((1 << CS42XX8_INTF_DAC_DIF_WIDTH) - 1) << CS42XX8_INTF_DAC_DIF_SHIFT) 1260c516b4fSNicolin Chen #define CS42XX8_INTF_DAC_DIF_LEFTJ (0 << CS42XX8_INTF_DAC_DIF_SHIFT) 1270c516b4fSNicolin Chen #define CS42XX8_INTF_DAC_DIF_I2S (1 << CS42XX8_INTF_DAC_DIF_SHIFT) 1280c516b4fSNicolin Chen #define CS42XX8_INTF_DAC_DIF_RIGHTJ (2 << CS42XX8_INTF_DAC_DIF_SHIFT) 1290c516b4fSNicolin Chen #define CS42XX8_INTF_DAC_DIF_RIGHTJ_16 (3 << CS42XX8_INTF_DAC_DIF_SHIFT) 1300c516b4fSNicolin Chen #define CS42XX8_INTF_DAC_DIF_ONELINE_20 (4 << CS42XX8_INTF_DAC_DIF_SHIFT) 131689dc643SShengjiu Wang #define CS42XX8_INTF_DAC_DIF_ONELINE_24 (5 << CS42XX8_INTF_DAC_DIF_SHIFT) 132689dc643SShengjiu Wang #define CS42XX8_INTF_DAC_DIF_TDM (6 << CS42XX8_INTF_DAC_DIF_SHIFT) 1330c516b4fSNicolin Chen #define CS42XX8_INTF_ADC_DIF_SHIFT 0 1340c516b4fSNicolin Chen #define CS42XX8_INTF_ADC_DIF_WIDTH 3 1350c516b4fSNicolin Chen #define CS42XX8_INTF_ADC_DIF_MASK (((1 << CS42XX8_INTF_ADC_DIF_WIDTH) - 1) << CS42XX8_INTF_ADC_DIF_SHIFT) 1360c516b4fSNicolin Chen #define CS42XX8_INTF_ADC_DIF_LEFTJ (0 << CS42XX8_INTF_ADC_DIF_SHIFT) 1370c516b4fSNicolin Chen #define CS42XX8_INTF_ADC_DIF_I2S (1 << CS42XX8_INTF_ADC_DIF_SHIFT) 1380c516b4fSNicolin Chen #define CS42XX8_INTF_ADC_DIF_RIGHTJ (2 << CS42XX8_INTF_ADC_DIF_SHIFT) 1390c516b4fSNicolin Chen #define CS42XX8_INTF_ADC_DIF_RIGHTJ_16 (3 << CS42XX8_INTF_ADC_DIF_SHIFT) 1400c516b4fSNicolin Chen #define CS42XX8_INTF_ADC_DIF_ONELINE_20 (4 << CS42XX8_INTF_ADC_DIF_SHIFT) 141689dc643SShengjiu Wang #define CS42XX8_INTF_ADC_DIF_ONELINE_24 (5 << CS42XX8_INTF_ADC_DIF_SHIFT) 142689dc643SShengjiu Wang #define CS42XX8_INTF_ADC_DIF_TDM (6 << CS42XX8_INTF_ADC_DIF_SHIFT) 1430c516b4fSNicolin Chen 1440c516b4fSNicolin Chen /* ADC Control & DAC De-Emphasis (Address 05h) */ 1450c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT 7 1460c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC_HPF_FREEZE_MASK (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT) 1470c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC_HPF_FREEZE (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT) 1480c516b4fSNicolin Chen #define CS42XX8_ADCCTL_DAC_DEM_SHIFT 5 1490c516b4fSNicolin Chen #define CS42XX8_ADCCTL_DAC_DEM_MASK (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT) 1500c516b4fSNicolin Chen #define CS42XX8_ADCCTL_DAC_DEM (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT) 1510c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT 4 1520c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC1_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT) 1530c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC1_SINGLE (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT) 1540c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT 3 1550c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC2_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT) 1560c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC2_SINGLE (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT) 1570c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT 2 1580c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC3_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT) 1590c516b4fSNicolin Chen #define CS42XX8_ADCCTL_ADC3_SINGLE (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT) 1600c516b4fSNicolin Chen #define CS42XX8_ADCCTL_AIN5_MUX_SHIFT 1 1610c516b4fSNicolin Chen #define CS42XX8_ADCCTL_AIN5_MUX_MASK (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT) 1620c516b4fSNicolin Chen #define CS42XX8_ADCCTL_AIN5_MUX (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT) 1630c516b4fSNicolin Chen #define CS42XX8_ADCCTL_AIN6_MUX_SHIFT 0 1640c516b4fSNicolin Chen #define CS42XX8_ADCCTL_AIN6_MUX_MASK (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT) 1650c516b4fSNicolin Chen #define CS42XX8_ADCCTL_AIN6_MUX (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT) 1660c516b4fSNicolin Chen 1670c516b4fSNicolin Chen /* Transition Control (Address 06h) */ 1680c516b4fSNicolin Chen #define CS42XX8_TXCTL_DAC_SNGVOL_SHIFT 7 1690c516b4fSNicolin Chen #define CS42XX8_TXCTL_DAC_SNGVOL_MASK (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT) 1700c516b4fSNicolin Chen #define CS42XX8_TXCTL_DAC_SNGVOL (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT) 1710c516b4fSNicolin Chen #define CS42XX8_TXCTL_DAC_SZC_SHIFT 5 1720c516b4fSNicolin Chen #define CS42XX8_TXCTL_DAC_SZC_WIDTH 2 1730c516b4fSNicolin Chen #define CS42XX8_TXCTL_DAC_SZC_MASK (((1 << CS42XX8_TXCTL_DAC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_DAC_SZC_SHIFT) 1740c516b4fSNicolin Chen #define CS42XX8_TXCTL_DAC_SZC_IC (0 << CS42XX8_TXCTL_DAC_SZC_SHIFT) 1750c516b4fSNicolin Chen #define CS42XX8_TXCTL_DAC_SZC_ZC (1 << CS42XX8_TXCTL_DAC_SZC_SHIFT) 1760c516b4fSNicolin Chen #define CS42XX8_TXCTL_DAC_SZC_SR (2 << CS42XX8_TXCTL_DAC_SZC_SHIFT) 1770c516b4fSNicolin Chen #define CS42XX8_TXCTL_DAC_SZC_SRZC (3 << CS42XX8_TXCTL_DAC_SZC_SHIFT) 1780c516b4fSNicolin Chen #define CS42XX8_TXCTL_AMUTE_SHIFT 4 1790c516b4fSNicolin Chen #define CS42XX8_TXCTL_AMUTE_MASK (1 << CS42XX8_TXCTL_AMUTE_SHIFT) 1800c516b4fSNicolin Chen #define CS42XX8_TXCTL_AMUTE (1 << CS42XX8_TXCTL_AMUTE_SHIFT) 1810c516b4fSNicolin Chen #define CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT 3 1820c516b4fSNicolin Chen #define CS42XX8_TXCTL_MUTE_ADC_SP_MASK (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT) 1830c516b4fSNicolin Chen #define CS42XX8_TXCTL_MUTE_ADC_SP (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT) 1840c516b4fSNicolin Chen #define CS42XX8_TXCTL_ADC_SNGVOL_SHIFT 2 1850c516b4fSNicolin Chen #define CS42XX8_TXCTL_ADC_SNGVOL_MASK (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT) 1860c516b4fSNicolin Chen #define CS42XX8_TXCTL_ADC_SNGVOL (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT) 1870c516b4fSNicolin Chen #define CS42XX8_TXCTL_ADC_SZC_SHIFT 0 1880c516b4fSNicolin Chen #define CS42XX8_TXCTL_ADC_SZC_MASK (((1 << CS42XX8_TXCTL_ADC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_ADC_SZC_SHIFT) 1890c516b4fSNicolin Chen #define CS42XX8_TXCTL_ADC_SZC_IC (0 << CS42XX8_TXCTL_ADC_SZC_SHIFT) 1900c516b4fSNicolin Chen #define CS42XX8_TXCTL_ADC_SZC_ZC (1 << CS42XX8_TXCTL_ADC_SZC_SHIFT) 1910c516b4fSNicolin Chen #define CS42XX8_TXCTL_ADC_SZC_SR (2 << CS42XX8_TXCTL_ADC_SZC_SHIFT) 1920c516b4fSNicolin Chen #define CS42XX8_TXCTL_ADC_SZC_SRZC (3 << CS42XX8_TXCTL_ADC_SZC_SHIFT) 1930c516b4fSNicolin Chen 1940c516b4fSNicolin Chen /* DAC Channel Mute (Address 07h) */ 1950c516b4fSNicolin Chen #define CS42XX8_DACMUTE_AOUT(n) (0x1 << n) 1960c516b4fSNicolin Chen #define CS42XX8_DACMUTE_ALL 0xff 1970c516b4fSNicolin Chen 1980c516b4fSNicolin Chen /* Status Control (Address 18h)*/ 1990c516b4fSNicolin Chen #define CS42XX8_STATUSCTL_INI_SHIFT 2 2000c516b4fSNicolin Chen #define CS42XX8_STATUSCTL_INI_WIDTH 2 2010c516b4fSNicolin Chen #define CS42XX8_STATUSCTL_INI_MASK (((1 << CS42XX8_STATUSCTL_INI_WIDTH) - 1) << CS42XX8_STATUSCTL_INI_SHIFT) 2020c516b4fSNicolin Chen #define CS42XX8_STATUSCTL_INT_ACTIVE_HIGH (0 << CS42XX8_STATUSCTL_INI_SHIFT) 2030c516b4fSNicolin Chen #define CS42XX8_STATUSCTL_INT_ACTIVE_LOW (1 << CS42XX8_STATUSCTL_INI_SHIFT) 2040c516b4fSNicolin Chen #define CS42XX8_STATUSCTL_INT_OPEN_DRAIN (2 << CS42XX8_STATUSCTL_INI_SHIFT) 2050c516b4fSNicolin Chen 2060c516b4fSNicolin Chen /* Status (Address 19h)*/ 2070c516b4fSNicolin Chen #define CS42XX8_STATUS_DAC_CLK_ERR_SHIFT 4 2080c516b4fSNicolin Chen #define CS42XX8_STATUS_DAC_CLK_ERR_MASK (1 << CS42XX8_STATUS_DAC_CLK_ERR_SHIFT) 2090c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC_CLK_ERR_SHIFT 3 2100c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC_CLK_ERR_MASK (1 << CS42XX8_STATUS_ADC_CLK_ERR_SHIFT) 2110c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC3_OVFL_SHIFT 2 2120c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC3_OVFL_MASK (1 << CS42XX8_STATUS_ADC3_OVFL_SHIFT) 2130c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC2_OVFL_SHIFT 1 2140c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC2_OVFL_MASK (1 << CS42XX8_STATUS_ADC2_OVFL_SHIFT) 2150c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC1_OVFL_SHIFT 0 2160c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC1_OVFL_MASK (1 << CS42XX8_STATUS_ADC1_OVFL_SHIFT) 2170c516b4fSNicolin Chen 2180c516b4fSNicolin Chen /* Status Mask (Address 1Ah) */ 2190c516b4fSNicolin Chen #define CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT 4 2200c516b4fSNicolin Chen #define CS42XX8_STATUS_DAC_CLK_ERR_M_MASK (1 << CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT) 2210c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT 3 2220c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC_CLK_ERR_M_MASK (1 << CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT) 2230c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC3_OVFL_M_SHIFT 2 2240c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC3_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC3_OVFL_M_SHIFT) 2250c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC2_OVFL_M_SHIFT 1 2260c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC2_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC2_OVFL_M_SHIFT) 2270c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC1_OVFL_M_SHIFT 0 2280c516b4fSNicolin Chen #define CS42XX8_STATUS_ADC1_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC1_OVFL_M_SHIFT) 2290c516b4fSNicolin Chen 2300c516b4fSNicolin Chen /* MUTEC Pin Control (Address 1Bh) */ 2310c516b4fSNicolin Chen #define CS42XX8_MUTEC_MCPOLARITY_SHIFT 1 2320c516b4fSNicolin Chen #define CS42XX8_MUTEC_MCPOLARITY_MASK (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT) 2330c516b4fSNicolin Chen #define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_LOW (0 << CS42XX8_MUTEC_MCPOLARITY_SHIFT) 2340c516b4fSNicolin Chen #define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_HIGH (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT) 2350c516b4fSNicolin Chen #define CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT 0 2360c516b4fSNicolin Chen #define CS42XX8_MUTEC_MUTEC_ACTIVE_MASK (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT) 2370c516b4fSNicolin Chen #define CS42XX8_MUTEC_MUTEC_ACTIVE (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT) 2380c516b4fSNicolin Chen #endif /* _CS42XX8_H */ 239