1 /* 2 * Cirrus Logic CS42448/CS42888 Audio CODEC Digital Audio Interface (DAI) driver 3 * 4 * Copyright (C) 2014 Freescale Semiconductor, Inc. 5 * 6 * Author: Nicolin Chen <Guangyu.Chen@freescale.com> 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regulator/consumer.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #include "cs42xx8.h" 24 25 #define CS42XX8_NUM_SUPPLIES 4 26 static const char *const cs42xx8_supply_names[CS42XX8_NUM_SUPPLIES] = { 27 "VA", 28 "VD", 29 "VLS", 30 "VLC", 31 }; 32 33 #define CS42XX8_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 34 SNDRV_PCM_FMTBIT_S20_3LE | \ 35 SNDRV_PCM_FMTBIT_S24_LE | \ 36 SNDRV_PCM_FMTBIT_S32_LE) 37 38 /* codec private data */ 39 struct cs42xx8_priv { 40 struct regulator_bulk_data supplies[CS42XX8_NUM_SUPPLIES]; 41 const struct cs42xx8_driver_data *drvdata; 42 struct regmap *regmap; 43 struct clk *clk; 44 45 bool slave_mode; 46 unsigned long sysclk; 47 u32 tx_channels; 48 }; 49 50 /* -127.5dB to 0dB with step of 0.5dB */ 51 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); 52 /* -64dB to 24dB with step of 0.5dB */ 53 static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 0); 54 55 static const char *const cs42xx8_adc_single[] = { "Differential", "Single-Ended" }; 56 static const char *const cs42xx8_szc[] = { "Immediate Change", "Zero Cross", 57 "Soft Ramp", "Soft Ramp on Zero Cross" }; 58 59 static const struct soc_enum adc1_single_enum = 60 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 4, 2, cs42xx8_adc_single); 61 static const struct soc_enum adc2_single_enum = 62 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 3, 2, cs42xx8_adc_single); 63 static const struct soc_enum adc3_single_enum = 64 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 2, 2, cs42xx8_adc_single); 65 static const struct soc_enum dac_szc_enum = 66 SOC_ENUM_SINGLE(CS42XX8_TXCTL, 5, 4, cs42xx8_szc); 67 static const struct soc_enum adc_szc_enum = 68 SOC_ENUM_SINGLE(CS42XX8_TXCTL, 0, 4, cs42xx8_szc); 69 70 static const struct snd_kcontrol_new cs42xx8_snd_controls[] = { 71 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", CS42XX8_VOLAOUT1, 72 CS42XX8_VOLAOUT2, 0, 0xff, 1, dac_tlv), 73 SOC_DOUBLE_R_TLV("DAC2 Playback Volume", CS42XX8_VOLAOUT3, 74 CS42XX8_VOLAOUT4, 0, 0xff, 1, dac_tlv), 75 SOC_DOUBLE_R_TLV("DAC3 Playback Volume", CS42XX8_VOLAOUT5, 76 CS42XX8_VOLAOUT6, 0, 0xff, 1, dac_tlv), 77 SOC_DOUBLE_R_TLV("DAC4 Playback Volume", CS42XX8_VOLAOUT7, 78 CS42XX8_VOLAOUT8, 0, 0xff, 1, dac_tlv), 79 SOC_DOUBLE_R_S_TLV("ADC1 Capture Volume", CS42XX8_VOLAIN1, 80 CS42XX8_VOLAIN2, 0, -0x80, 0x30, 7, 0, adc_tlv), 81 SOC_DOUBLE_R_S_TLV("ADC2 Capture Volume", CS42XX8_VOLAIN3, 82 CS42XX8_VOLAIN4, 0, -0x80, 0x30, 7, 0, adc_tlv), 83 SOC_DOUBLE("DAC1 Invert Switch", CS42XX8_DACINV, 0, 1, 1, 0), 84 SOC_DOUBLE("DAC2 Invert Switch", CS42XX8_DACINV, 2, 3, 1, 0), 85 SOC_DOUBLE("DAC3 Invert Switch", CS42XX8_DACINV, 4, 5, 1, 0), 86 SOC_DOUBLE("DAC4 Invert Switch", CS42XX8_DACINV, 6, 7, 1, 0), 87 SOC_DOUBLE("ADC1 Invert Switch", CS42XX8_ADCINV, 0, 1, 1, 0), 88 SOC_DOUBLE("ADC2 Invert Switch", CS42XX8_ADCINV, 2, 3, 1, 0), 89 SOC_SINGLE("ADC High-Pass Filter Switch", CS42XX8_ADCCTL, 7, 1, 1), 90 SOC_SINGLE("DAC De-emphasis Switch", CS42XX8_ADCCTL, 5, 1, 0), 91 SOC_ENUM("ADC1 Single Ended Mode Switch", adc1_single_enum), 92 SOC_ENUM("ADC2 Single Ended Mode Switch", adc2_single_enum), 93 SOC_SINGLE("DAC Single Volume Control Switch", CS42XX8_TXCTL, 7, 1, 0), 94 SOC_ENUM("DAC Soft Ramp & Zero Cross Control Switch", dac_szc_enum), 95 SOC_SINGLE("DAC Auto Mute Switch", CS42XX8_TXCTL, 4, 1, 0), 96 SOC_SINGLE("Mute ADC Serial Port Switch", CS42XX8_TXCTL, 3, 1, 0), 97 SOC_SINGLE("ADC Single Volume Control Switch", CS42XX8_TXCTL, 2, 1, 0), 98 SOC_ENUM("ADC Soft Ramp & Zero Cross Control Switch", adc_szc_enum), 99 }; 100 101 static const struct snd_kcontrol_new cs42xx8_adc3_snd_controls[] = { 102 SOC_DOUBLE_R_S_TLV("ADC3 Capture Volume", CS42XX8_VOLAIN5, 103 CS42XX8_VOLAIN6, 0, -0x80, 0x30, 7, 0, adc_tlv), 104 SOC_DOUBLE("ADC3 Invert Switch", CS42XX8_ADCINV, 4, 5, 1, 0), 105 SOC_ENUM("ADC3 Single Ended Mode Switch", adc3_single_enum), 106 }; 107 108 static const struct snd_soc_dapm_widget cs42xx8_dapm_widgets[] = { 109 SND_SOC_DAPM_DAC("DAC1", "Playback", CS42XX8_PWRCTL, 1, 1), 110 SND_SOC_DAPM_DAC("DAC2", "Playback", CS42XX8_PWRCTL, 2, 1), 111 SND_SOC_DAPM_DAC("DAC3", "Playback", CS42XX8_PWRCTL, 3, 1), 112 SND_SOC_DAPM_DAC("DAC4", "Playback", CS42XX8_PWRCTL, 4, 1), 113 114 SND_SOC_DAPM_OUTPUT("AOUT1L"), 115 SND_SOC_DAPM_OUTPUT("AOUT1R"), 116 SND_SOC_DAPM_OUTPUT("AOUT2L"), 117 SND_SOC_DAPM_OUTPUT("AOUT2R"), 118 SND_SOC_DAPM_OUTPUT("AOUT3L"), 119 SND_SOC_DAPM_OUTPUT("AOUT3R"), 120 SND_SOC_DAPM_OUTPUT("AOUT4L"), 121 SND_SOC_DAPM_OUTPUT("AOUT4R"), 122 123 SND_SOC_DAPM_ADC("ADC1", "Capture", CS42XX8_PWRCTL, 5, 1), 124 SND_SOC_DAPM_ADC("ADC2", "Capture", CS42XX8_PWRCTL, 6, 1), 125 126 SND_SOC_DAPM_INPUT("AIN1L"), 127 SND_SOC_DAPM_INPUT("AIN1R"), 128 SND_SOC_DAPM_INPUT("AIN2L"), 129 SND_SOC_DAPM_INPUT("AIN2R"), 130 131 SND_SOC_DAPM_SUPPLY("PWR", CS42XX8_PWRCTL, 0, 1, NULL, 0), 132 }; 133 134 static const struct snd_soc_dapm_widget cs42xx8_adc3_dapm_widgets[] = { 135 SND_SOC_DAPM_ADC("ADC3", "Capture", CS42XX8_PWRCTL, 7, 1), 136 137 SND_SOC_DAPM_INPUT("AIN3L"), 138 SND_SOC_DAPM_INPUT("AIN3R"), 139 }; 140 141 static const struct snd_soc_dapm_route cs42xx8_dapm_routes[] = { 142 /* Playback */ 143 { "AOUT1L", NULL, "DAC1" }, 144 { "AOUT1R", NULL, "DAC1" }, 145 { "DAC1", NULL, "PWR" }, 146 147 { "AOUT2L", NULL, "DAC2" }, 148 { "AOUT2R", NULL, "DAC2" }, 149 { "DAC2", NULL, "PWR" }, 150 151 { "AOUT3L", NULL, "DAC3" }, 152 { "AOUT3R", NULL, "DAC3" }, 153 { "DAC3", NULL, "PWR" }, 154 155 { "AOUT4L", NULL, "DAC4" }, 156 { "AOUT4R", NULL, "DAC4" }, 157 { "DAC4", NULL, "PWR" }, 158 159 /* Capture */ 160 { "ADC1", NULL, "AIN1L" }, 161 { "ADC1", NULL, "AIN1R" }, 162 { "ADC1", NULL, "PWR" }, 163 164 { "ADC2", NULL, "AIN2L" }, 165 { "ADC2", NULL, "AIN2R" }, 166 { "ADC2", NULL, "PWR" }, 167 }; 168 169 static const struct snd_soc_dapm_route cs42xx8_adc3_dapm_routes[] = { 170 /* Capture */ 171 { "ADC3", NULL, "AIN3L" }, 172 { "ADC3", NULL, "AIN3R" }, 173 { "ADC3", NULL, "PWR" }, 174 }; 175 176 struct cs42xx8_ratios { 177 unsigned int ratio; 178 unsigned char speed; 179 unsigned char mclk; 180 }; 181 182 static const struct cs42xx8_ratios cs42xx8_ratios[] = { 183 { 64, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_256(4) }, 184 { 96, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_384(4) }, 185 { 128, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_512(4) }, 186 { 192, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_768(4) }, 187 { 256, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_256(1) }, 188 { 384, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_384(1) }, 189 { 512, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_512(1) }, 190 { 768, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_768(1) }, 191 { 1024, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_1024(1) } 192 }; 193 194 static int cs42xx8_set_dai_sysclk(struct snd_soc_dai *codec_dai, 195 int clk_id, unsigned int freq, int dir) 196 { 197 struct snd_soc_codec *codec = codec_dai->codec; 198 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 199 200 cs42xx8->sysclk = freq; 201 202 return 0; 203 } 204 205 static int cs42xx8_set_dai_fmt(struct snd_soc_dai *codec_dai, 206 unsigned int format) 207 { 208 struct snd_soc_codec *codec = codec_dai->codec; 209 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 210 u32 val; 211 212 /* Set DAI format */ 213 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 214 case SND_SOC_DAIFMT_LEFT_J: 215 val = CS42XX8_INTF_DAC_DIF_LEFTJ | CS42XX8_INTF_ADC_DIF_LEFTJ; 216 break; 217 case SND_SOC_DAIFMT_I2S: 218 val = CS42XX8_INTF_DAC_DIF_I2S | CS42XX8_INTF_ADC_DIF_I2S; 219 break; 220 case SND_SOC_DAIFMT_RIGHT_J: 221 val = CS42XX8_INTF_DAC_DIF_RIGHTJ | CS42XX8_INTF_ADC_DIF_RIGHTJ; 222 break; 223 case SND_SOC_DAIFMT_DSP_A: 224 val = CS42XX8_INTF_DAC_DIF_TDM | CS42XX8_INTF_ADC_DIF_TDM; 225 break; 226 default: 227 dev_err(codec->dev, "unsupported dai format\n"); 228 return -EINVAL; 229 } 230 231 regmap_update_bits(cs42xx8->regmap, CS42XX8_INTF, 232 CS42XX8_INTF_DAC_DIF_MASK | 233 CS42XX8_INTF_ADC_DIF_MASK, val); 234 235 /* Set master/slave audio interface */ 236 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 237 case SND_SOC_DAIFMT_CBS_CFS: 238 cs42xx8->slave_mode = true; 239 break; 240 case SND_SOC_DAIFMT_CBM_CFM: 241 cs42xx8->slave_mode = false; 242 break; 243 default: 244 dev_err(codec->dev, "unsupported master/slave mode\n"); 245 return -EINVAL; 246 } 247 248 return 0; 249 } 250 251 static int cs42xx8_hw_params(struct snd_pcm_substream *substream, 252 struct snd_pcm_hw_params *params, 253 struct snd_soc_dai *dai) 254 { 255 struct snd_soc_codec *codec = dai->codec; 256 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 257 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 258 u32 ratio = cs42xx8->sysclk / params_rate(params); 259 u32 i, fm, val, mask; 260 261 if (tx) 262 cs42xx8->tx_channels = params_channels(params); 263 264 for (i = 0; i < ARRAY_SIZE(cs42xx8_ratios); i++) { 265 if (cs42xx8_ratios[i].ratio == ratio) 266 break; 267 } 268 269 if (i == ARRAY_SIZE(cs42xx8_ratios)) { 270 dev_err(codec->dev, "unsupported sysclk ratio\n"); 271 return -EINVAL; 272 } 273 274 mask = CS42XX8_FUNCMOD_MFREQ_MASK; 275 val = cs42xx8_ratios[i].mclk; 276 277 fm = cs42xx8->slave_mode ? CS42XX8_FM_AUTO : cs42xx8_ratios[i].speed; 278 279 regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD, 280 CS42XX8_FUNCMOD_xC_FM_MASK(tx) | mask, 281 CS42XX8_FUNCMOD_xC_FM(tx, fm) | val); 282 283 return 0; 284 } 285 286 static int cs42xx8_digital_mute(struct snd_soc_dai *dai, int mute) 287 { 288 struct snd_soc_codec *codec = dai->codec; 289 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 290 u8 dac_unmute = cs42xx8->tx_channels ? 291 ~((0x1 << cs42xx8->tx_channels) - 1) : 0; 292 293 regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, 294 mute ? CS42XX8_DACMUTE_ALL : dac_unmute); 295 296 return 0; 297 } 298 299 static const struct snd_soc_dai_ops cs42xx8_dai_ops = { 300 .set_fmt = cs42xx8_set_dai_fmt, 301 .set_sysclk = cs42xx8_set_dai_sysclk, 302 .hw_params = cs42xx8_hw_params, 303 .digital_mute = cs42xx8_digital_mute, 304 }; 305 306 static struct snd_soc_dai_driver cs42xx8_dai = { 307 .playback = { 308 .stream_name = "Playback", 309 .channels_min = 1, 310 .channels_max = 8, 311 .rates = SNDRV_PCM_RATE_8000_192000, 312 .formats = CS42XX8_FORMATS, 313 }, 314 .capture = { 315 .stream_name = "Capture", 316 .channels_min = 1, 317 .rates = SNDRV_PCM_RATE_8000_192000, 318 .formats = CS42XX8_FORMATS, 319 }, 320 .ops = &cs42xx8_dai_ops, 321 }; 322 323 static const struct reg_default cs42xx8_reg[] = { 324 { 0x01, 0x01 }, /* Chip I.D. and Revision Register */ 325 { 0x02, 0x00 }, /* Power Control */ 326 { 0x03, 0xF0 }, /* Functional Mode */ 327 { 0x04, 0x46 }, /* Interface Formats */ 328 { 0x05, 0x00 }, /* ADC Control & DAC De-Emphasis */ 329 { 0x06, 0x10 }, /* Transition Control */ 330 { 0x07, 0x00 }, /* DAC Channel Mute */ 331 { 0x08, 0x00 }, /* Volume Control AOUT1 */ 332 { 0x09, 0x00 }, /* Volume Control AOUT2 */ 333 { 0x0a, 0x00 }, /* Volume Control AOUT3 */ 334 { 0x0b, 0x00 }, /* Volume Control AOUT4 */ 335 { 0x0c, 0x00 }, /* Volume Control AOUT5 */ 336 { 0x0d, 0x00 }, /* Volume Control AOUT6 */ 337 { 0x0e, 0x00 }, /* Volume Control AOUT7 */ 338 { 0x0f, 0x00 }, /* Volume Control AOUT8 */ 339 { 0x10, 0x00 }, /* DAC Channel Invert */ 340 { 0x11, 0x00 }, /* Volume Control AIN1 */ 341 { 0x12, 0x00 }, /* Volume Control AIN2 */ 342 { 0x13, 0x00 }, /* Volume Control AIN3 */ 343 { 0x14, 0x00 }, /* Volume Control AIN4 */ 344 { 0x15, 0x00 }, /* Volume Control AIN5 */ 345 { 0x16, 0x00 }, /* Volume Control AIN6 */ 346 { 0x17, 0x00 }, /* ADC Channel Invert */ 347 { 0x18, 0x00 }, /* Status Control */ 348 { 0x1a, 0x00 }, /* Status Mask */ 349 { 0x1b, 0x00 }, /* MUTEC Pin Control */ 350 }; 351 352 static bool cs42xx8_volatile_register(struct device *dev, unsigned int reg) 353 { 354 switch (reg) { 355 case CS42XX8_STATUS: 356 return true; 357 default: 358 return false; 359 } 360 } 361 362 static bool cs42xx8_writeable_register(struct device *dev, unsigned int reg) 363 { 364 switch (reg) { 365 case CS42XX8_CHIPID: 366 case CS42XX8_STATUS: 367 return false; 368 default: 369 return true; 370 } 371 } 372 373 const struct regmap_config cs42xx8_regmap_config = { 374 .reg_bits = 8, 375 .val_bits = 8, 376 377 .max_register = CS42XX8_LASTREG, 378 .reg_defaults = cs42xx8_reg, 379 .num_reg_defaults = ARRAY_SIZE(cs42xx8_reg), 380 .volatile_reg = cs42xx8_volatile_register, 381 .writeable_reg = cs42xx8_writeable_register, 382 .cache_type = REGCACHE_RBTREE, 383 }; 384 EXPORT_SYMBOL_GPL(cs42xx8_regmap_config); 385 386 static int cs42xx8_codec_probe(struct snd_soc_codec *codec) 387 { 388 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 389 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 390 391 switch (cs42xx8->drvdata->num_adcs) { 392 case 3: 393 snd_soc_add_codec_controls(codec, cs42xx8_adc3_snd_controls, 394 ARRAY_SIZE(cs42xx8_adc3_snd_controls)); 395 snd_soc_dapm_new_controls(dapm, cs42xx8_adc3_dapm_widgets, 396 ARRAY_SIZE(cs42xx8_adc3_dapm_widgets)); 397 snd_soc_dapm_add_routes(dapm, cs42xx8_adc3_dapm_routes, 398 ARRAY_SIZE(cs42xx8_adc3_dapm_routes)); 399 break; 400 default: 401 break; 402 } 403 404 /* Mute all DAC channels */ 405 regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, CS42XX8_DACMUTE_ALL); 406 407 return 0; 408 } 409 410 static const struct snd_soc_codec_driver cs42xx8_driver = { 411 .probe = cs42xx8_codec_probe, 412 .idle_bias_off = true, 413 414 .component_driver = { 415 .controls = cs42xx8_snd_controls, 416 .num_controls = ARRAY_SIZE(cs42xx8_snd_controls), 417 .dapm_widgets = cs42xx8_dapm_widgets, 418 .num_dapm_widgets = ARRAY_SIZE(cs42xx8_dapm_widgets), 419 .dapm_routes = cs42xx8_dapm_routes, 420 .num_dapm_routes = ARRAY_SIZE(cs42xx8_dapm_routes), 421 }, 422 }; 423 424 const struct cs42xx8_driver_data cs42448_data = { 425 .name = "cs42448", 426 .num_adcs = 3, 427 }; 428 EXPORT_SYMBOL_GPL(cs42448_data); 429 430 const struct cs42xx8_driver_data cs42888_data = { 431 .name = "cs42888", 432 .num_adcs = 2, 433 }; 434 EXPORT_SYMBOL_GPL(cs42888_data); 435 436 const struct of_device_id cs42xx8_of_match[] = { 437 { .compatible = "cirrus,cs42448", .data = &cs42448_data, }, 438 { .compatible = "cirrus,cs42888", .data = &cs42888_data, }, 439 { /* sentinel */ } 440 }; 441 MODULE_DEVICE_TABLE(of, cs42xx8_of_match); 442 EXPORT_SYMBOL_GPL(cs42xx8_of_match); 443 444 int cs42xx8_probe(struct device *dev, struct regmap *regmap) 445 { 446 const struct of_device_id *of_id; 447 struct cs42xx8_priv *cs42xx8; 448 int ret, val, i; 449 450 if (IS_ERR(regmap)) { 451 ret = PTR_ERR(regmap); 452 dev_err(dev, "failed to allocate regmap: %d\n", ret); 453 return ret; 454 } 455 456 cs42xx8 = devm_kzalloc(dev, sizeof(*cs42xx8), GFP_KERNEL); 457 if (cs42xx8 == NULL) 458 return -ENOMEM; 459 460 cs42xx8->regmap = regmap; 461 dev_set_drvdata(dev, cs42xx8); 462 463 of_id = of_match_device(cs42xx8_of_match, dev); 464 if (of_id) 465 cs42xx8->drvdata = of_id->data; 466 467 if (!cs42xx8->drvdata) { 468 dev_err(dev, "failed to find driver data\n"); 469 return -EINVAL; 470 } 471 472 cs42xx8->clk = devm_clk_get(dev, "mclk"); 473 if (IS_ERR(cs42xx8->clk)) { 474 dev_err(dev, "failed to get the clock: %ld\n", 475 PTR_ERR(cs42xx8->clk)); 476 return -EINVAL; 477 } 478 479 cs42xx8->sysclk = clk_get_rate(cs42xx8->clk); 480 481 for (i = 0; i < ARRAY_SIZE(cs42xx8->supplies); i++) 482 cs42xx8->supplies[i].supply = cs42xx8_supply_names[i]; 483 484 ret = devm_regulator_bulk_get(dev, 485 ARRAY_SIZE(cs42xx8->supplies), cs42xx8->supplies); 486 if (ret) { 487 dev_err(dev, "failed to request supplies: %d\n", ret); 488 return ret; 489 } 490 491 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies), 492 cs42xx8->supplies); 493 if (ret) { 494 dev_err(dev, "failed to enable supplies: %d\n", ret); 495 return ret; 496 } 497 498 /* Make sure hardware reset done */ 499 msleep(5); 500 501 /* 502 * We haven't marked the chip revision as volatile due to 503 * sharing a register with the right input volume; explicitly 504 * bypass the cache to read it. 505 */ 506 regcache_cache_bypass(cs42xx8->regmap, true); 507 508 /* Validate the chip ID */ 509 ret = regmap_read(cs42xx8->regmap, CS42XX8_CHIPID, &val); 510 if (ret < 0) { 511 dev_err(dev, "failed to get device ID, ret = %d", ret); 512 goto err_enable; 513 } 514 515 /* The top four bits of the chip ID should be 0000 */ 516 if (((val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4) != 0x00) { 517 dev_err(dev, "unmatched chip ID: %d\n", 518 (val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4); 519 ret = -EINVAL; 520 goto err_enable; 521 } 522 523 dev_info(dev, "found device, revision %X\n", 524 val & CS42XX8_CHIPID_REV_ID_MASK); 525 526 regcache_cache_bypass(cs42xx8->regmap, false); 527 528 cs42xx8_dai.name = cs42xx8->drvdata->name; 529 530 /* Each adc supports stereo input */ 531 cs42xx8_dai.capture.channels_max = cs42xx8->drvdata->num_adcs * 2; 532 533 ret = snd_soc_register_codec(dev, &cs42xx8_driver, &cs42xx8_dai, 1); 534 if (ret) { 535 dev_err(dev, "failed to register codec:%d\n", ret); 536 goto err_enable; 537 } 538 539 regcache_cache_only(cs42xx8->regmap, true); 540 541 err_enable: 542 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), 543 cs42xx8->supplies); 544 545 return ret; 546 } 547 EXPORT_SYMBOL_GPL(cs42xx8_probe); 548 549 #ifdef CONFIG_PM 550 static int cs42xx8_runtime_resume(struct device *dev) 551 { 552 struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev); 553 int ret; 554 555 ret = clk_prepare_enable(cs42xx8->clk); 556 if (ret) { 557 dev_err(dev, "failed to enable mclk: %d\n", ret); 558 return ret; 559 } 560 561 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies), 562 cs42xx8->supplies); 563 if (ret) { 564 dev_err(dev, "failed to enable supplies: %d\n", ret); 565 goto err_clk; 566 } 567 568 /* Make sure hardware reset done */ 569 msleep(5); 570 571 regcache_cache_only(cs42xx8->regmap, false); 572 573 ret = regcache_sync(cs42xx8->regmap); 574 if (ret) { 575 dev_err(dev, "failed to sync regmap: %d\n", ret); 576 goto err_bulk; 577 } 578 579 return 0; 580 581 err_bulk: 582 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), 583 cs42xx8->supplies); 584 err_clk: 585 clk_disable_unprepare(cs42xx8->clk); 586 587 return ret; 588 } 589 590 static int cs42xx8_runtime_suspend(struct device *dev) 591 { 592 struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev); 593 594 regcache_cache_only(cs42xx8->regmap, true); 595 596 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), 597 cs42xx8->supplies); 598 599 clk_disable_unprepare(cs42xx8->clk); 600 601 return 0; 602 } 603 #endif 604 605 const struct dev_pm_ops cs42xx8_pm = { 606 SET_RUNTIME_PM_OPS(cs42xx8_runtime_suspend, cs42xx8_runtime_resume, NULL) 607 }; 608 EXPORT_SYMBOL_GPL(cs42xx8_pm); 609 610 MODULE_DESCRIPTION("Cirrus Logic CS42448/CS42888 ALSA SoC Codec Driver"); 611 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 612 MODULE_LICENSE("GPL"); 613