1 /* 2 * Cirrus Logic CS42448/CS42888 Audio CODEC Digital Audio Interface (DAI) driver 3 * 4 * Copyright (C) 2014 Freescale Semiconductor, Inc. 5 * 6 * Author: Nicolin Chen <Guangyu.Chen@freescale.com> 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regulator/consumer.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #include "cs42xx8.h" 24 25 #define CS42XX8_NUM_SUPPLIES 4 26 static const char *const cs42xx8_supply_names[CS42XX8_NUM_SUPPLIES] = { 27 "VA", 28 "VD", 29 "VLS", 30 "VLC", 31 }; 32 33 #define CS42XX8_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 34 SNDRV_PCM_FMTBIT_S20_3LE | \ 35 SNDRV_PCM_FMTBIT_S24_LE | \ 36 SNDRV_PCM_FMTBIT_S32_LE) 37 38 /* codec private data */ 39 struct cs42xx8_priv { 40 struct regulator_bulk_data supplies[CS42XX8_NUM_SUPPLIES]; 41 const struct cs42xx8_driver_data *drvdata; 42 struct regmap *regmap; 43 struct clk *clk; 44 45 bool slave_mode; 46 unsigned long sysclk; 47 }; 48 49 /* -127.5dB to 0dB with step of 0.5dB */ 50 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); 51 /* -64dB to 24dB with step of 0.5dB */ 52 static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 0); 53 54 static const char *const cs42xx8_adc_single[] = { "Differential", "Single-Ended" }; 55 static const char *const cs42xx8_szc[] = { "Immediate Change", "Zero Cross", 56 "Soft Ramp", "Soft Ramp on Zero Cross" }; 57 58 static const struct soc_enum adc1_single_enum = 59 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 4, 2, cs42xx8_adc_single); 60 static const struct soc_enum adc2_single_enum = 61 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 3, 2, cs42xx8_adc_single); 62 static const struct soc_enum adc3_single_enum = 63 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 2, 2, cs42xx8_adc_single); 64 static const struct soc_enum dac_szc_enum = 65 SOC_ENUM_SINGLE(CS42XX8_TXCTL, 5, 4, cs42xx8_szc); 66 static const struct soc_enum adc_szc_enum = 67 SOC_ENUM_SINGLE(CS42XX8_TXCTL, 0, 4, cs42xx8_szc); 68 69 static const struct snd_kcontrol_new cs42xx8_snd_controls[] = { 70 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", CS42XX8_VOLAOUT1, 71 CS42XX8_VOLAOUT2, 0, 0xff, 1, dac_tlv), 72 SOC_DOUBLE_R_TLV("DAC2 Playback Volume", CS42XX8_VOLAOUT3, 73 CS42XX8_VOLAOUT4, 0, 0xff, 1, dac_tlv), 74 SOC_DOUBLE_R_TLV("DAC3 Playback Volume", CS42XX8_VOLAOUT5, 75 CS42XX8_VOLAOUT6, 0, 0xff, 1, dac_tlv), 76 SOC_DOUBLE_R_TLV("DAC4 Playback Volume", CS42XX8_VOLAOUT7, 77 CS42XX8_VOLAOUT8, 0, 0xff, 1, dac_tlv), 78 SOC_DOUBLE_R_S_TLV("ADC1 Capture Volume", CS42XX8_VOLAIN1, 79 CS42XX8_VOLAIN2, 0, -0x80, 0x30, 7, 0, adc_tlv), 80 SOC_DOUBLE_R_S_TLV("ADC2 Capture Volume", CS42XX8_VOLAIN3, 81 CS42XX8_VOLAIN4, 0, -0x80, 0x30, 7, 0, adc_tlv), 82 SOC_DOUBLE("DAC1 Invert Switch", CS42XX8_DACINV, 0, 1, 1, 0), 83 SOC_DOUBLE("DAC2 Invert Switch", CS42XX8_DACINV, 2, 3, 1, 0), 84 SOC_DOUBLE("DAC3 Invert Switch", CS42XX8_DACINV, 4, 5, 1, 0), 85 SOC_DOUBLE("DAC4 Invert Switch", CS42XX8_DACINV, 6, 7, 1, 0), 86 SOC_DOUBLE("ADC1 Invert Switch", CS42XX8_ADCINV, 0, 1, 1, 0), 87 SOC_DOUBLE("ADC2 Invert Switch", CS42XX8_ADCINV, 2, 3, 1, 0), 88 SOC_SINGLE("ADC High-Pass Filter Switch", CS42XX8_ADCCTL, 7, 1, 1), 89 SOC_SINGLE("DAC De-emphasis Switch", CS42XX8_ADCCTL, 5, 1, 0), 90 SOC_ENUM("ADC1 Single Ended Mode Switch", adc1_single_enum), 91 SOC_ENUM("ADC2 Single Ended Mode Switch", adc2_single_enum), 92 SOC_SINGLE("DAC Single Volume Control Switch", CS42XX8_TXCTL, 7, 1, 0), 93 SOC_ENUM("DAC Soft Ramp & Zero Cross Control Switch", dac_szc_enum), 94 SOC_SINGLE("DAC Auto Mute Switch", CS42XX8_TXCTL, 4, 1, 0), 95 SOC_SINGLE("Mute ADC Serial Port Switch", CS42XX8_TXCTL, 3, 1, 0), 96 SOC_SINGLE("ADC Single Volume Control Switch", CS42XX8_TXCTL, 2, 1, 0), 97 SOC_ENUM("ADC Soft Ramp & Zero Cross Control Switch", adc_szc_enum), 98 }; 99 100 static const struct snd_kcontrol_new cs42xx8_adc3_snd_controls[] = { 101 SOC_DOUBLE_R_S_TLV("ADC3 Capture Volume", CS42XX8_VOLAIN5, 102 CS42XX8_VOLAIN6, 0, -0x80, 0x30, 7, 0, adc_tlv), 103 SOC_DOUBLE("ADC3 Invert Switch", CS42XX8_ADCINV, 4, 5, 1, 0), 104 SOC_ENUM("ADC3 Single Ended Mode Switch", adc3_single_enum), 105 }; 106 107 static const struct snd_soc_dapm_widget cs42xx8_dapm_widgets[] = { 108 SND_SOC_DAPM_DAC("DAC1", "Playback", CS42XX8_PWRCTL, 1, 1), 109 SND_SOC_DAPM_DAC("DAC2", "Playback", CS42XX8_PWRCTL, 2, 1), 110 SND_SOC_DAPM_DAC("DAC3", "Playback", CS42XX8_PWRCTL, 3, 1), 111 SND_SOC_DAPM_DAC("DAC4", "Playback", CS42XX8_PWRCTL, 4, 1), 112 113 SND_SOC_DAPM_OUTPUT("AOUT1L"), 114 SND_SOC_DAPM_OUTPUT("AOUT1R"), 115 SND_SOC_DAPM_OUTPUT("AOUT2L"), 116 SND_SOC_DAPM_OUTPUT("AOUT2R"), 117 SND_SOC_DAPM_OUTPUT("AOUT3L"), 118 SND_SOC_DAPM_OUTPUT("AOUT3R"), 119 SND_SOC_DAPM_OUTPUT("AOUT4L"), 120 SND_SOC_DAPM_OUTPUT("AOUT4R"), 121 122 SND_SOC_DAPM_ADC("ADC1", "Capture", CS42XX8_PWRCTL, 5, 1), 123 SND_SOC_DAPM_ADC("ADC2", "Capture", CS42XX8_PWRCTL, 6, 1), 124 125 SND_SOC_DAPM_INPUT("AIN1L"), 126 SND_SOC_DAPM_INPUT("AIN1R"), 127 SND_SOC_DAPM_INPUT("AIN2L"), 128 SND_SOC_DAPM_INPUT("AIN2R"), 129 130 SND_SOC_DAPM_SUPPLY("PWR", CS42XX8_PWRCTL, 0, 1, NULL, 0), 131 }; 132 133 static const struct snd_soc_dapm_widget cs42xx8_adc3_dapm_widgets[] = { 134 SND_SOC_DAPM_ADC("ADC3", "Capture", CS42XX8_PWRCTL, 7, 1), 135 136 SND_SOC_DAPM_INPUT("AIN3L"), 137 SND_SOC_DAPM_INPUT("AIN3R"), 138 }; 139 140 static const struct snd_soc_dapm_route cs42xx8_dapm_routes[] = { 141 /* Playback */ 142 { "AOUT1L", NULL, "DAC1" }, 143 { "AOUT1R", NULL, "DAC1" }, 144 { "DAC1", NULL, "PWR" }, 145 146 { "AOUT2L", NULL, "DAC2" }, 147 { "AOUT2R", NULL, "DAC2" }, 148 { "DAC2", NULL, "PWR" }, 149 150 { "AOUT3L", NULL, "DAC3" }, 151 { "AOUT3R", NULL, "DAC3" }, 152 { "DAC3", NULL, "PWR" }, 153 154 { "AOUT4L", NULL, "DAC4" }, 155 { "AOUT4R", NULL, "DAC4" }, 156 { "DAC4", NULL, "PWR" }, 157 158 /* Capture */ 159 { "ADC1", NULL, "AIN1L" }, 160 { "ADC1", NULL, "AIN1R" }, 161 { "ADC1", NULL, "PWR" }, 162 163 { "ADC2", NULL, "AIN2L" }, 164 { "ADC2", NULL, "AIN2R" }, 165 { "ADC2", NULL, "PWR" }, 166 }; 167 168 static const struct snd_soc_dapm_route cs42xx8_adc3_dapm_routes[] = { 169 /* Capture */ 170 { "ADC3", NULL, "AIN3L" }, 171 { "ADC3", NULL, "AIN3R" }, 172 { "ADC3", NULL, "PWR" }, 173 }; 174 175 struct cs42xx8_ratios { 176 unsigned int ratio; 177 unsigned char speed; 178 unsigned char mclk; 179 }; 180 181 static const struct cs42xx8_ratios cs42xx8_ratios[] = { 182 { 64, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_256(4) }, 183 { 96, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_384(4) }, 184 { 128, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_512(4) }, 185 { 192, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_768(4) }, 186 { 256, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_256(1) }, 187 { 384, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_384(1) }, 188 { 512, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_512(1) }, 189 { 768, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_768(1) }, 190 { 1024, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_1024(1) } 191 }; 192 193 static int cs42xx8_set_dai_sysclk(struct snd_soc_dai *codec_dai, 194 int clk_id, unsigned int freq, int dir) 195 { 196 struct snd_soc_codec *codec = codec_dai->codec; 197 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 198 199 cs42xx8->sysclk = freq; 200 201 return 0; 202 } 203 204 static int cs42xx8_set_dai_fmt(struct snd_soc_dai *codec_dai, 205 unsigned int format) 206 { 207 struct snd_soc_codec *codec = codec_dai->codec; 208 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 209 u32 val; 210 211 /* Set DAI format */ 212 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 213 case SND_SOC_DAIFMT_LEFT_J: 214 val = CS42XX8_INTF_DAC_DIF_LEFTJ | CS42XX8_INTF_ADC_DIF_LEFTJ; 215 break; 216 case SND_SOC_DAIFMT_I2S: 217 val = CS42XX8_INTF_DAC_DIF_I2S | CS42XX8_INTF_ADC_DIF_I2S; 218 break; 219 case SND_SOC_DAIFMT_RIGHT_J: 220 val = CS42XX8_INTF_DAC_DIF_RIGHTJ | CS42XX8_INTF_ADC_DIF_RIGHTJ; 221 break; 222 case SND_SOC_DAIFMT_DSP_A: 223 val = CS42XX8_INTF_DAC_DIF_TDM | CS42XX8_INTF_ADC_DIF_TDM; 224 break; 225 default: 226 dev_err(codec->dev, "unsupported dai format\n"); 227 return -EINVAL; 228 } 229 230 regmap_update_bits(cs42xx8->regmap, CS42XX8_INTF, 231 CS42XX8_INTF_DAC_DIF_MASK | 232 CS42XX8_INTF_ADC_DIF_MASK, val); 233 234 /* Set master/slave audio interface */ 235 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 236 case SND_SOC_DAIFMT_CBS_CFS: 237 cs42xx8->slave_mode = true; 238 break; 239 case SND_SOC_DAIFMT_CBM_CFM: 240 cs42xx8->slave_mode = false; 241 break; 242 default: 243 dev_err(codec->dev, "unsupported master/slave mode\n"); 244 return -EINVAL; 245 } 246 247 return 0; 248 } 249 250 static int cs42xx8_hw_params(struct snd_pcm_substream *substream, 251 struct snd_pcm_hw_params *params, 252 struct snd_soc_dai *dai) 253 { 254 struct snd_soc_codec *codec = dai->codec; 255 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 256 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 257 u32 ratio = cs42xx8->sysclk / params_rate(params); 258 u32 i, fm, val, mask; 259 260 for (i = 0; i < ARRAY_SIZE(cs42xx8_ratios); i++) { 261 if (cs42xx8_ratios[i].ratio == ratio) 262 break; 263 } 264 265 if (i == ARRAY_SIZE(cs42xx8_ratios)) { 266 dev_err(codec->dev, "unsupported sysclk ratio\n"); 267 return -EINVAL; 268 } 269 270 mask = CS42XX8_FUNCMOD_MFREQ_MASK; 271 val = cs42xx8_ratios[i].mclk; 272 273 fm = cs42xx8->slave_mode ? CS42XX8_FM_AUTO : cs42xx8_ratios[i].speed; 274 275 regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD, 276 CS42XX8_FUNCMOD_xC_FM_MASK(tx) | mask, 277 CS42XX8_FUNCMOD_xC_FM(tx, fm) | val); 278 279 return 0; 280 } 281 282 static int cs42xx8_digital_mute(struct snd_soc_dai *dai, int mute) 283 { 284 struct snd_soc_codec *codec = dai->codec; 285 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 286 287 regmap_update_bits(cs42xx8->regmap, CS42XX8_DACMUTE, 288 CS42XX8_DACMUTE_ALL, mute ? CS42XX8_DACMUTE_ALL : 0); 289 290 return 0; 291 } 292 293 static const struct snd_soc_dai_ops cs42xx8_dai_ops = { 294 .set_fmt = cs42xx8_set_dai_fmt, 295 .set_sysclk = cs42xx8_set_dai_sysclk, 296 .hw_params = cs42xx8_hw_params, 297 .digital_mute = cs42xx8_digital_mute, 298 }; 299 300 static struct snd_soc_dai_driver cs42xx8_dai = { 301 .playback = { 302 .stream_name = "Playback", 303 .channels_min = 1, 304 .channels_max = 8, 305 .rates = SNDRV_PCM_RATE_8000_192000, 306 .formats = CS42XX8_FORMATS, 307 }, 308 .capture = { 309 .stream_name = "Capture", 310 .channels_min = 1, 311 .rates = SNDRV_PCM_RATE_8000_192000, 312 .formats = CS42XX8_FORMATS, 313 }, 314 .ops = &cs42xx8_dai_ops, 315 }; 316 317 static const struct reg_default cs42xx8_reg[] = { 318 { 0x01, 0x01 }, /* Chip I.D. and Revision Register */ 319 { 0x02, 0x00 }, /* Power Control */ 320 { 0x03, 0xF0 }, /* Functional Mode */ 321 { 0x04, 0x46 }, /* Interface Formats */ 322 { 0x05, 0x00 }, /* ADC Control & DAC De-Emphasis */ 323 { 0x06, 0x10 }, /* Transition Control */ 324 { 0x07, 0x00 }, /* DAC Channel Mute */ 325 { 0x08, 0x00 }, /* Volume Control AOUT1 */ 326 { 0x09, 0x00 }, /* Volume Control AOUT2 */ 327 { 0x0a, 0x00 }, /* Volume Control AOUT3 */ 328 { 0x0b, 0x00 }, /* Volume Control AOUT4 */ 329 { 0x0c, 0x00 }, /* Volume Control AOUT5 */ 330 { 0x0d, 0x00 }, /* Volume Control AOUT6 */ 331 { 0x0e, 0x00 }, /* Volume Control AOUT7 */ 332 { 0x0f, 0x00 }, /* Volume Control AOUT8 */ 333 { 0x10, 0x00 }, /* DAC Channel Invert */ 334 { 0x11, 0x00 }, /* Volume Control AIN1 */ 335 { 0x12, 0x00 }, /* Volume Control AIN2 */ 336 { 0x13, 0x00 }, /* Volume Control AIN3 */ 337 { 0x14, 0x00 }, /* Volume Control AIN4 */ 338 { 0x15, 0x00 }, /* Volume Control AIN5 */ 339 { 0x16, 0x00 }, /* Volume Control AIN6 */ 340 { 0x17, 0x00 }, /* ADC Channel Invert */ 341 { 0x18, 0x00 }, /* Status Control */ 342 { 0x1a, 0x00 }, /* Status Mask */ 343 { 0x1b, 0x00 }, /* MUTEC Pin Control */ 344 }; 345 346 static bool cs42xx8_volatile_register(struct device *dev, unsigned int reg) 347 { 348 switch (reg) { 349 case CS42XX8_STATUS: 350 return true; 351 default: 352 return false; 353 } 354 } 355 356 static bool cs42xx8_writeable_register(struct device *dev, unsigned int reg) 357 { 358 switch (reg) { 359 case CS42XX8_CHIPID: 360 case CS42XX8_STATUS: 361 return false; 362 default: 363 return true; 364 } 365 } 366 367 const struct regmap_config cs42xx8_regmap_config = { 368 .reg_bits = 8, 369 .val_bits = 8, 370 371 .max_register = CS42XX8_LASTREG, 372 .reg_defaults = cs42xx8_reg, 373 .num_reg_defaults = ARRAY_SIZE(cs42xx8_reg), 374 .volatile_reg = cs42xx8_volatile_register, 375 .writeable_reg = cs42xx8_writeable_register, 376 .cache_type = REGCACHE_RBTREE, 377 }; 378 EXPORT_SYMBOL_GPL(cs42xx8_regmap_config); 379 380 static int cs42xx8_codec_probe(struct snd_soc_codec *codec) 381 { 382 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 383 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 384 385 switch (cs42xx8->drvdata->num_adcs) { 386 case 3: 387 snd_soc_add_codec_controls(codec, cs42xx8_adc3_snd_controls, 388 ARRAY_SIZE(cs42xx8_adc3_snd_controls)); 389 snd_soc_dapm_new_controls(dapm, cs42xx8_adc3_dapm_widgets, 390 ARRAY_SIZE(cs42xx8_adc3_dapm_widgets)); 391 snd_soc_dapm_add_routes(dapm, cs42xx8_adc3_dapm_routes, 392 ARRAY_SIZE(cs42xx8_adc3_dapm_routes)); 393 break; 394 default: 395 break; 396 } 397 398 /* Mute all DAC channels */ 399 regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, CS42XX8_DACMUTE_ALL); 400 401 return 0; 402 } 403 404 static const struct snd_soc_codec_driver cs42xx8_driver = { 405 .probe = cs42xx8_codec_probe, 406 .idle_bias_off = true, 407 408 .controls = cs42xx8_snd_controls, 409 .num_controls = ARRAY_SIZE(cs42xx8_snd_controls), 410 .dapm_widgets = cs42xx8_dapm_widgets, 411 .num_dapm_widgets = ARRAY_SIZE(cs42xx8_dapm_widgets), 412 .dapm_routes = cs42xx8_dapm_routes, 413 .num_dapm_routes = ARRAY_SIZE(cs42xx8_dapm_routes), 414 }; 415 416 const struct cs42xx8_driver_data cs42448_data = { 417 .name = "cs42448", 418 .num_adcs = 3, 419 }; 420 EXPORT_SYMBOL_GPL(cs42448_data); 421 422 const struct cs42xx8_driver_data cs42888_data = { 423 .name = "cs42888", 424 .num_adcs = 2, 425 }; 426 EXPORT_SYMBOL_GPL(cs42888_data); 427 428 static const struct of_device_id cs42xx8_of_match[] = { 429 { .compatible = "cirrus,cs42448", .data = &cs42448_data, }, 430 { .compatible = "cirrus,cs42888", .data = &cs42888_data, }, 431 { /* sentinel */ } 432 }; 433 MODULE_DEVICE_TABLE(of, cs42xx8_of_match); 434 EXPORT_SYMBOL_GPL(cs42xx8_of_match); 435 436 int cs42xx8_probe(struct device *dev, struct regmap *regmap) 437 { 438 const struct of_device_id *of_id = of_match_device(cs42xx8_of_match, dev); 439 struct cs42xx8_priv *cs42xx8; 440 int ret, val, i; 441 442 cs42xx8 = devm_kzalloc(dev, sizeof(*cs42xx8), GFP_KERNEL); 443 if (cs42xx8 == NULL) 444 return -ENOMEM; 445 446 dev_set_drvdata(dev, cs42xx8); 447 448 if (of_id) 449 cs42xx8->drvdata = of_id->data; 450 451 if (!cs42xx8->drvdata) { 452 dev_err(dev, "failed to find driver data\n"); 453 return -EINVAL; 454 } 455 456 cs42xx8->clk = devm_clk_get(dev, "mclk"); 457 if (IS_ERR(cs42xx8->clk)) { 458 dev_err(dev, "failed to get the clock: %ld\n", 459 PTR_ERR(cs42xx8->clk)); 460 return -EINVAL; 461 } 462 463 cs42xx8->sysclk = clk_get_rate(cs42xx8->clk); 464 465 for (i = 0; i < ARRAY_SIZE(cs42xx8->supplies); i++) 466 cs42xx8->supplies[i].supply = cs42xx8_supply_names[i]; 467 468 ret = devm_regulator_bulk_get(dev, 469 ARRAY_SIZE(cs42xx8->supplies), cs42xx8->supplies); 470 if (ret) { 471 dev_err(dev, "failed to request supplies: %d\n", ret); 472 return ret; 473 } 474 475 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies), 476 cs42xx8->supplies); 477 if (ret) { 478 dev_err(dev, "failed to enable supplies: %d\n", ret); 479 return ret; 480 } 481 482 /* Make sure hardware reset done */ 483 msleep(5); 484 485 cs42xx8->regmap = regmap; 486 if (IS_ERR(cs42xx8->regmap)) { 487 ret = PTR_ERR(cs42xx8->regmap); 488 dev_err(dev, "failed to allocate regmap: %d\n", ret); 489 goto err_enable; 490 } 491 492 /* 493 * We haven't marked the chip revision as volatile due to 494 * sharing a register with the right input volume; explicitly 495 * bypass the cache to read it. 496 */ 497 regcache_cache_bypass(cs42xx8->regmap, true); 498 499 /* Validate the chip ID */ 500 ret = regmap_read(cs42xx8->regmap, CS42XX8_CHIPID, &val); 501 if (ret < 0) { 502 dev_err(dev, "failed to get device ID, ret = %d", ret); 503 goto err_enable; 504 } 505 506 /* The top four bits of the chip ID should be 0000 */ 507 if (((val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4) != 0x00) { 508 dev_err(dev, "unmatched chip ID: %d\n", 509 (val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4); 510 ret = -EINVAL; 511 goto err_enable; 512 } 513 514 dev_info(dev, "found device, revision %X\n", 515 val & CS42XX8_CHIPID_REV_ID_MASK); 516 517 regcache_cache_bypass(cs42xx8->regmap, false); 518 519 cs42xx8_dai.name = cs42xx8->drvdata->name; 520 521 /* Each adc supports stereo input */ 522 cs42xx8_dai.capture.channels_max = cs42xx8->drvdata->num_adcs * 2; 523 524 ret = snd_soc_register_codec(dev, &cs42xx8_driver, &cs42xx8_dai, 1); 525 if (ret) { 526 dev_err(dev, "failed to register codec:%d\n", ret); 527 goto err_enable; 528 } 529 530 regcache_cache_only(cs42xx8->regmap, true); 531 532 err_enable: 533 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), 534 cs42xx8->supplies); 535 536 return ret; 537 } 538 EXPORT_SYMBOL_GPL(cs42xx8_probe); 539 540 #ifdef CONFIG_PM 541 static int cs42xx8_runtime_resume(struct device *dev) 542 { 543 struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev); 544 int ret; 545 546 ret = clk_prepare_enable(cs42xx8->clk); 547 if (ret) { 548 dev_err(dev, "failed to enable mclk: %d\n", ret); 549 return ret; 550 } 551 552 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies), 553 cs42xx8->supplies); 554 if (ret) { 555 dev_err(dev, "failed to enable supplies: %d\n", ret); 556 goto err_clk; 557 } 558 559 /* Make sure hardware reset done */ 560 msleep(5); 561 562 regcache_cache_only(cs42xx8->regmap, false); 563 564 ret = regcache_sync(cs42xx8->regmap); 565 if (ret) { 566 dev_err(dev, "failed to sync regmap: %d\n", ret); 567 goto err_bulk; 568 } 569 570 return 0; 571 572 err_bulk: 573 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), 574 cs42xx8->supplies); 575 err_clk: 576 clk_disable_unprepare(cs42xx8->clk); 577 578 return ret; 579 } 580 581 static int cs42xx8_runtime_suspend(struct device *dev) 582 { 583 struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev); 584 585 regcache_cache_only(cs42xx8->regmap, true); 586 587 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), 588 cs42xx8->supplies); 589 590 clk_disable_unprepare(cs42xx8->clk); 591 592 return 0; 593 } 594 #endif 595 596 const struct dev_pm_ops cs42xx8_pm = { 597 SET_RUNTIME_PM_OPS(cs42xx8_runtime_suspend, cs42xx8_runtime_resume, NULL) 598 }; 599 EXPORT_SYMBOL_GPL(cs42xx8_pm); 600 601 MODULE_DESCRIPTION("Cirrus Logic CS42448/CS42888 ALSA SoC Codec Driver"); 602 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 603 MODULE_LICENSE("GPL"); 604