1 /* 2 * ALSA SoC CS42L73 codec driver 3 * 4 * Copyright 2011 Cirrus Logic, Inc. 5 * 6 * Author: Georgi Vlaev <joe@nucleusys.com> 7 * Brian Austin <brian.austin@cirrus.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 */ 24 25 #ifndef __CS42L73_H__ 26 #define __CS42L73_H__ 27 28 /* I2C Registers */ 29 /* I2C Address: 1001010[R/W] - 10010100 = 0x94(Write); 10010101 = 0x95(Read) */ 30 #define CS42L73_CHIP_ID 0x4a 31 #define CS42L73_DEVID_AB 0x01 /* Device ID A & B [RO]. */ 32 #define CS42L73_DEVID_CD 0x02 /* Device ID C & D [RO]. */ 33 #define CS42L73_DEVID_E 0x03 /* Device ID E [RO]. */ 34 #define CS42L73_REVID 0x05 /* Revision ID [RO]. */ 35 #define CS42L73_PWRCTL1 0x06 /* Power Control 1. */ 36 #define CS42L73_PWRCTL2 0x07 /* Power Control 2. */ 37 #define CS42L73_PWRCTL3 0x08 /* Power Control 3. */ 38 #define CS42L73_CPFCHC 0x09 /* Charge Pump Freq. Class H Ctl. */ 39 #define CS42L73_OLMBMSDC 0x0A /* Output Load, MIC Bias, MIC2 SDT */ 40 #define CS42L73_DMMCC 0x0B /* Digital MIC & Master Clock Ctl. */ 41 #define CS42L73_XSPC 0x0C /* Auxiliary Serial Port (XSP) Ctl. */ 42 #define CS42L73_XSPMMCC 0x0D /* XSP Master Mode Clocking Control. */ 43 #define CS42L73_ASPC 0x0E /* Audio Serial Port (ASP) Control. */ 44 #define CS42L73_ASPMMCC 0x0F /* ASP Master Mode Clocking Control. */ 45 #define CS42L73_VSPC 0x10 /* Voice Serial Port (VSP) Control. */ 46 #define CS42L73_VSPMMCC 0x11 /* VSP Master Mode Clocking Control. */ 47 #define CS42L73_VXSPFS 0x12 /* VSP & XSP Sample Rate. */ 48 #define CS42L73_MIOPC 0x13 /* Misc. Input & Output Path Control. */ 49 #define CS42L73_ADCIPC 0x14 /* ADC/IP Control. */ 50 #define CS42L73_MICAPREPGAAVOL 0x15 /* MIC 1 [A] PreAmp, PGAA Vol. */ 51 #define CS42L73_MICBPREPGABVOL 0x16 /* MIC 2 [B] PreAmp, PGAB Vol. */ 52 #define CS42L73_IPADVOL 0x17 /* Input Pat7h A Digital Volume. */ 53 #define CS42L73_IPBDVOL 0x18 /* Input Path B Digital Volume. */ 54 #define CS42L73_PBDC 0x19 /* Playback Digital Control. */ 55 #define CS42L73_HLADVOL 0x1A /* HP/Line A Out Digital Vol. */ 56 #define CS42L73_HLBDVOL 0x1B /* HP/Line B Out Digital Vol. */ 57 #define CS42L73_SPKDVOL 0x1C /* Spkphone Out [A] Digital Vol. */ 58 #define CS42L73_ESLDVOL 0x1D /* Ear/Spkphone LO [B] Digital */ 59 #define CS42L73_HPAAVOL 0x1E /* HP A Analog Volume. */ 60 #define CS42L73_HPBAVOL 0x1F /* HP B Analog Volume. */ 61 #define CS42L73_LOAAVOL 0x20 /* Line Out A Analog Volume. */ 62 #define CS42L73_LOBAVOL 0x21 /* Line Out B Analog Volume. */ 63 #define CS42L73_STRINV 0x22 /* Stereo Input Path Adv. Vol. */ 64 #define CS42L73_XSPINV 0x23 /* Auxiliary Port Input Advisory Vol. */ 65 #define CS42L73_ASPINV 0x24 /* Audio Port Input Advisory Vol. */ 66 #define CS42L73_VSPINV 0x25 /* Voice Port Input Advisory Vol. */ 67 #define CS42L73_LIMARATEHL 0x26 /* Lmtr Attack Rate HP/Line. */ 68 #define CS42L73_LIMRRATEHL 0x27 /* Lmtr Ctl, Rel.Rate HP/Line. */ 69 #define CS42L73_LMAXHL 0x28 /* Lmtr Thresholds HP/Line. */ 70 #define CS42L73_LIMARATESPK 0x29 /* Lmtr Attack Rate Spkphone [A]. */ 71 #define CS42L73_LIMRRATESPK 0x2A /* Lmtr Ctl,Release Rate Spk. [A]. */ 72 #define CS42L73_LMAXSPK 0x2B /* Lmtr Thresholds Spkphone [A]. */ 73 #define CS42L73_LIMARATEESL 0x2C /* Lmtr Attack Rate */ 74 #define CS42L73_LIMRRATEESL 0x2D /* Lmtr Ctl,Release Rate */ 75 #define CS42L73_LMAXESL 0x2E /* Lmtr Thresholds */ 76 #define CS42L73_ALCARATE 0x2F /* ALC Enable, Attack Rate AB. */ 77 #define CS42L73_ALCRRATE 0x30 /* ALC Release Rate AB. */ 78 #define CS42L73_ALCMINMAX 0x31 /* ALC Thresholds AB. */ 79 #define CS42L73_NGCAB 0x32 /* Noise Gate Ctl AB. */ 80 #define CS42L73_ALCNGMC 0x33 /* ALC & Noise Gate Misc Ctl. */ 81 #define CS42L73_MIXERCTL 0x34 /* Mixer Control. */ 82 #define CS42L73_HLAIPAA 0x35 /* HP/LO Left Mixer: L. */ 83 #define CS42L73_HLBIPBA 0x36 /* HP/LO Right Mixer: R. */ 84 #define CS42L73_HLAXSPAA 0x37 /* HP/LO Left Mixer: XSP L */ 85 #define CS42L73_HLBXSPBA 0x38 /* HP/LO Right Mixer: XSP R */ 86 #define CS42L73_HLAASPAA 0x39 /* HP/LO Left Mixer: ASP L */ 87 #define CS42L73_HLBASPBA 0x3A /* HP/LO Right Mixer: ASP R */ 88 #define CS42L73_HLAVSPMA 0x3B /* HP/LO Left Mixer: VSP. */ 89 #define CS42L73_HLBVSPMA 0x3C /* HP/LO Right Mixer: VSP */ 90 #define CS42L73_XSPAIPAA 0x3D /* XSP Left Mixer: Left */ 91 #define CS42L73_XSPBIPBA 0x3E /* XSP Rt. Mixer: Right */ 92 #define CS42L73_XSPAXSPAA 0x3F /* XSP Left Mixer: XSP L */ 93 #define CS42L73_XSPBXSPBA 0x40 /* XSP Rt. Mixer: XSP R */ 94 #define CS42L73_XSPAASPAA 0x41 /* XSP Left Mixer: ASP L */ 95 #define CS42L73_XSPAASPBA 0x42 /* XSP Rt. Mixer: ASP R */ 96 #define CS42L73_XSPAVSPMA 0x43 /* XSP Left Mixer: VSP */ 97 #define CS42L73_XSPBVSPMA 0x44 /* XSP Rt. Mixer: VSP */ 98 #define CS42L73_ASPAIPAA 0x45 /* ASP Left Mixer: Left */ 99 #define CS42L73_ASPBIPBA 0x46 /* ASP Rt. Mixer: Right */ 100 #define CS42L73_ASPAXSPAA 0x47 /* ASP Left Mixer: XSP L */ 101 #define CS42L73_ASPBXSPBA 0x48 /* ASP Rt. Mixer: XSP R */ 102 #define CS42L73_ASPAASPAA 0x49 /* ASP Left Mixer: ASP L */ 103 #define CS42L73_ASPBASPBA 0x4A /* ASP Rt. Mixer: ASP R */ 104 #define CS42L73_ASPAVSPMA 0x4B /* ASP Left Mixer: VSP */ 105 #define CS42L73_ASPBVSPMA 0x4C /* ASP Rt. Mixer: VSP */ 106 #define CS42L73_VSPAIPAA 0x4D /* VSP Left Mixer: Left */ 107 #define CS42L73_VSPBIPBA 0x4E /* VSP Rt. Mixer: Right */ 108 #define CS42L73_VSPAXSPAA 0x4F /* VSP Left Mixer: XSP L */ 109 #define CS42L73_VSPBXSPBA 0x50 /* VSP Rt. Mixer: XSP R */ 110 #define CS42L73_VSPAASPAA 0x51 /* VSP Left Mixer: ASP Left */ 111 #define CS42L73_VSPBASPBA 0x52 /* VSP Rt. Mixer: ASP Right */ 112 #define CS42L73_VSPAVSPMA 0x53 /* VSP Left Mixer: VSP */ 113 #define CS42L73_VSPBVSPMA 0x54 /* VSP Rt. Mixer: VSP */ 114 #define CS42L73_MMIXCTL 0x55 /* Mono Mixer Controls. */ 115 #define CS42L73_SPKMIPMA 0x56 /* SPK Mono Mixer: In. Path */ 116 #define CS42L73_SPKMXSPA 0x57 /* SPK Mono Mixer: XSP Mono/L/R Att. */ 117 #define CS42L73_SPKMASPA 0x58 /* SPK Mono Mixer: ASP Mono/L/R Att. */ 118 #define CS42L73_SPKMVSPMA 0x59 /* SPK Mono Mixer: VSP Mono Atten. */ 119 #define CS42L73_ESLMIPMA 0x5A /* Ear/SpLO Mono Mixer: */ 120 #define CS42L73_ESLMXSPA 0x5B /* Ear/SpLO Mono Mixer: XSP */ 121 #define CS42L73_ESLMASPA 0x5C /* Ear/SpLO Mono Mixer: ASP */ 122 #define CS42L73_ESLMVSPMA 0x5D /* Ear/SpLO Mono Mixer: VSP */ 123 #define CS42L73_IM1 0x5E /* Interrupt Mask 1. */ 124 #define CS42L73_IM2 0x5F /* Interrupt Mask 2. */ 125 #define CS42L73_IS1 0x60 /* Interrupt Status 1 [RO]. */ 126 #define CS42L73_IS2 0x61 /* Interrupt Status 2 [RO]. */ 127 #define CS42L73_MAX_REGISTER 0x61 /* Total Registers */ 128 /* Bitfield Definitions */ 129 130 /* CS42L73_PWRCTL1 */ 131 #define PDN_ADCB (1 << 7) 132 #define PDN_DMICB (1 << 6) 133 #define PDN_ADCA (1 << 5) 134 #define PDN_DMICA (1 << 4) 135 #define PDN_LDO (1 << 2) 136 #define DISCHG_FILT (1 << 1) 137 #define PDN (1 << 0) 138 139 /* CS42L73_PWRCTL2 */ 140 #define PDN_MIC2_BIAS (1 << 7) 141 #define PDN_MIC1_BIAS (1 << 6) 142 #define PDN_VSP (1 << 4) 143 #define PDN_ASP_SDOUT (1 << 3) 144 #define PDN_ASP_SDIN (1 << 2) 145 #define PDN_XSP_SDOUT (1 << 1) 146 #define PDN_XSP_SDIN (1 << 0) 147 148 /* CS42L73_PWRCTL3 */ 149 #define PDN_THMS (1 << 5) 150 #define PDN_SPKLO (1 << 4) 151 #define PDN_EAR (1 << 3) 152 #define PDN_SPK (1 << 2) 153 #define PDN_LO (1 << 1) 154 #define PDN_HP (1 << 0) 155 156 /* Thermal Overload Detect. Requires interrupt ... */ 157 #define THMOVLD_150C 0 158 #define THMOVLD_132C 1 159 #define THMOVLD_115C 2 160 #define THMOVLD_098C 3 161 162 163 /* CS42L73_ASPC, CS42L73_XSPC, CS42L73_VSPC */ 164 #define SP_3ST (1 << 7) 165 #define SPDIF_I2S 0 166 #define SPDIF_PCM (1 << 6) 167 #define PCM_MODE0 0 168 #define PCM_MODE1 1 169 #define PCM_MODE2 2 170 #define PCM_BO_MSBLSB 0 171 #define PCM_BO_LSBMSB 1 172 #define MCK_SCLK_64FS 0 173 #define MCK_SCLK_MCLK 2 174 #define MCK_SCLK_PREMCLK 3 175 176 /* CS42L73_xSPMMCC */ 177 #define MS_MASTER (1 << 7) 178 179 180 /* CS42L73_DMMCC */ 181 #define MCLKDIS (1 << 0) 182 #define MCLKSEL_MCLK2 (1 << 4) 183 #define MCLKSEL_MCLK1 (0 << 4) 184 185 /* CS42L73 MCLK derived from MCLK1 or MCLK2 */ 186 #define CS42L73_CLKID_MCLK1 0 187 #define CS42L73_CLKID_MCLK2 1 188 189 #define CS42L73_MCLKXDIV 0 190 #define CS42L73_MMCCDIV 1 191 192 #define CS42L73_XSP 0 193 #define CS42L73_ASP 1 194 #define CS42L73_VSP 2 195 196 /* IS1, IM1 */ 197 #define MIC2_SDET (1 << 6) 198 #define THMOVLD (1 << 4) 199 #define DIGMIXOVFL (1 << 3) 200 #define IPBOVFL (1 << 1) 201 #define IPAOVFL (1 << 0) 202 203 /* Analog Softramp */ 204 #define ANLGOSFT (1 << 0) 205 206 /* HP A/B Analog Mute */ 207 #define HPA_MUTE (1 << 7) 208 /* LO A/B Analog Mute */ 209 #define LOA_MUTE (1 << 7) 210 /* Digital Mute */ 211 #define HLAD_MUTE (1 << 0) 212 #define HLBD_MUTE (1 << 1) 213 #define SPKD_MUTE (1 << 2) 214 #define ESLD_MUTE (1 << 3) 215 216 /* Misc defines for codec */ 217 #define CS42L73_RESET_GPIO 143 218 219 #define CS42L73_DEVID 0x00042A73 220 #define CS42L73_MCLKX_MIN 5644800 221 #define CS42L73_MCLKX_MAX 38400000 222 223 #define CS42L73_SPC(id) (CS42L73_XSPC + (id << 1)) 224 #define CS42L73_MMCC(id) (CS42L73_XSPMMCC + (id << 1)) 225 #define CS42L73_SPFS(id) ((id == CS42L73_ASP) ? CS42L73_ASPC : CS42L73_VXSPFS) 226 227 #endif /* __CS42L73_H__ */ 228