1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2272b5eddSBrian Austin /* 3272b5eddSBrian Austin * cs42l52.h -- CS42L56 ALSA SoC audio driver 4272b5eddSBrian Austin * 5272b5eddSBrian Austin * Copyright 2014 CirrusLogic, Inc. 6272b5eddSBrian Austin * 7272b5eddSBrian Austin * Author: Brian Austin <brian.austin@cirrus.com> 8272b5eddSBrian Austin */ 9272b5eddSBrian Austin 10272b5eddSBrian Austin #ifndef __CS42L56_H__ 11272b5eddSBrian Austin #define __CS42L56_H__ 12272b5eddSBrian Austin 13272b5eddSBrian Austin #define CS42L56_CHIP_ID_1 0x01 14272b5eddSBrian Austin #define CS42L56_CHIP_ID_2 0x02 15272b5eddSBrian Austin #define CS42L56_PWRCTL_1 0x03 16272b5eddSBrian Austin #define CS42L56_PWRCTL_2 0x04 17272b5eddSBrian Austin #define CS42L56_CLKCTL_1 0x05 18272b5eddSBrian Austin #define CS42L56_CLKCTL_2 0x06 19272b5eddSBrian Austin #define CS42L56_SERIAL_FMT 0x07 20272b5eddSBrian Austin #define CS42L56_CLASSH_CTL 0x08 21272b5eddSBrian Austin #define CS42L56_MISC_CTL 0x09 22272b5eddSBrian Austin #define CS42L56_INT_STATUS 0x0a 23272b5eddSBrian Austin #define CS42L56_PLAYBACK_CTL 0x0b 24272b5eddSBrian Austin #define CS42L56_DSP_MUTE_CTL 0x0c 25272b5eddSBrian Austin #define CS42L56_ADCA_MIX_VOLUME 0x0d 26272b5eddSBrian Austin #define CS42L56_ADCB_MIX_VOLUME 0x0e 27272b5eddSBrian Austin #define CS42L56_PCMA_MIX_VOLUME 0x0f 28272b5eddSBrian Austin #define CS42L56_PCMB_MIX_VOLUME 0x10 29272b5eddSBrian Austin #define CS42L56_ANAINPUT_ADV_VOLUME 0x11 30272b5eddSBrian Austin #define CS42L56_DIGINPUT_ADV_VOLUME 0x12 31272b5eddSBrian Austin #define CS42L56_MASTER_A_VOLUME 0x13 32272b5eddSBrian Austin #define CS42L56_MASTER_B_VOLUME 0x14 33272b5eddSBrian Austin #define CS42L56_BEEP_FREQ_ONTIME 0x15 34272b5eddSBrian Austin #define CS42L56_BEEP_FREQ_OFFTIME 0x16 35272b5eddSBrian Austin #define CS42L56_BEEP_TONE_CFG 0x17 36272b5eddSBrian Austin #define CS42L56_TONE_CTL 0x18 37272b5eddSBrian Austin #define CS42L56_CHAN_MIX_SWAP 0x19 38272b5eddSBrian Austin #define CS42L56_AIN_REFCFG_ADC_MUX 0x1a 39272b5eddSBrian Austin #define CS42L56_HPF_CTL 0x1b 40272b5eddSBrian Austin #define CS42L56_MISC_ADC_CTL 0x1c 41272b5eddSBrian Austin #define CS42L56_GAIN_BIAS_CTL 0x1d 42272b5eddSBrian Austin #define CS42L56_PGAA_MUX_VOLUME 0x1e 43272b5eddSBrian Austin #define CS42L56_PGAB_MUX_VOLUME 0x1f 44272b5eddSBrian Austin #define CS42L56_ADCA_ATTENUATOR 0x20 45272b5eddSBrian Austin #define CS42L56_ADCB_ATTENUATOR 0x21 46272b5eddSBrian Austin #define CS42L56_ALC_EN_ATTACK_RATE 0x22 47272b5eddSBrian Austin #define CS42L56_ALC_RELEASE_RATE 0x23 48272b5eddSBrian Austin #define CS42L56_ALC_THRESHOLD 0x24 49272b5eddSBrian Austin #define CS42L56_NOISE_GATE_CTL 0x25 50272b5eddSBrian Austin #define CS42L56_ALC_LIM_SFT_ZC 0x26 51272b5eddSBrian Austin #define CS42L56_AMUTE_HPLO_MUX 0x27 52272b5eddSBrian Austin #define CS42L56_HPA_VOLUME 0x28 53272b5eddSBrian Austin #define CS42L56_HPB_VOLUME 0x29 54272b5eddSBrian Austin #define CS42L56_LOA_VOLUME 0x2a 55272b5eddSBrian Austin #define CS42L56_LOB_VOLUME 0x2b 56272b5eddSBrian Austin #define CS42L56_LIM_THRESHOLD_CTL 0x2c 57272b5eddSBrian Austin #define CS42L56_LIM_CTL_RELEASE_RATE 0x2d 58272b5eddSBrian Austin #define CS42L56_LIM_ATTACK_RATE 0x2e 59272b5eddSBrian Austin 60272b5eddSBrian Austin /* Device ID and Rev ID Masks */ 61272b5eddSBrian Austin #define CS42L56_DEVID 0x56 62272b5eddSBrian Austin #define CS42L56_CHIP_ID_MASK 0xff 63272b5eddSBrian Austin #define CS42L56_AREV_MASK 0x1c 64272b5eddSBrian Austin #define CS42L56_MTLREV_MASK 0x03 65272b5eddSBrian Austin 66272b5eddSBrian Austin /* Power bit masks */ 67272b5eddSBrian Austin #define CS42L56_PDN_ALL_MASK 0x01 68272b5eddSBrian Austin #define CS42L56_PDN_ADCA_MASK 0x02 69272b5eddSBrian Austin #define CS42L56_PDN_ADCB_MASK 0x04 70272b5eddSBrian Austin #define CS42L56_PDN_CHRG_MASK 0x08 71272b5eddSBrian Austin #define CS42L56_PDN_BIAS_MASK 0x10 72272b5eddSBrian Austin #define CS42L56_PDN_VBUF_MASK 0x20 73272b5eddSBrian Austin #define CS42L56_PDN_LOA_MASK 0x03 74272b5eddSBrian Austin #define CS42L56_PDN_LOB_MASK 0x0c 75272b5eddSBrian Austin #define CS42L56_PDN_HPA_MASK 0x30 76272b5eddSBrian Austin #define CS42L56_PDN_HPB_MASK 0xc0 77272b5eddSBrian Austin 78272b5eddSBrian Austin /* serial port and clk masks */ 794641c771SAxel Lin #define CS42L56_MASTER_MODE 0x40 80272b5eddSBrian Austin #define CS42L56_SLAVE_MODE 0 81272b5eddSBrian Austin #define CS42L56_MS_MODE_MASK 0x40 824641c771SAxel Lin #define CS42L56_SCLK_INV 0x20 83272b5eddSBrian Austin #define CS42L56_SCLK_INV_MASK 0x20 84272b5eddSBrian Austin #define CS42L56_SCLK_MCLK_MASK 0x18 854641c771SAxel Lin #define CS42L56_MCLK_PREDIV 0x04 86272b5eddSBrian Austin #define CS42L56_MCLK_PREDIV_MASK 0x04 874641c771SAxel Lin #define CS42L56_MCLK_DIV2 0x02 88272b5eddSBrian Austin #define CS42L56_MCLK_DIV2_MASK 0x02 89272b5eddSBrian Austin #define CS42L56_MCLK_DIS_MASK 0x01 90272b5eddSBrian Austin #define CS42L56_CLK_AUTO_MASK 0x20 91272b5eddSBrian Austin #define CS42L56_CLK_RATIO_MASK 0x1f 92272b5eddSBrian Austin #define CS42L56_DIG_FMT_I2S 0 934641c771SAxel Lin #define CS42L56_DIG_FMT_LEFT_J 0x08 94272b5eddSBrian Austin #define CS42L56_DIG_FMT_MASK 0x08 95272b5eddSBrian Austin 96272b5eddSBrian Austin /* Class H and misc ctl masks */ 97272b5eddSBrian Austin #define CS42L56_ADAPT_PWR_MASK 0xc0 98272b5eddSBrian Austin #define CS42L56_CHRG_FREQ_MASK 0x0f 99272b5eddSBrian Austin #define CS42L56_DIG_MUX_MASK 0x80 100272b5eddSBrian Austin #define CS42L56_ANLGSFT_MASK 0x10 101272b5eddSBrian Austin #define CS42L56_ANLGZC_MASK 0x08 102272b5eddSBrian Austin #define CS42L56_DIGSFT_MASK 0x04 103272b5eddSBrian Austin #define CS42L56_FREEZE_MASK 0x01 104272b5eddSBrian Austin #define CS42L56_MIC_BIAS_MASK 0x03 105272b5eddSBrian Austin #define CS42L56_HPFA_FREQ_MASK 0x03 106272b5eddSBrian Austin #define CS42L56_HPFB_FREQ_MASK 0xc0 107272b5eddSBrian Austin #define CS42L56_AIN1A_REF_MASK 0x10 108272b5eddSBrian Austin #define CS42L56_AIN2A_REF_MASK 0x40 109272b5eddSBrian Austin #define CS42L56_AIN1B_REF_MASK 0x20 110272b5eddSBrian Austin #define CS42L56_AIN2B_REF_MASK 0x80 111272b5eddSBrian Austin 112272b5eddSBrian Austin /* Playback Capture ctl masks */ 113272b5eddSBrian Austin #define CS42L56_PDN_DSP_MASK 0x80 114272b5eddSBrian Austin #define CS42L56_DEEMPH_MASK 0x40 115272b5eddSBrian Austin #define CS42L56_PLYBCK_GANG_MASK 0x10 116272b5eddSBrian Austin #define CS42L56_PCM_INV_MASK 0x0c 1174641c771SAxel Lin #define CS42L56_MUTE_ALL 0xff 118272b5eddSBrian Austin #define CS42L56_UNMUTE 0 119272b5eddSBrian Austin #define CS42L56_ADCAMIX_MUTE_MASK 0x40 120272b5eddSBrian Austin #define CS42L56_ADCBMIX_MUTE_MASK 0x80 121272b5eddSBrian Austin #define CS42L56_PCMAMIX_MUTE_MASK 0x10 122272b5eddSBrian Austin #define CS42L56_PCMBMIX_MUTE_MASK 0x20 123272b5eddSBrian Austin #define CS42L56_MSTB_MUTE_MASK 0x02 124272b5eddSBrian Austin #define CS42L56_MSTA_MUTE_MASK 0x01 125272b5eddSBrian Austin #define CS42L56_ADCA_MUTE_MASK 0x01 126272b5eddSBrian Austin #define CS42L56_ADCB_MUTE_MASK 0x02 127272b5eddSBrian Austin #define CS42L56_HP_MUTE_MASK 0x80 128272b5eddSBrian Austin #define CS42L56_LO_MUTE_MASK 0x80 129272b5eddSBrian Austin 130272b5eddSBrian Austin /* Beep masks */ 131272b5eddSBrian Austin #define CS42L56_BEEP_FREQ_MASK 0xf0 132272b5eddSBrian Austin #define CS42L56_BEEP_ONTIME_MASK 0x0f 133272b5eddSBrian Austin #define CS42L56_BEEP_OFFTIME_MASK 0xe0 134272b5eddSBrian Austin #define CS42L56_BEEP_CFG_MASK 0xc0 135272b5eddSBrian Austin #define CS42L56_BEEP_TREBCF_MASK 0x18 136272b5eddSBrian Austin #define CS42L56_BEEP_BASSCF_MASK 0x06 137272b5eddSBrian Austin #define CS42L56_BEEP_TCEN_MASK 0x01 138272b5eddSBrian Austin #define CS42L56_BEEP_RATE_SHIFT 4 139272b5eddSBrian Austin #define CS42L56_BEEP_EN_MASK 0x3f 140272b5eddSBrian Austin 141272b5eddSBrian Austin 142272b5eddSBrian Austin /* Supported MCLKS */ 143272b5eddSBrian Austin #define CS42L56_MCLK_5P6448MHZ 5644800 144272b5eddSBrian Austin #define CS42L56_MCLK_6MHZ 6000000 145272b5eddSBrian Austin #define CS42L56_MCLK_6P144MHZ 6144000 146272b5eddSBrian Austin #define CS42L56_MCLK_11P2896MHZ 11289600 147272b5eddSBrian Austin #define CS42L56_MCLK_12MHZ 12000000 148272b5eddSBrian Austin #define CS42L56_MCLK_12P288MHZ 12288000 149272b5eddSBrian Austin #define CS42L56_MCLK_22P5792MHZ 22579200 150272b5eddSBrian Austin #define CS42L56_MCLK_24MHZ 24000000 151272b5eddSBrian Austin #define CS42L56_MCLK_24P576MHZ 24576000 152272b5eddSBrian Austin 153272b5eddSBrian Austin /* Clock ratios */ 154272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_128 0x08 155272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_125 0x09 156272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_136 0x0b 157272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_192 0x0c 158272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_187P5 0x0d 159272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_256 0x10 160272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_250 0x11 161272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_272 0x13 162272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_384 0x14 163272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_375 0x15 164272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_512 0x18 165272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_500 0x19 166272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_544 0x1b 167272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_750 0x1c 168272b5eddSBrian Austin #define CS42L56_MCLK_LRCLK_768 0x1d 169272b5eddSBrian Austin 170272b5eddSBrian Austin 171272b5eddSBrian Austin #define CS42L56_MAX_REGISTER 0x34 172272b5eddSBrian Austin 173272b5eddSBrian Austin #endif 174