1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l52.c -- CS42L52 ALSA SoC audio driver 4 * 5 * Copyright 2012 CirrusLogic, Inc. 6 * 7 * Author: Georgi Vlaev <joe@nucleusys.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pm.h> 18 #include <linux/i2c.h> 19 #include <linux/input.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/workqueue.h> 23 #include <linux/platform_device.h> 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dapm.h> 29 #include <sound/initval.h> 30 #include <sound/tlv.h> 31 #include <sound/cs42l52.h> 32 #include "cs42l52.h" 33 34 struct sp_config { 35 u8 spc, format, spfs; 36 u32 srate; 37 }; 38 39 struct cs42l52_private { 40 struct regmap *regmap; 41 struct snd_soc_component *component; 42 struct device *dev; 43 struct sp_config config; 44 struct cs42l52_platform_data pdata; 45 u32 sysclk; 46 u8 mclksel; 47 u32 mclk; 48 u8 flags; 49 struct input_dev *beep; 50 struct work_struct beep_work; 51 int beep_rate; 52 }; 53 54 static const struct reg_default cs42l52_reg_defaults[] = { 55 { CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */ 56 { CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */ 57 { CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */ 58 { CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */ 59 { CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */ 60 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */ 61 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */ 62 { CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */ 63 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */ 64 { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */ 65 { CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */ 66 { CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */ 67 { CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */ 68 { CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */ 69 { CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */ 70 { CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */ 71 { CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */ 72 { CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */ 73 { CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */ 74 { CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */ 75 { CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */ 76 { CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */ 77 { CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */ 78 { CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */ 79 { CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */ 80 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */ 81 { CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */ 82 { CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */ 83 { CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */ 84 { CS42L52_MASTERA_VOL, 0x00 }, /* r20 Master A Volume */ 85 { CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */ 86 { CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */ 87 { CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */ 88 { CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */ 89 { CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */ 90 { CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */ 91 { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */ 92 { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */ 93 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */ 94 { CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */ 95 { CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */ 96 { CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */ 97 { CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */ 98 { CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */ 99 { CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */ 100 { CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */ 101 { CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */ 102 { CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */ 103 { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */ 104 }; 105 106 static bool cs42l52_readable_register(struct device *dev, unsigned int reg) 107 { 108 switch (reg) { 109 case CS42L52_CHIP ... CS42L52_CHARGE_PUMP: 110 return true; 111 default: 112 return false; 113 } 114 } 115 116 static bool cs42l52_volatile_register(struct device *dev, unsigned int reg) 117 { 118 switch (reg) { 119 case CS42L52_IFACE_CTL2: 120 case CS42L52_CLK_STATUS: 121 case CS42L52_BATT_LEVEL: 122 case CS42L52_SPK_STATUS: 123 case CS42L52_CHARGE_PUMP: 124 return true; 125 default: 126 return false; 127 } 128 } 129 130 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0); 131 132 static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1); 133 134 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0); 135 136 static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0); 137 138 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0); 139 140 static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0); 141 142 static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0); 143 144 static const DECLARE_TLV_DB_RANGE(limiter_tlv, 145 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0), 146 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0) 147 ); 148 149 static const char * const cs42l52_adca_text[] = { 150 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"}; 151 152 static const char * const cs42l52_adcb_text[] = { 153 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"}; 154 155 static SOC_ENUM_SINGLE_DECL(adca_enum, 156 CS42L52_ADC_PGA_A, 5, cs42l52_adca_text); 157 158 static SOC_ENUM_SINGLE_DECL(adcb_enum, 159 CS42L52_ADC_PGA_B, 5, cs42l52_adcb_text); 160 161 static const struct snd_kcontrol_new adca_mux = 162 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum); 163 164 static const struct snd_kcontrol_new adcb_mux = 165 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum); 166 167 static const char * const mic_bias_level_text[] = { 168 "0.5 +VA", "0.6 +VA", "0.7 +VA", 169 "0.8 +VA", "0.83 +VA", "0.91 +VA" 170 }; 171 172 static SOC_ENUM_SINGLE_DECL(mic_bias_level_enum, 173 CS42L52_IFACE_CTL2, 0, mic_bias_level_text); 174 175 static const char * const cs42l52_mic_text[] = { "MIC1", "MIC2" }; 176 177 static SOC_ENUM_SINGLE_DECL(mica_enum, 178 CS42L52_MICA_CTL, 5, cs42l52_mic_text); 179 180 static SOC_ENUM_SINGLE_DECL(micb_enum, 181 CS42L52_MICB_CTL, 5, cs42l52_mic_text); 182 183 static const char * const digital_output_mux_text[] = {"ADC", "DSP"}; 184 185 static SOC_ENUM_SINGLE_DECL(digital_output_mux_enum, 186 CS42L52_ADC_MISC_CTL, 6, 187 digital_output_mux_text); 188 189 static const struct snd_kcontrol_new digital_output_mux = 190 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum); 191 192 static const char * const hp_gain_num_text[] = { 193 "0.3959", "0.4571", "0.5111", "0.6047", 194 "0.7099", "0.8399", "1.000", "1.1430" 195 }; 196 197 static SOC_ENUM_SINGLE_DECL(hp_gain_enum, 198 CS42L52_PB_CTL1, 5, 199 hp_gain_num_text); 200 201 static const char * const beep_pitch_text[] = { 202 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5", 203 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7" 204 }; 205 206 static SOC_ENUM_SINGLE_DECL(beep_pitch_enum, 207 CS42L52_BEEP_FREQ, 4, 208 beep_pitch_text); 209 210 static const char * const beep_ontime_text[] = { 211 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s", 212 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s", 213 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s" 214 }; 215 216 static SOC_ENUM_SINGLE_DECL(beep_ontime_enum, 217 CS42L52_BEEP_FREQ, 0, 218 beep_ontime_text); 219 220 static const char * const beep_offtime_text[] = { 221 "1.23 s", "2.58 s", "3.90 s", "5.20 s", 222 "6.60 s", "8.05 s", "9.35 s", "10.80 s" 223 }; 224 225 static SOC_ENUM_SINGLE_DECL(beep_offtime_enum, 226 CS42L52_BEEP_VOL, 5, 227 beep_offtime_text); 228 229 static const char * const beep_config_text[] = { 230 "Off", "Single", "Multiple", "Continuous" 231 }; 232 233 static SOC_ENUM_SINGLE_DECL(beep_config_enum, 234 CS42L52_BEEP_TONE_CTL, 6, 235 beep_config_text); 236 237 static const char * const beep_bass_text[] = { 238 "50 Hz", "100 Hz", "200 Hz", "250 Hz" 239 }; 240 241 static SOC_ENUM_SINGLE_DECL(beep_bass_enum, 242 CS42L52_BEEP_TONE_CTL, 1, 243 beep_bass_text); 244 245 static const char * const beep_treble_text[] = { 246 "5 kHz", "7 kHz", "10 kHz", " 15 kHz" 247 }; 248 249 static SOC_ENUM_SINGLE_DECL(beep_treble_enum, 250 CS42L52_BEEP_TONE_CTL, 3, 251 beep_treble_text); 252 253 static const char * const ng_threshold_text[] = { 254 "-34dB", "-37dB", "-40dB", "-43dB", 255 "-46dB", "-52dB", "-58dB", "-64dB" 256 }; 257 258 static SOC_ENUM_SINGLE_DECL(ng_threshold_enum, 259 CS42L52_NOISE_GATE_CTL, 2, 260 ng_threshold_text); 261 262 static const char * const cs42l52_ng_delay_text[] = { 263 "50ms", "100ms", "150ms", "200ms"}; 264 265 static SOC_ENUM_SINGLE_DECL(ng_delay_enum, 266 CS42L52_NOISE_GATE_CTL, 0, 267 cs42l52_ng_delay_text); 268 269 static const char * const cs42l52_ng_type_text[] = { 270 "Apply Specific", "Apply All" 271 }; 272 273 static SOC_ENUM_SINGLE_DECL(ng_type_enum, 274 CS42L52_NOISE_GATE_CTL, 6, 275 cs42l52_ng_type_text); 276 277 static const char * const left_swap_text[] = { 278 "Left", "LR 2", "Right"}; 279 280 static const char * const right_swap_text[] = { 281 "Right", "LR 2", "Left"}; 282 283 static const unsigned int swap_values[] = { 0, 1, 3 }; 284 285 static const struct soc_enum adca_swap_enum = 286 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 3, 287 ARRAY_SIZE(left_swap_text), 288 left_swap_text, 289 swap_values); 290 291 static const struct snd_kcontrol_new adca_mixer = 292 SOC_DAPM_ENUM("Route", adca_swap_enum); 293 294 static const struct soc_enum pcma_swap_enum = 295 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 3, 296 ARRAY_SIZE(left_swap_text), 297 left_swap_text, 298 swap_values); 299 300 static const struct snd_kcontrol_new pcma_mixer = 301 SOC_DAPM_ENUM("Route", pcma_swap_enum); 302 303 static const struct soc_enum adcb_swap_enum = 304 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 3, 305 ARRAY_SIZE(right_swap_text), 306 right_swap_text, 307 swap_values); 308 309 static const struct snd_kcontrol_new adcb_mixer = 310 SOC_DAPM_ENUM("Route", adcb_swap_enum); 311 312 static const struct soc_enum pcmb_swap_enum = 313 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 3, 314 ARRAY_SIZE(right_swap_text), 315 right_swap_text, 316 swap_values); 317 318 static const struct snd_kcontrol_new pcmb_mixer = 319 SOC_DAPM_ENUM("Route", pcmb_swap_enum); 320 321 322 static const struct snd_kcontrol_new passthrul_ctl = 323 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0); 324 325 static const struct snd_kcontrol_new passthrur_ctl = 326 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0); 327 328 static const struct snd_kcontrol_new spkl_ctl = 329 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1); 330 331 static const struct snd_kcontrol_new spkr_ctl = 332 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1); 333 334 static const struct snd_kcontrol_new hpl_ctl = 335 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1); 336 337 static const struct snd_kcontrol_new hpr_ctl = 338 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1); 339 340 static const struct snd_kcontrol_new cs42l52_snd_controls[] = { 341 342 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL, 343 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv), 344 345 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL, 346 CS42L52_HPB_VOL, 0, 0x34, 0xC0, hpd_tlv), 347 348 SOC_ENUM("Headphone Analog Gain", hp_gain_enum), 349 350 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL, 351 CS42L52_SPKB_VOL, 0, 0x40, 0xC0, hl_tlv), 352 353 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL, 354 CS42L52_PASSTHRUB_VOL, 0, 0x88, 0x90, pga_tlv), 355 356 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0), 357 358 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL, 359 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv), 360 361 SOC_ENUM("MIC Bias Level", mic_bias_level_enum), 362 363 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL, 364 CS42L52_ADCB_VOL, 0, 0xA0, 0x78, ipd_tlv), 365 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume", 366 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL, 367 0, 0x19, 0x7F, ipd_tlv), 368 369 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0), 370 371 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL, 372 CS42L52_ADCB_MIXER_VOL, 7, 1, 1), 373 374 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL, 375 CS42L52_PGAB_CTL, 0, 0x28, 0x24, pga_tlv), 376 377 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume", 378 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 379 0, 0x19, 0x7f, mix_tlv), 380 SOC_DOUBLE_R("PCM Mixer Switch", 381 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1), 382 383 SOC_ENUM("Beep Config", beep_config_enum), 384 SOC_ENUM("Beep Pitch", beep_pitch_enum), 385 SOC_ENUM("Beep on Time", beep_ontime_enum), 386 SOC_ENUM("Beep off Time", beep_offtime_enum), 387 SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL, 388 0, 0x07, 0x1f, beep_tlv), 389 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1), 390 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum), 391 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum), 392 393 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1), 394 SOC_SINGLE_TLV("Treble Gain Volume", 395 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv), 396 SOC_SINGLE_TLV("Bass Gain Volume", 397 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv), 398 399 /* Limiter */ 400 SOC_SINGLE_TLV("Limiter Max Threshold Volume", 401 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv), 402 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume", 403 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv), 404 SOC_SINGLE_TLV("Limiter Release Rate Volume", 405 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv), 406 SOC_SINGLE_TLV("Limiter Attack Rate Volume", 407 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv), 408 409 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0), 410 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0), 411 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0), 412 413 /* ALC */ 414 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL, 415 0, 63, 0, limiter_tlv), 416 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE, 417 0, 63, 0, limiter_tlv), 418 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD, 419 5, 7, 0, limiter_tlv), 420 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD, 421 2, 7, 0, limiter_tlv), 422 423 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL, 424 CS42L52_PGAB_CTL, 7, 1, 1), 425 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL, 426 CS42L52_PGAB_CTL, 6, 1, 1), 427 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0), 428 429 /* Noise gate */ 430 SOC_ENUM("NG Type Switch", ng_type_enum), 431 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0), 432 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1), 433 SOC_ENUM("NG Threshold", ng_threshold_enum), 434 SOC_ENUM("NG Delay", ng_delay_enum), 435 436 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0), 437 438 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1), 439 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1), 440 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0), 441 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0), 442 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0), 443 444 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0), 445 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0), 446 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0), 447 448 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0), 449 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0), 450 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0), 451 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0), 452 453 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0), 454 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0), 455 456 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0), 457 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0), 458 459 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0), 460 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0), 461 462 }; 463 464 static const struct snd_kcontrol_new cs42l52_mica_controls[] = { 465 SOC_ENUM("MICA Select", mica_enum), 466 }; 467 468 static const struct snd_kcontrol_new cs42l52_micb_controls[] = { 469 SOC_ENUM("MICB Select", micb_enum), 470 }; 471 472 static int cs42l52_add_mic_controls(struct snd_soc_component *component) 473 { 474 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component); 475 struct cs42l52_platform_data *pdata = &cs42l52->pdata; 476 477 if (!pdata->mica_diff_cfg) 478 snd_soc_add_component_controls(component, cs42l52_mica_controls, 479 ARRAY_SIZE(cs42l52_mica_controls)); 480 481 if (!pdata->micb_diff_cfg) 482 snd_soc_add_component_controls(component, cs42l52_micb_controls, 483 ARRAY_SIZE(cs42l52_micb_controls)); 484 485 return 0; 486 } 487 488 static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = { 489 490 SND_SOC_DAPM_INPUT("AIN1L"), 491 SND_SOC_DAPM_INPUT("AIN1R"), 492 SND_SOC_DAPM_INPUT("AIN2L"), 493 SND_SOC_DAPM_INPUT("AIN2R"), 494 SND_SOC_DAPM_INPUT("AIN3L"), 495 SND_SOC_DAPM_INPUT("AIN3R"), 496 SND_SOC_DAPM_INPUT("AIN4L"), 497 SND_SOC_DAPM_INPUT("AIN4R"), 498 SND_SOC_DAPM_INPUT("MICA"), 499 SND_SOC_DAPM_INPUT("MICB"), 500 SND_SOC_DAPM_SIGGEN("Beep"), 501 502 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0, 503 SND_SOC_NOPM, 0, 0), 504 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0, 505 SND_SOC_NOPM, 0, 0), 506 507 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1), 508 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1), 509 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0), 510 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0), 511 512 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux), 513 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux), 514 515 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM, 516 0, 0, &adca_mixer), 517 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM, 518 0, 0, &adcb_mixer), 519 520 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 521 0, 0, &digital_output_mux), 522 523 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0), 524 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0), 525 526 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0), 527 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0), 528 529 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0, 530 SND_SOC_NOPM, 0, 0), 531 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0, 532 SND_SOC_NOPM, 0, 0), 533 534 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0), 535 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0), 536 537 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL, 538 6, 0, &passthrul_ctl), 539 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL, 540 7, 0, &passthrur_ctl), 541 542 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM, 543 0, 0, &pcma_mixer), 544 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM, 545 0, 0, &pcmb_mixer), 546 547 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl), 548 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl), 549 550 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl), 551 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl), 552 553 SND_SOC_DAPM_OUTPUT("HPOUTA"), 554 SND_SOC_DAPM_OUTPUT("HPOUTB"), 555 SND_SOC_DAPM_OUTPUT("SPKOUTA"), 556 SND_SOC_DAPM_OUTPUT("SPKOUTB"), 557 558 }; 559 560 static const struct snd_soc_dapm_route cs42l52_audio_map[] = { 561 562 {"Capture", NULL, "AIFOUTL"}, 563 {"Capture", NULL, "AIFOUTL"}, 564 565 {"AIFOUTL", NULL, "Output Mux"}, 566 {"AIFOUTR", NULL, "Output Mux"}, 567 568 {"Output Mux", "ADC", "ADC Left"}, 569 {"Output Mux", "ADC", "ADC Right"}, 570 571 {"ADC Left", NULL, "Charge Pump"}, 572 {"ADC Right", NULL, "Charge Pump"}, 573 574 {"Charge Pump", NULL, "ADC Left Mux"}, 575 {"Charge Pump", NULL, "ADC Right Mux"}, 576 577 {"ADC Left Mux", "Input1A", "AIN1L"}, 578 {"ADC Right Mux", "Input1B", "AIN1R"}, 579 {"ADC Left Mux", "Input2A", "AIN2L"}, 580 {"ADC Right Mux", "Input2B", "AIN2R"}, 581 {"ADC Left Mux", "Input3A", "AIN3L"}, 582 {"ADC Right Mux", "Input3B", "AIN3R"}, 583 {"ADC Left Mux", "Input4A", "AIN4L"}, 584 {"ADC Right Mux", "Input4B", "AIN4R"}, 585 {"ADC Left Mux", "PGA Input Left", "PGA Left"}, 586 {"ADC Right Mux", "PGA Input Right" , "PGA Right"}, 587 588 {"PGA Left", "Switch", "AIN1L"}, 589 {"PGA Right", "Switch", "AIN1R"}, 590 {"PGA Left", "Switch", "AIN2L"}, 591 {"PGA Right", "Switch", "AIN2R"}, 592 {"PGA Left", "Switch", "AIN3L"}, 593 {"PGA Right", "Switch", "AIN3R"}, 594 {"PGA Left", "Switch", "AIN4L"}, 595 {"PGA Right", "Switch", "AIN4R"}, 596 597 {"PGA Left", "Switch", "PGA MICA"}, 598 {"PGA MICA", NULL, "MICA"}, 599 600 {"PGA Right", "Switch", "PGA MICB"}, 601 {"PGA MICB", NULL, "MICB"}, 602 603 {"HPOUTA", NULL, "HP Left Amp"}, 604 {"HPOUTB", NULL, "HP Right Amp"}, 605 {"HP Left Amp", NULL, "Bypass Left"}, 606 {"HP Right Amp", NULL, "Bypass Right"}, 607 {"Bypass Left", "Switch", "PGA Left"}, 608 {"Bypass Right", "Switch", "PGA Right"}, 609 {"HP Left Amp", "Switch", "DAC Left"}, 610 {"HP Right Amp", "Switch", "DAC Right"}, 611 612 {"SPKOUTA", NULL, "SPK Left Amp"}, 613 {"SPKOUTB", NULL, "SPK Right Amp"}, 614 615 {"SPK Left Amp", NULL, "Beep"}, 616 {"SPK Right Amp", NULL, "Beep"}, 617 {"SPK Left Amp", "Switch", "Playback"}, 618 {"SPK Right Amp", "Switch", "Playback"}, 619 620 {"DAC Left", NULL, "Beep"}, 621 {"DAC Right", NULL, "Beep"}, 622 {"DAC Left", NULL, "Playback"}, 623 {"DAC Right", NULL, "Playback"}, 624 625 {"Output Mux", "DSP", "Playback"}, 626 {"Output Mux", "DSP", "Playback"}, 627 628 {"AIFINL", NULL, "Playback"}, 629 {"AIFINR", NULL, "Playback"}, 630 631 }; 632 633 struct cs42l52_clk_para { 634 u32 mclk; 635 u32 rate; 636 u8 speed; 637 u8 group; 638 u8 videoclk; 639 u8 ratio; 640 u8 mclkdiv2; 641 }; 642 643 static const struct cs42l52_clk_para clk_map_table[] = { 644 /*8k*/ 645 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0}, 646 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0}, 647 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0}, 648 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1}, 649 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0}, 650 651 /*11.025k*/ 652 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 653 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 654 655 /*16k*/ 656 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0}, 657 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0}, 658 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0}, 659 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1}, 660 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1}, 661 662 /*22.05k*/ 663 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 664 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 665 666 /* 32k */ 667 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0}, 668 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0}, 669 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0}, 670 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1}, 671 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0}, 672 673 /* 44.1k */ 674 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 675 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 676 677 /* 48k */ 678 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 679 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 680 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0}, 681 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1}, 682 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1}, 683 684 /* 88.2k */ 685 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 686 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 687 688 /* 96k */ 689 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 690 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0}, 691 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0}, 692 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1}, 693 }; 694 695 static int cs42l52_get_clk(int mclk, int rate) 696 { 697 int i, ret = -EINVAL; 698 u_int mclk1, mclk2 = 0; 699 700 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) { 701 if (clk_map_table[i].rate == rate) { 702 mclk1 = clk_map_table[i].mclk; 703 if (abs(mclk - mclk1) < abs(mclk - mclk2)) { 704 mclk2 = mclk1; 705 ret = i; 706 } 707 } 708 } 709 return ret; 710 } 711 712 static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai, 713 int clk_id, unsigned int freq, int dir) 714 { 715 struct snd_soc_component *component = codec_dai->component; 716 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component); 717 718 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) { 719 cs42l52->sysclk = freq; 720 } else { 721 dev_err(component->dev, "Invalid freq parameter\n"); 722 return -EINVAL; 723 } 724 return 0; 725 } 726 727 static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 728 { 729 struct snd_soc_component *component = codec_dai->component; 730 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component); 731 u8 iface = 0; 732 733 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 734 case SND_SOC_DAIFMT_CBM_CFM: 735 iface = CS42L52_IFACE_CTL1_MASTER; 736 break; 737 case SND_SOC_DAIFMT_CBS_CFS: 738 iface = CS42L52_IFACE_CTL1_SLAVE; 739 break; 740 default: 741 return -EINVAL; 742 } 743 744 /* interface format */ 745 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 746 case SND_SOC_DAIFMT_I2S: 747 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S | 748 CS42L52_IFACE_CTL1_DAC_FMT_I2S; 749 break; 750 case SND_SOC_DAIFMT_RIGHT_J: 751 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J; 752 break; 753 case SND_SOC_DAIFMT_LEFT_J: 754 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J | 755 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J; 756 break; 757 case SND_SOC_DAIFMT_DSP_A: 758 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN; 759 break; 760 case SND_SOC_DAIFMT_DSP_B: 761 break; 762 default: 763 return -EINVAL; 764 } 765 766 /* clock inversion */ 767 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 768 case SND_SOC_DAIFMT_NB_NF: 769 break; 770 case SND_SOC_DAIFMT_IB_IF: 771 iface |= CS42L52_IFACE_CTL1_INV_SCLK; 772 break; 773 case SND_SOC_DAIFMT_IB_NF: 774 iface |= CS42L52_IFACE_CTL1_INV_SCLK; 775 break; 776 case SND_SOC_DAIFMT_NB_IF: 777 break; 778 default: 779 return -EINVAL; 780 } 781 cs42l52->config.format = iface; 782 snd_soc_component_write(component, CS42L52_IFACE_CTL1, cs42l52->config.format); 783 784 return 0; 785 } 786 787 static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute) 788 { 789 struct snd_soc_component *component = dai->component; 790 791 if (mute) 792 snd_soc_component_update_bits(component, CS42L52_PB_CTL1, 793 CS42L52_PB_CTL1_MUTE_MASK, 794 CS42L52_PB_CTL1_MUTE); 795 else 796 snd_soc_component_update_bits(component, CS42L52_PB_CTL1, 797 CS42L52_PB_CTL1_MUTE_MASK, 798 CS42L52_PB_CTL1_UNMUTE); 799 800 return 0; 801 } 802 803 static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream, 804 struct snd_pcm_hw_params *params, 805 struct snd_soc_dai *dai) 806 { 807 struct snd_soc_component *component = dai->component; 808 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component); 809 u32 clk = 0; 810 int index; 811 812 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params)); 813 if (index >= 0) { 814 cs42l52->sysclk = clk_map_table[index].mclk; 815 816 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) | 817 (clk_map_table[index].group << CLK_32K_SR_SHIFT) | 818 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) | 819 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) | 820 clk_map_table[index].mclkdiv2; 821 822 snd_soc_component_write(component, CS42L52_CLK_CTL, clk); 823 } else { 824 dev_err(component->dev, "can't get correct mclk\n"); 825 return -EINVAL; 826 } 827 828 return 0; 829 } 830 831 static int cs42l52_set_bias_level(struct snd_soc_component *component, 832 enum snd_soc_bias_level level) 833 { 834 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component); 835 836 switch (level) { 837 case SND_SOC_BIAS_ON: 838 break; 839 case SND_SOC_BIAS_PREPARE: 840 snd_soc_component_update_bits(component, CS42L52_PWRCTL1, 841 CS42L52_PWRCTL1_PDN_CODEC, 0); 842 break; 843 case SND_SOC_BIAS_STANDBY: 844 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 845 regcache_cache_only(cs42l52->regmap, false); 846 regcache_sync(cs42l52->regmap); 847 } 848 snd_soc_component_write(component, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL); 849 break; 850 case SND_SOC_BIAS_OFF: 851 snd_soc_component_write(component, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL); 852 regcache_cache_only(cs42l52->regmap, true); 853 break; 854 } 855 856 return 0; 857 } 858 859 #define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000) 860 861 #define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \ 862 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \ 863 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \ 864 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE) 865 866 static const struct snd_soc_dai_ops cs42l52_ops = { 867 .hw_params = cs42l52_pcm_hw_params, 868 .digital_mute = cs42l52_digital_mute, 869 .set_fmt = cs42l52_set_fmt, 870 .set_sysclk = cs42l52_set_sysclk, 871 }; 872 873 static struct snd_soc_dai_driver cs42l52_dai = { 874 .name = "cs42l52", 875 .playback = { 876 .stream_name = "Playback", 877 .channels_min = 1, 878 .channels_max = 2, 879 .rates = CS42L52_RATES, 880 .formats = CS42L52_FORMATS, 881 }, 882 .capture = { 883 .stream_name = "Capture", 884 .channels_min = 1, 885 .channels_max = 2, 886 .rates = CS42L52_RATES, 887 .formats = CS42L52_FORMATS, 888 }, 889 .ops = &cs42l52_ops, 890 }; 891 892 static int beep_rates[] = { 893 261, 522, 585, 667, 706, 774, 889, 1000, 894 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182 895 }; 896 897 static void cs42l52_beep_work(struct work_struct *work) 898 { 899 struct cs42l52_private *cs42l52 = 900 container_of(work, struct cs42l52_private, beep_work); 901 struct snd_soc_component *component = cs42l52->component; 902 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 903 int i; 904 int val = 0; 905 int best = 0; 906 907 if (cs42l52->beep_rate) { 908 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) { 909 if (abs(cs42l52->beep_rate - beep_rates[i]) < 910 abs(cs42l52->beep_rate - beep_rates[best])) 911 best = i; 912 } 913 914 dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n", 915 beep_rates[best], cs42l52->beep_rate); 916 917 val = (best << CS42L52_BEEP_RATE_SHIFT); 918 919 snd_soc_dapm_enable_pin(dapm, "Beep"); 920 } else { 921 dev_dbg(component->dev, "Disabling beep\n"); 922 snd_soc_dapm_disable_pin(dapm, "Beep"); 923 } 924 925 snd_soc_component_update_bits(component, CS42L52_BEEP_FREQ, 926 CS42L52_BEEP_RATE_MASK, val); 927 928 snd_soc_dapm_sync(dapm); 929 } 930 931 /* For usability define a way of injecting beep events for the device - 932 * many systems will not have a keyboard. 933 */ 934 static int cs42l52_beep_event(struct input_dev *dev, unsigned int type, 935 unsigned int code, int hz) 936 { 937 struct snd_soc_component *component = input_get_drvdata(dev); 938 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component); 939 940 dev_dbg(component->dev, "Beep event %x %x\n", code, hz); 941 942 switch (code) { 943 case SND_BELL: 944 if (hz) 945 hz = 261; 946 case SND_TONE: 947 break; 948 default: 949 return -1; 950 } 951 952 /* Kick the beep from a workqueue */ 953 cs42l52->beep_rate = hz; 954 schedule_work(&cs42l52->beep_work); 955 return 0; 956 } 957 958 static ssize_t cs42l52_beep_set(struct device *dev, 959 struct device_attribute *attr, 960 const char *buf, size_t count) 961 { 962 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev); 963 long int time; 964 int ret; 965 966 ret = kstrtol(buf, 10, &time); 967 if (ret != 0) 968 return ret; 969 970 input_event(cs42l52->beep, EV_SND, SND_TONE, time); 971 972 return count; 973 } 974 975 static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set); 976 977 static void cs42l52_init_beep(struct snd_soc_component *component) 978 { 979 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component); 980 int ret; 981 982 cs42l52->beep = devm_input_allocate_device(component->dev); 983 if (!cs42l52->beep) { 984 dev_err(component->dev, "Failed to allocate beep device\n"); 985 return; 986 } 987 988 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work); 989 cs42l52->beep_rate = 0; 990 991 cs42l52->beep->name = "CS42L52 Beep Generator"; 992 cs42l52->beep->phys = dev_name(component->dev); 993 cs42l52->beep->id.bustype = BUS_I2C; 994 995 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND); 996 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); 997 cs42l52->beep->event = cs42l52_beep_event; 998 cs42l52->beep->dev.parent = component->dev; 999 input_set_drvdata(cs42l52->beep, component); 1000 1001 ret = input_register_device(cs42l52->beep); 1002 if (ret != 0) { 1003 cs42l52->beep = NULL; 1004 dev_err(component->dev, "Failed to register beep device\n"); 1005 } 1006 1007 ret = device_create_file(component->dev, &dev_attr_beep); 1008 if (ret != 0) { 1009 dev_err(component->dev, "Failed to create keyclick file: %d\n", 1010 ret); 1011 } 1012 } 1013 1014 static void cs42l52_free_beep(struct snd_soc_component *component) 1015 { 1016 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component); 1017 1018 device_remove_file(component->dev, &dev_attr_beep); 1019 cancel_work_sync(&cs42l52->beep_work); 1020 cs42l52->beep = NULL; 1021 1022 snd_soc_component_update_bits(component, CS42L52_BEEP_TONE_CTL, 1023 CS42L52_BEEP_EN_MASK, 0); 1024 } 1025 1026 static int cs42l52_probe(struct snd_soc_component *component) 1027 { 1028 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component); 1029 1030 regcache_cache_only(cs42l52->regmap, true); 1031 1032 cs42l52_add_mic_controls(component); 1033 1034 cs42l52_init_beep(component); 1035 1036 cs42l52->sysclk = CS42L52_DEFAULT_CLK; 1037 cs42l52->config.format = CS42L52_DEFAULT_FORMAT; 1038 1039 return 0; 1040 } 1041 1042 static void cs42l52_remove(struct snd_soc_component *component) 1043 { 1044 cs42l52_free_beep(component); 1045 } 1046 1047 static const struct snd_soc_component_driver soc_component_dev_cs42l52 = { 1048 .probe = cs42l52_probe, 1049 .remove = cs42l52_remove, 1050 .set_bias_level = cs42l52_set_bias_level, 1051 .controls = cs42l52_snd_controls, 1052 .num_controls = ARRAY_SIZE(cs42l52_snd_controls), 1053 .dapm_widgets = cs42l52_dapm_widgets, 1054 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets), 1055 .dapm_routes = cs42l52_audio_map, 1056 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map), 1057 .suspend_bias_off = 1, 1058 .idle_bias_on = 1, 1059 .use_pmdown_time = 1, 1060 .endianness = 1, 1061 .non_legacy_dai_naming = 1, 1062 }; 1063 1064 /* Current and threshold powerup sequence Pg37 */ 1065 static const struct reg_sequence cs42l52_threshold_patch[] = { 1066 1067 { 0x00, 0x99 }, 1068 { 0x3E, 0xBA }, 1069 { 0x47, 0x80 }, 1070 { 0x32, 0xBB }, 1071 { 0x32, 0x3B }, 1072 { 0x00, 0x00 }, 1073 1074 }; 1075 1076 static const struct regmap_config cs42l52_regmap = { 1077 .reg_bits = 8, 1078 .val_bits = 8, 1079 1080 .max_register = CS42L52_MAX_REGISTER, 1081 .reg_defaults = cs42l52_reg_defaults, 1082 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults), 1083 .readable_reg = cs42l52_readable_register, 1084 .volatile_reg = cs42l52_volatile_register, 1085 .cache_type = REGCACHE_RBTREE, 1086 }; 1087 1088 static int cs42l52_i2c_probe(struct i2c_client *i2c_client, 1089 const struct i2c_device_id *id) 1090 { 1091 struct cs42l52_private *cs42l52; 1092 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev); 1093 int ret; 1094 unsigned int devid = 0; 1095 unsigned int reg; 1096 u32 val32; 1097 1098 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l52), GFP_KERNEL); 1099 if (cs42l52 == NULL) 1100 return -ENOMEM; 1101 cs42l52->dev = &i2c_client->dev; 1102 1103 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap); 1104 if (IS_ERR(cs42l52->regmap)) { 1105 ret = PTR_ERR(cs42l52->regmap); 1106 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1107 return ret; 1108 } 1109 if (pdata) { 1110 cs42l52->pdata = *pdata; 1111 } else { 1112 pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata), 1113 GFP_KERNEL); 1114 if (!pdata) 1115 return -ENOMEM; 1116 1117 if (i2c_client->dev.of_node) { 1118 if (of_property_read_bool(i2c_client->dev.of_node, 1119 "cirrus,mica-differential-cfg")) 1120 pdata->mica_diff_cfg = true; 1121 1122 if (of_property_read_bool(i2c_client->dev.of_node, 1123 "cirrus,micb-differential-cfg")) 1124 pdata->micb_diff_cfg = true; 1125 1126 if (of_property_read_u32(i2c_client->dev.of_node, 1127 "cirrus,micbias-lvl", &val32) >= 0) 1128 pdata->micbias_lvl = val32; 1129 1130 if (of_property_read_u32(i2c_client->dev.of_node, 1131 "cirrus,chgfreq-divisor", &val32) >= 0) 1132 pdata->chgfreq = val32; 1133 1134 pdata->reset_gpio = 1135 of_get_named_gpio(i2c_client->dev.of_node, 1136 "cirrus,reset-gpio", 0); 1137 } 1138 cs42l52->pdata = *pdata; 1139 } 1140 1141 if (cs42l52->pdata.reset_gpio) { 1142 ret = devm_gpio_request_one(&i2c_client->dev, 1143 cs42l52->pdata.reset_gpio, 1144 GPIOF_OUT_INIT_HIGH, 1145 "CS42L52 /RST"); 1146 if (ret < 0) { 1147 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n", 1148 cs42l52->pdata.reset_gpio, ret); 1149 return ret; 1150 } 1151 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0); 1152 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1); 1153 } 1154 1155 i2c_set_clientdata(i2c_client, cs42l52); 1156 1157 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch, 1158 ARRAY_SIZE(cs42l52_threshold_patch)); 1159 if (ret != 0) 1160 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n", 1161 ret); 1162 1163 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, ®); 1164 devid = reg & CS42L52_CHIP_ID_MASK; 1165 if (devid != CS42L52_CHIP_ID) { 1166 ret = -ENODEV; 1167 dev_err(&i2c_client->dev, 1168 "CS42L52 Device ID (%X). Expected %X\n", 1169 devid, CS42L52_CHIP_ID); 1170 return ret; 1171 } 1172 1173 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n", 1174 reg & CS42L52_CHIP_REV_MASK); 1175 1176 /* Set Platform Data */ 1177 if (cs42l52->pdata.mica_diff_cfg) 1178 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL, 1179 CS42L52_MIC_CTL_TYPE_MASK, 1180 cs42l52->pdata.mica_diff_cfg << 1181 CS42L52_MIC_CTL_TYPE_SHIFT); 1182 1183 if (cs42l52->pdata.micb_diff_cfg) 1184 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL, 1185 CS42L52_MIC_CTL_TYPE_MASK, 1186 cs42l52->pdata.micb_diff_cfg << 1187 CS42L52_MIC_CTL_TYPE_SHIFT); 1188 1189 if (cs42l52->pdata.chgfreq) 1190 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP, 1191 CS42L52_CHARGE_PUMP_MASK, 1192 cs42l52->pdata.chgfreq << 1193 CS42L52_CHARGE_PUMP_SHIFT); 1194 1195 if (cs42l52->pdata.micbias_lvl) 1196 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2, 1197 CS42L52_IFACE_CTL2_BIAS_LVL, 1198 cs42l52->pdata.micbias_lvl); 1199 1200 ret = devm_snd_soc_register_component(&i2c_client->dev, 1201 &soc_component_dev_cs42l52, &cs42l52_dai, 1); 1202 if (ret < 0) 1203 return ret; 1204 return 0; 1205 } 1206 1207 static const struct of_device_id cs42l52_of_match[] = { 1208 { .compatible = "cirrus,cs42l52", }, 1209 {}, 1210 }; 1211 MODULE_DEVICE_TABLE(of, cs42l52_of_match); 1212 1213 1214 static const struct i2c_device_id cs42l52_id[] = { 1215 { "cs42l52", 0 }, 1216 { } 1217 }; 1218 MODULE_DEVICE_TABLE(i2c, cs42l52_id); 1219 1220 static struct i2c_driver cs42l52_i2c_driver = { 1221 .driver = { 1222 .name = "cs42l52", 1223 .of_match_table = cs42l52_of_match, 1224 }, 1225 .id_table = cs42l52_id, 1226 .probe = cs42l52_i2c_probe, 1227 }; 1228 1229 module_i2c_driver(cs42l52_i2c_driver); 1230 1231 MODULE_DESCRIPTION("ASoC CS42L52 driver"); 1232 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>"); 1233 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 1234 MODULE_LICENSE("GPL"); 1235