1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l51.c 4 * 5 * ASoC Driver for Cirrus Logic CS42L51 codecs 6 * 7 * Copyright (c) 2010 Arnaud Patard <apatard@mandriva.com> 8 * 9 * Based on cs4270.c - Copyright (c) Freescale Semiconductor 10 * 11 * For now: 12 * - Only I2C is support. Not SPI 13 * - master mode *NOT* supported 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/module.h> 18 #include <linux/slab.h> 19 #include <sound/core.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 #include <sound/initval.h> 23 #include <sound/pcm_params.h> 24 #include <sound/pcm.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/regmap.h> 27 #include <linux/regulator/consumer.h> 28 29 #include "cs42l51.h" 30 31 enum master_slave_mode { 32 MODE_SLAVE, 33 MODE_SLAVE_AUTO, 34 MODE_MASTER, 35 }; 36 37 static const char * const cs42l51_supply_names[] = { 38 "VL", 39 "VD", 40 "VA", 41 "VAHP", 42 }; 43 44 struct cs42l51_private { 45 unsigned int mclk; 46 struct clk *mclk_handle; 47 unsigned int audio_mode; /* The mode (I2S or left-justified) */ 48 enum master_slave_mode func; 49 struct regulator_bulk_data supplies[ARRAY_SIZE(cs42l51_supply_names)]; 50 struct gpio_desc *reset_gpio; 51 struct regmap *regmap; 52 }; 53 54 #define CS42L51_FORMATS ( \ 55 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \ 56 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \ 57 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \ 58 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE) 59 60 static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol, 61 struct snd_ctl_elem_value *ucontrol) 62 { 63 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 64 unsigned long value = snd_soc_component_read32(component, CS42L51_PCM_MIXER)&3; 65 66 switch (value) { 67 default: 68 case 0: 69 ucontrol->value.enumerated.item[0] = 0; 70 break; 71 /* same value : (L+R)/2 and (R+L)/2 */ 72 case 1: 73 case 2: 74 ucontrol->value.enumerated.item[0] = 1; 75 break; 76 case 3: 77 ucontrol->value.enumerated.item[0] = 2; 78 break; 79 } 80 81 return 0; 82 } 83 84 #define CHAN_MIX_NORMAL 0x00 85 #define CHAN_MIX_BOTH 0x55 86 #define CHAN_MIX_SWAP 0xFF 87 88 static int cs42l51_set_chan_mix(struct snd_kcontrol *kcontrol, 89 struct snd_ctl_elem_value *ucontrol) 90 { 91 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 92 unsigned char val; 93 94 switch (ucontrol->value.enumerated.item[0]) { 95 default: 96 case 0: 97 val = CHAN_MIX_NORMAL; 98 break; 99 case 1: 100 val = CHAN_MIX_BOTH; 101 break; 102 case 2: 103 val = CHAN_MIX_SWAP; 104 break; 105 } 106 107 snd_soc_component_write(component, CS42L51_PCM_MIXER, val); 108 109 return 1; 110 } 111 112 static const DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -5150, 50, 0); 113 static const DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0); 114 115 static const DECLARE_TLV_DB_SCALE(aout_tlv, -10200, 50, 0); 116 117 static const DECLARE_TLV_DB_SCALE(boost_tlv, 1600, 1600, 0); 118 static const DECLARE_TLV_DB_SCALE(adc_boost_tlv, 2000, 2000, 0); 119 static const char *chan_mix[] = { 120 "L R", 121 "L+R", 122 "R L", 123 }; 124 125 static SOC_ENUM_SINGLE_EXT_DECL(cs42l51_chan_mix, chan_mix); 126 127 static const struct snd_kcontrol_new cs42l51_snd_controls[] = { 128 SOC_DOUBLE_R_SX_TLV("PCM Playback Volume", 129 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 130 0, 0x19, 0x7F, adc_pcm_tlv), 131 SOC_DOUBLE_R("PCM Playback Switch", 132 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 7, 1, 1), 133 SOC_DOUBLE_R_SX_TLV("Analog Playback Volume", 134 CS42L51_AOUTA_VOL, CS42L51_AOUTB_VOL, 135 0, 0x34, 0xE4, aout_tlv), 136 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume", 137 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 138 0, 0x19, 0x7F, adc_pcm_tlv), 139 SOC_DOUBLE_R("ADC Mixer Switch", 140 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 7, 1, 1), 141 SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0), 142 SOC_SINGLE("Auto-Mute Switch", CS42L51_DAC_CTL, 2, 1, 0), 143 SOC_SINGLE("Soft Ramp Switch", CS42L51_DAC_CTL, 1, 1, 0), 144 SOC_SINGLE("Zero Cross Switch", CS42L51_DAC_CTL, 0, 0, 0), 145 SOC_DOUBLE_TLV("Mic Boost Volume", 146 CS42L51_MIC_CTL, 0, 1, 1, 0, boost_tlv), 147 SOC_DOUBLE_TLV("ADC Boost Volume", 148 CS42L51_MIC_CTL, 5, 6, 1, 0, adc_boost_tlv), 149 SOC_SINGLE_TLV("Bass Volume", CS42L51_TONE_CTL, 0, 0xf, 1, tone_tlv), 150 SOC_SINGLE_TLV("Treble Volume", CS42L51_TONE_CTL, 4, 0xf, 1, tone_tlv), 151 SOC_ENUM_EXT("PCM channel mixer", 152 cs42l51_chan_mix, 153 cs42l51_get_chan_mix, cs42l51_set_chan_mix), 154 }; 155 156 /* 157 * to power down, one must: 158 * 1.) Enable the PDN bit 159 * 2.) enable power-down for the select channels 160 * 3.) disable the PDN bit. 161 */ 162 static int cs42l51_pdn_event(struct snd_soc_dapm_widget *w, 163 struct snd_kcontrol *kcontrol, int event) 164 { 165 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 166 167 switch (event) { 168 case SND_SOC_DAPM_PRE_PMD: 169 snd_soc_component_update_bits(component, CS42L51_POWER_CTL1, 170 CS42L51_POWER_CTL1_PDN, 171 CS42L51_POWER_CTL1_PDN); 172 break; 173 default: 174 case SND_SOC_DAPM_POST_PMD: 175 snd_soc_component_update_bits(component, CS42L51_POWER_CTL1, 176 CS42L51_POWER_CTL1_PDN, 0); 177 break; 178 } 179 180 return 0; 181 } 182 183 static const char *cs42l51_dac_names[] = {"Direct PCM", 184 "DSP PCM", "ADC"}; 185 static SOC_ENUM_SINGLE_DECL(cs42l51_dac_mux_enum, 186 CS42L51_DAC_CTL, 6, cs42l51_dac_names); 187 static const struct snd_kcontrol_new cs42l51_dac_mux_controls = 188 SOC_DAPM_ENUM("Route", cs42l51_dac_mux_enum); 189 190 static const char *cs42l51_adcl_names[] = {"AIN1 Left", "AIN2 Left", 191 "MIC Left", "MIC+preamp Left"}; 192 static SOC_ENUM_SINGLE_DECL(cs42l51_adcl_mux_enum, 193 CS42L51_ADC_INPUT, 4, cs42l51_adcl_names); 194 static const struct snd_kcontrol_new cs42l51_adcl_mux_controls = 195 SOC_DAPM_ENUM("Route", cs42l51_adcl_mux_enum); 196 197 static const char *cs42l51_adcr_names[] = {"AIN1 Right", "AIN2 Right", 198 "MIC Right", "MIC+preamp Right"}; 199 static SOC_ENUM_SINGLE_DECL(cs42l51_adcr_mux_enum, 200 CS42L51_ADC_INPUT, 6, cs42l51_adcr_names); 201 static const struct snd_kcontrol_new cs42l51_adcr_mux_controls = 202 SOC_DAPM_ENUM("Route", cs42l51_adcr_mux_enum); 203 204 static const struct snd_soc_dapm_widget cs42l51_dapm_widgets[] = { 205 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L51_MIC_POWER_CTL, 1, 1, NULL, 206 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 207 SND_SOC_DAPM_PGA_E("Left PGA", CS42L51_POWER_CTL1, 3, 1, NULL, 0, 208 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD), 209 SND_SOC_DAPM_PGA_E("Right PGA", CS42L51_POWER_CTL1, 4, 1, NULL, 0, 210 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD), 211 SND_SOC_DAPM_ADC_E("Left ADC", "Left HiFi Capture", 212 CS42L51_POWER_CTL1, 1, 1, 213 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD), 214 SND_SOC_DAPM_ADC_E("Right ADC", "Right HiFi Capture", 215 CS42L51_POWER_CTL1, 2, 1, 216 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD), 217 SND_SOC_DAPM_DAC_E("Left DAC", "Left HiFi Playback", 218 CS42L51_POWER_CTL1, 5, 1, 219 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD), 220 SND_SOC_DAPM_DAC_E("Right DAC", "Right HiFi Playback", 221 CS42L51_POWER_CTL1, 6, 1, 222 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD), 223 224 /* analog/mic */ 225 SND_SOC_DAPM_INPUT("AIN1L"), 226 SND_SOC_DAPM_INPUT("AIN1R"), 227 SND_SOC_DAPM_INPUT("AIN2L"), 228 SND_SOC_DAPM_INPUT("AIN2R"), 229 SND_SOC_DAPM_INPUT("MICL"), 230 SND_SOC_DAPM_INPUT("MICR"), 231 232 SND_SOC_DAPM_MIXER("Mic Preamp Left", 233 CS42L51_MIC_POWER_CTL, 2, 1, NULL, 0), 234 SND_SOC_DAPM_MIXER("Mic Preamp Right", 235 CS42L51_MIC_POWER_CTL, 3, 1, NULL, 0), 236 237 /* HP */ 238 SND_SOC_DAPM_OUTPUT("HPL"), 239 SND_SOC_DAPM_OUTPUT("HPR"), 240 241 /* mux */ 242 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0, 243 &cs42l51_dac_mux_controls), 244 SND_SOC_DAPM_MUX("PGA-ADC Mux Left", SND_SOC_NOPM, 0, 0, 245 &cs42l51_adcl_mux_controls), 246 SND_SOC_DAPM_MUX("PGA-ADC Mux Right", SND_SOC_NOPM, 0, 0, 247 &cs42l51_adcr_mux_controls), 248 }; 249 250 static const struct snd_soc_dapm_widget cs42l51_dapm_mclk_widgets[] = { 251 SND_SOC_DAPM_CLOCK_SUPPLY("MCLK") 252 }; 253 254 static const struct snd_soc_dapm_route cs42l51_routes[] = { 255 {"HPL", NULL, "Left DAC"}, 256 {"HPR", NULL, "Right DAC"}, 257 258 {"Left ADC", NULL, "Left PGA"}, 259 {"Right ADC", NULL, "Right PGA"}, 260 261 {"Mic Preamp Left", NULL, "MICL"}, 262 {"Mic Preamp Right", NULL, "MICR"}, 263 264 {"PGA-ADC Mux Left", "AIN1 Left", "AIN1L" }, 265 {"PGA-ADC Mux Left", "AIN2 Left", "AIN2L" }, 266 {"PGA-ADC Mux Left", "MIC Left", "MICL" }, 267 {"PGA-ADC Mux Left", "MIC+preamp Left", "Mic Preamp Left" }, 268 {"PGA-ADC Mux Right", "AIN1 Right", "AIN1R" }, 269 {"PGA-ADC Mux Right", "AIN2 Right", "AIN2R" }, 270 {"PGA-ADC Mux Right", "MIC Right", "MICR" }, 271 {"PGA-ADC Mux Right", "MIC+preamp Right", "Mic Preamp Right" }, 272 273 {"Left PGA", NULL, "PGA-ADC Mux Left"}, 274 {"Right PGA", NULL, "PGA-ADC Mux Right"}, 275 }; 276 277 static int cs42l51_set_dai_fmt(struct snd_soc_dai *codec_dai, 278 unsigned int format) 279 { 280 struct snd_soc_component *component = codec_dai->component; 281 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component); 282 283 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 284 case SND_SOC_DAIFMT_I2S: 285 case SND_SOC_DAIFMT_LEFT_J: 286 case SND_SOC_DAIFMT_RIGHT_J: 287 cs42l51->audio_mode = format & SND_SOC_DAIFMT_FORMAT_MASK; 288 break; 289 default: 290 dev_err(component->dev, "invalid DAI format\n"); 291 return -EINVAL; 292 } 293 294 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 295 case SND_SOC_DAIFMT_CBM_CFM: 296 cs42l51->func = MODE_MASTER; 297 break; 298 case SND_SOC_DAIFMT_CBS_CFS: 299 cs42l51->func = MODE_SLAVE_AUTO; 300 break; 301 default: 302 dev_err(component->dev, "Unknown master/slave configuration\n"); 303 return -EINVAL; 304 } 305 306 return 0; 307 } 308 309 struct cs42l51_ratios { 310 unsigned int ratio; 311 unsigned char speed_mode; 312 unsigned char mclk; 313 }; 314 315 static struct cs42l51_ratios slave_ratios[] = { 316 { 512, CS42L51_QSM_MODE, 0 }, { 768, CS42L51_QSM_MODE, 0 }, 317 { 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 }, 318 { 2048, CS42L51_QSM_MODE, 0 }, { 3072, CS42L51_QSM_MODE, 0 }, 319 { 256, CS42L51_HSM_MODE, 0 }, { 384, CS42L51_HSM_MODE, 0 }, 320 { 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 }, 321 { 1024, CS42L51_HSM_MODE, 0 }, { 1536, CS42L51_HSM_MODE, 0 }, 322 { 128, CS42L51_SSM_MODE, 0 }, { 192, CS42L51_SSM_MODE, 0 }, 323 { 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 }, 324 { 512, CS42L51_SSM_MODE, 0 }, { 768, CS42L51_SSM_MODE, 0 }, 325 { 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 }, 326 { 256, CS42L51_DSM_MODE, 0 }, { 384, CS42L51_DSM_MODE, 0 }, 327 }; 328 329 static struct cs42l51_ratios slave_auto_ratios[] = { 330 { 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 }, 331 { 2048, CS42L51_QSM_MODE, 1 }, { 3072, CS42L51_QSM_MODE, 1 }, 332 { 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 }, 333 { 1024, CS42L51_HSM_MODE, 1 }, { 1536, CS42L51_HSM_MODE, 1 }, 334 { 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 }, 335 { 512, CS42L51_SSM_MODE, 1 }, { 768, CS42L51_SSM_MODE, 1 }, 336 { 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 }, 337 { 256, CS42L51_DSM_MODE, 1 }, { 384, CS42L51_DSM_MODE, 1 }, 338 }; 339 340 /* 341 * Master mode mclk/fs ratios. 342 * Recommended configurations are SSM for 4-50khz and DSM for 50-100kHz ranges 343 * The table below provides support of following ratios: 344 * 128: SSM (%128) with div2 disabled 345 * 256: SSM (%128) with div2 enabled 346 * In both cases, if sampling rate is above 50kHz, SSM is overridden 347 * with DSM (%128) configuration 348 */ 349 static struct cs42l51_ratios master_ratios[] = { 350 { 128, CS42L51_SSM_MODE, 0 }, { 256, CS42L51_SSM_MODE, 1 }, 351 }; 352 353 static int cs42l51_set_dai_sysclk(struct snd_soc_dai *codec_dai, 354 int clk_id, unsigned int freq, int dir) 355 { 356 struct snd_soc_component *component = codec_dai->component; 357 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component); 358 359 cs42l51->mclk = freq; 360 return 0; 361 } 362 363 static int cs42l51_hw_params(struct snd_pcm_substream *substream, 364 struct snd_pcm_hw_params *params, 365 struct snd_soc_dai *dai) 366 { 367 struct snd_soc_component *component = dai->component; 368 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component); 369 int ret; 370 unsigned int i; 371 unsigned int rate; 372 unsigned int ratio; 373 struct cs42l51_ratios *ratios = NULL; 374 int nr_ratios = 0; 375 int intf_ctl, power_ctl, fmt, mode; 376 377 switch (cs42l51->func) { 378 case MODE_MASTER: 379 ratios = master_ratios; 380 nr_ratios = ARRAY_SIZE(master_ratios); 381 break; 382 case MODE_SLAVE: 383 ratios = slave_ratios; 384 nr_ratios = ARRAY_SIZE(slave_ratios); 385 break; 386 case MODE_SLAVE_AUTO: 387 ratios = slave_auto_ratios; 388 nr_ratios = ARRAY_SIZE(slave_auto_ratios); 389 break; 390 } 391 392 /* Figure out which MCLK/LRCK ratio to use */ 393 rate = params_rate(params); /* Sampling rate, in Hz */ 394 ratio = cs42l51->mclk / rate; /* MCLK/LRCK ratio */ 395 for (i = 0; i < nr_ratios; i++) { 396 if (ratios[i].ratio == ratio) 397 break; 398 } 399 400 if (i == nr_ratios) { 401 /* We did not find a matching ratio */ 402 dev_err(component->dev, "could not find matching ratio\n"); 403 return -EINVAL; 404 } 405 406 intf_ctl = snd_soc_component_read32(component, CS42L51_INTF_CTL); 407 power_ctl = snd_soc_component_read32(component, CS42L51_MIC_POWER_CTL); 408 409 intf_ctl &= ~(CS42L51_INTF_CTL_MASTER | CS42L51_INTF_CTL_ADC_I2S 410 | CS42L51_INTF_CTL_DAC_FORMAT(7)); 411 power_ctl &= ~(CS42L51_MIC_POWER_CTL_SPEED(3) 412 | CS42L51_MIC_POWER_CTL_MCLK_DIV2); 413 414 switch (cs42l51->func) { 415 case MODE_MASTER: 416 intf_ctl |= CS42L51_INTF_CTL_MASTER; 417 mode = ratios[i].speed_mode; 418 /* Force DSM mode if sampling rate is above 50kHz */ 419 if (rate > 50000) 420 mode = CS42L51_DSM_MODE; 421 power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(mode); 422 /* 423 * Auto detect mode is not applicable for master mode and has to 424 * be disabled. Otherwise SPEED[1:0] bits will be ignored. 425 */ 426 power_ctl &= ~CS42L51_MIC_POWER_CTL_AUTO; 427 break; 428 case MODE_SLAVE: 429 power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(ratios[i].speed_mode); 430 break; 431 case MODE_SLAVE_AUTO: 432 power_ctl |= CS42L51_MIC_POWER_CTL_AUTO; 433 break; 434 } 435 436 switch (cs42l51->audio_mode) { 437 case SND_SOC_DAIFMT_I2S: 438 intf_ctl |= CS42L51_INTF_CTL_ADC_I2S; 439 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_I2S); 440 break; 441 case SND_SOC_DAIFMT_LEFT_J: 442 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_LJ24); 443 break; 444 case SND_SOC_DAIFMT_RIGHT_J: 445 switch (params_width(params)) { 446 case 16: 447 fmt = CS42L51_DAC_DIF_RJ16; 448 break; 449 case 18: 450 fmt = CS42L51_DAC_DIF_RJ18; 451 break; 452 case 20: 453 fmt = CS42L51_DAC_DIF_RJ20; 454 break; 455 case 24: 456 fmt = CS42L51_DAC_DIF_RJ24; 457 break; 458 default: 459 dev_err(component->dev, "unknown format\n"); 460 return -EINVAL; 461 } 462 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(fmt); 463 break; 464 default: 465 dev_err(component->dev, "unknown format\n"); 466 return -EINVAL; 467 } 468 469 if (ratios[i].mclk) 470 power_ctl |= CS42L51_MIC_POWER_CTL_MCLK_DIV2; 471 472 ret = snd_soc_component_write(component, CS42L51_INTF_CTL, intf_ctl); 473 if (ret < 0) 474 return ret; 475 476 ret = snd_soc_component_write(component, CS42L51_MIC_POWER_CTL, power_ctl); 477 if (ret < 0) 478 return ret; 479 480 return 0; 481 } 482 483 static int cs42l51_dai_mute(struct snd_soc_dai *dai, int mute) 484 { 485 struct snd_soc_component *component = dai->component; 486 int reg; 487 int mask = CS42L51_DAC_OUT_CTL_DACA_MUTE|CS42L51_DAC_OUT_CTL_DACB_MUTE; 488 489 reg = snd_soc_component_read32(component, CS42L51_DAC_OUT_CTL); 490 491 if (mute) 492 reg |= mask; 493 else 494 reg &= ~mask; 495 496 return snd_soc_component_write(component, CS42L51_DAC_OUT_CTL, reg); 497 } 498 499 static int cs42l51_of_xlate_dai_id(struct snd_soc_component *component, 500 struct device_node *endpoint) 501 { 502 /* return dai id 0, whatever the endpoint index */ 503 return 0; 504 } 505 506 static const struct snd_soc_dai_ops cs42l51_dai_ops = { 507 .hw_params = cs42l51_hw_params, 508 .set_sysclk = cs42l51_set_dai_sysclk, 509 .set_fmt = cs42l51_set_dai_fmt, 510 .digital_mute = cs42l51_dai_mute, 511 }; 512 513 static struct snd_soc_dai_driver cs42l51_dai = { 514 .name = "cs42l51-hifi", 515 .playback = { 516 .stream_name = "Playback", 517 .channels_min = 1, 518 .channels_max = 2, 519 .rates = SNDRV_PCM_RATE_8000_96000, 520 .formats = CS42L51_FORMATS, 521 }, 522 .capture = { 523 .stream_name = "Capture", 524 .channels_min = 1, 525 .channels_max = 2, 526 .rates = SNDRV_PCM_RATE_8000_96000, 527 .formats = CS42L51_FORMATS, 528 }, 529 .ops = &cs42l51_dai_ops, 530 }; 531 532 static int cs42l51_component_probe(struct snd_soc_component *component) 533 { 534 int ret, reg; 535 struct snd_soc_dapm_context *dapm; 536 struct cs42l51_private *cs42l51; 537 538 cs42l51 = snd_soc_component_get_drvdata(component); 539 dapm = snd_soc_component_get_dapm(component); 540 541 if (cs42l51->mclk_handle) 542 snd_soc_dapm_new_controls(dapm, cs42l51_dapm_mclk_widgets, 1); 543 544 /* 545 * DAC configuration 546 * - Use signal processor 547 * - auto mute 548 * - vol changes immediate 549 * - no de-emphasize 550 */ 551 reg = CS42L51_DAC_CTL_DATA_SEL(1) 552 | CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0); 553 ret = snd_soc_component_write(component, CS42L51_DAC_CTL, reg); 554 if (ret < 0) 555 return ret; 556 557 return 0; 558 } 559 560 static const struct snd_soc_component_driver soc_component_device_cs42l51 = { 561 .probe = cs42l51_component_probe, 562 .controls = cs42l51_snd_controls, 563 .num_controls = ARRAY_SIZE(cs42l51_snd_controls), 564 .dapm_widgets = cs42l51_dapm_widgets, 565 .num_dapm_widgets = ARRAY_SIZE(cs42l51_dapm_widgets), 566 .dapm_routes = cs42l51_routes, 567 .num_dapm_routes = ARRAY_SIZE(cs42l51_routes), 568 .of_xlate_dai_id = cs42l51_of_xlate_dai_id, 569 .idle_bias_on = 1, 570 .use_pmdown_time = 1, 571 .endianness = 1, 572 .non_legacy_dai_naming = 1, 573 }; 574 575 static bool cs42l51_writeable_reg(struct device *dev, unsigned int reg) 576 { 577 switch (reg) { 578 case CS42L51_POWER_CTL1: 579 case CS42L51_MIC_POWER_CTL: 580 case CS42L51_INTF_CTL: 581 case CS42L51_MIC_CTL: 582 case CS42L51_ADC_CTL: 583 case CS42L51_ADC_INPUT: 584 case CS42L51_DAC_OUT_CTL: 585 case CS42L51_DAC_CTL: 586 case CS42L51_ALC_PGA_CTL: 587 case CS42L51_ALC_PGB_CTL: 588 case CS42L51_ADCA_ATT: 589 case CS42L51_ADCB_ATT: 590 case CS42L51_ADCA_VOL: 591 case CS42L51_ADCB_VOL: 592 case CS42L51_PCMA_VOL: 593 case CS42L51_PCMB_VOL: 594 case CS42L51_BEEP_FREQ: 595 case CS42L51_BEEP_VOL: 596 case CS42L51_BEEP_CONF: 597 case CS42L51_TONE_CTL: 598 case CS42L51_AOUTA_VOL: 599 case CS42L51_AOUTB_VOL: 600 case CS42L51_PCM_MIXER: 601 case CS42L51_LIMIT_THRES_DIS: 602 case CS42L51_LIMIT_REL: 603 case CS42L51_LIMIT_ATT: 604 case CS42L51_ALC_EN: 605 case CS42L51_ALC_REL: 606 case CS42L51_ALC_THRES: 607 case CS42L51_NOISE_CONF: 608 case CS42L51_CHARGE_FREQ: 609 return true; 610 default: 611 return false; 612 } 613 } 614 615 static bool cs42l51_volatile_reg(struct device *dev, unsigned int reg) 616 { 617 switch (reg) { 618 case CS42L51_STATUS: 619 return true; 620 default: 621 return false; 622 } 623 } 624 625 static bool cs42l51_readable_reg(struct device *dev, unsigned int reg) 626 { 627 switch (reg) { 628 case CS42L51_CHIP_REV_ID: 629 case CS42L51_POWER_CTL1: 630 case CS42L51_MIC_POWER_CTL: 631 case CS42L51_INTF_CTL: 632 case CS42L51_MIC_CTL: 633 case CS42L51_ADC_CTL: 634 case CS42L51_ADC_INPUT: 635 case CS42L51_DAC_OUT_CTL: 636 case CS42L51_DAC_CTL: 637 case CS42L51_ALC_PGA_CTL: 638 case CS42L51_ALC_PGB_CTL: 639 case CS42L51_ADCA_ATT: 640 case CS42L51_ADCB_ATT: 641 case CS42L51_ADCA_VOL: 642 case CS42L51_ADCB_VOL: 643 case CS42L51_PCMA_VOL: 644 case CS42L51_PCMB_VOL: 645 case CS42L51_BEEP_FREQ: 646 case CS42L51_BEEP_VOL: 647 case CS42L51_BEEP_CONF: 648 case CS42L51_TONE_CTL: 649 case CS42L51_AOUTA_VOL: 650 case CS42L51_AOUTB_VOL: 651 case CS42L51_PCM_MIXER: 652 case CS42L51_LIMIT_THRES_DIS: 653 case CS42L51_LIMIT_REL: 654 case CS42L51_LIMIT_ATT: 655 case CS42L51_ALC_EN: 656 case CS42L51_ALC_REL: 657 case CS42L51_ALC_THRES: 658 case CS42L51_NOISE_CONF: 659 case CS42L51_STATUS: 660 case CS42L51_CHARGE_FREQ: 661 return true; 662 default: 663 return false; 664 } 665 } 666 667 const struct regmap_config cs42l51_regmap = { 668 .reg_bits = 8, 669 .reg_stride = 1, 670 .val_bits = 8, 671 .use_single_write = true, 672 .readable_reg = cs42l51_readable_reg, 673 .volatile_reg = cs42l51_volatile_reg, 674 .writeable_reg = cs42l51_writeable_reg, 675 .max_register = CS42L51_CHARGE_FREQ, 676 .cache_type = REGCACHE_RBTREE, 677 }; 678 EXPORT_SYMBOL_GPL(cs42l51_regmap); 679 680 int cs42l51_probe(struct device *dev, struct regmap *regmap) 681 { 682 struct cs42l51_private *cs42l51; 683 unsigned int val; 684 int ret, i; 685 686 if (IS_ERR(regmap)) 687 return PTR_ERR(regmap); 688 689 cs42l51 = devm_kzalloc(dev, sizeof(struct cs42l51_private), 690 GFP_KERNEL); 691 if (!cs42l51) 692 return -ENOMEM; 693 694 dev_set_drvdata(dev, cs42l51); 695 cs42l51->regmap = regmap; 696 697 cs42l51->mclk_handle = devm_clk_get(dev, "MCLK"); 698 if (IS_ERR(cs42l51->mclk_handle)) { 699 if (PTR_ERR(cs42l51->mclk_handle) != -ENOENT) 700 return PTR_ERR(cs42l51->mclk_handle); 701 cs42l51->mclk_handle = NULL; 702 } 703 704 for (i = 0; i < ARRAY_SIZE(cs42l51->supplies); i++) 705 cs42l51->supplies[i].supply = cs42l51_supply_names[i]; 706 707 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs42l51->supplies), 708 cs42l51->supplies); 709 if (ret != 0) { 710 dev_err(dev, "Failed to request supplies: %d\n", ret); 711 return ret; 712 } 713 714 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l51->supplies), 715 cs42l51->supplies); 716 if (ret != 0) { 717 dev_err(dev, "Failed to enable supplies: %d\n", ret); 718 return ret; 719 } 720 721 cs42l51->reset_gpio = devm_gpiod_get_optional(dev, "reset", 722 GPIOD_OUT_LOW); 723 if (IS_ERR(cs42l51->reset_gpio)) 724 return PTR_ERR(cs42l51->reset_gpio); 725 726 if (cs42l51->reset_gpio) { 727 dev_dbg(dev, "Release reset gpio\n"); 728 gpiod_set_value_cansleep(cs42l51->reset_gpio, 0); 729 mdelay(2); 730 } 731 732 /* Verify that we have a CS42L51 */ 733 ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val); 734 if (ret < 0) { 735 dev_err(dev, "failed to read I2C\n"); 736 goto error; 737 } 738 739 if ((val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) && 740 (val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) { 741 dev_err(dev, "Invalid chip id: %x\n", val); 742 ret = -ENODEV; 743 goto error; 744 } 745 dev_info(dev, "Cirrus Logic CS42L51, Revision: %02X\n", 746 val & CS42L51_CHIP_REV_MASK); 747 748 ret = devm_snd_soc_register_component(dev, 749 &soc_component_device_cs42l51, &cs42l51_dai, 1); 750 if (ret < 0) 751 goto error; 752 753 return 0; 754 755 error: 756 regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies), 757 cs42l51->supplies); 758 return ret; 759 } 760 EXPORT_SYMBOL_GPL(cs42l51_probe); 761 762 int cs42l51_remove(struct device *dev) 763 { 764 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev); 765 766 gpiod_set_value_cansleep(cs42l51->reset_gpio, 1); 767 768 return regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies), 769 cs42l51->supplies); 770 } 771 EXPORT_SYMBOL_GPL(cs42l51_remove); 772 773 int __maybe_unused cs42l51_suspend(struct device *dev) 774 { 775 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev); 776 777 regcache_cache_only(cs42l51->regmap, true); 778 regcache_mark_dirty(cs42l51->regmap); 779 780 return 0; 781 } 782 EXPORT_SYMBOL_GPL(cs42l51_suspend); 783 784 int __maybe_unused cs42l51_resume(struct device *dev) 785 { 786 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev); 787 788 regcache_cache_only(cs42l51->regmap, false); 789 790 return regcache_sync(cs42l51->regmap); 791 } 792 EXPORT_SYMBOL_GPL(cs42l51_resume); 793 794 const struct of_device_id cs42l51_of_match[] = { 795 { .compatible = "cirrus,cs42l51", }, 796 { } 797 }; 798 MODULE_DEVICE_TABLE(of, cs42l51_of_match); 799 EXPORT_SYMBOL_GPL(cs42l51_of_match); 800 801 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>"); 802 MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver"); 803 MODULE_LICENSE("GPL"); 804