1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * cs42l42.h -- CS42L42 ALSA SoC audio driver header 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #ifndef __CS42L42_H__ 13 #define __CS42L42_H__ 14 15 #define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */ 16 #define CS42L42_WIN_START 0x00 17 #define CS42L42_WIN_LEN 0x100 18 #define CS42L42_RANGE_MIN 0x00 19 #define CS42L42_RANGE_MAX 0x7F 20 21 #define CS42L42_PAGE_10 0x1000 22 #define CS42L42_PAGE_11 0x1100 23 #define CS42L42_PAGE_12 0x1200 24 #define CS42L42_PAGE_13 0x1300 25 #define CS42L42_PAGE_15 0x1500 26 #define CS42L42_PAGE_19 0x1900 27 #define CS42L42_PAGE_1B 0x1B00 28 #define CS42L42_PAGE_1C 0x1C00 29 #define CS42L42_PAGE_1D 0x1D00 30 #define CS42L42_PAGE_1F 0x1F00 31 #define CS42L42_PAGE_20 0x2000 32 #define CS42L42_PAGE_21 0x2100 33 #define CS42L42_PAGE_23 0x2300 34 #define CS42L42_PAGE_24 0x2400 35 #define CS42L42_PAGE_25 0x2500 36 #define CS42L42_PAGE_26 0x2600 37 #define CS42L42_PAGE_28 0x2800 38 #define CS42L42_PAGE_29 0x2900 39 #define CS42L42_PAGE_2A 0x2A00 40 #define CS42L42_PAGE_30 0x3000 41 42 #define CS42L42_CHIP_ID 0x42A42 43 44 /* Page 0x10 Global Registers */ 45 #define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01) 46 #define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02) 47 #define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03) 48 #define CS42L42_FABID (CS42L42_PAGE_10 + 0x04) 49 #define CS42L42_REVID (CS42L42_PAGE_10 + 0x05) 50 #define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06) 51 52 #define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07) 53 #define CS42L42_SRC_BYPASS_DAC_SHIFT 1 54 #define CS42L42_SRC_BYPASS_DAC_MASK (1 << CS42L42_SRC_BYPASS_DAC_SHIFT) 55 56 #define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08) 57 58 #define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09) 59 #define CS42L42_INTERNAL_FS_SHIFT 1 60 #define CS42L42_INTERNAL_FS_MASK (1 << CS42L42_INTERNAL_FS_SHIFT) 61 62 #define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A) 63 #define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E) 64 #define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F) 65 #define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10) 66 67 /* Page 0x11 Power and Headset Detect Registers */ 68 #define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01) 69 #define CS42L42_ASP_DAO_PDN_SHIFT 7 70 #define CS42L42_ASP_DAO_PDN_MASK (1 << CS42L42_ASP_DAO_PDN_SHIFT) 71 #define CS42L42_ASP_DAI_PDN_SHIFT 6 72 #define CS42L42_ASP_DAI_PDN_MASK (1 << CS42L42_ASP_DAI_PDN_SHIFT) 73 #define CS42L42_MIXER_PDN_SHIFT 5 74 #define CS42L42_MIXER_PDN_MASK (1 << CS42L42_MIXER_PDN_SHIFT) 75 #define CS42L42_EQ_PDN_SHIFT 4 76 #define CS42L42_EQ_PDN_MASK (1 << CS42L42_EQ_PDN_SHIFT) 77 #define CS42L42_HP_PDN_SHIFT 3 78 #define CS42L42_HP_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT) 79 #define CS42L42_ADC_PDN_SHIFT 2 80 #define CS42L42_ADC_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT) 81 #define CS42L42_PDN_ALL_SHIFT 0 82 #define CS42L42_PDN_ALL_MASK (1 << CS42L42_PDN_ALL_SHIFT) 83 84 #define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02) 85 #define CS42L42_ADC_SRC_PDNB_SHIFT 0 86 #define CS42L42_ADC_SRC_PDNB_MASK (1 << CS42L42_ADC_SRC_PDNB_SHIFT) 87 #define CS42L42_DAC_SRC_PDNB_SHIFT 1 88 #define CS42L42_DAC_SRC_PDNB_MASK (1 << CS42L42_DAC_SRC_PDNB_SHIFT) 89 #define CS42L42_ASP_DAI1_PDN_SHIFT 2 90 #define CS42L42_ASP_DAI1_PDN_MASK (1 << CS42L42_ASP_DAI1_PDN_SHIFT) 91 #define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3 92 #define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT) 93 #define CS42L42_DISCHARGE_FILT_SHIFT 4 94 #define CS42L42_DISCHARGE_FILT_MASK (1 << CS42L42_DISCHARGE_FILT_SHIFT) 95 96 #define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03) 97 #define CS42L42_RING_SENSE_PDNB_SHIFT 1 98 #define CS42L42_RING_SENSE_PDNB_MASK (1 << \ 99 CS42L42_RING_SENSE_PDNB_SHIFT) 100 #define CS42L42_VPMON_PDNB_SHIFT 2 101 #define CS42L42_VPMON_PDNB_MASK (1 << \ 102 CS42L42_VPMON_PDNB_SHIFT) 103 #define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 5 104 #define CS42L42_SW_CLK_STP_STAT_SEL_MASK (3 << \ 105 CS42L42_SW_CLK_STP_STAT_SEL_SHIFT) 106 107 #define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04) 108 #define CS42L42_RS_TRIM_R_SHIFT 0 109 #define CS42L42_RS_TRIM_R_MASK (1 << \ 110 CS42L42_RS_TRIM_R_SHIFT) 111 #define CS42L42_RS_TRIM_T_SHIFT 1 112 #define CS42L42_RS_TRIM_T_MASK (1 << \ 113 CS42L42_RS_TRIM_T_SHIFT) 114 #define CS42L42_HPREF_RS_SHIFT 2 115 #define CS42L42_HPREF_RS_MASK (1 << \ 116 CS42L42_HPREF_RS_SHIFT) 117 #define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 3 118 #define CS42L42_HSBIAS_FILT_REF_RS_MASK (1 << \ 119 CS42L42_HSBIAS_FILT_REF_RS_SHIFT) 120 #define CS42L42_RING_SENSE_PU_HIZ_SHIFT 6 121 #define CS42L42_RING_SENSE_PU_HIZ_MASK (1 << \ 122 CS42L42_RING_SENSE_PU_HIZ_SHIFT) 123 124 #define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05) 125 #define CS42L42_TS_RS_GATE_SHIFT 7 126 #define CS42L42_TS_RS_GATE_MAS (1 << CS42L42_TS_RS_GATE_SHIFT) 127 128 #define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07) 129 #define CS42L42_SCLK_PRESENT_SHIFT 0 130 #define CS42L42_SCLK_PRESENT_MASK (1 << CS42L42_SCLK_PRESENT_SHIFT) 131 132 #define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09) 133 #define CS42L42_OSC_SW_SEL_STAT_SHIFT 0 134 #define CS42L42_OSC_SW_SEL_STAT_MASK (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT) 135 #define CS42L42_OSC_PDNB_STAT_SHIFT 2 136 #define CS42L42_OSC_PDNB_STAT_MASK (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT) 137 138 #define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12) 139 #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0 140 #define CS42L42_RS_RISE_DBNCE_TIME_MASK (7 << \ 141 CS42L42_RS_RISE_DBNCE_TIME_SHIFT) 142 #define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 3 143 #define CS42L42_RS_FALL_DBNCE_TIME_MASK (7 << \ 144 CS42L42_RS_FALL_DBNCE_TIME_SHIFT) 145 #define CS42L42_RS_PU_EN_SHIFT 6 146 #define CS42L42_RS_PU_EN_MASK (1 << \ 147 CS42L42_RS_PU_EN_SHIFT) 148 #define CS42L42_RS_INV_SHIFT 7 149 #define CS42L42_RS_INV_MASK (1 << \ 150 CS42L42_RS_INV_SHIFT) 151 152 #define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13) 153 #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0 154 #define CS42L42_TS_RISE_DBNCE_TIME_MASK (7 << \ 155 CS42L42_TS_RISE_DBNCE_TIME_SHIFT) 156 #define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 3 157 #define CS42L42_TS_FALL_DBNCE_TIME_MASK (7 << \ 158 CS42L42_TS_FALL_DBNCE_TIME_SHIFT) 159 #define CS42L42_TS_INV_SHIFT 7 160 #define CS42L42_TS_INV_MASK (1 << \ 161 CS42L42_TS_INV_SHIFT) 162 163 #define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14) 164 #define CS42L42_D_RS_PLUG_DBNC_SHIFT 0 165 #define CS42L42_D_RS_PLUG_DBNC_MASK (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT) 166 #define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1 167 #define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT) 168 #define CS42L42_D_TS_PLUG_DBNC_SHIFT 2 169 #define CS42L42_D_TS_PLUG_DBNC_MASK (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT) 170 #define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3 171 #define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT) 172 173 #define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15) 174 #define CS42L42_RS_PLUG_DBNC_SHIFT 0 175 #define CS42L42_RS_PLUG_DBNC_MASK (1 << CS42L42_RS_PLUG_DBNC_SHIFT) 176 #define CS42L42_RS_UNPLUG_DBNC_SHIFT 1 177 #define CS42L42_RS_UNPLUG_DBNC_MASK (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT) 178 #define CS42L42_TS_PLUG_DBNC_SHIFT 2 179 #define CS42L42_TS_PLUG_DBNC_MASK (1 << CS42L42_TS_PLUG_DBNC_SHIFT) 180 #define CS42L42_TS_UNPLUG_DBNC_SHIFT 3 181 #define CS42L42_TS_UNPLUG_DBNC_MASK (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT) 182 183 #define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F) 184 #define CS42L42_HSDET_COMP1_LVL_SHIFT 0 185 #define CS42L42_HSDET_COMP1_LVL_MASK (15 << CS42L42_HSDET_COMP1_LVL_SHIFT) 186 #define CS42L42_HSDET_COMP2_LVL_SHIFT 4 187 #define CS42L42_HSDET_COMP2_LVL_MASK (15 << CS42L42_HSDET_COMP2_LVL_SHIFT) 188 189 #define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20) 190 #define CS42L42_HSDET_AUTO_TIME_SHIFT 0 191 #define CS42L42_HSDET_AUTO_TIME_MASK (3 << CS42L42_HSDET_AUTO_TIME_SHIFT) 192 #define CS42L42_HSBIAS_REF_SHIFT 3 193 #define CS42L42_HSBIAS_REF_MASK (1 << CS42L42_HSBIAS_REF_SHIFT) 194 #define CS42L42_HSDET_SET_SHIFT 4 195 #define CS42L42_HSDET_SET_MASK (3 << CS42L42_HSDET_SET_SHIFT) 196 #define CS42L42_HSDET_CTRL_SHIFT 6 197 #define CS42L42_HSDET_CTRL_MASK (3 << CS42L42_HSDET_CTRL_SHIFT) 198 199 #define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21) 200 #define CS42L42_SW_GNDHS_HS4_SHIFT 0 201 #define CS42L42_SW_GNDHS_HS4_MASK (1 << CS42L42_SW_GNDHS_HS4_SHIFT) 202 #define CS42L42_SW_GNDHS_HS3_SHIFT 1 203 #define CS42L42_SW_GNDHS_HS3_MASK (1 << CS42L42_SW_GNDHS_HS3_SHIFT) 204 #define CS42L42_SW_HSB_HS4_SHIFT 2 205 #define CS42L42_SW_HSB_HS4_MASK (1 << CS42L42_SW_HSB_HS4_SHIFT) 206 #define CS42L42_SW_HSB_HS3_SHIFT 3 207 #define CS42L42_SW_HSB_HS3_MASK (1 << CS42L42_SW_HSB_HS3_SHIFT) 208 #define CS42L42_SW_HSB_FILT_HS4_SHIFT 4 209 #define CS42L42_SW_HSB_FILT_HS4_MASK (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) 210 #define CS42L42_SW_HSB_FILT_HS3_SHIFT 5 211 #define CS42L42_SW_HSB_FILT_HS3_MASK (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) 212 #define CS42L42_SW_REF_HS4_SHIFT 6 213 #define CS42L42_SW_REF_HS4_MASK (1 << CS42L42_SW_REF_HS4_SHIFT) 214 #define CS42L42_SW_REF_HS3_SHIFT 7 215 #define CS42L42_SW_REF_HS3_MASK (1 << CS42L42_SW_REF_HS3_SHIFT) 216 217 #define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24) 218 #define CS42L42_HSDET_TYPE_SHIFT 0 219 #define CS42L42_HSDET_TYPE_MASK (3 << CS42L42_HSDET_TYPE_SHIFT) 220 #define CS42L42_HSDET_COMP1_OUT_SHIFT 6 221 #define CS42L42_HSDET_COMP1_OUT_MASK (1 << CS42L42_HSDET_COMP1_OUT_SHIFT) 222 #define CS42L42_HSDET_COMP2_OUT_SHIFT 7 223 #define CS42L42_HSDET_COMP2_OUT_MASK (1 << CS42L42_HSDET_COMP2_OUT_SHIFT) 224 #define CS42L42_PLUG_CTIA 0 225 #define CS42L42_PLUG_OMTP 1 226 #define CS42L42_PLUG_HEADPHONE 2 227 #define CS42L42_PLUG_INVALID 3 228 229 #define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29) 230 #define CS42L42_HS_CLAMP_DISABLE_SHIFT 0 231 #define CS42L42_HS_CLAMP_DISABLE_MASK (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT) 232 233 /* Page 0x12 Clocking Registers */ 234 #define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01) 235 #define CS42L42_MCLKDIV_SHIFT 1 236 #define CS42L42_MCLKDIV_MASK (1 << CS42L42_MCLKDIV_SHIFT) 237 #define CS42L42_MCLK_SRC_SEL_SHIFT 0 238 #define CS42L42_MCLK_SRC_SEL_MASK (1 << CS42L42_MCLK_SRC_SEL_SHIFT) 239 240 #define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02) 241 #define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03) 242 243 #define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04) 244 #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0 245 #define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \ 246 CS42L42_FSYNC_PULSE_WIDTH_SHIFT) 247 248 #define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05) 249 250 #define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06) 251 #define CS42L42_FSYNC_PERIOD_SHIFT 0 252 #define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT) 253 254 #define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07) 255 #define CS42L42_ASP_SCLK_EN_SHIFT 5 256 #define CS42L42_ASP_SCLK_EN_MASK (1 << CS42L42_ASP_SCLK_EN_SHIFT) 257 #define CS42L42_ASP_MASTER_MODE 0x01 258 #define CS42L42_ASP_SLAVE_MODE 0x00 259 #define CS42L42_ASP_MODE_SHIFT 4 260 #define CS42L42_ASP_MODE_MASK (1 << CS42L42_ASP_MODE_SHIFT) 261 #define CS42L42_ASP_SCPOL_IN_DAC_SHIFT 2 262 #define CS42L42_ASP_SCPOL_IN_DAC_MASK (1 << CS42L42_ASP_SCPOL_IN_DAC_SHIFT) 263 #define CS42L42_ASP_LCPOL_IN_SHIFT 0 264 #define CS42L42_ASP_LCPOL_IN_MASK (1 << CS42L42_ASP_LCPOL_IN_SHIFT) 265 #define CS42L42_ASP_POL_INV 1 266 267 #define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08) 268 #define CS42L42_ASP_STP_SHIFT 4 269 #define CS42L42_ASP_STP_MASK (1 << CS42L42_ASP_STP_SHIFT) 270 #define CS42L42_ASP_5050_SHIFT 3 271 #define CS42L42_ASP_5050_MASK (1 << CS42L42_ASP_5050_SHIFT) 272 #define CS42L42_ASP_FSD_SHIFT 0 273 #define CS42L42_ASP_FSD_MASK (7 << CS42L42_ASP_FSD_SHIFT) 274 #define CS42L42_ASP_FSD_0_5 1 275 #define CS42L42_ASP_FSD_1_0 2 276 #define CS42L42_ASP_FSD_1_5 3 277 #define CS42L42_ASP_FSD_2_0 4 278 279 #define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09) 280 #define CS42L42_FS_EN_SHIFT 0 281 #define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT) 282 #define CS42L42_FS_EN_IASRC_96K 0x1 283 #define CS42L42_FS_EN_OASRC_96K 0x2 284 285 #define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A) 286 #define CS42L42_CLK_IASRC_SEL_SHIFT 0 287 #define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT) 288 #define CS42L42_CLK_IASRC_SEL_12 1 289 290 #define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B) 291 #define CS42L42_CLK_OASRC_SEL_SHIFT 0 292 #define CS42L42_CLK_OASRC_SEL_MASK (1 << CS42L42_CLK_OASRC_SEL_SHIFT) 293 #define CS42L42_CLK_OASRC_SEL_12 1 294 295 #define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C) 296 #define CS42L42_SCLK_PREDIV_SHIFT 0 297 #define CS42L42_SCLK_PREDIV_MASK (3 << CS42L42_SCLK_PREDIV_SHIFT) 298 299 /* Page 0x13 Interrupt Registers */ 300 /* Interrupts */ 301 #define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01) 302 #define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02) 303 #define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03) 304 #define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04) 305 #define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05) 306 #define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08) 307 #define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09) 308 #define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A) 309 #define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B) 310 #define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D) 311 #define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E) 312 #define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F) 313 /* Masks */ 314 #define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16) 315 #define CS42L42_ADC_OVFL_SHIFT 0 316 #define CS42L42_ADC_OVFL_MASK (1 << CS42L42_ADC_OVFL_SHIFT) 317 #define CS42L42_ADC_OVFL_VAL_MASK CS42L42_ADC_OVFL_MASK 318 319 #define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17) 320 #define CS42L42_MIX_CHB_OVFL_SHIFT 0 321 #define CS42L42_MIX_CHB_OVFL_MASK (1 << CS42L42_MIX_CHB_OVFL_SHIFT) 322 #define CS42L42_MIX_CHA_OVFL_SHIFT 1 323 #define CS42L42_MIX_CHA_OVFL_MASK (1 << CS42L42_MIX_CHA_OVFL_SHIFT) 324 #define CS42L42_EQ_OVFL_SHIFT 2 325 #define CS42L42_EQ_OVFL_MASK (1 << CS42L42_EQ_OVFL_SHIFT) 326 #define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3 327 #define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT) 328 #define CS42L42_MIXER_VAL_MASK (CS42L42_MIX_CHB_OVFL_MASK | \ 329 CS42L42_MIX_CHA_OVFL_MASK | \ 330 CS42L42_EQ_OVFL_MASK | \ 331 CS42L42_EQ_BIQUAD_OVFL_MASK) 332 333 #define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18) 334 #define CS42L42_SRC_ILK_SHIFT 0 335 #define CS42L42_SRC_ILK_MASK (1 << CS42L42_SRC_ILK_SHIFT) 336 #define CS42L42_SRC_OLK_SHIFT 1 337 #define CS42L42_SRC_OLK_MASK (1 << CS42L42_SRC_OLK_SHIFT) 338 #define CS42L42_SRC_IUNLK_SHIFT 2 339 #define CS42L42_SRC_IUNLK_MASK (1 << CS42L42_SRC_IUNLK_SHIFT) 340 #define CS42L42_SRC_OUNLK_SHIFT 3 341 #define CS42L42_SRC_OUNLK_MASK (1 << CS42L42_SRC_OUNLK_SHIFT) 342 #define CS42L42_SRC_VAL_MASK (CS42L42_SRC_ILK_MASK | \ 343 CS42L42_SRC_OLK_MASK | \ 344 CS42L42_SRC_IUNLK_MASK | \ 345 CS42L42_SRC_OUNLK_MASK) 346 347 #define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19) 348 #define CS42L42_ASPRX_NOLRCK_SHIFT 0 349 #define CS42L42_ASPRX_NOLRCK_MASK (1 << CS42L42_ASPRX_NOLRCK_SHIFT) 350 #define CS42L42_ASPRX_EARLY_SHIFT 1 351 #define CS42L42_ASPRX_EARLY_MASK (1 << CS42L42_ASPRX_EARLY_SHIFT) 352 #define CS42L42_ASPRX_LATE_SHIFT 2 353 #define CS42L42_ASPRX_LATE_MASK (1 << CS42L42_ASPRX_LATE_SHIFT) 354 #define CS42L42_ASPRX_ERROR_SHIFT 3 355 #define CS42L42_ASPRX_ERROR_MASK (1 << CS42L42_ASPRX_ERROR_SHIFT) 356 #define CS42L42_ASPRX_OVLD_SHIFT 4 357 #define CS42L42_ASPRX_OVLD_MASK (1 << CS42L42_ASPRX_OVLD_SHIFT) 358 #define CS42L42_ASP_RX_VAL_MASK (CS42L42_ASPRX_NOLRCK_MASK | \ 359 CS42L42_ASPRX_EARLY_MASK | \ 360 CS42L42_ASPRX_LATE_MASK | \ 361 CS42L42_ASPRX_ERROR_MASK | \ 362 CS42L42_ASPRX_OVLD_MASK) 363 364 #define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A) 365 #define CS42L42_ASPTX_NOLRCK_SHIFT 0 366 #define CS42L42_ASPTX_NOLRCK_MASK (1 << CS42L42_ASPTX_NOLRCK_SHIFT) 367 #define CS42L42_ASPTX_EARLY_SHIFT 1 368 #define CS42L42_ASPTX_EARLY_MASK (1 << CS42L42_ASPTX_EARLY_SHIFT) 369 #define CS42L42_ASPTX_LATE_SHIFT 2 370 #define CS42L42_ASPTX_LATE_MASK (1 << CS42L42_ASPTX_LATE_SHIFT) 371 #define CS42L42_ASPTX_SMERROR_SHIFT 3 372 #define CS42L42_ASPTX_SMERROR_MASK (1 << CS42L42_ASPTX_SMERROR_SHIFT) 373 #define CS42L42_ASP_TX_VAL_MASK (CS42L42_ASPTX_NOLRCK_MASK | \ 374 CS42L42_ASPTX_EARLY_MASK | \ 375 CS42L42_ASPTX_LATE_MASK | \ 376 CS42L42_ASPTX_SMERROR_MASK) 377 378 #define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B) 379 #define CS42L42_PDN_DONE_SHIFT 0 380 #define CS42L42_PDN_DONE_MASK (1 << CS42L42_PDN_DONE_SHIFT) 381 #define CS42L42_HSDET_AUTO_DONE_SHIFT 1 382 #define CS42L42_HSDET_AUTO_DONE_MASK (1 << CS42L42_HSDET_AUTO_DONE_SHIFT) 383 #define CS42L42_CODEC_VAL_MASK (CS42L42_PDN_DONE_MASK | \ 384 CS42L42_HSDET_AUTO_DONE_MASK) 385 386 #define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C) 387 #define CS42L42_SRCPL_ADC_LK_SHIFT 0 388 #define CS42L42_SRCPL_ADC_LK_MASK (1 << CS42L42_SRCPL_ADC_LK_SHIFT) 389 #define CS42L42_SRCPL_DAC_LK_SHIFT 2 390 #define CS42L42_SRCPL_DAC_LK_MASK (1 << CS42L42_SRCPL_DAC_LK_SHIFT) 391 #define CS42L42_SRCPL_ADC_UNLK_SHIFT 5 392 #define CS42L42_SRCPL_ADC_UNLK_MASK (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) 393 #define CS42L42_SRCPL_DAC_UNLK_SHIFT 6 394 #define CS42L42_SRCPL_DAC_UNLK_MASK (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT) 395 #define CS42L42_SRCPL_VAL_MASK (CS42L42_SRCPL_ADC_LK_MASK | \ 396 CS42L42_SRCPL_DAC_LK_MASK | \ 397 CS42L42_SRCPL_ADC_UNLK_MASK | \ 398 CS42L42_SRCPL_DAC_UNLK_MASK) 399 400 #define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E) 401 #define CS42L42_VPMON_SHIFT 0 402 #define CS42L42_VPMON_MASK (1 << CS42L42_VPMON_SHIFT) 403 #define CS42L42_VPMON_VAL_MASK CS42L42_VPMON_MASK 404 405 #define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F) 406 #define CS42L42_PLL_LOCK_SHIFT 0 407 #define CS42L42_PLL_LOCK_MASK (1 << CS42L42_PLL_LOCK_SHIFT) 408 #define CS42L42_PLL_LOCK_VAL_MASK CS42L42_PLL_LOCK_MASK 409 410 #define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20) 411 #define CS42L42_RS_PLUG_SHIFT 0 412 #define CS42L42_RS_PLUG_MASK (1 << CS42L42_RS_PLUG_SHIFT) 413 #define CS42L42_RS_UNPLUG_SHIFT 1 414 #define CS42L42_RS_UNPLUG_MASK (1 << CS42L42_RS_UNPLUG_SHIFT) 415 #define CS42L42_TS_PLUG_SHIFT 2 416 #define CS42L42_TS_PLUG_MASK (1 << CS42L42_TS_PLUG_SHIFT) 417 #define CS42L42_TS_UNPLUG_SHIFT 3 418 #define CS42L42_TS_UNPLUG_MASK (1 << CS42L42_TS_UNPLUG_SHIFT) 419 #define CS42L42_TSRS_PLUG_VAL_MASK (CS42L42_RS_PLUG_MASK | \ 420 CS42L42_RS_UNPLUG_MASK | \ 421 CS42L42_TS_PLUG_MASK | \ 422 CS42L42_TS_UNPLUG_MASK) 423 #define CS42L42_TS_PLUG 3 424 #define CS42L42_TS_UNPLUG 0 425 #define CS42L42_TS_TRANS 1 426 427 /* Page 0x15 Fractional-N PLL Registers */ 428 #define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01) 429 #define CS42L42_PLL_START_SHIFT 0 430 #define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT) 431 432 #define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02) 433 #define CS42L42_PLL_DIV_FRAC_SHIFT 0 434 #define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT) 435 436 #define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03) 437 #define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04) 438 439 #define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05) 440 #define CS42L42_PLL_DIV_INT_SHIFT 0 441 #define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT) 442 443 #define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08) 444 #define CS42L42_PLL_DIVOUT_SHIFT 0 445 #define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT) 446 447 #define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A) 448 #define CS42L42_PLL_CAL_RATIO_SHIFT 0 449 #define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT) 450 451 #define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B) 452 #define CS42L42_PLL_MODE_SHIFT 0 453 #define CS42L42_PLL_MODE_MASK (3 << CS42L42_PLL_MODE_SHIFT) 454 455 /* Page 0x19 HP Load Detect Registers */ 456 #define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25) 457 #define CS42L42_RLA_STAT_SHIFT 0 458 #define CS42L42_RLA_STAT_MASK (3 << CS42L42_RLA_STAT_SHIFT) 459 #define CS42L42_RLA_STAT_15_OHM 0 460 461 #define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26) 462 #define CS42L42_HPLOAD_DET_DONE_SHIFT 0 463 #define CS42L42_HPLOAD_DET_DONE_MASK (1 << CS42L42_HPLOAD_DET_DONE_SHIFT) 464 465 #define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27) 466 #define CS42L42_HP_LD_EN_SHIFT 0 467 #define CS42L42_HP_LD_EN_MASK (1 << CS42L42_HP_LD_EN_SHIFT) 468 469 /* Page 0x1B Headset Interface Registers */ 470 #define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70) 471 #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0 472 #define CS42L42_HSBIAS_SENSE_TRIP_MASK (7 << \ 473 CS42L42_HSBIAS_SENSE_TRIP_SHIFT) 474 #define CS42L42_TIP_SENSE_EN_SHIFT 5 475 #define CS42L42_TIP_SENSE_EN_MASK (1 << \ 476 CS42L42_TIP_SENSE_EN_SHIFT) 477 #define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 6 478 #define CS42L42_AUTO_HSBIAS_HIZ_MASK (1 << \ 479 CS42L42_AUTO_HSBIAS_HIZ_SHIFT) 480 #define CS42L42_HSBIAS_SENSE_EN_SHIFT 7 481 #define CS42L42_HSBIAS_SENSE_EN_MASK (1 << \ 482 CS42L42_HSBIAS_SENSE_EN_SHIFT) 483 484 #define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71) 485 #define CS42L42_WAKEB_CLEAR_SHIFT 0 486 #define CS42L42_WAKEB_CLEAR_MASK (1 << CS42L42_WAKEB_CLEAR_SHIFT) 487 #define CS42L42_WAKEB_MODE_SHIFT 5 488 #define CS42L42_WAKEB_MODE_MASK (1 << CS42L42_WAKEB_MODE_SHIFT) 489 #define CS42L42_M_HP_WAKE_SHIFT 6 490 #define CS42L42_M_HP_WAKE_MASK (1 << CS42L42_M_HP_WAKE_SHIFT) 491 #define CS42L42_M_MIC_WAKE_SHIFT 7 492 #define CS42L42_M_MIC_WAKE_MASK (1 << CS42L42_M_MIC_WAKE_SHIFT) 493 494 #define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72) 495 #define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 7 496 #define CS42L42_ADC_DISABLE_S0_MUTE_MASK (1 << \ 497 CS42L42_ADC_DISABLE_S0_MUTE_SHIFT) 498 499 #define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73) 500 #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0 501 #define CS42L42_TIP_SENSE_DEBOUNCE_MASK (3 << \ 502 CS42L42_TIP_SENSE_DEBOUNCE_SHIFT) 503 #define CS42L42_TIP_SENSE_INV_SHIFT 5 504 #define CS42L42_TIP_SENSE_INV_MASK (1 << \ 505 CS42L42_TIP_SENSE_INV_SHIFT) 506 #define CS42L42_TIP_SENSE_CTRL_SHIFT 6 507 #define CS42L42_TIP_SENSE_CTRL_MASK (3 << \ 508 CS42L42_TIP_SENSE_CTRL_SHIFT) 509 510 #define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74) 511 #define CS42L42_PDN_MIC_LVL_DET_SHIFT 0 512 #define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT) 513 #define CS42L42_HSBIAS_CTL_SHIFT 1 514 #define CS42L42_HSBIAS_CTL_MASK (3 << CS42L42_HSBIAS_CTL_SHIFT) 515 #define CS42L42_DETECT_MODE_SHIFT 3 516 #define CS42L42_DETECT_MODE_MASK (3 << CS42L42_DETECT_MODE_SHIFT) 517 518 #define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75) 519 #define CS42L42_HS_DET_LEVEL_SHIFT 0 520 #define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT) 521 #define CS42L42_EVENT_STAT_SEL_SHIFT 6 522 #define CS42L42_EVENT_STAT_SEL_MASK (1 << CS42L42_EVENT_STAT_SEL_SHIFT) 523 #define CS42L42_LATCH_TO_VP_SHIFT 7 524 #define CS42L42_LATCH_TO_VP_MASK (1 << CS42L42_LATCH_TO_VP_SHIFT) 525 526 #define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76) 527 #define CS42L42_DEBOUNCE_TIME_SHIFT 5 528 #define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT) 529 530 #define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77) 531 #define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6 532 #define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT) 533 #define CS42L42_TIP_SENSE_SHIFT 7 534 #define CS42L42_TIP_SENSE_MASK (1 << CS42L42_TIP_SENSE_SHIFT) 535 536 #define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78) 537 #define CS42L42_SHORT_TRUE_SHIFT 0 538 #define CS42L42_SHORT_TRUE_MASK (1 << CS42L42_SHORT_TRUE_SHIFT) 539 #define CS42L42_HS_TRUE_SHIFT 1 540 #define CS42L42_HS_TRUE_MASK (1 << CS42L42_HS_TRUE_SHIFT) 541 542 #define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79) 543 #define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5 544 #define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) 545 #define CS42L42_TIP_SENSE_PLUG_SHIFT 6 546 #define CS42L42_TIP_SENSE_PLUG_MASK (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) 547 #define CS42L42_HSBIAS_SENSE_SHIFT 7 548 #define CS42L42_HSBIAS_SENSE_MASK (1 << CS42L42_HSBIAS_SENSE_SHIFT) 549 #define CS42L42_DET_INT_VAL1_MASK (CS42L42_TIP_SENSE_UNPLUG_MASK | \ 550 CS42L42_TIP_SENSE_PLUG_MASK | \ 551 CS42L42_HSBIAS_SENSE_MASK) 552 553 #define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A) 554 #define CS42L42_M_SHORT_DET_SHIFT 0 555 #define CS42L42_M_SHORT_DET_MASK (1 << \ 556 CS42L42_M_SHORT_DET_SHIFT) 557 #define CS42L42_M_SHORT_RLS_SHIFT 1 558 #define CS42L42_M_SHORT_RLS_MASK (1 << \ 559 CS42L42_M_SHORT_RLS_SHIFT) 560 #define CS42L42_M_HSBIAS_HIZ_SHIFT 2 561 #define CS42L42_M_HSBIAS_HIZ_MASK (1 << \ 562 CS42L42_M_HSBIAS_HIZ_SHIFT) 563 #define CS42L42_M_DETECT_FT_SHIFT 6 564 #define CS42L42_M_DETECT_FT_MASK (1 << \ 565 CS42L42_M_DETECT_FT_SHIFT) 566 #define CS42L42_M_DETECT_TF_SHIFT 7 567 #define CS42L42_M_DETECT_TF_MASK (1 << \ 568 CS42L42_M_DETECT_TF_SHIFT) 569 #define CS42L42_DET_INT_VAL2_MASK (CS42L42_M_SHORT_DET_MASK | \ 570 CS42L42_M_SHORT_RLS_MASK | \ 571 CS42L42_M_HSBIAS_HIZ_MASK | \ 572 CS42L42_M_DETECT_FT_MASK | \ 573 CS42L42_M_DETECT_TF_MASK) 574 575 /* Page 0x1C Headset Bias Registers */ 576 #define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03) 577 #define CS42L42_HSBIAS_RAMP_SHIFT 0 578 #define CS42L42_HSBIAS_RAMP_MASK (3 << CS42L42_HSBIAS_RAMP_SHIFT) 579 #define CS42L42_HSBIAS_PD_SHIFT 4 580 #define CS42L42_HSBIAS_PD_MASK (1 << CS42L42_HSBIAS_PD_SHIFT) 581 #define CS42L42_HSBIAS_CAPLESS_SHIFT 7 582 #define CS42L42_HSBIAS_CAPLESS_MASK (1 << CS42L42_HSBIAS_CAPLESS_SHIFT) 583 584 /* Page 0x1D ADC Registers */ 585 #define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01) 586 #define CS42L42_ADC_NOTCH_DIS_SHIFT 5 587 #define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 4 588 #define CS42L42_ADC_INV_SHIFT 2 589 #define CS42L42_ADC_DIG_BOOST_SHIFT 0 590 591 #define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03) 592 #define CS42L42_ADC_VOL_SHIFT 0 593 594 #define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04) 595 #define CS42L42_ADC_WNF_CF_SHIFT 4 596 #define CS42L42_ADC_WNF_EN_SHIFT 3 597 #define CS42L42_ADC_HPF_CF_SHIFT 1 598 #define CS42L42_ADC_HPF_EN_SHIFT 0 599 600 /* Page 0x1F DAC Registers */ 601 #define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01) 602 #define CS42L42_DACB_INV_SHIFT 1 603 #define CS42L42_DACA_INV_SHIFT 0 604 605 #define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06) 606 #define CS42L42_HPOUT_PULLDOWN_SHIFT 4 607 #define CS42L42_HPOUT_PULLDOWN_MASK (15 << CS42L42_HPOUT_PULLDOWN_SHIFT) 608 #define CS42L42_HPOUT_LOAD_SHIFT 3 609 #define CS42L42_HPOUT_LOAD_MASK (1 << CS42L42_HPOUT_LOAD_SHIFT) 610 #define CS42L42_HPOUT_CLAMP_SHIFT 2 611 #define CS42L42_HPOUT_CLAMP_MASK (1 << CS42L42_HPOUT_CLAMP_SHIFT) 612 #define CS42L42_DAC_HPF_EN_SHIFT 1 613 #define CS42L42_DAC_HPF_EN_MASK (1 << CS42L42_DAC_HPF_EN_SHIFT) 614 #define CS42L42_DAC_MON_EN_SHIFT 0 615 #define CS42L42_DAC_MON_EN_MASK (1 << CS42L42_DAC_MON_EN_SHIFT) 616 617 /* Page 0x20 HP CTL Registers */ 618 #define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01) 619 #define CS42L42_HP_ANA_BMUTE_SHIFT 3 620 #define CS42L42_HP_ANA_BMUTE_MASK (1 << CS42L42_HP_ANA_BMUTE_SHIFT) 621 #define CS42L42_HP_ANA_AMUTE_SHIFT 2 622 #define CS42L42_HP_ANA_AMUTE_MASK (1 << CS42L42_HP_ANA_AMUTE_SHIFT) 623 #define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1 624 #define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT) 625 626 /* Page 0x21 Class H Registers */ 627 #define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01) 628 629 /* Page 0x23 Mixer Volume Registers */ 630 #define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01) 631 #define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02) 632 633 #define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03) 634 #define CS42L42_MIXER_CH_VOL_SHIFT 0 635 #define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT) 636 637 /* Page 0x24 EQ Registers */ 638 #define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01) 639 #define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02) 640 #define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03) 641 #define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04) 642 #define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06) 643 #define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07) 644 #define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08) 645 #define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09) 646 #define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A) 647 #define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B) 648 #define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C) 649 #define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E) 650 651 /* Page 0x25 Audio Port Registers */ 652 #define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01) 653 654 #define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02) 655 #define CS42L42_SP_RX_RSYNC_SHIFT 6 656 #define CS42L42_SP_RX_RSYNC_MASK (1 << CS42L42_SP_RX_RSYNC_SHIFT) 657 #define CS42L42_SP_RX_NSB_POS_SHIFT 3 658 #define CS42L42_SP_RX_NSB_POS_MASK (7 << CS42L42_SP_RX_NSB_POS_SHIFT) 659 #define CS42L42_SP_RX_NFS_NSBB_SHIFT 2 660 #define CS42L42_SP_RX_NFS_NSBB_MASK (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT) 661 #define CS42L42_SP_RX_ISOC_MODE_SHIFT 0 662 #define CS42L42_SP_RX_ISOC_MODE_MASK (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT) 663 664 #define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03) 665 #define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04) 666 #define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05) 667 #define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06) 668 #define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07) 669 670 /* Page 0x26 SRC Registers */ 671 #define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01) 672 #define CS42L42_SRC_SDIN_FS_SHIFT 0 673 #define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT) 674 675 #define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09) 676 677 /* Page 0x28 S/PDIF Registers */ 678 #define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01) 679 #define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02) 680 #define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03) 681 #define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04) 682 683 /* Page 0x29 Serial Port TX Registers */ 684 #define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01) 685 #define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02) 686 #define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03) 687 #define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04) 688 #define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05) 689 #define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06) 690 #define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A) 691 #define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B) 692 693 /* Page 0x2A Serial Port RX Registers */ 694 #define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01) 695 #define CS42L42_ASP_RX0_CH_EN_SHIFT 2 696 #define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT) 697 #define CS42L42_ASP_RX0_CH1_EN 1 698 #define CS42L42_ASP_RX0_CH2_EN 2 699 #define CS42L42_ASP_RX0_CH3_EN 4 700 #define CS42L42_ASP_RX0_CH4_EN 8 701 702 #define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02) 703 #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03) 704 #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04) 705 #define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05) 706 #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06) 707 #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07) 708 #define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08) 709 #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09) 710 #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A) 711 #define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B) 712 #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C) 713 #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D) 714 #define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E) 715 #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F) 716 #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10) 717 #define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11) 718 #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12) 719 #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13) 720 721 #define CS42L42_ASP_RX_CH_AP_SHIFT 6 722 #define CS42L42_ASP_RX_CH_AP_MASK (1 << CS42L42_ASP_RX_CH_AP_SHIFT) 723 #define CS42L42_ASP_RX_CH_AP_LOW 0 724 #define CS42L42_ASP_RX_CH_AP_HI 1 725 #define CS42L42_ASP_RX_CH_RES_SHIFT 0 726 #define CS42L42_ASP_RX_CH_RES_MASK (3 << CS42L42_ASP_RX_CH_RES_SHIFT) 727 #define CS42L42_ASP_RX_CH_RES_32 3 728 #define CS42L42_ASP_RX_CH_RES_16 1 729 #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0 730 #define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT) 731 732 /* Page 0x30 ID Registers */ 733 #define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14) 734 #define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14) 735 736 /* Defines for fracturing values spread across multiple registers */ 737 #define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff) 738 #define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8) 739 #define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16) 740 741 #define CS42L42_NUM_SUPPLIES 5 742 743 static const char *const cs42l42_supply_names[CS42L42_NUM_SUPPLIES] = { 744 "VA", 745 "VP", 746 "VCP", 747 "VD_FILT", 748 "VL", 749 }; 750 751 struct cs42l42_private { 752 struct regmap *regmap; 753 struct snd_soc_component *component; 754 struct regulator_bulk_data supplies[CS42L42_NUM_SUPPLIES]; 755 struct gpio_desc *reset_gpio; 756 struct completion pdn_done; 757 u32 sclk; 758 u32 srate; 759 u32 swidth; 760 u8 plug_state; 761 u8 hs_type; 762 u8 ts_inv; 763 u8 ts_dbnc_rise; 764 u8 ts_dbnc_fall; 765 u8 btn_det_init_dbnce; 766 u8 btn_det_event_dbnce; 767 u8 bias_thresholds[CS42L42_NUM_BIASES]; 768 u8 hs_bias_ramp_rate; 769 u8 hs_bias_ramp_time; 770 }; 771 772 #endif /* __CS42L42_H__ */ 773