1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/i2c.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/gpio/consumer.h> 25 #include <linux/of.h> 26 #include <linux/of_gpio.h> 27 #include <linux/of_device.h> 28 #include <linux/pm_runtime.h> 29 #include <sound/core.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc.h> 33 #include <sound/soc-dapm.h> 34 #include <sound/initval.h> 35 #include <sound/tlv.h> 36 #include <dt-bindings/sound/cs42l42.h> 37 38 #include "cs42l42.h" 39 40 static const struct reg_default cs42l42_reg_defaults[] = { 41 { CS42L42_FRZ_CTL, 0x00 }, 42 { CS42L42_SRC_CTL, 0x10 }, 43 { CS42L42_MCLK_STATUS, 0x02 }, 44 { CS42L42_MCLK_CTL, 0x02 }, 45 { CS42L42_SFTRAMP_RATE, 0xA4 }, 46 { CS42L42_I2C_DEBOUNCE, 0x88 }, 47 { CS42L42_I2C_STRETCH, 0x03 }, 48 { CS42L42_I2C_TIMEOUT, 0xB7 }, 49 { CS42L42_PWR_CTL1, 0xFF }, 50 { CS42L42_PWR_CTL2, 0x84 }, 51 { CS42L42_PWR_CTL3, 0x20 }, 52 { CS42L42_RSENSE_CTL1, 0x40 }, 53 { CS42L42_RSENSE_CTL2, 0x00 }, 54 { CS42L42_OSC_SWITCH, 0x00 }, 55 { CS42L42_OSC_SWITCH_STATUS, 0x05 }, 56 { CS42L42_RSENSE_CTL3, 0x1B }, 57 { CS42L42_TSENSE_CTL, 0x1B }, 58 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 59 { CS42L42_TRSENSE_STATUS, 0x00 }, 60 { CS42L42_HSDET_CTL1, 0x77 }, 61 { CS42L42_HSDET_CTL2, 0x00 }, 62 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 63 { CS42L42_HS_DET_STATUS, 0x00 }, 64 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 65 { CS42L42_MCLK_SRC_SEL, 0x00 }, 66 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 67 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 68 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 69 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 70 { CS42L42_FSYNC_P_UPPER, 0x00 }, 71 { CS42L42_ASP_CLK_CFG, 0x00 }, 72 { CS42L42_ASP_FRM_CFG, 0x10 }, 73 { CS42L42_FS_RATE_EN, 0x00 }, 74 { CS42L42_IN_ASRC_CLK, 0x00 }, 75 { CS42L42_OUT_ASRC_CLK, 0x00 }, 76 { CS42L42_PLL_DIV_CFG1, 0x00 }, 77 { CS42L42_ADC_OVFL_STATUS, 0x00 }, 78 { CS42L42_MIXER_STATUS, 0x00 }, 79 { CS42L42_SRC_STATUS, 0x00 }, 80 { CS42L42_ASP_RX_STATUS, 0x00 }, 81 { CS42L42_ASP_TX_STATUS, 0x00 }, 82 { CS42L42_CODEC_STATUS, 0x00 }, 83 { CS42L42_DET_INT_STATUS1, 0x00 }, 84 { CS42L42_DET_INT_STATUS2, 0x00 }, 85 { CS42L42_SRCPL_INT_STATUS, 0x00 }, 86 { CS42L42_VPMON_STATUS, 0x00 }, 87 { CS42L42_PLL_LOCK_STATUS, 0x00 }, 88 { CS42L42_TSRS_PLUG_STATUS, 0x00 }, 89 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 90 { CS42L42_MIXER_INT_MASK, 0x0F }, 91 { CS42L42_SRC_INT_MASK, 0x0F }, 92 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 93 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 94 { CS42L42_CODEC_INT_MASK, 0x03 }, 95 { CS42L42_SRCPL_INT_MASK, 0xFF }, 96 { CS42L42_VPMON_INT_MASK, 0x01 }, 97 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 98 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 99 { CS42L42_PLL_CTL1, 0x00 }, 100 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 101 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 102 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 103 { CS42L42_PLL_DIV_INT, 0x40 }, 104 { CS42L42_PLL_CTL3, 0x10 }, 105 { CS42L42_PLL_CAL_RATIO, 0x80 }, 106 { CS42L42_PLL_CTL4, 0x03 }, 107 { CS42L42_LOAD_DET_RCSTAT, 0x00 }, 108 { CS42L42_LOAD_DET_DONE, 0x00 }, 109 { CS42L42_LOAD_DET_EN, 0x00 }, 110 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 111 { CS42L42_WAKE_CTL, 0xC0 }, 112 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 113 { CS42L42_TIPSENSE_CTL, 0x02 }, 114 { CS42L42_MISC_DET_CTL, 0x03 }, 115 { CS42L42_MIC_DET_CTL1, 0x1F }, 116 { CS42L42_MIC_DET_CTL2, 0x2F }, 117 { CS42L42_DET_STATUS1, 0x00 }, 118 { CS42L42_DET_STATUS2, 0x00 }, 119 { CS42L42_DET_INT1_MASK, 0xE0 }, 120 { CS42L42_DET_INT2_MASK, 0xFF }, 121 { CS42L42_HS_BIAS_CTL, 0xC2 }, 122 { CS42L42_ADC_CTL, 0x00 }, 123 { CS42L42_ADC_VOLUME, 0x00 }, 124 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 125 { CS42L42_DAC_CTL1, 0x00 }, 126 { CS42L42_DAC_CTL2, 0x02 }, 127 { CS42L42_HP_CTL, 0x0D }, 128 { CS42L42_CLASSH_CTL, 0x07 }, 129 { CS42L42_MIXER_CHA_VOL, 0x3F }, 130 { CS42L42_MIXER_ADC_VOL, 0x3F }, 131 { CS42L42_MIXER_CHB_VOL, 0x3F }, 132 { CS42L42_EQ_COEF_IN0, 0x22 }, 133 { CS42L42_EQ_COEF_IN1, 0x00 }, 134 { CS42L42_EQ_COEF_IN2, 0x00 }, 135 { CS42L42_EQ_COEF_IN3, 0x00 }, 136 { CS42L42_EQ_COEF_RW, 0x00 }, 137 { CS42L42_EQ_COEF_OUT0, 0x00 }, 138 { CS42L42_EQ_COEF_OUT1, 0x00 }, 139 { CS42L42_EQ_COEF_OUT2, 0x00 }, 140 { CS42L42_EQ_COEF_OUT3, 0x00 }, 141 { CS42L42_EQ_INIT_STAT, 0x00 }, 142 { CS42L42_EQ_START_FILT, 0x00 }, 143 { CS42L42_EQ_MUTE_CTL, 0x00 }, 144 { CS42L42_SP_RX_CH_SEL, 0x04 }, 145 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 146 { CS42L42_SP_RX_FS, 0x8C }, 147 { CS42l42_SPDIF_CH_SEL, 0x0E }, 148 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 149 { CS42L42_SP_TX_FS, 0xCC }, 150 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 151 { CS42L42_SRC_SDIN_FS, 0x40 }, 152 { CS42L42_SRC_SDOUT_FS, 0x40 }, 153 { CS42L42_SPDIF_CTL1, 0x01 }, 154 { CS42L42_SPDIF_CTL2, 0x00 }, 155 { CS42L42_SPDIF_CTL3, 0x00 }, 156 { CS42L42_SPDIF_CTL4, 0x42 }, 157 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 158 { CS42L42_ASP_TX_CH_EN, 0x00 }, 159 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 160 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 161 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 162 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 163 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 164 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 165 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 166 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 167 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 168 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 169 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 170 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 171 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 172 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 173 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 174 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 175 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 176 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 177 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 178 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 179 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 180 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 181 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 182 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 183 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 184 { CS42L42_SUB_REVID, 0x03 }, 185 }; 186 187 static bool cs42l42_readable_register(struct device *dev, unsigned int reg) 188 { 189 switch (reg) { 190 case CS42L42_PAGE_REGISTER: 191 case CS42L42_DEVID_AB: 192 case CS42L42_DEVID_CD: 193 case CS42L42_DEVID_E: 194 case CS42L42_FABID: 195 case CS42L42_REVID: 196 case CS42L42_FRZ_CTL: 197 case CS42L42_SRC_CTL: 198 case CS42L42_MCLK_STATUS: 199 case CS42L42_MCLK_CTL: 200 case CS42L42_SFTRAMP_RATE: 201 case CS42L42_I2C_DEBOUNCE: 202 case CS42L42_I2C_STRETCH: 203 case CS42L42_I2C_TIMEOUT: 204 case CS42L42_PWR_CTL1: 205 case CS42L42_PWR_CTL2: 206 case CS42L42_PWR_CTL3: 207 case CS42L42_RSENSE_CTL1: 208 case CS42L42_RSENSE_CTL2: 209 case CS42L42_OSC_SWITCH: 210 case CS42L42_OSC_SWITCH_STATUS: 211 case CS42L42_RSENSE_CTL3: 212 case CS42L42_TSENSE_CTL: 213 case CS42L42_TSRS_INT_DISABLE: 214 case CS42L42_TRSENSE_STATUS: 215 case CS42L42_HSDET_CTL1: 216 case CS42L42_HSDET_CTL2: 217 case CS42L42_HS_SWITCH_CTL: 218 case CS42L42_HS_DET_STATUS: 219 case CS42L42_HS_CLAMP_DISABLE: 220 case CS42L42_MCLK_SRC_SEL: 221 case CS42L42_SPDIF_CLK_CFG: 222 case CS42L42_FSYNC_PW_LOWER: 223 case CS42L42_FSYNC_PW_UPPER: 224 case CS42L42_FSYNC_P_LOWER: 225 case CS42L42_FSYNC_P_UPPER: 226 case CS42L42_ASP_CLK_CFG: 227 case CS42L42_ASP_FRM_CFG: 228 case CS42L42_FS_RATE_EN: 229 case CS42L42_IN_ASRC_CLK: 230 case CS42L42_OUT_ASRC_CLK: 231 case CS42L42_PLL_DIV_CFG1: 232 case CS42L42_ADC_OVFL_STATUS: 233 case CS42L42_MIXER_STATUS: 234 case CS42L42_SRC_STATUS: 235 case CS42L42_ASP_RX_STATUS: 236 case CS42L42_ASP_TX_STATUS: 237 case CS42L42_CODEC_STATUS: 238 case CS42L42_DET_INT_STATUS1: 239 case CS42L42_DET_INT_STATUS2: 240 case CS42L42_SRCPL_INT_STATUS: 241 case CS42L42_VPMON_STATUS: 242 case CS42L42_PLL_LOCK_STATUS: 243 case CS42L42_TSRS_PLUG_STATUS: 244 case CS42L42_ADC_OVFL_INT_MASK: 245 case CS42L42_MIXER_INT_MASK: 246 case CS42L42_SRC_INT_MASK: 247 case CS42L42_ASP_RX_INT_MASK: 248 case CS42L42_ASP_TX_INT_MASK: 249 case CS42L42_CODEC_INT_MASK: 250 case CS42L42_SRCPL_INT_MASK: 251 case CS42L42_VPMON_INT_MASK: 252 case CS42L42_PLL_LOCK_INT_MASK: 253 case CS42L42_TSRS_PLUG_INT_MASK: 254 case CS42L42_PLL_CTL1: 255 case CS42L42_PLL_DIV_FRAC0: 256 case CS42L42_PLL_DIV_FRAC1: 257 case CS42L42_PLL_DIV_FRAC2: 258 case CS42L42_PLL_DIV_INT: 259 case CS42L42_PLL_CTL3: 260 case CS42L42_PLL_CAL_RATIO: 261 case CS42L42_PLL_CTL4: 262 case CS42L42_LOAD_DET_RCSTAT: 263 case CS42L42_LOAD_DET_DONE: 264 case CS42L42_LOAD_DET_EN: 265 case CS42L42_HSBIAS_SC_AUTOCTL: 266 case CS42L42_WAKE_CTL: 267 case CS42L42_ADC_DISABLE_MUTE: 268 case CS42L42_TIPSENSE_CTL: 269 case CS42L42_MISC_DET_CTL: 270 case CS42L42_MIC_DET_CTL1: 271 case CS42L42_MIC_DET_CTL2: 272 case CS42L42_DET_STATUS1: 273 case CS42L42_DET_STATUS2: 274 case CS42L42_DET_INT1_MASK: 275 case CS42L42_DET_INT2_MASK: 276 case CS42L42_HS_BIAS_CTL: 277 case CS42L42_ADC_CTL: 278 case CS42L42_ADC_VOLUME: 279 case CS42L42_ADC_WNF_HPF_CTL: 280 case CS42L42_DAC_CTL1: 281 case CS42L42_DAC_CTL2: 282 case CS42L42_HP_CTL: 283 case CS42L42_CLASSH_CTL: 284 case CS42L42_MIXER_CHA_VOL: 285 case CS42L42_MIXER_ADC_VOL: 286 case CS42L42_MIXER_CHB_VOL: 287 case CS42L42_EQ_COEF_IN0: 288 case CS42L42_EQ_COEF_IN1: 289 case CS42L42_EQ_COEF_IN2: 290 case CS42L42_EQ_COEF_IN3: 291 case CS42L42_EQ_COEF_RW: 292 case CS42L42_EQ_COEF_OUT0: 293 case CS42L42_EQ_COEF_OUT1: 294 case CS42L42_EQ_COEF_OUT2: 295 case CS42L42_EQ_COEF_OUT3: 296 case CS42L42_EQ_INIT_STAT: 297 case CS42L42_EQ_START_FILT: 298 case CS42L42_EQ_MUTE_CTL: 299 case CS42L42_SP_RX_CH_SEL: 300 case CS42L42_SP_RX_ISOC_CTL: 301 case CS42L42_SP_RX_FS: 302 case CS42l42_SPDIF_CH_SEL: 303 case CS42L42_SP_TX_ISOC_CTL: 304 case CS42L42_SP_TX_FS: 305 case CS42L42_SPDIF_SW_CTL1: 306 case CS42L42_SRC_SDIN_FS: 307 case CS42L42_SRC_SDOUT_FS: 308 case CS42L42_SPDIF_CTL1: 309 case CS42L42_SPDIF_CTL2: 310 case CS42L42_SPDIF_CTL3: 311 case CS42L42_SPDIF_CTL4: 312 case CS42L42_ASP_TX_SZ_EN: 313 case CS42L42_ASP_TX_CH_EN: 314 case CS42L42_ASP_TX_CH_AP_RES: 315 case CS42L42_ASP_TX_CH1_BIT_MSB: 316 case CS42L42_ASP_TX_CH1_BIT_LSB: 317 case CS42L42_ASP_TX_HIZ_DLY_CFG: 318 case CS42L42_ASP_TX_CH2_BIT_MSB: 319 case CS42L42_ASP_TX_CH2_BIT_LSB: 320 case CS42L42_ASP_RX_DAI0_EN: 321 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 322 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 323 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 324 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 325 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 326 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 327 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 328 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 329 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 330 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 331 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 332 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 333 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 334 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 335 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 336 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 337 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 338 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 339 case CS42L42_SUB_REVID: 340 return true; 341 default: 342 return false; 343 } 344 } 345 346 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 347 { 348 switch (reg) { 349 case CS42L42_DEVID_AB: 350 case CS42L42_DEVID_CD: 351 case CS42L42_DEVID_E: 352 case CS42L42_MCLK_STATUS: 353 case CS42L42_TRSENSE_STATUS: 354 case CS42L42_HS_DET_STATUS: 355 case CS42L42_ADC_OVFL_STATUS: 356 case CS42L42_MIXER_STATUS: 357 case CS42L42_SRC_STATUS: 358 case CS42L42_ASP_RX_STATUS: 359 case CS42L42_ASP_TX_STATUS: 360 case CS42L42_CODEC_STATUS: 361 case CS42L42_DET_INT_STATUS1: 362 case CS42L42_DET_INT_STATUS2: 363 case CS42L42_SRCPL_INT_STATUS: 364 case CS42L42_VPMON_STATUS: 365 case CS42L42_PLL_LOCK_STATUS: 366 case CS42L42_TSRS_PLUG_STATUS: 367 case CS42L42_LOAD_DET_RCSTAT: 368 case CS42L42_LOAD_DET_DONE: 369 case CS42L42_DET_STATUS1: 370 case CS42L42_DET_STATUS2: 371 return true; 372 default: 373 return false; 374 } 375 } 376 377 static const struct regmap_range_cfg cs42l42_page_range = { 378 .name = "Pages", 379 .range_min = 0, 380 .range_max = CS42L42_MAX_REGISTER, 381 .selector_reg = CS42L42_PAGE_REGISTER, 382 .selector_mask = 0xff, 383 .selector_shift = 0, 384 .window_start = 0, 385 .window_len = 256, 386 }; 387 388 static const struct regmap_config cs42l42_regmap = { 389 .reg_bits = 8, 390 .val_bits = 8, 391 392 .readable_reg = cs42l42_readable_register, 393 .volatile_reg = cs42l42_volatile_register, 394 395 .ranges = &cs42l42_page_range, 396 .num_ranges = 1, 397 398 .max_register = CS42L42_MAX_REGISTER, 399 .reg_defaults = cs42l42_reg_defaults, 400 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 401 .cache_type = REGCACHE_RBTREE, 402 }; 403 404 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false); 405 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 406 407 static const char * const cs42l42_hpf_freq_text[] = { 408 "1.86Hz", "120Hz", "235Hz", "466Hz" 409 }; 410 411 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 412 CS42L42_ADC_HPF_CF_SHIFT, 413 cs42l42_hpf_freq_text); 414 415 static const char * const cs42l42_wnf3_freq_text[] = { 416 "160Hz", "180Hz", "200Hz", "220Hz", 417 "240Hz", "260Hz", "280Hz", "300Hz" 418 }; 419 420 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 421 CS42L42_ADC_WNF_CF_SHIFT, 422 cs42l42_wnf3_freq_text); 423 424 static const char * const cs42l42_wnf05_freq_text[] = { 425 "280Hz", "315Hz", "350Hz", "385Hz", 426 "420Hz", "455Hz", "490Hz", "525Hz" 427 }; 428 429 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 430 CS42L42_ADC_WNF_CF_SHIFT, 431 cs42l42_wnf05_freq_text); 432 433 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 434 /* ADC Volume and Filter Controls */ 435 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 436 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false), 437 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 438 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 439 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 440 CS42L42_ADC_INV_SHIFT, true, false), 441 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 442 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 443 SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME, 444 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv), 445 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 446 CS42L42_ADC_WNF_EN_SHIFT, true, false), 447 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 448 CS42L42_ADC_HPF_EN_SHIFT, true, false), 449 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 450 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 451 SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum), 452 453 /* DAC Volume and Filter Controls */ 454 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 455 CS42L42_DACA_INV_SHIFT, true, false), 456 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 457 CS42L42_DACB_INV_SHIFT, true, false), 458 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 459 CS42L42_DAC_HPF_EN_SHIFT, true, false), 460 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 461 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 462 0x3f, 1, mixer_tlv) 463 }; 464 465 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 466 /* Playback Path */ 467 SND_SOC_DAPM_OUTPUT("HP"), 468 SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1), 469 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 470 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH1_SHIFT, 0), 471 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH2_SHIFT, 0), 472 473 /* Playback Requirements */ 474 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 475 476 /* Capture Path */ 477 SND_SOC_DAPM_INPUT("HS"), 478 SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1), 479 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 480 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 481 482 /* Capture Requirements */ 483 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 484 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 485 486 /* Playback/Capture Requirements */ 487 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 488 }; 489 490 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 491 /* Playback Path */ 492 {"HP", NULL, "DAC"}, 493 {"DAC", NULL, "MIXER"}, 494 {"MIXER", NULL, "SDIN1"}, 495 {"MIXER", NULL, "SDIN2"}, 496 {"SDIN1", NULL, "Playback"}, 497 {"SDIN2", NULL, "Playback"}, 498 499 /* Playback Requirements */ 500 {"SDIN1", NULL, "ASP DAI0"}, 501 {"SDIN2", NULL, "ASP DAI0"}, 502 {"SDIN1", NULL, "SCLK"}, 503 {"SDIN2", NULL, "SCLK"}, 504 505 /* Capture Path */ 506 {"ADC", NULL, "HS"}, 507 { "SDOUT1", NULL, "ADC" }, 508 { "SDOUT2", NULL, "ADC" }, 509 { "Capture", NULL, "SDOUT1" }, 510 { "Capture", NULL, "SDOUT2" }, 511 512 /* Capture Requirements */ 513 { "SDOUT1", NULL, "ASP DAO0" }, 514 { "SDOUT2", NULL, "ASP DAO0" }, 515 { "SDOUT1", NULL, "SCLK" }, 516 { "SDOUT2", NULL, "SCLK" }, 517 { "SDOUT1", NULL, "ASP TX EN" }, 518 { "SDOUT2", NULL, "ASP TX EN" }, 519 }; 520 521 static int cs42l42_component_probe(struct snd_soc_component *component) 522 { 523 struct cs42l42_private *cs42l42 = 524 (struct cs42l42_private *)snd_soc_component_get_drvdata(component); 525 struct snd_soc_card *crd = component->card; 526 int ret = 0; 527 528 cs42l42->component = component; 529 530 ret = snd_soc_card_jack_new(crd, "CS42L42 Headset", SND_JACK_HEADSET | SND_JACK_BTN_0 | 531 SND_JACK_BTN_1 | SND_JACK_BTN_2 | SND_JACK_BTN_3, 532 &cs42l42->jack, NULL, 0); 533 if (ret < 0) 534 dev_err(component->dev, "Cannot create CS42L42 Headset: %d\n", ret); 535 536 return ret; 537 } 538 539 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = { 540 .probe = cs42l42_component_probe, 541 .dapm_widgets = cs42l42_dapm_widgets, 542 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 543 .dapm_routes = cs42l42_audio_map, 544 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 545 .controls = cs42l42_snd_controls, 546 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 547 .idle_bias_on = 1, 548 .endianness = 1, 549 .non_legacy_dai_naming = 1, 550 }; 551 552 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 553 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 554 { 555 .reg = CS42L42_OSC_SWITCH, 556 .def = CS42L42_SCLK_PRESENT_MASK, 557 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 558 }, 559 }; 560 561 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 562 static const struct reg_sequence cs42l42_to_osc_seq[] = { 563 { 564 .reg = CS42L42_OSC_SWITCH, 565 .def = 0, 566 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 567 }, 568 }; 569 570 struct cs42l42_pll_params { 571 u32 sclk; 572 u8 mclk_div; 573 u8 mclk_src_sel; 574 u8 sclk_prediv; 575 u8 pll_div_int; 576 u32 pll_div_frac; 577 u8 pll_mode; 578 u8 pll_divout; 579 u32 mclk_int; 580 u8 pll_cal_ratio; 581 }; 582 583 /* 584 * Common PLL Settings for given SCLK 585 * Table 4-5 from the Datasheet 586 */ 587 static const struct cs42l42_pll_params pll_ratio_table[] = { 588 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 }, 589 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 }, 590 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 }, 591 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 }, 592 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 }, 593 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 }, 594 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 }, 595 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 }, 596 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 }, 597 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 }, 598 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 }, 599 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 }, 600 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 }, 601 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 }, 602 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 } 603 }; 604 605 static int cs42l42_pll_config(struct snd_soc_component *component) 606 { 607 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 608 int i; 609 u32 clk; 610 u32 fsync; 611 612 if (!cs42l42->sclk) 613 clk = cs42l42->bclk; 614 else 615 clk = cs42l42->sclk; 616 617 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 618 if (pll_ratio_table[i].sclk == clk) { 619 /* Configure the internal sample rate */ 620 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 621 CS42L42_INTERNAL_FS_MASK, 622 ((pll_ratio_table[i].mclk_int != 623 12000000) && 624 (pll_ratio_table[i].mclk_int != 625 24000000)) << 626 CS42L42_INTERNAL_FS_SHIFT); 627 /* Set the MCLK src (PLL or SCLK) and the divide 628 * ratio 629 */ 630 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL, 631 CS42L42_MCLK_SRC_SEL_MASK | 632 CS42L42_MCLKDIV_MASK, 633 (pll_ratio_table[i].mclk_src_sel 634 << CS42L42_MCLK_SRC_SEL_SHIFT) | 635 (pll_ratio_table[i].mclk_div << 636 CS42L42_MCLKDIV_SHIFT)); 637 /* Set up the LRCLK */ 638 fsync = clk / cs42l42->srate; 639 if (((fsync * cs42l42->srate) != clk) 640 || ((fsync % 2) != 0)) { 641 dev_err(component->dev, 642 "Unsupported sclk %d/sample rate %d\n", 643 clk, 644 cs42l42->srate); 645 return -EINVAL; 646 } 647 /* Set the LRCLK period */ 648 snd_soc_component_update_bits(component, 649 CS42L42_FSYNC_P_LOWER, 650 CS42L42_FSYNC_PERIOD_MASK, 651 CS42L42_FRAC0_VAL(fsync - 1) << 652 CS42L42_FSYNC_PERIOD_SHIFT); 653 snd_soc_component_update_bits(component, 654 CS42L42_FSYNC_P_UPPER, 655 CS42L42_FSYNC_PERIOD_MASK, 656 CS42L42_FRAC1_VAL(fsync - 1) << 657 CS42L42_FSYNC_PERIOD_SHIFT); 658 /* Set the LRCLK to 50% duty cycle */ 659 fsync = fsync / 2; 660 snd_soc_component_update_bits(component, 661 CS42L42_FSYNC_PW_LOWER, 662 CS42L42_FSYNC_PULSE_WIDTH_MASK, 663 CS42L42_FRAC0_VAL(fsync - 1) << 664 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 665 snd_soc_component_update_bits(component, 666 CS42L42_FSYNC_PW_UPPER, 667 CS42L42_FSYNC_PULSE_WIDTH_MASK, 668 CS42L42_FRAC1_VAL(fsync - 1) << 669 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 670 snd_soc_component_update_bits(component, 671 CS42L42_ASP_FRM_CFG, 672 CS42L42_ASP_5050_MASK, 673 CS42L42_ASP_5050_MASK); 674 /* Set the frame delay to 1.0 SCLK clocks */ 675 snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG, 676 CS42L42_ASP_FSD_MASK, 677 CS42L42_ASP_FSD_1_0 << 678 CS42L42_ASP_FSD_SHIFT); 679 /* Set the sample rates (96k or lower) */ 680 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN, 681 CS42L42_FS_EN_MASK, 682 (CS42L42_FS_EN_IASRC_96K | 683 CS42L42_FS_EN_OASRC_96K) << 684 CS42L42_FS_EN_SHIFT); 685 /* Set the input/output internal MCLK clock ~12 MHz */ 686 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK, 687 CS42L42_CLK_IASRC_SEL_MASK, 688 CS42L42_CLK_IASRC_SEL_12 << 689 CS42L42_CLK_IASRC_SEL_SHIFT); 690 snd_soc_component_update_bits(component, 691 CS42L42_OUT_ASRC_CLK, 692 CS42L42_CLK_OASRC_SEL_MASK, 693 CS42L42_CLK_OASRC_SEL_12 << 694 CS42L42_CLK_OASRC_SEL_SHIFT); 695 if (pll_ratio_table[i].mclk_src_sel == 0) { 696 /* Pass the clock straight through */ 697 snd_soc_component_update_bits(component, 698 CS42L42_PLL_CTL1, 699 CS42L42_PLL_START_MASK, 0); 700 } else { 701 /* Configure PLL per table 4-5 */ 702 snd_soc_component_update_bits(component, 703 CS42L42_PLL_DIV_CFG1, 704 CS42L42_SCLK_PREDIV_MASK, 705 pll_ratio_table[i].sclk_prediv 706 << CS42L42_SCLK_PREDIV_SHIFT); 707 snd_soc_component_update_bits(component, 708 CS42L42_PLL_DIV_INT, 709 CS42L42_PLL_DIV_INT_MASK, 710 pll_ratio_table[i].pll_div_int 711 << CS42L42_PLL_DIV_INT_SHIFT); 712 snd_soc_component_update_bits(component, 713 CS42L42_PLL_DIV_FRAC0, 714 CS42L42_PLL_DIV_FRAC_MASK, 715 CS42L42_FRAC0_VAL( 716 pll_ratio_table[i].pll_div_frac) 717 << CS42L42_PLL_DIV_FRAC_SHIFT); 718 snd_soc_component_update_bits(component, 719 CS42L42_PLL_DIV_FRAC1, 720 CS42L42_PLL_DIV_FRAC_MASK, 721 CS42L42_FRAC1_VAL( 722 pll_ratio_table[i].pll_div_frac) 723 << CS42L42_PLL_DIV_FRAC_SHIFT); 724 snd_soc_component_update_bits(component, 725 CS42L42_PLL_DIV_FRAC2, 726 CS42L42_PLL_DIV_FRAC_MASK, 727 CS42L42_FRAC2_VAL( 728 pll_ratio_table[i].pll_div_frac) 729 << CS42L42_PLL_DIV_FRAC_SHIFT); 730 snd_soc_component_update_bits(component, 731 CS42L42_PLL_CTL4, 732 CS42L42_PLL_MODE_MASK, 733 pll_ratio_table[i].pll_mode 734 << CS42L42_PLL_MODE_SHIFT); 735 snd_soc_component_update_bits(component, 736 CS42L42_PLL_CTL3, 737 CS42L42_PLL_DIVOUT_MASK, 738 pll_ratio_table[i].pll_divout 739 << CS42L42_PLL_DIVOUT_SHIFT); 740 snd_soc_component_update_bits(component, 741 CS42L42_PLL_CAL_RATIO, 742 CS42L42_PLL_CAL_RATIO_MASK, 743 pll_ratio_table[i].pll_cal_ratio 744 << CS42L42_PLL_CAL_RATIO_SHIFT); 745 } 746 return 0; 747 } 748 } 749 750 return -EINVAL; 751 } 752 753 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 754 { 755 struct snd_soc_component *component = codec_dai->component; 756 u32 asp_cfg_val = 0; 757 758 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 759 case SND_SOC_DAIFMT_CBS_CFM: 760 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 761 CS42L42_ASP_MODE_SHIFT; 762 break; 763 case SND_SOC_DAIFMT_CBS_CFS: 764 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 765 CS42L42_ASP_MODE_SHIFT; 766 break; 767 default: 768 return -EINVAL; 769 } 770 771 /* interface format */ 772 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 773 case SND_SOC_DAIFMT_I2S: 774 case SND_SOC_DAIFMT_LEFT_J: 775 break; 776 default: 777 return -EINVAL; 778 } 779 780 /* Bitclock/frame inversion */ 781 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 782 case SND_SOC_DAIFMT_NB_NF: 783 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 784 break; 785 case SND_SOC_DAIFMT_NB_IF: 786 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 787 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 788 break; 789 case SND_SOC_DAIFMT_IB_NF: 790 break; 791 case SND_SOC_DAIFMT_IB_IF: 792 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 793 break; 794 } 795 796 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 797 CS42L42_ASP_SCPOL_MASK | 798 CS42L42_ASP_LCPOL_MASK, 799 asp_cfg_val); 800 801 return 0; 802 } 803 804 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 805 struct snd_pcm_hw_params *params, 806 struct snd_soc_dai *dai) 807 { 808 struct snd_soc_component *component = dai->component; 809 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 810 unsigned int channels = params_channels(params); 811 unsigned int width = (params_width(params) / 8) - 1; 812 unsigned int val = 0; 813 814 cs42l42->srate = params_rate(params); 815 cs42l42->bclk = snd_soc_params_to_bclk(params); 816 817 switch(substream->stream) { 818 case SNDRV_PCM_STREAM_CAPTURE: 819 if (channels == 2) { 820 val |= CS42L42_ASP_TX_CH2_AP_MASK; 821 val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT; 822 } 823 val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT; 824 825 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 826 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 827 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 828 break; 829 case SNDRV_PCM_STREAM_PLAYBACK: 830 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 831 /* channel 1 on low LRCLK */ 832 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 833 CS42L42_ASP_RX_CH_AP_MASK | 834 CS42L42_ASP_RX_CH_RES_MASK, val); 835 /* Channel 2 on high LRCLK */ 836 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 837 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 838 CS42L42_ASP_RX_CH_AP_MASK | 839 CS42L42_ASP_RX_CH_RES_MASK, val); 840 break; 841 default: 842 break; 843 } 844 845 return cs42l42_pll_config(component); 846 } 847 848 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 849 int clk_id, unsigned int freq, int dir) 850 { 851 struct snd_soc_component *component = dai->component; 852 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 853 854 cs42l42->sclk = freq; 855 856 return 0; 857 } 858 859 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 860 { 861 struct snd_soc_component *component = dai->component; 862 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 863 unsigned int regval; 864 u8 fullScaleVol; 865 int ret; 866 867 if (mute) { 868 /* Mute the headphone */ 869 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 870 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 871 CS42L42_HP_ANA_AMUTE_MASK | 872 CS42L42_HP_ANA_BMUTE_MASK, 873 CS42L42_HP_ANA_AMUTE_MASK | 874 CS42L42_HP_ANA_BMUTE_MASK); 875 876 cs42l42->stream_use &= ~(1 << stream); 877 if(!cs42l42->stream_use) { 878 /* 879 * Switch to the internal oscillator. 880 * SCLK must remain running until after this clock switch. 881 * Without a source of clock the I2C bus doesn't work. 882 */ 883 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 884 ARRAY_SIZE(cs42l42_to_osc_seq)); 885 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 886 CS42L42_PLL_START_MASK, 0); 887 } 888 } else { 889 if (!cs42l42->stream_use) { 890 /* SCLK must be running before codec unmute */ 891 if ((cs42l42->bclk < 11289600) && (cs42l42->sclk < 11289600)) { 892 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 893 CS42L42_PLL_START_MASK, 1); 894 ret = regmap_read_poll_timeout(cs42l42->regmap, 895 CS42L42_PLL_LOCK_STATUS, 896 regval, 897 (regval & 1), 898 CS42L42_PLL_LOCK_POLL_US, 899 CS42L42_PLL_LOCK_TIMEOUT_US); 900 if (ret < 0) 901 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 902 } 903 904 /* Mark SCLK as present, turn off internal oscillator */ 905 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 906 ARRAY_SIZE(cs42l42_to_sclk_seq)); 907 } 908 cs42l42->stream_use |= 1 << stream; 909 910 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 911 /* Read the headphone load */ 912 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT); 913 if (((regval & CS42L42_RLA_STAT_MASK) >> CS42L42_RLA_STAT_SHIFT) == 914 CS42L42_RLA_STAT_15_OHM) { 915 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK; 916 } else { 917 fullScaleVol = 0; 918 } 919 920 /* Un-mute the headphone, set the full scale volume flag */ 921 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 922 CS42L42_HP_ANA_AMUTE_MASK | 923 CS42L42_HP_ANA_BMUTE_MASK | 924 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol); 925 } 926 } 927 928 return 0; 929 } 930 931 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 932 SNDRV_PCM_FMTBIT_S24_LE |\ 933 SNDRV_PCM_FMTBIT_S32_LE ) 934 935 936 static const struct snd_soc_dai_ops cs42l42_ops = { 937 .hw_params = cs42l42_pcm_hw_params, 938 .set_fmt = cs42l42_set_dai_fmt, 939 .set_sysclk = cs42l42_set_sysclk, 940 .mute_stream = cs42l42_mute_stream, 941 }; 942 943 static struct snd_soc_dai_driver cs42l42_dai = { 944 .name = "cs42l42", 945 .playback = { 946 .stream_name = "Playback", 947 .channels_min = 1, 948 .channels_max = 2, 949 .rates = SNDRV_PCM_RATE_8000_192000, 950 .formats = CS42L42_FORMATS, 951 }, 952 .capture = { 953 .stream_name = "Capture", 954 .channels_min = 1, 955 .channels_max = 2, 956 .rates = SNDRV_PCM_RATE_8000_192000, 957 .formats = CS42L42_FORMATS, 958 }, 959 .symmetric_rate = 1, 960 .symmetric_sample_bits = 1, 961 .ops = &cs42l42_ops, 962 }; 963 964 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 965 { 966 unsigned int hs_det_status; 967 unsigned int int_status; 968 969 /* Mask the auto detect interrupt */ 970 regmap_update_bits(cs42l42->regmap, 971 CS42L42_CODEC_INT_MASK, 972 CS42L42_PDN_DONE_MASK | 973 CS42L42_HSDET_AUTO_DONE_MASK, 974 (1 << CS42L42_PDN_DONE_SHIFT) | 975 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 976 977 /* Set hs detect to automatic, disabled mode */ 978 regmap_update_bits(cs42l42->regmap, 979 CS42L42_HSDET_CTL2, 980 CS42L42_HSDET_CTRL_MASK | 981 CS42L42_HSDET_SET_MASK | 982 CS42L42_HSBIAS_REF_MASK | 983 CS42L42_HSDET_AUTO_TIME_MASK, 984 (2 << CS42L42_HSDET_CTRL_SHIFT) | 985 (2 << CS42L42_HSDET_SET_SHIFT) | 986 (0 << CS42L42_HSBIAS_REF_SHIFT) | 987 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 988 989 /* Read and save the hs detection result */ 990 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 991 992 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 993 CS42L42_HSDET_TYPE_SHIFT; 994 995 /* Set up button detection */ 996 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 997 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 998 /* Set auto HS bias settings to default */ 999 regmap_update_bits(cs42l42->regmap, 1000 CS42L42_HSBIAS_SC_AUTOCTL, 1001 CS42L42_HSBIAS_SENSE_EN_MASK | 1002 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1003 CS42L42_TIP_SENSE_EN_MASK | 1004 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1005 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1006 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1007 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1008 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1009 1010 /* Set up hs detect level sensitivity */ 1011 regmap_update_bits(cs42l42->regmap, 1012 CS42L42_MIC_DET_CTL1, 1013 CS42L42_LATCH_TO_VP_MASK | 1014 CS42L42_EVENT_STAT_SEL_MASK | 1015 CS42L42_HS_DET_LEVEL_MASK, 1016 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1017 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1018 (cs42l42->bias_thresholds[0] << 1019 CS42L42_HS_DET_LEVEL_SHIFT)); 1020 1021 /* Set auto HS bias settings to default */ 1022 regmap_update_bits(cs42l42->regmap, 1023 CS42L42_HSBIAS_SC_AUTOCTL, 1024 CS42L42_HSBIAS_SENSE_EN_MASK | 1025 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1026 CS42L42_TIP_SENSE_EN_MASK | 1027 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1028 (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1029 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1030 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1031 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1032 1033 /* Turn on level detect circuitry */ 1034 regmap_update_bits(cs42l42->regmap, 1035 CS42L42_MISC_DET_CTL, 1036 CS42L42_DETECT_MODE_MASK | 1037 CS42L42_HSBIAS_CTL_MASK | 1038 CS42L42_PDN_MIC_LVL_DET_MASK, 1039 (0 << CS42L42_DETECT_MODE_SHIFT) | 1040 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1041 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1042 1043 msleep(cs42l42->btn_det_init_dbnce); 1044 1045 /* Clear any button interrupts before unmasking them */ 1046 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1047 &int_status); 1048 1049 /* Unmask button detect interrupts */ 1050 regmap_update_bits(cs42l42->regmap, 1051 CS42L42_DET_INT2_MASK, 1052 CS42L42_M_DETECT_TF_MASK | 1053 CS42L42_M_DETECT_FT_MASK | 1054 CS42L42_M_HSBIAS_HIZ_MASK | 1055 CS42L42_M_SHORT_RLS_MASK | 1056 CS42L42_M_SHORT_DET_MASK, 1057 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1058 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1059 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1060 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1061 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1062 } else { 1063 /* Make sure button detect and HS bias circuits are off */ 1064 regmap_update_bits(cs42l42->regmap, 1065 CS42L42_MISC_DET_CTL, 1066 CS42L42_DETECT_MODE_MASK | 1067 CS42L42_HSBIAS_CTL_MASK | 1068 CS42L42_PDN_MIC_LVL_DET_MASK, 1069 (0 << CS42L42_DETECT_MODE_SHIFT) | 1070 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1071 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1072 } 1073 1074 regmap_update_bits(cs42l42->regmap, 1075 CS42L42_DAC_CTL2, 1076 CS42L42_HPOUT_PULLDOWN_MASK | 1077 CS42L42_HPOUT_LOAD_MASK | 1078 CS42L42_HPOUT_CLAMP_MASK | 1079 CS42L42_DAC_HPF_EN_MASK | 1080 CS42L42_DAC_MON_EN_MASK, 1081 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1082 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1083 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1084 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1085 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1086 1087 /* Unmask tip sense interrupts */ 1088 regmap_update_bits(cs42l42->regmap, 1089 CS42L42_TSRS_PLUG_INT_MASK, 1090 CS42L42_RS_PLUG_MASK | 1091 CS42L42_RS_UNPLUG_MASK | 1092 CS42L42_TS_PLUG_MASK | 1093 CS42L42_TS_UNPLUG_MASK, 1094 (1 << CS42L42_RS_PLUG_SHIFT) | 1095 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1096 (0 << CS42L42_TS_PLUG_SHIFT) | 1097 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1098 } 1099 1100 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1101 { 1102 /* Mask tip sense interrupts */ 1103 regmap_update_bits(cs42l42->regmap, 1104 CS42L42_TSRS_PLUG_INT_MASK, 1105 CS42L42_RS_PLUG_MASK | 1106 CS42L42_RS_UNPLUG_MASK | 1107 CS42L42_TS_PLUG_MASK | 1108 CS42L42_TS_UNPLUG_MASK, 1109 (1 << CS42L42_RS_PLUG_SHIFT) | 1110 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1111 (1 << CS42L42_TS_PLUG_SHIFT) | 1112 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1113 1114 /* Make sure button detect and HS bias circuits are off */ 1115 regmap_update_bits(cs42l42->regmap, 1116 CS42L42_MISC_DET_CTL, 1117 CS42L42_DETECT_MODE_MASK | 1118 CS42L42_HSBIAS_CTL_MASK | 1119 CS42L42_PDN_MIC_LVL_DET_MASK, 1120 (0 << CS42L42_DETECT_MODE_SHIFT) | 1121 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1122 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1123 1124 /* Set auto HS bias settings to default */ 1125 regmap_update_bits(cs42l42->regmap, 1126 CS42L42_HSBIAS_SC_AUTOCTL, 1127 CS42L42_HSBIAS_SENSE_EN_MASK | 1128 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1129 CS42L42_TIP_SENSE_EN_MASK | 1130 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1131 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1132 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1133 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1134 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1135 1136 /* Set hs detect to manual, disabled mode */ 1137 regmap_update_bits(cs42l42->regmap, 1138 CS42L42_HSDET_CTL2, 1139 CS42L42_HSDET_CTRL_MASK | 1140 CS42L42_HSDET_SET_MASK | 1141 CS42L42_HSBIAS_REF_MASK | 1142 CS42L42_HSDET_AUTO_TIME_MASK, 1143 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1144 (2 << CS42L42_HSDET_SET_SHIFT) | 1145 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1146 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1147 1148 regmap_update_bits(cs42l42->regmap, 1149 CS42L42_DAC_CTL2, 1150 CS42L42_HPOUT_PULLDOWN_MASK | 1151 CS42L42_HPOUT_LOAD_MASK | 1152 CS42L42_HPOUT_CLAMP_MASK | 1153 CS42L42_DAC_HPF_EN_MASK | 1154 CS42L42_DAC_MON_EN_MASK, 1155 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1156 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1157 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1158 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1159 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1160 1161 /* Power up HS bias to 2.7V */ 1162 regmap_update_bits(cs42l42->regmap, 1163 CS42L42_MISC_DET_CTL, 1164 CS42L42_DETECT_MODE_MASK | 1165 CS42L42_HSBIAS_CTL_MASK | 1166 CS42L42_PDN_MIC_LVL_DET_MASK, 1167 (0 << CS42L42_DETECT_MODE_SHIFT) | 1168 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1169 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1170 1171 /* Wait for HS bias to ramp up */ 1172 msleep(cs42l42->hs_bias_ramp_time); 1173 1174 /* Unmask auto detect interrupt */ 1175 regmap_update_bits(cs42l42->regmap, 1176 CS42L42_CODEC_INT_MASK, 1177 CS42L42_PDN_DONE_MASK | 1178 CS42L42_HSDET_AUTO_DONE_MASK, 1179 (1 << CS42L42_PDN_DONE_SHIFT) | 1180 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1181 1182 /* Set hs detect to automatic, enabled mode */ 1183 regmap_update_bits(cs42l42->regmap, 1184 CS42L42_HSDET_CTL2, 1185 CS42L42_HSDET_CTRL_MASK | 1186 CS42L42_HSDET_SET_MASK | 1187 CS42L42_HSBIAS_REF_MASK | 1188 CS42L42_HSDET_AUTO_TIME_MASK, 1189 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1190 (2 << CS42L42_HSDET_SET_SHIFT) | 1191 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1192 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1193 } 1194 1195 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1196 { 1197 /* Mask button detect interrupts */ 1198 regmap_update_bits(cs42l42->regmap, 1199 CS42L42_DET_INT2_MASK, 1200 CS42L42_M_DETECT_TF_MASK | 1201 CS42L42_M_DETECT_FT_MASK | 1202 CS42L42_M_HSBIAS_HIZ_MASK | 1203 CS42L42_M_SHORT_RLS_MASK | 1204 CS42L42_M_SHORT_DET_MASK, 1205 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1206 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1207 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1208 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1209 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1210 1211 /* Ground HS bias */ 1212 regmap_update_bits(cs42l42->regmap, 1213 CS42L42_MISC_DET_CTL, 1214 CS42L42_DETECT_MODE_MASK | 1215 CS42L42_HSBIAS_CTL_MASK | 1216 CS42L42_PDN_MIC_LVL_DET_MASK, 1217 (0 << CS42L42_DETECT_MODE_SHIFT) | 1218 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1219 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1220 1221 /* Set auto HS bias settings to default */ 1222 regmap_update_bits(cs42l42->regmap, 1223 CS42L42_HSBIAS_SC_AUTOCTL, 1224 CS42L42_HSBIAS_SENSE_EN_MASK | 1225 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1226 CS42L42_TIP_SENSE_EN_MASK | 1227 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1228 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1229 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1230 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1231 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1232 1233 /* Set hs detect to manual, disabled mode */ 1234 regmap_update_bits(cs42l42->regmap, 1235 CS42L42_HSDET_CTL2, 1236 CS42L42_HSDET_CTRL_MASK | 1237 CS42L42_HSDET_SET_MASK | 1238 CS42L42_HSBIAS_REF_MASK | 1239 CS42L42_HSDET_AUTO_TIME_MASK, 1240 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1241 (2 << CS42L42_HSDET_SET_SHIFT) | 1242 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1243 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1244 } 1245 1246 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1247 { 1248 int bias_level; 1249 unsigned int detect_status; 1250 1251 /* Mask button detect interrupts */ 1252 regmap_update_bits(cs42l42->regmap, 1253 CS42L42_DET_INT2_MASK, 1254 CS42L42_M_DETECT_TF_MASK | 1255 CS42L42_M_DETECT_FT_MASK | 1256 CS42L42_M_HSBIAS_HIZ_MASK | 1257 CS42L42_M_SHORT_RLS_MASK | 1258 CS42L42_M_SHORT_DET_MASK, 1259 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1260 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1261 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1262 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1263 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1264 1265 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1266 cs42l42->btn_det_event_dbnce * 2000); 1267 1268 /* Test all 4 level detect biases */ 1269 bias_level = 1; 1270 do { 1271 /* Adjust button detect level sensitivity */ 1272 regmap_update_bits(cs42l42->regmap, 1273 CS42L42_MIC_DET_CTL1, 1274 CS42L42_LATCH_TO_VP_MASK | 1275 CS42L42_EVENT_STAT_SEL_MASK | 1276 CS42L42_HS_DET_LEVEL_MASK, 1277 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1278 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1279 (cs42l42->bias_thresholds[bias_level] << 1280 CS42L42_HS_DET_LEVEL_SHIFT)); 1281 1282 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1283 &detect_status); 1284 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1285 (++bias_level < CS42L42_NUM_BIASES)); 1286 1287 switch (bias_level) { 1288 case 1: /* Function C button press */ 1289 bias_level = SND_JACK_BTN_2; 1290 dev_dbg(cs42l42->component->dev, "Function C button press\n"); 1291 break; 1292 case 2: /* Function B button press */ 1293 bias_level = SND_JACK_BTN_1; 1294 dev_dbg(cs42l42->component->dev, "Function B button press\n"); 1295 break; 1296 case 3: /* Function D button press */ 1297 bias_level = SND_JACK_BTN_3; 1298 dev_dbg(cs42l42->component->dev, "Function D button press\n"); 1299 break; 1300 case 4: /* Function A button press */ 1301 bias_level = SND_JACK_BTN_0; 1302 dev_dbg(cs42l42->component->dev, "Function A button press\n"); 1303 break; 1304 default: 1305 bias_level = 0; 1306 break; 1307 } 1308 1309 /* Set button detect level sensitivity back to default */ 1310 regmap_update_bits(cs42l42->regmap, 1311 CS42L42_MIC_DET_CTL1, 1312 CS42L42_LATCH_TO_VP_MASK | 1313 CS42L42_EVENT_STAT_SEL_MASK | 1314 CS42L42_HS_DET_LEVEL_MASK, 1315 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1316 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1317 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1318 1319 /* Clear any button interrupts before unmasking them */ 1320 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1321 &detect_status); 1322 1323 /* Unmask button detect interrupts */ 1324 regmap_update_bits(cs42l42->regmap, 1325 CS42L42_DET_INT2_MASK, 1326 CS42L42_M_DETECT_TF_MASK | 1327 CS42L42_M_DETECT_FT_MASK | 1328 CS42L42_M_HSBIAS_HIZ_MASK | 1329 CS42L42_M_SHORT_RLS_MASK | 1330 CS42L42_M_SHORT_DET_MASK, 1331 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1332 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1333 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1334 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1335 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1336 1337 return bias_level; 1338 } 1339 1340 struct cs42l42_irq_params { 1341 u16 status_addr; 1342 u16 mask_addr; 1343 u8 mask; 1344 }; 1345 1346 static const struct cs42l42_irq_params irq_params_table[] = { 1347 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1348 CS42L42_ADC_OVFL_VAL_MASK}, 1349 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1350 CS42L42_MIXER_VAL_MASK}, 1351 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1352 CS42L42_SRC_VAL_MASK}, 1353 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1354 CS42L42_ASP_RX_VAL_MASK}, 1355 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1356 CS42L42_ASP_TX_VAL_MASK}, 1357 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1358 CS42L42_CODEC_VAL_MASK}, 1359 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1360 CS42L42_DET_INT_VAL1_MASK}, 1361 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1362 CS42L42_DET_INT_VAL2_MASK}, 1363 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1364 CS42L42_SRCPL_VAL_MASK}, 1365 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1366 CS42L42_VPMON_VAL_MASK}, 1367 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1368 CS42L42_PLL_LOCK_VAL_MASK}, 1369 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1370 CS42L42_TSRS_PLUG_VAL_MASK} 1371 }; 1372 1373 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1374 { 1375 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1376 struct snd_soc_component *component = cs42l42->component; 1377 unsigned int stickies[12]; 1378 unsigned int masks[12]; 1379 unsigned int current_plug_status; 1380 unsigned int current_button_status; 1381 unsigned int i; 1382 int report = 0; 1383 1384 1385 /* Read sticky registers to clear interurpt */ 1386 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1387 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1388 &(stickies[i])); 1389 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1390 &(masks[i])); 1391 stickies[i] = stickies[i] & (~masks[i]) & 1392 irq_params_table[i].mask; 1393 } 1394 1395 /* Read tip sense status before handling type detect */ 1396 current_plug_status = (stickies[11] & 1397 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1398 CS42L42_TS_PLUG_SHIFT; 1399 1400 /* Read button sense status */ 1401 current_button_status = stickies[7] & 1402 (CS42L42_M_DETECT_TF_MASK | 1403 CS42L42_M_DETECT_FT_MASK | 1404 CS42L42_M_HSBIAS_HIZ_MASK); 1405 1406 /* Check auto-detect status */ 1407 if ((~masks[5]) & irq_params_table[5].mask) { 1408 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1409 cs42l42_process_hs_type_detect(cs42l42); 1410 switch(cs42l42->hs_type){ 1411 case CS42L42_PLUG_CTIA: 1412 case CS42L42_PLUG_OMTP: 1413 snd_soc_jack_report(&cs42l42->jack, SND_JACK_HEADSET, 1414 SND_JACK_HEADSET); 1415 break; 1416 case CS42L42_PLUG_HEADPHONE: 1417 snd_soc_jack_report(&cs42l42->jack, SND_JACK_HEADPHONE, 1418 SND_JACK_HEADPHONE); 1419 break; 1420 default: 1421 break; 1422 } 1423 dev_dbg(component->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1424 } 1425 } 1426 1427 /* Check tip sense status */ 1428 if ((~masks[11]) & irq_params_table[11].mask) { 1429 switch (current_plug_status) { 1430 case CS42L42_TS_PLUG: 1431 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1432 cs42l42->plug_state = CS42L42_TS_PLUG; 1433 cs42l42_init_hs_type_detect(cs42l42); 1434 } 1435 break; 1436 1437 case CS42L42_TS_UNPLUG: 1438 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1439 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1440 cs42l42_cancel_hs_type_detect(cs42l42); 1441 1442 switch(cs42l42->hs_type){ 1443 case CS42L42_PLUG_CTIA: 1444 case CS42L42_PLUG_OMTP: 1445 snd_soc_jack_report(&cs42l42->jack, 0, SND_JACK_HEADSET); 1446 break; 1447 case CS42L42_PLUG_HEADPHONE: 1448 snd_soc_jack_report(&cs42l42->jack, 0, SND_JACK_HEADPHONE); 1449 break; 1450 default: 1451 break; 1452 } 1453 dev_dbg(component->dev, "Unplug event\n"); 1454 } 1455 break; 1456 1457 default: 1458 if (cs42l42->plug_state != CS42L42_TS_TRANS) 1459 cs42l42->plug_state = CS42L42_TS_TRANS; 1460 } 1461 } 1462 1463 /* Check button detect status */ 1464 if ((~masks[7]) & irq_params_table[7].mask) { 1465 if (!(current_button_status & 1466 CS42L42_M_HSBIAS_HIZ_MASK)) { 1467 1468 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1469 dev_dbg(component->dev, "Button released\n"); 1470 report = 0; 1471 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1472 report = cs42l42_handle_button_press(cs42l42); 1473 1474 } 1475 snd_soc_jack_report(&cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1476 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1477 } 1478 } 1479 1480 return IRQ_HANDLED; 1481 } 1482 1483 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1484 { 1485 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1486 CS42L42_ADC_OVFL_MASK, 1487 (1 << CS42L42_ADC_OVFL_SHIFT)); 1488 1489 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1490 CS42L42_MIX_CHB_OVFL_MASK | 1491 CS42L42_MIX_CHA_OVFL_MASK | 1492 CS42L42_EQ_OVFL_MASK | 1493 CS42L42_EQ_BIQUAD_OVFL_MASK, 1494 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1495 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1496 (1 << CS42L42_EQ_OVFL_SHIFT) | 1497 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1498 1499 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1500 CS42L42_SRC_ILK_MASK | 1501 CS42L42_SRC_OLK_MASK | 1502 CS42L42_SRC_IUNLK_MASK | 1503 CS42L42_SRC_OUNLK_MASK, 1504 (1 << CS42L42_SRC_ILK_SHIFT) | 1505 (1 << CS42L42_SRC_OLK_SHIFT) | 1506 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1507 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1508 1509 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1510 CS42L42_ASPRX_NOLRCK_MASK | 1511 CS42L42_ASPRX_EARLY_MASK | 1512 CS42L42_ASPRX_LATE_MASK | 1513 CS42L42_ASPRX_ERROR_MASK | 1514 CS42L42_ASPRX_OVLD_MASK, 1515 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1516 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1517 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1518 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1519 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1520 1521 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1522 CS42L42_ASPTX_NOLRCK_MASK | 1523 CS42L42_ASPTX_EARLY_MASK | 1524 CS42L42_ASPTX_LATE_MASK | 1525 CS42L42_ASPTX_SMERROR_MASK, 1526 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1527 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1528 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1529 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1530 1531 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1532 CS42L42_PDN_DONE_MASK | 1533 CS42L42_HSDET_AUTO_DONE_MASK, 1534 (1 << CS42L42_PDN_DONE_SHIFT) | 1535 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1536 1537 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1538 CS42L42_SRCPL_ADC_LK_MASK | 1539 CS42L42_SRCPL_DAC_LK_MASK | 1540 CS42L42_SRCPL_ADC_UNLK_MASK | 1541 CS42L42_SRCPL_DAC_UNLK_MASK, 1542 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1543 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1544 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1545 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1546 1547 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1548 CS42L42_TIP_SENSE_UNPLUG_MASK | 1549 CS42L42_TIP_SENSE_PLUG_MASK | 1550 CS42L42_HSBIAS_SENSE_MASK, 1551 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1552 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1553 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1554 1555 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1556 CS42L42_M_DETECT_TF_MASK | 1557 CS42L42_M_DETECT_FT_MASK | 1558 CS42L42_M_HSBIAS_HIZ_MASK | 1559 CS42L42_M_SHORT_RLS_MASK | 1560 CS42L42_M_SHORT_DET_MASK, 1561 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1562 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1563 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1564 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1565 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1566 1567 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1568 CS42L42_VPMON_MASK, 1569 (1 << CS42L42_VPMON_SHIFT)); 1570 1571 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1572 CS42L42_PLL_LOCK_MASK, 1573 (1 << CS42L42_PLL_LOCK_SHIFT)); 1574 1575 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1576 CS42L42_RS_PLUG_MASK | 1577 CS42L42_RS_UNPLUG_MASK | 1578 CS42L42_TS_PLUG_MASK | 1579 CS42L42_TS_UNPLUG_MASK, 1580 (1 << CS42L42_RS_PLUG_SHIFT) | 1581 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1582 (0 << CS42L42_TS_PLUG_SHIFT) | 1583 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1584 } 1585 1586 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1587 { 1588 unsigned int reg; 1589 1590 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1591 1592 /* Latch analog controls to VP power domain */ 1593 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1594 CS42L42_LATCH_TO_VP_MASK | 1595 CS42L42_EVENT_STAT_SEL_MASK | 1596 CS42L42_HS_DET_LEVEL_MASK, 1597 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1598 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1599 (cs42l42->bias_thresholds[0] << 1600 CS42L42_HS_DET_LEVEL_SHIFT)); 1601 1602 /* Remove ground noise-suppression clamps */ 1603 regmap_update_bits(cs42l42->regmap, 1604 CS42L42_HS_CLAMP_DISABLE, 1605 CS42L42_HS_CLAMP_DISABLE_MASK, 1606 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1607 1608 /* Enable the tip sense circuit */ 1609 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1610 CS42L42_TIP_SENSE_CTRL_MASK | 1611 CS42L42_TIP_SENSE_INV_MASK | 1612 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1613 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1614 (0 << CS42L42_TIP_SENSE_INV_SHIFT) | 1615 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1616 1617 /* Save the initial status of the tip sense */ 1618 regmap_read(cs42l42->regmap, 1619 CS42L42_TSRS_PLUG_STATUS, 1620 ®); 1621 cs42l42->plug_state = (((char) reg) & 1622 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1623 CS42L42_TS_PLUG_SHIFT; 1624 } 1625 1626 static const unsigned int threshold_defaults[] = { 1627 CS42L42_HS_DET_LEVEL_15, 1628 CS42L42_HS_DET_LEVEL_8, 1629 CS42L42_HS_DET_LEVEL_4, 1630 CS42L42_HS_DET_LEVEL_1 1631 }; 1632 1633 static int cs42l42_handle_device_data(struct i2c_client *i2c_client, 1634 struct cs42l42_private *cs42l42) 1635 { 1636 struct device_node *np = i2c_client->dev.of_node; 1637 unsigned int val; 1638 unsigned int thresholds[CS42L42_NUM_BIASES]; 1639 int ret; 1640 int i; 1641 1642 ret = of_property_read_u32(np, "cirrus,ts-inv", &val); 1643 1644 if (!ret) { 1645 switch (val) { 1646 case CS42L42_TS_INV_EN: 1647 case CS42L42_TS_INV_DIS: 1648 cs42l42->ts_inv = val; 1649 break; 1650 default: 1651 dev_err(&i2c_client->dev, 1652 "Wrong cirrus,ts-inv DT value %d\n", 1653 val); 1654 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1655 } 1656 } else { 1657 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1658 } 1659 1660 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1661 CS42L42_TS_INV_MASK, 1662 (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT)); 1663 1664 ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val); 1665 1666 if (!ret) { 1667 switch (val) { 1668 case CS42L42_TS_DBNCE_0: 1669 case CS42L42_TS_DBNCE_125: 1670 case CS42L42_TS_DBNCE_250: 1671 case CS42L42_TS_DBNCE_500: 1672 case CS42L42_TS_DBNCE_750: 1673 case CS42L42_TS_DBNCE_1000: 1674 case CS42L42_TS_DBNCE_1250: 1675 case CS42L42_TS_DBNCE_1500: 1676 cs42l42->ts_dbnc_rise = val; 1677 break; 1678 default: 1679 dev_err(&i2c_client->dev, 1680 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1681 val); 1682 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1683 } 1684 } else { 1685 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1686 } 1687 1688 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1689 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1690 (cs42l42->ts_dbnc_rise << 1691 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1692 1693 ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val); 1694 1695 if (!ret) { 1696 switch (val) { 1697 case CS42L42_TS_DBNCE_0: 1698 case CS42L42_TS_DBNCE_125: 1699 case CS42L42_TS_DBNCE_250: 1700 case CS42L42_TS_DBNCE_500: 1701 case CS42L42_TS_DBNCE_750: 1702 case CS42L42_TS_DBNCE_1000: 1703 case CS42L42_TS_DBNCE_1250: 1704 case CS42L42_TS_DBNCE_1500: 1705 cs42l42->ts_dbnc_fall = val; 1706 break; 1707 default: 1708 dev_err(&i2c_client->dev, 1709 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1710 val); 1711 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1712 } 1713 } else { 1714 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1715 } 1716 1717 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1718 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1719 (cs42l42->ts_dbnc_fall << 1720 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1721 1722 ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val); 1723 1724 if (!ret) { 1725 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1726 cs42l42->btn_det_init_dbnce = val; 1727 else { 1728 dev_err(&i2c_client->dev, 1729 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1730 val); 1731 cs42l42->btn_det_init_dbnce = 1732 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1733 } 1734 } else { 1735 cs42l42->btn_det_init_dbnce = 1736 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1737 } 1738 1739 ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val); 1740 1741 if (!ret) { 1742 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 1743 cs42l42->btn_det_event_dbnce = val; 1744 else { 1745 dev_err(&i2c_client->dev, 1746 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 1747 cs42l42->btn_det_event_dbnce = 1748 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1749 } 1750 } else { 1751 cs42l42->btn_det_event_dbnce = 1752 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1753 } 1754 1755 ret = of_property_read_u32_array(np, "cirrus,bias-lvls", 1756 (u32 *)thresholds, CS42L42_NUM_BIASES); 1757 1758 if (!ret) { 1759 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 1760 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 1761 cs42l42->bias_thresholds[i] = thresholds[i]; 1762 else { 1763 dev_err(&i2c_client->dev, 1764 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 1765 thresholds[i]); 1766 cs42l42->bias_thresholds[i] = 1767 threshold_defaults[i]; 1768 } 1769 } 1770 } else { 1771 for (i = 0; i < CS42L42_NUM_BIASES; i++) 1772 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1773 } 1774 1775 ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val); 1776 1777 if (!ret) { 1778 switch (val) { 1779 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 1780 cs42l42->hs_bias_ramp_rate = val; 1781 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 1782 break; 1783 case CS42L42_HSBIAS_RAMP_FAST: 1784 cs42l42->hs_bias_ramp_rate = val; 1785 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 1786 break; 1787 case CS42L42_HSBIAS_RAMP_SLOW: 1788 cs42l42->hs_bias_ramp_rate = val; 1789 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1790 break; 1791 case CS42L42_HSBIAS_RAMP_SLOWEST: 1792 cs42l42->hs_bias_ramp_rate = val; 1793 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 1794 break; 1795 default: 1796 dev_err(&i2c_client->dev, 1797 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 1798 val); 1799 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1800 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1801 } 1802 } else { 1803 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1804 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1805 } 1806 1807 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 1808 CS42L42_HSBIAS_RAMP_MASK, 1809 (cs42l42->hs_bias_ramp_rate << 1810 CS42L42_HSBIAS_RAMP_SHIFT)); 1811 1812 return 0; 1813 } 1814 1815 static int cs42l42_i2c_probe(struct i2c_client *i2c_client, 1816 const struct i2c_device_id *id) 1817 { 1818 struct cs42l42_private *cs42l42; 1819 int ret, i; 1820 unsigned int devid = 0; 1821 unsigned int reg; 1822 1823 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private), 1824 GFP_KERNEL); 1825 if (!cs42l42) 1826 return -ENOMEM; 1827 1828 i2c_set_clientdata(i2c_client, cs42l42); 1829 1830 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap); 1831 if (IS_ERR(cs42l42->regmap)) { 1832 ret = PTR_ERR(cs42l42->regmap); 1833 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1834 return ret; 1835 } 1836 1837 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 1838 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 1839 1840 ret = devm_regulator_bulk_get(&i2c_client->dev, 1841 ARRAY_SIZE(cs42l42->supplies), 1842 cs42l42->supplies); 1843 if (ret != 0) { 1844 dev_err(&i2c_client->dev, 1845 "Failed to request supplies: %d\n", ret); 1846 return ret; 1847 } 1848 1849 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1850 cs42l42->supplies); 1851 if (ret != 0) { 1852 dev_err(&i2c_client->dev, 1853 "Failed to enable supplies: %d\n", ret); 1854 return ret; 1855 } 1856 1857 /* Reset the Device */ 1858 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 1859 "reset", GPIOD_OUT_LOW); 1860 if (IS_ERR(cs42l42->reset_gpio)) { 1861 ret = PTR_ERR(cs42l42->reset_gpio); 1862 goto err_disable; 1863 } 1864 1865 if (cs42l42->reset_gpio) { 1866 dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); 1867 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1868 } 1869 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 1870 1871 /* Request IRQ */ 1872 ret = devm_request_threaded_irq(&i2c_client->dev, 1873 i2c_client->irq, 1874 NULL, cs42l42_irq_thread, 1875 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 1876 "cs42l42", cs42l42); 1877 1878 if (ret != 0) 1879 dev_err(&i2c_client->dev, 1880 "Failed to request IRQ: %d\n", ret); 1881 1882 /* initialize codec */ 1883 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, ®); 1884 devid = (reg & 0xFF) << 12; 1885 1886 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, ®); 1887 devid |= (reg & 0xFF) << 4; 1888 1889 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, ®); 1890 devid |= (reg & 0xF0) >> 4; 1891 1892 if (devid != CS42L42_CHIP_ID) { 1893 ret = -ENODEV; 1894 dev_err(&i2c_client->dev, 1895 "CS42L42 Device ID (%X). Expected %X\n", 1896 devid, CS42L42_CHIP_ID); 1897 goto err_disable; 1898 } 1899 1900 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 1901 if (ret < 0) { 1902 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1903 goto err_disable; 1904 } 1905 1906 dev_info(&i2c_client->dev, 1907 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); 1908 1909 /* Power up the codec */ 1910 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 1911 CS42L42_ASP_DAO_PDN_MASK | 1912 CS42L42_ASP_DAI_PDN_MASK | 1913 CS42L42_MIXER_PDN_MASK | 1914 CS42L42_EQ_PDN_MASK | 1915 CS42L42_HP_PDN_MASK | 1916 CS42L42_ADC_PDN_MASK | 1917 CS42L42_PDN_ALL_MASK, 1918 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 1919 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 1920 (1 << CS42L42_MIXER_PDN_SHIFT) | 1921 (1 << CS42L42_EQ_PDN_SHIFT) | 1922 (1 << CS42L42_HP_PDN_SHIFT) | 1923 (1 << CS42L42_ADC_PDN_SHIFT) | 1924 (0 << CS42L42_PDN_ALL_SHIFT)); 1925 1926 if (i2c_client->dev.of_node) { 1927 ret = cs42l42_handle_device_data(i2c_client, cs42l42); 1928 if (ret != 0) 1929 goto err_disable; 1930 } 1931 1932 /* Setup headset detection */ 1933 cs42l42_setup_hs_type_detect(cs42l42); 1934 1935 /* Mask/Unmask Interrupts */ 1936 cs42l42_set_interrupt_masks(cs42l42); 1937 1938 /* Register codec for machine driver */ 1939 ret = devm_snd_soc_register_component(&i2c_client->dev, 1940 &soc_component_dev_cs42l42, &cs42l42_dai, 1); 1941 if (ret < 0) 1942 goto err_disable; 1943 return 0; 1944 1945 err_disable: 1946 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1947 cs42l42->supplies); 1948 return ret; 1949 } 1950 1951 static int cs42l42_i2c_remove(struct i2c_client *i2c_client) 1952 { 1953 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client); 1954 1955 devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42); 1956 pm_runtime_suspend(&i2c_client->dev); 1957 pm_runtime_disable(&i2c_client->dev); 1958 1959 return 0; 1960 } 1961 1962 #ifdef CONFIG_PM 1963 static int cs42l42_runtime_suspend(struct device *dev) 1964 { 1965 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1966 1967 regcache_cache_only(cs42l42->regmap, true); 1968 regcache_mark_dirty(cs42l42->regmap); 1969 1970 /* Hold down reset */ 1971 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 1972 1973 /* remove power */ 1974 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1975 cs42l42->supplies); 1976 1977 return 0; 1978 } 1979 1980 static int cs42l42_runtime_resume(struct device *dev) 1981 { 1982 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1983 int ret; 1984 1985 /* Enable power */ 1986 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1987 cs42l42->supplies); 1988 if (ret != 0) { 1989 dev_err(dev, "Failed to enable supplies: %d\n", 1990 ret); 1991 return ret; 1992 } 1993 1994 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1995 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 1996 1997 regcache_cache_only(cs42l42->regmap, false); 1998 regcache_sync(cs42l42->regmap); 1999 2000 return 0; 2001 } 2002 #endif 2003 2004 static const struct dev_pm_ops cs42l42_runtime_pm = { 2005 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume, 2006 NULL) 2007 }; 2008 2009 static const struct of_device_id cs42l42_of_match[] = { 2010 { .compatible = "cirrus,cs42l42", }, 2011 {}, 2012 }; 2013 MODULE_DEVICE_TABLE(of, cs42l42_of_match); 2014 2015 2016 static const struct i2c_device_id cs42l42_id[] = { 2017 {"cs42l42", 0}, 2018 {} 2019 }; 2020 2021 MODULE_DEVICE_TABLE(i2c, cs42l42_id); 2022 2023 static struct i2c_driver cs42l42_i2c_driver = { 2024 .driver = { 2025 .name = "cs42l42", 2026 .pm = &cs42l42_runtime_pm, 2027 .of_match_table = cs42l42_of_match, 2028 }, 2029 .id_table = cs42l42_id, 2030 .probe = cs42l42_i2c_probe, 2031 .remove = cs42l42_i2c_remove, 2032 }; 2033 2034 module_i2c_driver(cs42l42_i2c_driver); 2035 2036 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2037 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2038 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2039 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2040 MODULE_LICENSE("GPL"); 2041