1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/i2c.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/acpi.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/of_device.h> 28 #include <sound/core.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 #include <sound/soc-dapm.h> 33 #include <sound/initval.h> 34 #include <sound/tlv.h> 35 #include <dt-bindings/sound/cs42l42.h> 36 37 #include "cs42l42.h" 38 #include "cirrus_legacy.h" 39 40 static const struct reg_default cs42l42_reg_defaults[] = { 41 { CS42L42_FRZ_CTL, 0x00 }, 42 { CS42L42_SRC_CTL, 0x10 }, 43 { CS42L42_MCLK_CTL, 0x02 }, 44 { CS42L42_SFTRAMP_RATE, 0xA4 }, 45 { CS42L42_I2C_DEBOUNCE, 0x88 }, 46 { CS42L42_I2C_STRETCH, 0x03 }, 47 { CS42L42_I2C_TIMEOUT, 0xB7 }, 48 { CS42L42_PWR_CTL1, 0xFF }, 49 { CS42L42_PWR_CTL2, 0x84 }, 50 { CS42L42_PWR_CTL3, 0x20 }, 51 { CS42L42_RSENSE_CTL1, 0x40 }, 52 { CS42L42_RSENSE_CTL2, 0x00 }, 53 { CS42L42_OSC_SWITCH, 0x00 }, 54 { CS42L42_RSENSE_CTL3, 0x1B }, 55 { CS42L42_TSENSE_CTL, 0x1B }, 56 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 57 { CS42L42_HSDET_CTL1, 0x77 }, 58 { CS42L42_HSDET_CTL2, 0x00 }, 59 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 60 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 61 { CS42L42_MCLK_SRC_SEL, 0x00 }, 62 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 63 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 64 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 65 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 66 { CS42L42_FSYNC_P_UPPER, 0x00 }, 67 { CS42L42_ASP_CLK_CFG, 0x00 }, 68 { CS42L42_ASP_FRM_CFG, 0x10 }, 69 { CS42L42_FS_RATE_EN, 0x00 }, 70 { CS42L42_IN_ASRC_CLK, 0x00 }, 71 { CS42L42_OUT_ASRC_CLK, 0x00 }, 72 { CS42L42_PLL_DIV_CFG1, 0x00 }, 73 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 74 { CS42L42_MIXER_INT_MASK, 0x0F }, 75 { CS42L42_SRC_INT_MASK, 0x0F }, 76 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 77 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 78 { CS42L42_CODEC_INT_MASK, 0x03 }, 79 { CS42L42_SRCPL_INT_MASK, 0x7F }, 80 { CS42L42_VPMON_INT_MASK, 0x01 }, 81 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 82 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 83 { CS42L42_PLL_CTL1, 0x00 }, 84 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 85 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 86 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 87 { CS42L42_PLL_DIV_INT, 0x40 }, 88 { CS42L42_PLL_CTL3, 0x10 }, 89 { CS42L42_PLL_CAL_RATIO, 0x80 }, 90 { CS42L42_PLL_CTL4, 0x03 }, 91 { CS42L42_LOAD_DET_EN, 0x00 }, 92 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 93 { CS42L42_WAKE_CTL, 0xC0 }, 94 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 95 { CS42L42_TIPSENSE_CTL, 0x02 }, 96 { CS42L42_MISC_DET_CTL, 0x03 }, 97 { CS42L42_MIC_DET_CTL1, 0x1F }, 98 { CS42L42_MIC_DET_CTL2, 0x2F }, 99 { CS42L42_DET_INT1_MASK, 0xE0 }, 100 { CS42L42_DET_INT2_MASK, 0xFF }, 101 { CS42L42_HS_BIAS_CTL, 0xC2 }, 102 { CS42L42_ADC_CTL, 0x00 }, 103 { CS42L42_ADC_VOLUME, 0x00 }, 104 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 105 { CS42L42_DAC_CTL1, 0x00 }, 106 { CS42L42_DAC_CTL2, 0x02 }, 107 { CS42L42_HP_CTL, 0x0D }, 108 { CS42L42_CLASSH_CTL, 0x07 }, 109 { CS42L42_MIXER_CHA_VOL, 0x3F }, 110 { CS42L42_MIXER_ADC_VOL, 0x3F }, 111 { CS42L42_MIXER_CHB_VOL, 0x3F }, 112 { CS42L42_EQ_COEF_IN0, 0x00 }, 113 { CS42L42_EQ_COEF_IN1, 0x00 }, 114 { CS42L42_EQ_COEF_IN2, 0x00 }, 115 { CS42L42_EQ_COEF_IN3, 0x00 }, 116 { CS42L42_EQ_COEF_RW, 0x00 }, 117 { CS42L42_EQ_COEF_OUT0, 0x00 }, 118 { CS42L42_EQ_COEF_OUT1, 0x00 }, 119 { CS42L42_EQ_COEF_OUT2, 0x00 }, 120 { CS42L42_EQ_COEF_OUT3, 0x00 }, 121 { CS42L42_EQ_INIT_STAT, 0x00 }, 122 { CS42L42_EQ_START_FILT, 0x00 }, 123 { CS42L42_EQ_MUTE_CTL, 0x00 }, 124 { CS42L42_SP_RX_CH_SEL, 0x04 }, 125 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 126 { CS42L42_SP_RX_FS, 0x8C }, 127 { CS42l42_SPDIF_CH_SEL, 0x0E }, 128 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 129 { CS42L42_SP_TX_FS, 0xCC }, 130 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 131 { CS42L42_SRC_SDIN_FS, 0x40 }, 132 { CS42L42_SRC_SDOUT_FS, 0x40 }, 133 { CS42L42_SPDIF_CTL1, 0x01 }, 134 { CS42L42_SPDIF_CTL2, 0x00 }, 135 { CS42L42_SPDIF_CTL3, 0x00 }, 136 { CS42L42_SPDIF_CTL4, 0x42 }, 137 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 138 { CS42L42_ASP_TX_CH_EN, 0x00 }, 139 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 140 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 141 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 142 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 143 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 144 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 145 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 146 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 147 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 148 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 149 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 150 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 151 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 152 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 153 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 154 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 155 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 156 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 157 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 158 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 159 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 160 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 161 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 162 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 163 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 164 }; 165 166 static bool cs42l42_readable_register(struct device *dev, unsigned int reg) 167 { 168 switch (reg) { 169 case CS42L42_PAGE_REGISTER: 170 case CS42L42_DEVID_AB: 171 case CS42L42_DEVID_CD: 172 case CS42L42_DEVID_E: 173 case CS42L42_FABID: 174 case CS42L42_REVID: 175 case CS42L42_FRZ_CTL: 176 case CS42L42_SRC_CTL: 177 case CS42L42_MCLK_STATUS: 178 case CS42L42_MCLK_CTL: 179 case CS42L42_SFTRAMP_RATE: 180 case CS42L42_I2C_DEBOUNCE: 181 case CS42L42_I2C_STRETCH: 182 case CS42L42_I2C_TIMEOUT: 183 case CS42L42_PWR_CTL1: 184 case CS42L42_PWR_CTL2: 185 case CS42L42_PWR_CTL3: 186 case CS42L42_RSENSE_CTL1: 187 case CS42L42_RSENSE_CTL2: 188 case CS42L42_OSC_SWITCH: 189 case CS42L42_OSC_SWITCH_STATUS: 190 case CS42L42_RSENSE_CTL3: 191 case CS42L42_TSENSE_CTL: 192 case CS42L42_TSRS_INT_DISABLE: 193 case CS42L42_TRSENSE_STATUS: 194 case CS42L42_HSDET_CTL1: 195 case CS42L42_HSDET_CTL2: 196 case CS42L42_HS_SWITCH_CTL: 197 case CS42L42_HS_DET_STATUS: 198 case CS42L42_HS_CLAMP_DISABLE: 199 case CS42L42_MCLK_SRC_SEL: 200 case CS42L42_SPDIF_CLK_CFG: 201 case CS42L42_FSYNC_PW_LOWER: 202 case CS42L42_FSYNC_PW_UPPER: 203 case CS42L42_FSYNC_P_LOWER: 204 case CS42L42_FSYNC_P_UPPER: 205 case CS42L42_ASP_CLK_CFG: 206 case CS42L42_ASP_FRM_CFG: 207 case CS42L42_FS_RATE_EN: 208 case CS42L42_IN_ASRC_CLK: 209 case CS42L42_OUT_ASRC_CLK: 210 case CS42L42_PLL_DIV_CFG1: 211 case CS42L42_ADC_OVFL_STATUS: 212 case CS42L42_MIXER_STATUS: 213 case CS42L42_SRC_STATUS: 214 case CS42L42_ASP_RX_STATUS: 215 case CS42L42_ASP_TX_STATUS: 216 case CS42L42_CODEC_STATUS: 217 case CS42L42_DET_INT_STATUS1: 218 case CS42L42_DET_INT_STATUS2: 219 case CS42L42_SRCPL_INT_STATUS: 220 case CS42L42_VPMON_STATUS: 221 case CS42L42_PLL_LOCK_STATUS: 222 case CS42L42_TSRS_PLUG_STATUS: 223 case CS42L42_ADC_OVFL_INT_MASK: 224 case CS42L42_MIXER_INT_MASK: 225 case CS42L42_SRC_INT_MASK: 226 case CS42L42_ASP_RX_INT_MASK: 227 case CS42L42_ASP_TX_INT_MASK: 228 case CS42L42_CODEC_INT_MASK: 229 case CS42L42_SRCPL_INT_MASK: 230 case CS42L42_VPMON_INT_MASK: 231 case CS42L42_PLL_LOCK_INT_MASK: 232 case CS42L42_TSRS_PLUG_INT_MASK: 233 case CS42L42_PLL_CTL1: 234 case CS42L42_PLL_DIV_FRAC0: 235 case CS42L42_PLL_DIV_FRAC1: 236 case CS42L42_PLL_DIV_FRAC2: 237 case CS42L42_PLL_DIV_INT: 238 case CS42L42_PLL_CTL3: 239 case CS42L42_PLL_CAL_RATIO: 240 case CS42L42_PLL_CTL4: 241 case CS42L42_LOAD_DET_RCSTAT: 242 case CS42L42_LOAD_DET_DONE: 243 case CS42L42_LOAD_DET_EN: 244 case CS42L42_HSBIAS_SC_AUTOCTL: 245 case CS42L42_WAKE_CTL: 246 case CS42L42_ADC_DISABLE_MUTE: 247 case CS42L42_TIPSENSE_CTL: 248 case CS42L42_MISC_DET_CTL: 249 case CS42L42_MIC_DET_CTL1: 250 case CS42L42_MIC_DET_CTL2: 251 case CS42L42_DET_STATUS1: 252 case CS42L42_DET_STATUS2: 253 case CS42L42_DET_INT1_MASK: 254 case CS42L42_DET_INT2_MASK: 255 case CS42L42_HS_BIAS_CTL: 256 case CS42L42_ADC_CTL: 257 case CS42L42_ADC_VOLUME: 258 case CS42L42_ADC_WNF_HPF_CTL: 259 case CS42L42_DAC_CTL1: 260 case CS42L42_DAC_CTL2: 261 case CS42L42_HP_CTL: 262 case CS42L42_CLASSH_CTL: 263 case CS42L42_MIXER_CHA_VOL: 264 case CS42L42_MIXER_ADC_VOL: 265 case CS42L42_MIXER_CHB_VOL: 266 case CS42L42_EQ_COEF_IN0: 267 case CS42L42_EQ_COEF_IN1: 268 case CS42L42_EQ_COEF_IN2: 269 case CS42L42_EQ_COEF_IN3: 270 case CS42L42_EQ_COEF_RW: 271 case CS42L42_EQ_COEF_OUT0: 272 case CS42L42_EQ_COEF_OUT1: 273 case CS42L42_EQ_COEF_OUT2: 274 case CS42L42_EQ_COEF_OUT3: 275 case CS42L42_EQ_INIT_STAT: 276 case CS42L42_EQ_START_FILT: 277 case CS42L42_EQ_MUTE_CTL: 278 case CS42L42_SP_RX_CH_SEL: 279 case CS42L42_SP_RX_ISOC_CTL: 280 case CS42L42_SP_RX_FS: 281 case CS42l42_SPDIF_CH_SEL: 282 case CS42L42_SP_TX_ISOC_CTL: 283 case CS42L42_SP_TX_FS: 284 case CS42L42_SPDIF_SW_CTL1: 285 case CS42L42_SRC_SDIN_FS: 286 case CS42L42_SRC_SDOUT_FS: 287 case CS42L42_SPDIF_CTL1: 288 case CS42L42_SPDIF_CTL2: 289 case CS42L42_SPDIF_CTL3: 290 case CS42L42_SPDIF_CTL4: 291 case CS42L42_ASP_TX_SZ_EN: 292 case CS42L42_ASP_TX_CH_EN: 293 case CS42L42_ASP_TX_CH_AP_RES: 294 case CS42L42_ASP_TX_CH1_BIT_MSB: 295 case CS42L42_ASP_TX_CH1_BIT_LSB: 296 case CS42L42_ASP_TX_HIZ_DLY_CFG: 297 case CS42L42_ASP_TX_CH2_BIT_MSB: 298 case CS42L42_ASP_TX_CH2_BIT_LSB: 299 case CS42L42_ASP_RX_DAI0_EN: 300 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 301 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 302 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 303 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 304 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 305 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 306 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 307 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 308 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 309 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 310 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 311 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 312 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 313 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 314 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 315 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 316 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 317 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 318 case CS42L42_SUB_REVID: 319 return true; 320 default: 321 return false; 322 } 323 } 324 325 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 326 { 327 switch (reg) { 328 case CS42L42_DEVID_AB: 329 case CS42L42_DEVID_CD: 330 case CS42L42_DEVID_E: 331 case CS42L42_MCLK_STATUS: 332 case CS42L42_OSC_SWITCH_STATUS: 333 case CS42L42_TRSENSE_STATUS: 334 case CS42L42_HS_DET_STATUS: 335 case CS42L42_ADC_OVFL_STATUS: 336 case CS42L42_MIXER_STATUS: 337 case CS42L42_SRC_STATUS: 338 case CS42L42_ASP_RX_STATUS: 339 case CS42L42_ASP_TX_STATUS: 340 case CS42L42_CODEC_STATUS: 341 case CS42L42_DET_INT_STATUS1: 342 case CS42L42_DET_INT_STATUS2: 343 case CS42L42_SRCPL_INT_STATUS: 344 case CS42L42_VPMON_STATUS: 345 case CS42L42_PLL_LOCK_STATUS: 346 case CS42L42_TSRS_PLUG_STATUS: 347 case CS42L42_LOAD_DET_RCSTAT: 348 case CS42L42_LOAD_DET_DONE: 349 case CS42L42_DET_STATUS1: 350 case CS42L42_DET_STATUS2: 351 return true; 352 default: 353 return false; 354 } 355 } 356 357 static const struct regmap_range_cfg cs42l42_page_range = { 358 .name = "Pages", 359 .range_min = 0, 360 .range_max = CS42L42_MAX_REGISTER, 361 .selector_reg = CS42L42_PAGE_REGISTER, 362 .selector_mask = 0xff, 363 .selector_shift = 0, 364 .window_start = 0, 365 .window_len = 256, 366 }; 367 368 static const struct regmap_config cs42l42_regmap = { 369 .reg_bits = 8, 370 .val_bits = 8, 371 372 .readable_reg = cs42l42_readable_register, 373 .volatile_reg = cs42l42_volatile_register, 374 375 .ranges = &cs42l42_page_range, 376 .num_ranges = 1, 377 378 .max_register = CS42L42_MAX_REGISTER, 379 .reg_defaults = cs42l42_reg_defaults, 380 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 381 .cache_type = REGCACHE_RBTREE, 382 383 .use_single_read = true, 384 .use_single_write = true, 385 }; 386 387 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true); 388 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 389 390 static const char * const cs42l42_hpf_freq_text[] = { 391 "1.86Hz", "120Hz", "235Hz", "466Hz" 392 }; 393 394 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 395 CS42L42_ADC_HPF_CF_SHIFT, 396 cs42l42_hpf_freq_text); 397 398 static const char * const cs42l42_wnf3_freq_text[] = { 399 "160Hz", "180Hz", "200Hz", "220Hz", 400 "240Hz", "260Hz", "280Hz", "300Hz" 401 }; 402 403 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 404 CS42L42_ADC_WNF_CF_SHIFT, 405 cs42l42_wnf3_freq_text); 406 407 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 408 /* ADC Volume and Filter Controls */ 409 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 410 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true), 411 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 412 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 413 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 414 CS42L42_ADC_INV_SHIFT, true, false), 415 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 416 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 417 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv), 418 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 419 CS42L42_ADC_WNF_EN_SHIFT, true, false), 420 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 421 CS42L42_ADC_HPF_EN_SHIFT, true, false), 422 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 423 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 424 425 /* DAC Volume and Filter Controls */ 426 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 427 CS42L42_DACA_INV_SHIFT, true, false), 428 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 429 CS42L42_DACB_INV_SHIFT, true, false), 430 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 431 CS42L42_DAC_HPF_EN_SHIFT, true, false), 432 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 433 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 434 0x3f, 1, mixer_tlv) 435 }; 436 437 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w, 438 struct snd_kcontrol *kcontrol, int event) 439 { 440 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 441 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 442 443 switch (event) { 444 case SND_SOC_DAPM_PRE_PMU: 445 cs42l42->hp_adc_up_pending = true; 446 break; 447 case SND_SOC_DAPM_POST_PMU: 448 /* Only need one delay if HP and ADC are both powering-up */ 449 if (cs42l42->hp_adc_up_pending) { 450 usleep_range(CS42L42_HP_ADC_EN_TIME_US, 451 CS42L42_HP_ADC_EN_TIME_US + 1000); 452 cs42l42->hp_adc_up_pending = false; 453 } 454 break; 455 default: 456 break; 457 } 458 459 return 0; 460 } 461 462 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 463 /* Playback Path */ 464 SND_SOC_DAPM_OUTPUT("HP"), 465 SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1, 466 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 467 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 468 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0), 469 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0), 470 471 /* Playback Requirements */ 472 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 473 474 /* Capture Path */ 475 SND_SOC_DAPM_INPUT("HS"), 476 SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1, 477 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 478 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 479 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 480 481 /* Capture Requirements */ 482 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 483 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 484 485 /* Playback/Capture Requirements */ 486 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 487 }; 488 489 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 490 /* Playback Path */ 491 {"HP", NULL, "DAC"}, 492 {"DAC", NULL, "MIXER"}, 493 {"MIXER", NULL, "SDIN1"}, 494 {"MIXER", NULL, "SDIN2"}, 495 {"SDIN1", NULL, "Playback"}, 496 {"SDIN2", NULL, "Playback"}, 497 498 /* Playback Requirements */ 499 {"SDIN1", NULL, "ASP DAI0"}, 500 {"SDIN2", NULL, "ASP DAI0"}, 501 {"SDIN1", NULL, "SCLK"}, 502 {"SDIN2", NULL, "SCLK"}, 503 504 /* Capture Path */ 505 {"ADC", NULL, "HS"}, 506 { "SDOUT1", NULL, "ADC" }, 507 { "SDOUT2", NULL, "ADC" }, 508 { "Capture", NULL, "SDOUT1" }, 509 { "Capture", NULL, "SDOUT2" }, 510 511 /* Capture Requirements */ 512 { "SDOUT1", NULL, "ASP DAO0" }, 513 { "SDOUT2", NULL, "ASP DAO0" }, 514 { "SDOUT1", NULL, "SCLK" }, 515 { "SDOUT2", NULL, "SCLK" }, 516 { "SDOUT1", NULL, "ASP TX EN" }, 517 { "SDOUT2", NULL, "ASP TX EN" }, 518 }; 519 520 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) 521 { 522 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 523 524 cs42l42->jack = jk; 525 526 return 0; 527 } 528 529 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = { 530 .set_jack = cs42l42_set_jack, 531 .dapm_widgets = cs42l42_dapm_widgets, 532 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 533 .dapm_routes = cs42l42_audio_map, 534 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 535 .controls = cs42l42_snd_controls, 536 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 537 .idle_bias_on = 1, 538 .endianness = 1, 539 .non_legacy_dai_naming = 1, 540 }; 541 542 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 543 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 544 { 545 .reg = CS42L42_OSC_SWITCH, 546 .def = CS42L42_SCLK_PRESENT_MASK, 547 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 548 }, 549 }; 550 551 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 552 static const struct reg_sequence cs42l42_to_osc_seq[] = { 553 { 554 .reg = CS42L42_OSC_SWITCH, 555 .def = 0, 556 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 557 }, 558 }; 559 560 struct cs42l42_pll_params { 561 u32 sclk; 562 u8 mclk_src_sel; 563 u8 sclk_prediv; 564 u8 pll_div_int; 565 u32 pll_div_frac; 566 u8 pll_mode; 567 u8 pll_divout; 568 u32 mclk_int; 569 u8 pll_cal_ratio; 570 u8 n; 571 }; 572 573 /* 574 * Common PLL Settings for given SCLK 575 * Table 4-5 from the Datasheet 576 */ 577 static const struct cs42l42_pll_params pll_ratio_table[] = { 578 { 1411200, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2}, 579 { 1536000, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2}, 580 { 2304000, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2}, 581 { 2400000, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 582 { 2822400, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 583 { 3000000, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 584 { 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 585 { 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1}, 586 { 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1}, 587 { 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 588 { 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 589 { 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 590 { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1}, 591 { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1}, 592 { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1}, 593 { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 594 { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 595 { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1} 596 }; 597 598 static int cs42l42_pll_config(struct snd_soc_component *component) 599 { 600 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 601 int i; 602 u32 clk; 603 u32 fsync; 604 605 if (!cs42l42->sclk) 606 clk = cs42l42->bclk; 607 else 608 clk = cs42l42->sclk; 609 610 /* Don't reconfigure if there is an audio stream running */ 611 if (cs42l42->stream_use) { 612 if (pll_ratio_table[cs42l42->pll_config].sclk == clk) 613 return 0; 614 else 615 return -EBUSY; 616 } 617 618 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 619 if (pll_ratio_table[i].sclk == clk) { 620 cs42l42->pll_config = i; 621 622 /* Configure the internal sample rate */ 623 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 624 CS42L42_INTERNAL_FS_MASK, 625 ((pll_ratio_table[i].mclk_int != 626 12000000) && 627 (pll_ratio_table[i].mclk_int != 628 24000000)) << 629 CS42L42_INTERNAL_FS_SHIFT); 630 631 /* Set up the LRCLK */ 632 fsync = clk / cs42l42->srate; 633 if (((fsync * cs42l42->srate) != clk) 634 || ((fsync % 2) != 0)) { 635 dev_err(component->dev, 636 "Unsupported sclk %d/sample rate %d\n", 637 clk, 638 cs42l42->srate); 639 return -EINVAL; 640 } 641 /* Set the LRCLK period */ 642 snd_soc_component_update_bits(component, 643 CS42L42_FSYNC_P_LOWER, 644 CS42L42_FSYNC_PERIOD_MASK, 645 CS42L42_FRAC0_VAL(fsync - 1) << 646 CS42L42_FSYNC_PERIOD_SHIFT); 647 snd_soc_component_update_bits(component, 648 CS42L42_FSYNC_P_UPPER, 649 CS42L42_FSYNC_PERIOD_MASK, 650 CS42L42_FRAC1_VAL(fsync - 1) << 651 CS42L42_FSYNC_PERIOD_SHIFT); 652 /* Set the LRCLK to 50% duty cycle */ 653 fsync = fsync / 2; 654 snd_soc_component_update_bits(component, 655 CS42L42_FSYNC_PW_LOWER, 656 CS42L42_FSYNC_PULSE_WIDTH_MASK, 657 CS42L42_FRAC0_VAL(fsync - 1) << 658 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 659 snd_soc_component_update_bits(component, 660 CS42L42_FSYNC_PW_UPPER, 661 CS42L42_FSYNC_PULSE_WIDTH_MASK, 662 CS42L42_FRAC1_VAL(fsync - 1) << 663 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 664 if (pll_ratio_table[i].mclk_src_sel == 0) { 665 /* Pass the clock straight through */ 666 snd_soc_component_update_bits(component, 667 CS42L42_PLL_CTL1, 668 CS42L42_PLL_START_MASK, 0); 669 } else { 670 /* Configure PLL per table 4-5 */ 671 snd_soc_component_update_bits(component, 672 CS42L42_PLL_DIV_CFG1, 673 CS42L42_SCLK_PREDIV_MASK, 674 pll_ratio_table[i].sclk_prediv 675 << CS42L42_SCLK_PREDIV_SHIFT); 676 snd_soc_component_update_bits(component, 677 CS42L42_PLL_DIV_INT, 678 CS42L42_PLL_DIV_INT_MASK, 679 pll_ratio_table[i].pll_div_int 680 << CS42L42_PLL_DIV_INT_SHIFT); 681 snd_soc_component_update_bits(component, 682 CS42L42_PLL_DIV_FRAC0, 683 CS42L42_PLL_DIV_FRAC_MASK, 684 CS42L42_FRAC0_VAL( 685 pll_ratio_table[i].pll_div_frac) 686 << CS42L42_PLL_DIV_FRAC_SHIFT); 687 snd_soc_component_update_bits(component, 688 CS42L42_PLL_DIV_FRAC1, 689 CS42L42_PLL_DIV_FRAC_MASK, 690 CS42L42_FRAC1_VAL( 691 pll_ratio_table[i].pll_div_frac) 692 << CS42L42_PLL_DIV_FRAC_SHIFT); 693 snd_soc_component_update_bits(component, 694 CS42L42_PLL_DIV_FRAC2, 695 CS42L42_PLL_DIV_FRAC_MASK, 696 CS42L42_FRAC2_VAL( 697 pll_ratio_table[i].pll_div_frac) 698 << CS42L42_PLL_DIV_FRAC_SHIFT); 699 snd_soc_component_update_bits(component, 700 CS42L42_PLL_CTL4, 701 CS42L42_PLL_MODE_MASK, 702 pll_ratio_table[i].pll_mode 703 << CS42L42_PLL_MODE_SHIFT); 704 snd_soc_component_update_bits(component, 705 CS42L42_PLL_CTL3, 706 CS42L42_PLL_DIVOUT_MASK, 707 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n) 708 << CS42L42_PLL_DIVOUT_SHIFT); 709 if (pll_ratio_table[i].n != 1) 710 cs42l42->pll_divout = pll_ratio_table[i].pll_divout; 711 else 712 cs42l42->pll_divout = 0; 713 snd_soc_component_update_bits(component, 714 CS42L42_PLL_CAL_RATIO, 715 CS42L42_PLL_CAL_RATIO_MASK, 716 pll_ratio_table[i].pll_cal_ratio 717 << CS42L42_PLL_CAL_RATIO_SHIFT); 718 } 719 return 0; 720 } 721 } 722 723 return -EINVAL; 724 } 725 726 static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate) 727 { 728 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 729 unsigned int fs; 730 731 /* Don't reconfigure if there is an audio stream running */ 732 if (cs42l42->stream_use) 733 return; 734 735 /* SRC MCLK must be as close as possible to 125 * sample rate */ 736 if (sample_rate <= 48000) 737 fs = CS42L42_CLK_IASRC_SEL_6; 738 else 739 fs = CS42L42_CLK_IASRC_SEL_12; 740 741 /* Set the sample rates (96k or lower) */ 742 snd_soc_component_update_bits(component, 743 CS42L42_FS_RATE_EN, 744 CS42L42_FS_EN_MASK, 745 (CS42L42_FS_EN_IASRC_96K | 746 CS42L42_FS_EN_OASRC_96K) << 747 CS42L42_FS_EN_SHIFT); 748 749 snd_soc_component_update_bits(component, 750 CS42L42_IN_ASRC_CLK, 751 CS42L42_CLK_IASRC_SEL_MASK, 752 fs << CS42L42_CLK_IASRC_SEL_SHIFT); 753 snd_soc_component_update_bits(component, 754 CS42L42_OUT_ASRC_CLK, 755 CS42L42_CLK_OASRC_SEL_MASK, 756 fs << CS42L42_CLK_OASRC_SEL_SHIFT); 757 } 758 759 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 760 { 761 struct snd_soc_component *component = codec_dai->component; 762 u32 asp_cfg_val = 0; 763 764 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 765 case SND_SOC_DAIFMT_CBS_CFM: 766 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 767 CS42L42_ASP_MODE_SHIFT; 768 break; 769 case SND_SOC_DAIFMT_CBS_CFS: 770 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 771 CS42L42_ASP_MODE_SHIFT; 772 break; 773 default: 774 return -EINVAL; 775 } 776 777 /* interface format */ 778 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 779 case SND_SOC_DAIFMT_I2S: 780 /* 781 * 5050 mode, frame starts on falling edge of LRCLK, 782 * frame delayed by 1.0 SCLKs 783 */ 784 snd_soc_component_update_bits(component, 785 CS42L42_ASP_FRM_CFG, 786 CS42L42_ASP_STP_MASK | 787 CS42L42_ASP_5050_MASK | 788 CS42L42_ASP_FSD_MASK, 789 CS42L42_ASP_5050_MASK | 790 (CS42L42_ASP_FSD_1_0 << 791 CS42L42_ASP_FSD_SHIFT)); 792 break; 793 default: 794 return -EINVAL; 795 } 796 797 /* Bitclock/frame inversion */ 798 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 799 case SND_SOC_DAIFMT_NB_NF: 800 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 801 break; 802 case SND_SOC_DAIFMT_NB_IF: 803 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 804 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 805 break; 806 case SND_SOC_DAIFMT_IB_NF: 807 break; 808 case SND_SOC_DAIFMT_IB_IF: 809 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 810 break; 811 } 812 813 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 814 CS42L42_ASP_SCPOL_MASK | 815 CS42L42_ASP_LCPOL_MASK, 816 asp_cfg_val); 817 818 return 0; 819 } 820 821 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 822 { 823 struct snd_soc_component *component = dai->component; 824 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 825 826 /* 827 * Sample rates < 44.1 kHz would produce an out-of-range SCLK with 828 * a standard I2S frame. If the machine driver sets SCLK it must be 829 * legal. 830 */ 831 if (cs42l42->sclk) 832 return 0; 833 834 /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */ 835 return snd_pcm_hw_constraint_minmax(substream->runtime, 836 SNDRV_PCM_HW_PARAM_RATE, 837 44100, 96000); 838 } 839 840 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 841 struct snd_pcm_hw_params *params, 842 struct snd_soc_dai *dai) 843 { 844 struct snd_soc_component *component = dai->component; 845 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 846 unsigned int channels = params_channels(params); 847 unsigned int width = (params_width(params) / 8) - 1; 848 unsigned int val = 0; 849 int ret; 850 851 cs42l42->srate = params_rate(params); 852 cs42l42->bclk = snd_soc_params_to_bclk(params); 853 854 /* I2S frame always has 2 channels even for mono audio */ 855 if (channels == 1) 856 cs42l42->bclk *= 2; 857 858 /* 859 * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being 860 * more than assumed (which would result in overclocking). 861 */ 862 if (params_width(params) == 24) 863 cs42l42->bclk = (cs42l42->bclk / 3) * 4; 864 865 switch (substream->stream) { 866 case SNDRV_PCM_STREAM_CAPTURE: 867 /* channel 2 on high LRCLK */ 868 val = CS42L42_ASP_TX_CH2_AP_MASK | 869 (width << CS42L42_ASP_TX_CH2_RES_SHIFT) | 870 (width << CS42L42_ASP_TX_CH1_RES_SHIFT); 871 872 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 873 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 874 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 875 break; 876 case SNDRV_PCM_STREAM_PLAYBACK: 877 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 878 /* channel 1 on low LRCLK */ 879 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 880 CS42L42_ASP_RX_CH_AP_MASK | 881 CS42L42_ASP_RX_CH_RES_MASK, val); 882 /* Channel 2 on high LRCLK */ 883 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 884 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 885 CS42L42_ASP_RX_CH_AP_MASK | 886 CS42L42_ASP_RX_CH_RES_MASK, val); 887 888 /* Channel B comes from the last active channel */ 889 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL, 890 CS42L42_SP_RX_CHB_SEL_MASK, 891 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT); 892 893 /* Both LRCLK slots must be enabled */ 894 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, 895 CS42L42_ASP_RX0_CH_EN_MASK, 896 BIT(CS42L42_ASP_RX0_CH1_SHIFT) | 897 BIT(CS42L42_ASP_RX0_CH2_SHIFT)); 898 break; 899 default: 900 break; 901 } 902 903 ret = cs42l42_pll_config(component); 904 if (ret) 905 return ret; 906 907 cs42l42_src_config(component, params_rate(params)); 908 909 return 0; 910 } 911 912 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 913 int clk_id, unsigned int freq, int dir) 914 { 915 struct snd_soc_component *component = dai->component; 916 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 917 int i; 918 919 if (freq == 0) { 920 cs42l42->sclk = 0; 921 return 0; 922 } 923 924 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 925 if (pll_ratio_table[i].sclk == freq) { 926 cs42l42->sclk = freq; 927 return 0; 928 } 929 } 930 931 dev_err(component->dev, "SCLK %u not supported\n", freq); 932 933 return -EINVAL; 934 } 935 936 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 937 { 938 struct snd_soc_component *component = dai->component; 939 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 940 unsigned int regval; 941 int ret; 942 943 if (mute) { 944 /* Mute the headphone */ 945 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 946 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 947 CS42L42_HP_ANA_AMUTE_MASK | 948 CS42L42_HP_ANA_BMUTE_MASK, 949 CS42L42_HP_ANA_AMUTE_MASK | 950 CS42L42_HP_ANA_BMUTE_MASK); 951 952 cs42l42->stream_use &= ~(1 << stream); 953 if (!cs42l42->stream_use) { 954 /* 955 * Switch to the internal oscillator. 956 * SCLK must remain running until after this clock switch. 957 * Without a source of clock the I2C bus doesn't work. 958 */ 959 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 960 ARRAY_SIZE(cs42l42_to_osc_seq)); 961 962 /* Must disconnect PLL before stopping it */ 963 snd_soc_component_update_bits(component, 964 CS42L42_MCLK_SRC_SEL, 965 CS42L42_MCLK_SRC_SEL_MASK, 966 0); 967 usleep_range(100, 200); 968 969 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 970 CS42L42_PLL_START_MASK, 0); 971 } 972 } else { 973 if (!cs42l42->stream_use) { 974 /* SCLK must be running before codec unmute */ 975 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) { 976 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 977 CS42L42_PLL_START_MASK, 1); 978 979 if (cs42l42->pll_divout) { 980 usleep_range(CS42L42_PLL_DIVOUT_TIME_US, 981 CS42L42_PLL_DIVOUT_TIME_US * 2); 982 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3, 983 CS42L42_PLL_DIVOUT_MASK, 984 cs42l42->pll_divout << 985 CS42L42_PLL_DIVOUT_SHIFT); 986 } 987 988 ret = regmap_read_poll_timeout(cs42l42->regmap, 989 CS42L42_PLL_LOCK_STATUS, 990 regval, 991 (regval & 1), 992 CS42L42_PLL_LOCK_POLL_US, 993 CS42L42_PLL_LOCK_TIMEOUT_US); 994 if (ret < 0) 995 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 996 997 /* PLL must be running to drive glitchless switch logic */ 998 snd_soc_component_update_bits(component, 999 CS42L42_MCLK_SRC_SEL, 1000 CS42L42_MCLK_SRC_SEL_MASK, 1001 CS42L42_MCLK_SRC_SEL_MASK); 1002 } 1003 1004 /* Mark SCLK as present, turn off internal oscillator */ 1005 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 1006 ARRAY_SIZE(cs42l42_to_sclk_seq)); 1007 } 1008 cs42l42->stream_use |= 1 << stream; 1009 1010 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1011 /* Un-mute the headphone */ 1012 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 1013 CS42L42_HP_ANA_AMUTE_MASK | 1014 CS42L42_HP_ANA_BMUTE_MASK, 1015 0); 1016 } 1017 } 1018 1019 return 0; 1020 } 1021 1022 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1023 SNDRV_PCM_FMTBIT_S24_LE |\ 1024 SNDRV_PCM_FMTBIT_S32_LE) 1025 1026 static const struct snd_soc_dai_ops cs42l42_ops = { 1027 .startup = cs42l42_dai_startup, 1028 .hw_params = cs42l42_pcm_hw_params, 1029 .set_fmt = cs42l42_set_dai_fmt, 1030 .set_sysclk = cs42l42_set_sysclk, 1031 .mute_stream = cs42l42_mute_stream, 1032 }; 1033 1034 static struct snd_soc_dai_driver cs42l42_dai = { 1035 .name = "cs42l42", 1036 .playback = { 1037 .stream_name = "Playback", 1038 .channels_min = 1, 1039 .channels_max = 2, 1040 .rates = SNDRV_PCM_RATE_8000_96000, 1041 .formats = CS42L42_FORMATS, 1042 }, 1043 .capture = { 1044 .stream_name = "Capture", 1045 .channels_min = 1, 1046 .channels_max = 2, 1047 .rates = SNDRV_PCM_RATE_8000_96000, 1048 .formats = CS42L42_FORMATS, 1049 }, 1050 .symmetric_rate = 1, 1051 .symmetric_sample_bits = 1, 1052 .ops = &cs42l42_ops, 1053 }; 1054 1055 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42) 1056 { 1057 unsigned int hs_det_status; 1058 unsigned int hs_det_comp1; 1059 unsigned int hs_det_comp2; 1060 unsigned int hs_det_sw; 1061 1062 /* Set hs detect to manual, active mode */ 1063 regmap_update_bits(cs42l42->regmap, 1064 CS42L42_HSDET_CTL2, 1065 CS42L42_HSDET_CTRL_MASK | 1066 CS42L42_HSDET_SET_MASK | 1067 CS42L42_HSBIAS_REF_MASK | 1068 CS42L42_HSDET_AUTO_TIME_MASK, 1069 (1 << CS42L42_HSDET_CTRL_SHIFT) | 1070 (0 << CS42L42_HSDET_SET_SHIFT) | 1071 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1072 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1073 1074 /* Configure HS DET comparator reference levels. */ 1075 regmap_update_bits(cs42l42->regmap, 1076 CS42L42_HSDET_CTL1, 1077 CS42L42_HSDET_COMP1_LVL_MASK | 1078 CS42L42_HSDET_COMP2_LVL_MASK, 1079 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1080 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1081 1082 /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ 1083 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); 1084 1085 msleep(100); 1086 1087 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1088 1089 hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1090 CS42L42_HSDET_COMP1_OUT_SHIFT; 1091 hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1092 CS42L42_HSDET_COMP2_OUT_SHIFT; 1093 1094 /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ 1095 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); 1096 1097 msleep(100); 1098 1099 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1100 1101 hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1102 CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; 1103 hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1104 CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; 1105 1106 /* Use Comparator 1 with 1.25V Threshold. */ 1107 switch (hs_det_comp1) { 1108 case CS42L42_HSDET_COMP_TYPE1: 1109 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1110 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1111 break; 1112 case CS42L42_HSDET_COMP_TYPE2: 1113 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1114 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1115 break; 1116 default: 1117 /* Fallback to Comparator 2 with 1.75V Threshold. */ 1118 switch (hs_det_comp2) { 1119 case CS42L42_HSDET_COMP_TYPE1: 1120 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1121 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1122 break; 1123 case CS42L42_HSDET_COMP_TYPE2: 1124 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1125 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1126 break; 1127 case CS42L42_HSDET_COMP_TYPE3: 1128 cs42l42->hs_type = CS42L42_PLUG_HEADPHONE; 1129 hs_det_sw = CS42L42_HSDET_SW_TYPE3; 1130 break; 1131 default: 1132 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1133 hs_det_sw = CS42L42_HSDET_SW_TYPE4; 1134 break; 1135 } 1136 } 1137 1138 /* Set Switches */ 1139 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw); 1140 1141 /* Set HSDET mode to Manual—Disabled */ 1142 regmap_update_bits(cs42l42->regmap, 1143 CS42L42_HSDET_CTL2, 1144 CS42L42_HSDET_CTRL_MASK | 1145 CS42L42_HSDET_SET_MASK | 1146 CS42L42_HSBIAS_REF_MASK | 1147 CS42L42_HSDET_AUTO_TIME_MASK, 1148 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1149 (0 << CS42L42_HSDET_SET_SHIFT) | 1150 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1151 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1152 1153 /* Configure HS DET comparator reference levels. */ 1154 regmap_update_bits(cs42l42->regmap, 1155 CS42L42_HSDET_CTL1, 1156 CS42L42_HSDET_COMP1_LVL_MASK | 1157 CS42L42_HSDET_COMP2_LVL_MASK, 1158 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1159 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1160 } 1161 1162 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 1163 { 1164 unsigned int hs_det_status; 1165 unsigned int int_status; 1166 1167 /* Read and save the hs detection result */ 1168 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1169 1170 /* Mask the auto detect interrupt */ 1171 regmap_update_bits(cs42l42->regmap, 1172 CS42L42_CODEC_INT_MASK, 1173 CS42L42_PDN_DONE_MASK | 1174 CS42L42_HSDET_AUTO_DONE_MASK, 1175 (1 << CS42L42_PDN_DONE_SHIFT) | 1176 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1177 1178 1179 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 1180 CS42L42_HSDET_TYPE_SHIFT; 1181 1182 /* Set hs detect to automatic, disabled mode */ 1183 regmap_update_bits(cs42l42->regmap, 1184 CS42L42_HSDET_CTL2, 1185 CS42L42_HSDET_CTRL_MASK | 1186 CS42L42_HSDET_SET_MASK | 1187 CS42L42_HSBIAS_REF_MASK | 1188 CS42L42_HSDET_AUTO_TIME_MASK, 1189 (2 << CS42L42_HSDET_CTRL_SHIFT) | 1190 (2 << CS42L42_HSDET_SET_SHIFT) | 1191 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1192 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1193 1194 /* Run Manual detection if auto detect has not found a headset. 1195 * We Re-Run with Manual Detection if the original detection was invalid or headphones, 1196 * to ensure that a headset mic is detected in all cases. 1197 */ 1198 if (cs42l42->hs_type == CS42L42_PLUG_INVALID || 1199 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) { 1200 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n"); 1201 cs42l42_manual_hs_type_detect(cs42l42); 1202 } 1203 1204 /* Set up button detection */ 1205 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1206 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1207 /* Set auto HS bias settings to default */ 1208 regmap_update_bits(cs42l42->regmap, 1209 CS42L42_HSBIAS_SC_AUTOCTL, 1210 CS42L42_HSBIAS_SENSE_EN_MASK | 1211 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1212 CS42L42_TIP_SENSE_EN_MASK | 1213 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1214 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1215 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1216 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1217 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1218 1219 /* Set up hs detect level sensitivity */ 1220 regmap_update_bits(cs42l42->regmap, 1221 CS42L42_MIC_DET_CTL1, 1222 CS42L42_LATCH_TO_VP_MASK | 1223 CS42L42_EVENT_STAT_SEL_MASK | 1224 CS42L42_HS_DET_LEVEL_MASK, 1225 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1226 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1227 (cs42l42->bias_thresholds[0] << 1228 CS42L42_HS_DET_LEVEL_SHIFT)); 1229 1230 /* Set auto HS bias settings to default */ 1231 regmap_update_bits(cs42l42->regmap, 1232 CS42L42_HSBIAS_SC_AUTOCTL, 1233 CS42L42_HSBIAS_SENSE_EN_MASK | 1234 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1235 CS42L42_TIP_SENSE_EN_MASK | 1236 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1237 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1238 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1239 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1240 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1241 1242 /* Turn on level detect circuitry */ 1243 regmap_update_bits(cs42l42->regmap, 1244 CS42L42_MISC_DET_CTL, 1245 CS42L42_DETECT_MODE_MASK | 1246 CS42L42_HSBIAS_CTL_MASK | 1247 CS42L42_PDN_MIC_LVL_DET_MASK, 1248 (0 << CS42L42_DETECT_MODE_SHIFT) | 1249 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1250 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1251 1252 msleep(cs42l42->btn_det_init_dbnce); 1253 1254 /* Clear any button interrupts before unmasking them */ 1255 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1256 &int_status); 1257 1258 /* Unmask button detect interrupts */ 1259 regmap_update_bits(cs42l42->regmap, 1260 CS42L42_DET_INT2_MASK, 1261 CS42L42_M_DETECT_TF_MASK | 1262 CS42L42_M_DETECT_FT_MASK | 1263 CS42L42_M_HSBIAS_HIZ_MASK | 1264 CS42L42_M_SHORT_RLS_MASK | 1265 CS42L42_M_SHORT_DET_MASK, 1266 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1267 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1268 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1269 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1270 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1271 } else { 1272 /* Make sure button detect and HS bias circuits are off */ 1273 regmap_update_bits(cs42l42->regmap, 1274 CS42L42_MISC_DET_CTL, 1275 CS42L42_DETECT_MODE_MASK | 1276 CS42L42_HSBIAS_CTL_MASK | 1277 CS42L42_PDN_MIC_LVL_DET_MASK, 1278 (0 << CS42L42_DETECT_MODE_SHIFT) | 1279 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1280 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1281 } 1282 1283 regmap_update_bits(cs42l42->regmap, 1284 CS42L42_DAC_CTL2, 1285 CS42L42_HPOUT_PULLDOWN_MASK | 1286 CS42L42_HPOUT_LOAD_MASK | 1287 CS42L42_HPOUT_CLAMP_MASK | 1288 CS42L42_DAC_HPF_EN_MASK | 1289 CS42L42_DAC_MON_EN_MASK, 1290 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1291 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1292 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1293 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1294 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1295 1296 /* Unmask tip sense interrupts */ 1297 regmap_update_bits(cs42l42->regmap, 1298 CS42L42_TSRS_PLUG_INT_MASK, 1299 CS42L42_RS_PLUG_MASK | 1300 CS42L42_RS_UNPLUG_MASK | 1301 CS42L42_TS_PLUG_MASK | 1302 CS42L42_TS_UNPLUG_MASK, 1303 (1 << CS42L42_RS_PLUG_SHIFT) | 1304 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1305 (0 << CS42L42_TS_PLUG_SHIFT) | 1306 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1307 } 1308 1309 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1310 { 1311 /* Mask tip sense interrupts */ 1312 regmap_update_bits(cs42l42->regmap, 1313 CS42L42_TSRS_PLUG_INT_MASK, 1314 CS42L42_RS_PLUG_MASK | 1315 CS42L42_RS_UNPLUG_MASK | 1316 CS42L42_TS_PLUG_MASK | 1317 CS42L42_TS_UNPLUG_MASK, 1318 (1 << CS42L42_RS_PLUG_SHIFT) | 1319 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1320 (1 << CS42L42_TS_PLUG_SHIFT) | 1321 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1322 1323 /* Make sure button detect and HS bias circuits are off */ 1324 regmap_update_bits(cs42l42->regmap, 1325 CS42L42_MISC_DET_CTL, 1326 CS42L42_DETECT_MODE_MASK | 1327 CS42L42_HSBIAS_CTL_MASK | 1328 CS42L42_PDN_MIC_LVL_DET_MASK, 1329 (0 << CS42L42_DETECT_MODE_SHIFT) | 1330 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1331 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1332 1333 /* Set auto HS bias settings to default */ 1334 regmap_update_bits(cs42l42->regmap, 1335 CS42L42_HSBIAS_SC_AUTOCTL, 1336 CS42L42_HSBIAS_SENSE_EN_MASK | 1337 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1338 CS42L42_TIP_SENSE_EN_MASK | 1339 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1340 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1341 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1342 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1343 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1344 1345 /* Set hs detect to manual, disabled mode */ 1346 regmap_update_bits(cs42l42->regmap, 1347 CS42L42_HSDET_CTL2, 1348 CS42L42_HSDET_CTRL_MASK | 1349 CS42L42_HSDET_SET_MASK | 1350 CS42L42_HSBIAS_REF_MASK | 1351 CS42L42_HSDET_AUTO_TIME_MASK, 1352 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1353 (2 << CS42L42_HSDET_SET_SHIFT) | 1354 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1355 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1356 1357 regmap_update_bits(cs42l42->regmap, 1358 CS42L42_DAC_CTL2, 1359 CS42L42_HPOUT_PULLDOWN_MASK | 1360 CS42L42_HPOUT_LOAD_MASK | 1361 CS42L42_HPOUT_CLAMP_MASK | 1362 CS42L42_DAC_HPF_EN_MASK | 1363 CS42L42_DAC_MON_EN_MASK, 1364 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1365 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1366 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1367 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1368 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1369 1370 /* Power up HS bias to 2.7V */ 1371 regmap_update_bits(cs42l42->regmap, 1372 CS42L42_MISC_DET_CTL, 1373 CS42L42_DETECT_MODE_MASK | 1374 CS42L42_HSBIAS_CTL_MASK | 1375 CS42L42_PDN_MIC_LVL_DET_MASK, 1376 (0 << CS42L42_DETECT_MODE_SHIFT) | 1377 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1378 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1379 1380 /* Wait for HS bias to ramp up */ 1381 msleep(cs42l42->hs_bias_ramp_time); 1382 1383 /* Unmask auto detect interrupt */ 1384 regmap_update_bits(cs42l42->regmap, 1385 CS42L42_CODEC_INT_MASK, 1386 CS42L42_PDN_DONE_MASK | 1387 CS42L42_HSDET_AUTO_DONE_MASK, 1388 (1 << CS42L42_PDN_DONE_SHIFT) | 1389 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1390 1391 /* Set hs detect to automatic, enabled mode */ 1392 regmap_update_bits(cs42l42->regmap, 1393 CS42L42_HSDET_CTL2, 1394 CS42L42_HSDET_CTRL_MASK | 1395 CS42L42_HSDET_SET_MASK | 1396 CS42L42_HSBIAS_REF_MASK | 1397 CS42L42_HSDET_AUTO_TIME_MASK, 1398 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1399 (2 << CS42L42_HSDET_SET_SHIFT) | 1400 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1401 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1402 } 1403 1404 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1405 { 1406 /* Mask button detect interrupts */ 1407 regmap_update_bits(cs42l42->regmap, 1408 CS42L42_DET_INT2_MASK, 1409 CS42L42_M_DETECT_TF_MASK | 1410 CS42L42_M_DETECT_FT_MASK | 1411 CS42L42_M_HSBIAS_HIZ_MASK | 1412 CS42L42_M_SHORT_RLS_MASK | 1413 CS42L42_M_SHORT_DET_MASK, 1414 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1415 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1416 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1417 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1418 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1419 1420 /* Ground HS bias */ 1421 regmap_update_bits(cs42l42->regmap, 1422 CS42L42_MISC_DET_CTL, 1423 CS42L42_DETECT_MODE_MASK | 1424 CS42L42_HSBIAS_CTL_MASK | 1425 CS42L42_PDN_MIC_LVL_DET_MASK, 1426 (0 << CS42L42_DETECT_MODE_SHIFT) | 1427 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1428 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1429 1430 /* Set auto HS bias settings to default */ 1431 regmap_update_bits(cs42l42->regmap, 1432 CS42L42_HSBIAS_SC_AUTOCTL, 1433 CS42L42_HSBIAS_SENSE_EN_MASK | 1434 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1435 CS42L42_TIP_SENSE_EN_MASK | 1436 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1437 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1438 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1439 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1440 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1441 1442 /* Set hs detect to manual, disabled mode */ 1443 regmap_update_bits(cs42l42->regmap, 1444 CS42L42_HSDET_CTL2, 1445 CS42L42_HSDET_CTRL_MASK | 1446 CS42L42_HSDET_SET_MASK | 1447 CS42L42_HSBIAS_REF_MASK | 1448 CS42L42_HSDET_AUTO_TIME_MASK, 1449 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1450 (2 << CS42L42_HSDET_SET_SHIFT) | 1451 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1452 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1453 } 1454 1455 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1456 { 1457 int bias_level; 1458 unsigned int detect_status; 1459 1460 /* Mask button detect interrupts */ 1461 regmap_update_bits(cs42l42->regmap, 1462 CS42L42_DET_INT2_MASK, 1463 CS42L42_M_DETECT_TF_MASK | 1464 CS42L42_M_DETECT_FT_MASK | 1465 CS42L42_M_HSBIAS_HIZ_MASK | 1466 CS42L42_M_SHORT_RLS_MASK | 1467 CS42L42_M_SHORT_DET_MASK, 1468 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1469 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1470 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1471 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1472 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1473 1474 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1475 cs42l42->btn_det_event_dbnce * 2000); 1476 1477 /* Test all 4 level detect biases */ 1478 bias_level = 1; 1479 do { 1480 /* Adjust button detect level sensitivity */ 1481 regmap_update_bits(cs42l42->regmap, 1482 CS42L42_MIC_DET_CTL1, 1483 CS42L42_LATCH_TO_VP_MASK | 1484 CS42L42_EVENT_STAT_SEL_MASK | 1485 CS42L42_HS_DET_LEVEL_MASK, 1486 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1487 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1488 (cs42l42->bias_thresholds[bias_level] << 1489 CS42L42_HS_DET_LEVEL_SHIFT)); 1490 1491 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1492 &detect_status); 1493 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1494 (++bias_level < CS42L42_NUM_BIASES)); 1495 1496 switch (bias_level) { 1497 case 1: /* Function C button press */ 1498 bias_level = SND_JACK_BTN_2; 1499 dev_dbg(cs42l42->dev, "Function C button press\n"); 1500 break; 1501 case 2: /* Function B button press */ 1502 bias_level = SND_JACK_BTN_1; 1503 dev_dbg(cs42l42->dev, "Function B button press\n"); 1504 break; 1505 case 3: /* Function D button press */ 1506 bias_level = SND_JACK_BTN_3; 1507 dev_dbg(cs42l42->dev, "Function D button press\n"); 1508 break; 1509 case 4: /* Function A button press */ 1510 bias_level = SND_JACK_BTN_0; 1511 dev_dbg(cs42l42->dev, "Function A button press\n"); 1512 break; 1513 default: 1514 bias_level = 0; 1515 break; 1516 } 1517 1518 /* Set button detect level sensitivity back to default */ 1519 regmap_update_bits(cs42l42->regmap, 1520 CS42L42_MIC_DET_CTL1, 1521 CS42L42_LATCH_TO_VP_MASK | 1522 CS42L42_EVENT_STAT_SEL_MASK | 1523 CS42L42_HS_DET_LEVEL_MASK, 1524 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1525 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1526 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1527 1528 /* Clear any button interrupts before unmasking them */ 1529 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1530 &detect_status); 1531 1532 /* Unmask button detect interrupts */ 1533 regmap_update_bits(cs42l42->regmap, 1534 CS42L42_DET_INT2_MASK, 1535 CS42L42_M_DETECT_TF_MASK | 1536 CS42L42_M_DETECT_FT_MASK | 1537 CS42L42_M_HSBIAS_HIZ_MASK | 1538 CS42L42_M_SHORT_RLS_MASK | 1539 CS42L42_M_SHORT_DET_MASK, 1540 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1541 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1542 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1543 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1544 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1545 1546 return bias_level; 1547 } 1548 1549 struct cs42l42_irq_params { 1550 u16 status_addr; 1551 u16 mask_addr; 1552 u8 mask; 1553 }; 1554 1555 static const struct cs42l42_irq_params irq_params_table[] = { 1556 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1557 CS42L42_ADC_OVFL_VAL_MASK}, 1558 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1559 CS42L42_MIXER_VAL_MASK}, 1560 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1561 CS42L42_SRC_VAL_MASK}, 1562 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1563 CS42L42_ASP_RX_VAL_MASK}, 1564 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1565 CS42L42_ASP_TX_VAL_MASK}, 1566 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1567 CS42L42_CODEC_VAL_MASK}, 1568 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1569 CS42L42_DET_INT_VAL1_MASK}, 1570 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1571 CS42L42_DET_INT_VAL2_MASK}, 1572 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1573 CS42L42_SRCPL_VAL_MASK}, 1574 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1575 CS42L42_VPMON_VAL_MASK}, 1576 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1577 CS42L42_PLL_LOCK_VAL_MASK}, 1578 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1579 CS42L42_TSRS_PLUG_VAL_MASK} 1580 }; 1581 1582 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1583 { 1584 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1585 unsigned int stickies[12]; 1586 unsigned int masks[12]; 1587 unsigned int current_plug_status; 1588 unsigned int current_button_status; 1589 unsigned int i; 1590 int report = 0; 1591 1592 1593 /* Read sticky registers to clear interurpt */ 1594 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1595 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1596 &(stickies[i])); 1597 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1598 &(masks[i])); 1599 stickies[i] = stickies[i] & (~masks[i]) & 1600 irq_params_table[i].mask; 1601 } 1602 1603 /* Read tip sense status before handling type detect */ 1604 current_plug_status = (stickies[11] & 1605 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1606 CS42L42_TS_PLUG_SHIFT; 1607 1608 /* Read button sense status */ 1609 current_button_status = stickies[7] & 1610 (CS42L42_M_DETECT_TF_MASK | 1611 CS42L42_M_DETECT_FT_MASK | 1612 CS42L42_M_HSBIAS_HIZ_MASK); 1613 1614 /* Check auto-detect status */ 1615 if ((~masks[5]) & irq_params_table[5].mask) { 1616 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1617 cs42l42_process_hs_type_detect(cs42l42); 1618 switch (cs42l42->hs_type) { 1619 case CS42L42_PLUG_CTIA: 1620 case CS42L42_PLUG_OMTP: 1621 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET, 1622 SND_JACK_HEADSET); 1623 break; 1624 case CS42L42_PLUG_HEADPHONE: 1625 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE, 1626 SND_JACK_HEADPHONE); 1627 break; 1628 default: 1629 break; 1630 } 1631 dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1632 } 1633 } 1634 1635 /* Check tip sense status */ 1636 if ((~masks[11]) & irq_params_table[11].mask) { 1637 switch (current_plug_status) { 1638 case CS42L42_TS_PLUG: 1639 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1640 cs42l42->plug_state = CS42L42_TS_PLUG; 1641 cs42l42_init_hs_type_detect(cs42l42); 1642 } 1643 break; 1644 1645 case CS42L42_TS_UNPLUG: 1646 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1647 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1648 cs42l42_cancel_hs_type_detect(cs42l42); 1649 1650 switch (cs42l42->hs_type) { 1651 case CS42L42_PLUG_CTIA: 1652 case CS42L42_PLUG_OMTP: 1653 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADSET); 1654 break; 1655 case CS42L42_PLUG_HEADPHONE: 1656 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADPHONE); 1657 break; 1658 default: 1659 break; 1660 } 1661 snd_soc_jack_report(cs42l42->jack, 0, 1662 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1663 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1664 1665 dev_dbg(cs42l42->dev, "Unplug event\n"); 1666 } 1667 break; 1668 1669 default: 1670 if (cs42l42->plug_state != CS42L42_TS_TRANS) 1671 cs42l42->plug_state = CS42L42_TS_TRANS; 1672 } 1673 } 1674 1675 /* Check button detect status */ 1676 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) { 1677 if (!(current_button_status & 1678 CS42L42_M_HSBIAS_HIZ_MASK)) { 1679 1680 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1681 dev_dbg(cs42l42->dev, "Button released\n"); 1682 report = 0; 1683 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1684 report = cs42l42_handle_button_press(cs42l42); 1685 1686 } 1687 snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1688 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1689 } 1690 } 1691 1692 return IRQ_HANDLED; 1693 } 1694 1695 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1696 { 1697 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1698 CS42L42_ADC_OVFL_MASK, 1699 (1 << CS42L42_ADC_OVFL_SHIFT)); 1700 1701 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1702 CS42L42_MIX_CHB_OVFL_MASK | 1703 CS42L42_MIX_CHA_OVFL_MASK | 1704 CS42L42_EQ_OVFL_MASK | 1705 CS42L42_EQ_BIQUAD_OVFL_MASK, 1706 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1707 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1708 (1 << CS42L42_EQ_OVFL_SHIFT) | 1709 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1710 1711 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1712 CS42L42_SRC_ILK_MASK | 1713 CS42L42_SRC_OLK_MASK | 1714 CS42L42_SRC_IUNLK_MASK | 1715 CS42L42_SRC_OUNLK_MASK, 1716 (1 << CS42L42_SRC_ILK_SHIFT) | 1717 (1 << CS42L42_SRC_OLK_SHIFT) | 1718 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1719 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1720 1721 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1722 CS42L42_ASPRX_NOLRCK_MASK | 1723 CS42L42_ASPRX_EARLY_MASK | 1724 CS42L42_ASPRX_LATE_MASK | 1725 CS42L42_ASPRX_ERROR_MASK | 1726 CS42L42_ASPRX_OVLD_MASK, 1727 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1728 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1729 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1730 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1731 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1732 1733 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1734 CS42L42_ASPTX_NOLRCK_MASK | 1735 CS42L42_ASPTX_EARLY_MASK | 1736 CS42L42_ASPTX_LATE_MASK | 1737 CS42L42_ASPTX_SMERROR_MASK, 1738 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1739 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1740 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1741 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1742 1743 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1744 CS42L42_PDN_DONE_MASK | 1745 CS42L42_HSDET_AUTO_DONE_MASK, 1746 (1 << CS42L42_PDN_DONE_SHIFT) | 1747 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1748 1749 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1750 CS42L42_SRCPL_ADC_LK_MASK | 1751 CS42L42_SRCPL_DAC_LK_MASK | 1752 CS42L42_SRCPL_ADC_UNLK_MASK | 1753 CS42L42_SRCPL_DAC_UNLK_MASK, 1754 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1755 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1756 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1757 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1758 1759 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1760 CS42L42_TIP_SENSE_UNPLUG_MASK | 1761 CS42L42_TIP_SENSE_PLUG_MASK | 1762 CS42L42_HSBIAS_SENSE_MASK, 1763 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1764 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1765 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1766 1767 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1768 CS42L42_M_DETECT_TF_MASK | 1769 CS42L42_M_DETECT_FT_MASK | 1770 CS42L42_M_HSBIAS_HIZ_MASK | 1771 CS42L42_M_SHORT_RLS_MASK | 1772 CS42L42_M_SHORT_DET_MASK, 1773 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1774 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1775 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1776 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1777 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1778 1779 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1780 CS42L42_VPMON_MASK, 1781 (1 << CS42L42_VPMON_SHIFT)); 1782 1783 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1784 CS42L42_PLL_LOCK_MASK, 1785 (1 << CS42L42_PLL_LOCK_SHIFT)); 1786 1787 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1788 CS42L42_RS_PLUG_MASK | 1789 CS42L42_RS_UNPLUG_MASK | 1790 CS42L42_TS_PLUG_MASK | 1791 CS42L42_TS_UNPLUG_MASK, 1792 (1 << CS42L42_RS_PLUG_SHIFT) | 1793 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1794 (0 << CS42L42_TS_PLUG_SHIFT) | 1795 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1796 } 1797 1798 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1799 { 1800 unsigned int reg; 1801 1802 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1803 1804 /* Latch analog controls to VP power domain */ 1805 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1806 CS42L42_LATCH_TO_VP_MASK | 1807 CS42L42_EVENT_STAT_SEL_MASK | 1808 CS42L42_HS_DET_LEVEL_MASK, 1809 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1810 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1811 (cs42l42->bias_thresholds[0] << 1812 CS42L42_HS_DET_LEVEL_SHIFT)); 1813 1814 /* Remove ground noise-suppression clamps */ 1815 regmap_update_bits(cs42l42->regmap, 1816 CS42L42_HS_CLAMP_DISABLE, 1817 CS42L42_HS_CLAMP_DISABLE_MASK, 1818 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1819 1820 /* Enable the tip sense circuit */ 1821 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1822 CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK); 1823 1824 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1825 CS42L42_TIP_SENSE_CTRL_MASK | 1826 CS42L42_TIP_SENSE_INV_MASK | 1827 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1828 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1829 (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) | 1830 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1831 1832 /* Save the initial status of the tip sense */ 1833 regmap_read(cs42l42->regmap, 1834 CS42L42_TSRS_PLUG_STATUS, 1835 ®); 1836 cs42l42->plug_state = (((char) reg) & 1837 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1838 CS42L42_TS_PLUG_SHIFT; 1839 } 1840 1841 static const unsigned int threshold_defaults[] = { 1842 CS42L42_HS_DET_LEVEL_15, 1843 CS42L42_HS_DET_LEVEL_8, 1844 CS42L42_HS_DET_LEVEL_4, 1845 CS42L42_HS_DET_LEVEL_1 1846 }; 1847 1848 static int cs42l42_handle_device_data(struct device *dev, 1849 struct cs42l42_private *cs42l42) 1850 { 1851 unsigned int val; 1852 u32 thresholds[CS42L42_NUM_BIASES]; 1853 int ret; 1854 int i; 1855 1856 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val); 1857 if (!ret) { 1858 switch (val) { 1859 case CS42L42_TS_INV_EN: 1860 case CS42L42_TS_INV_DIS: 1861 cs42l42->ts_inv = val; 1862 break; 1863 default: 1864 dev_err(dev, 1865 "Wrong cirrus,ts-inv DT value %d\n", 1866 val); 1867 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1868 } 1869 } else { 1870 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1871 } 1872 1873 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val); 1874 if (!ret) { 1875 switch (val) { 1876 case CS42L42_TS_DBNCE_0: 1877 case CS42L42_TS_DBNCE_125: 1878 case CS42L42_TS_DBNCE_250: 1879 case CS42L42_TS_DBNCE_500: 1880 case CS42L42_TS_DBNCE_750: 1881 case CS42L42_TS_DBNCE_1000: 1882 case CS42L42_TS_DBNCE_1250: 1883 case CS42L42_TS_DBNCE_1500: 1884 cs42l42->ts_dbnc_rise = val; 1885 break; 1886 default: 1887 dev_err(dev, 1888 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1889 val); 1890 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1891 } 1892 } else { 1893 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1894 } 1895 1896 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1897 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1898 (cs42l42->ts_dbnc_rise << 1899 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1900 1901 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val); 1902 if (!ret) { 1903 switch (val) { 1904 case CS42L42_TS_DBNCE_0: 1905 case CS42L42_TS_DBNCE_125: 1906 case CS42L42_TS_DBNCE_250: 1907 case CS42L42_TS_DBNCE_500: 1908 case CS42L42_TS_DBNCE_750: 1909 case CS42L42_TS_DBNCE_1000: 1910 case CS42L42_TS_DBNCE_1250: 1911 case CS42L42_TS_DBNCE_1500: 1912 cs42l42->ts_dbnc_fall = val; 1913 break; 1914 default: 1915 dev_err(dev, 1916 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1917 val); 1918 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1919 } 1920 } else { 1921 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1922 } 1923 1924 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1925 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1926 (cs42l42->ts_dbnc_fall << 1927 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1928 1929 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val); 1930 if (!ret) { 1931 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1932 cs42l42->btn_det_init_dbnce = val; 1933 else { 1934 dev_err(dev, 1935 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1936 val); 1937 cs42l42->btn_det_init_dbnce = 1938 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1939 } 1940 } else { 1941 cs42l42->btn_det_init_dbnce = 1942 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1943 } 1944 1945 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val); 1946 if (!ret) { 1947 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 1948 cs42l42->btn_det_event_dbnce = val; 1949 else { 1950 dev_err(dev, 1951 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 1952 cs42l42->btn_det_event_dbnce = 1953 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1954 } 1955 } else { 1956 cs42l42->btn_det_event_dbnce = 1957 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1958 } 1959 1960 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls", 1961 thresholds, ARRAY_SIZE(thresholds)); 1962 if (!ret) { 1963 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 1964 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 1965 cs42l42->bias_thresholds[i] = thresholds[i]; 1966 else { 1967 dev_err(dev, 1968 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 1969 thresholds[i]); 1970 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1971 } 1972 } 1973 } else { 1974 for (i = 0; i < CS42L42_NUM_BIASES; i++) 1975 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1976 } 1977 1978 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val); 1979 if (!ret) { 1980 switch (val) { 1981 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 1982 cs42l42->hs_bias_ramp_rate = val; 1983 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 1984 break; 1985 case CS42L42_HSBIAS_RAMP_FAST: 1986 cs42l42->hs_bias_ramp_rate = val; 1987 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 1988 break; 1989 case CS42L42_HSBIAS_RAMP_SLOW: 1990 cs42l42->hs_bias_ramp_rate = val; 1991 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1992 break; 1993 case CS42L42_HSBIAS_RAMP_SLOWEST: 1994 cs42l42->hs_bias_ramp_rate = val; 1995 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 1996 break; 1997 default: 1998 dev_err(dev, 1999 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 2000 val); 2001 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2002 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2003 } 2004 } else { 2005 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2006 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2007 } 2008 2009 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 2010 CS42L42_HSBIAS_RAMP_MASK, 2011 (cs42l42->hs_bias_ramp_rate << 2012 CS42L42_HSBIAS_RAMP_SHIFT)); 2013 2014 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable")) 2015 cs42l42->hs_bias_sense_en = 0; 2016 else 2017 cs42l42->hs_bias_sense_en = 1; 2018 2019 return 0; 2020 } 2021 2022 static int cs42l42_i2c_probe(struct i2c_client *i2c_client, 2023 const struct i2c_device_id *id) 2024 { 2025 struct cs42l42_private *cs42l42; 2026 int ret, i, devid; 2027 unsigned int reg; 2028 2029 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private), 2030 GFP_KERNEL); 2031 if (!cs42l42) 2032 return -ENOMEM; 2033 2034 cs42l42->dev = &i2c_client->dev; 2035 i2c_set_clientdata(i2c_client, cs42l42); 2036 2037 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap); 2038 if (IS_ERR(cs42l42->regmap)) { 2039 ret = PTR_ERR(cs42l42->regmap); 2040 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 2041 return ret; 2042 } 2043 2044 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 2045 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 2046 2047 ret = devm_regulator_bulk_get(&i2c_client->dev, 2048 ARRAY_SIZE(cs42l42->supplies), 2049 cs42l42->supplies); 2050 if (ret != 0) { 2051 dev_err(&i2c_client->dev, 2052 "Failed to request supplies: %d\n", ret); 2053 return ret; 2054 } 2055 2056 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 2057 cs42l42->supplies); 2058 if (ret != 0) { 2059 dev_err(&i2c_client->dev, 2060 "Failed to enable supplies: %d\n", ret); 2061 return ret; 2062 } 2063 2064 /* Reset the Device */ 2065 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 2066 "reset", GPIOD_OUT_LOW); 2067 if (IS_ERR(cs42l42->reset_gpio)) { 2068 ret = PTR_ERR(cs42l42->reset_gpio); 2069 goto err_disable_noreset; 2070 } 2071 2072 if (cs42l42->reset_gpio) { 2073 dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); 2074 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2075 } 2076 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2077 2078 /* Request IRQ if one was specified */ 2079 if (i2c_client->irq) { 2080 ret = request_threaded_irq(i2c_client->irq, 2081 NULL, cs42l42_irq_thread, 2082 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 2083 "cs42l42", cs42l42); 2084 if (ret == -EPROBE_DEFER) { 2085 goto err_disable_noirq; 2086 } else if (ret != 0) { 2087 dev_err(&i2c_client->dev, 2088 "Failed to request IRQ: %d\n", ret); 2089 goto err_disable_noirq; 2090 } 2091 } 2092 2093 /* initialize codec */ 2094 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB); 2095 if (devid < 0) { 2096 ret = devid; 2097 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret); 2098 goto err_disable; 2099 } 2100 2101 if (devid != CS42L42_CHIP_ID) { 2102 ret = -ENODEV; 2103 dev_err(&i2c_client->dev, 2104 "CS42L42 Device ID (%X). Expected %X\n", 2105 devid, CS42L42_CHIP_ID); 2106 goto err_disable; 2107 } 2108 2109 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 2110 if (ret < 0) { 2111 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 2112 goto err_shutdown; 2113 } 2114 2115 dev_info(&i2c_client->dev, 2116 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); 2117 2118 /* Power up the codec */ 2119 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 2120 CS42L42_ASP_DAO_PDN_MASK | 2121 CS42L42_ASP_DAI_PDN_MASK | 2122 CS42L42_MIXER_PDN_MASK | 2123 CS42L42_EQ_PDN_MASK | 2124 CS42L42_HP_PDN_MASK | 2125 CS42L42_ADC_PDN_MASK | 2126 CS42L42_PDN_ALL_MASK, 2127 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 2128 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 2129 (1 << CS42L42_MIXER_PDN_SHIFT) | 2130 (1 << CS42L42_EQ_PDN_SHIFT) | 2131 (1 << CS42L42_HP_PDN_SHIFT) | 2132 (1 << CS42L42_ADC_PDN_SHIFT) | 2133 (0 << CS42L42_PDN_ALL_SHIFT)); 2134 2135 ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42); 2136 if (ret != 0) 2137 goto err_shutdown; 2138 2139 /* Setup headset detection */ 2140 cs42l42_setup_hs_type_detect(cs42l42); 2141 2142 /* Mask/Unmask Interrupts */ 2143 cs42l42_set_interrupt_masks(cs42l42); 2144 2145 /* Register codec for machine driver */ 2146 ret = devm_snd_soc_register_component(&i2c_client->dev, 2147 &soc_component_dev_cs42l42, &cs42l42_dai, 1); 2148 if (ret < 0) 2149 goto err_shutdown; 2150 2151 return 0; 2152 2153 err_shutdown: 2154 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2155 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2156 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2157 2158 err_disable: 2159 if (i2c_client->irq) 2160 free_irq(i2c_client->irq, cs42l42); 2161 2162 err_disable_noirq: 2163 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2164 err_disable_noreset: 2165 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 2166 cs42l42->supplies); 2167 return ret; 2168 } 2169 2170 static int cs42l42_i2c_remove(struct i2c_client *i2c_client) 2171 { 2172 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client); 2173 2174 if (i2c_client->irq) 2175 free_irq(i2c_client->irq, cs42l42); 2176 2177 /* 2178 * The driver might not have control of reset and power supplies, 2179 * so ensure that the chip internals are powered down. 2180 */ 2181 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2182 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2183 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2184 2185 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2186 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2187 2188 return 0; 2189 } 2190 2191 #ifdef CONFIG_OF 2192 static const struct of_device_id cs42l42_of_match[] = { 2193 { .compatible = "cirrus,cs42l42", }, 2194 {} 2195 }; 2196 MODULE_DEVICE_TABLE(of, cs42l42_of_match); 2197 #endif 2198 2199 #ifdef CONFIG_ACPI 2200 static const struct acpi_device_id cs42l42_acpi_match[] = { 2201 {"10134242", 0,}, 2202 {} 2203 }; 2204 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match); 2205 #endif 2206 2207 static const struct i2c_device_id cs42l42_id[] = { 2208 {"cs42l42", 0}, 2209 {} 2210 }; 2211 2212 MODULE_DEVICE_TABLE(i2c, cs42l42_id); 2213 2214 static struct i2c_driver cs42l42_i2c_driver = { 2215 .driver = { 2216 .name = "cs42l42", 2217 .of_match_table = of_match_ptr(cs42l42_of_match), 2218 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match), 2219 }, 2220 .id_table = cs42l42_id, 2221 .probe = cs42l42_i2c_probe, 2222 .remove = cs42l42_i2c_remove, 2223 }; 2224 2225 module_i2c_driver(cs42l42_i2c_driver); 2226 2227 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2228 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2229 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2230 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2231 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>"); 2232 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 2233 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>"); 2234 MODULE_LICENSE("GPL"); 2235