1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/i2c.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/gpio/consumer.h> 25 #include <linux/of.h> 26 #include <linux/of_gpio.h> 27 #include <linux/of_device.h> 28 #include <linux/pm_runtime.h> 29 #include <sound/core.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc.h> 33 #include <sound/soc-dapm.h> 34 #include <sound/initval.h> 35 #include <sound/tlv.h> 36 #include <dt-bindings/sound/cs42l42.h> 37 38 #include "cs42l42.h" 39 40 static const struct reg_default cs42l42_reg_defaults[] = { 41 { CS42L42_FRZ_CTL, 0x00 }, 42 { CS42L42_SRC_CTL, 0x10 }, 43 { CS42L42_MCLK_STATUS, 0x02 }, 44 { CS42L42_MCLK_CTL, 0x02 }, 45 { CS42L42_SFTRAMP_RATE, 0xA4 }, 46 { CS42L42_I2C_DEBOUNCE, 0x88 }, 47 { CS42L42_I2C_STRETCH, 0x03 }, 48 { CS42L42_I2C_TIMEOUT, 0xB7 }, 49 { CS42L42_PWR_CTL1, 0xFF }, 50 { CS42L42_PWR_CTL2, 0x84 }, 51 { CS42L42_PWR_CTL3, 0x20 }, 52 { CS42L42_RSENSE_CTL1, 0x40 }, 53 { CS42L42_RSENSE_CTL2, 0x00 }, 54 { CS42L42_OSC_SWITCH, 0x00 }, 55 { CS42L42_OSC_SWITCH_STATUS, 0x05 }, 56 { CS42L42_RSENSE_CTL3, 0x1B }, 57 { CS42L42_TSENSE_CTL, 0x1B }, 58 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 59 { CS42L42_TRSENSE_STATUS, 0x00 }, 60 { CS42L42_HSDET_CTL1, 0x77 }, 61 { CS42L42_HSDET_CTL2, 0x00 }, 62 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 63 { CS42L42_HS_DET_STATUS, 0x00 }, 64 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 65 { CS42L42_MCLK_SRC_SEL, 0x00 }, 66 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 67 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 68 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 69 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 70 { CS42L42_FSYNC_P_UPPER, 0x00 }, 71 { CS42L42_ASP_CLK_CFG, 0x00 }, 72 { CS42L42_ASP_FRM_CFG, 0x10 }, 73 { CS42L42_FS_RATE_EN, 0x00 }, 74 { CS42L42_IN_ASRC_CLK, 0x00 }, 75 { CS42L42_OUT_ASRC_CLK, 0x00 }, 76 { CS42L42_PLL_DIV_CFG1, 0x00 }, 77 { CS42L42_ADC_OVFL_STATUS, 0x00 }, 78 { CS42L42_MIXER_STATUS, 0x00 }, 79 { CS42L42_SRC_STATUS, 0x00 }, 80 { CS42L42_ASP_RX_STATUS, 0x00 }, 81 { CS42L42_ASP_TX_STATUS, 0x00 }, 82 { CS42L42_CODEC_STATUS, 0x00 }, 83 { CS42L42_DET_INT_STATUS1, 0x00 }, 84 { CS42L42_DET_INT_STATUS2, 0x00 }, 85 { CS42L42_SRCPL_INT_STATUS, 0x00 }, 86 { CS42L42_VPMON_STATUS, 0x00 }, 87 { CS42L42_PLL_LOCK_STATUS, 0x00 }, 88 { CS42L42_TSRS_PLUG_STATUS, 0x00 }, 89 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 90 { CS42L42_MIXER_INT_MASK, 0x0F }, 91 { CS42L42_SRC_INT_MASK, 0x0F }, 92 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 93 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 94 { CS42L42_CODEC_INT_MASK, 0x03 }, 95 { CS42L42_SRCPL_INT_MASK, 0xFF }, 96 { CS42L42_VPMON_INT_MASK, 0x01 }, 97 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 98 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 99 { CS42L42_PLL_CTL1, 0x00 }, 100 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 101 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 102 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 103 { CS42L42_PLL_DIV_INT, 0x40 }, 104 { CS42L42_PLL_CTL3, 0x10 }, 105 { CS42L42_PLL_CAL_RATIO, 0x80 }, 106 { CS42L42_PLL_CTL4, 0x03 }, 107 { CS42L42_LOAD_DET_RCSTAT, 0x00 }, 108 { CS42L42_LOAD_DET_DONE, 0x00 }, 109 { CS42L42_LOAD_DET_EN, 0x00 }, 110 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 111 { CS42L42_WAKE_CTL, 0xC0 }, 112 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 113 { CS42L42_TIPSENSE_CTL, 0x02 }, 114 { CS42L42_MISC_DET_CTL, 0x03 }, 115 { CS42L42_MIC_DET_CTL1, 0x1F }, 116 { CS42L42_MIC_DET_CTL2, 0x2F }, 117 { CS42L42_DET_STATUS1, 0x00 }, 118 { CS42L42_DET_STATUS2, 0x00 }, 119 { CS42L42_DET_INT1_MASK, 0xE0 }, 120 { CS42L42_DET_INT2_MASK, 0xFF }, 121 { CS42L42_HS_BIAS_CTL, 0xC2 }, 122 { CS42L42_ADC_CTL, 0x00 }, 123 { CS42L42_ADC_VOLUME, 0x00 }, 124 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 125 { CS42L42_DAC_CTL1, 0x00 }, 126 { CS42L42_DAC_CTL2, 0x02 }, 127 { CS42L42_HP_CTL, 0x0D }, 128 { CS42L42_CLASSH_CTL, 0x07 }, 129 { CS42L42_MIXER_CHA_VOL, 0x3F }, 130 { CS42L42_MIXER_ADC_VOL, 0x3F }, 131 { CS42L42_MIXER_CHB_VOL, 0x3F }, 132 { CS42L42_EQ_COEF_IN0, 0x22 }, 133 { CS42L42_EQ_COEF_IN1, 0x00 }, 134 { CS42L42_EQ_COEF_IN2, 0x00 }, 135 { CS42L42_EQ_COEF_IN3, 0x00 }, 136 { CS42L42_EQ_COEF_RW, 0x00 }, 137 { CS42L42_EQ_COEF_OUT0, 0x00 }, 138 { CS42L42_EQ_COEF_OUT1, 0x00 }, 139 { CS42L42_EQ_COEF_OUT2, 0x00 }, 140 { CS42L42_EQ_COEF_OUT3, 0x00 }, 141 { CS42L42_EQ_INIT_STAT, 0x00 }, 142 { CS42L42_EQ_START_FILT, 0x00 }, 143 { CS42L42_EQ_MUTE_CTL, 0x00 }, 144 { CS42L42_SP_RX_CH_SEL, 0x04 }, 145 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 146 { CS42L42_SP_RX_FS, 0x8C }, 147 { CS42l42_SPDIF_CH_SEL, 0x0E }, 148 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 149 { CS42L42_SP_TX_FS, 0xCC }, 150 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 151 { CS42L42_SRC_SDIN_FS, 0x40 }, 152 { CS42L42_SRC_SDOUT_FS, 0x40 }, 153 { CS42L42_SPDIF_CTL1, 0x01 }, 154 { CS42L42_SPDIF_CTL2, 0x00 }, 155 { CS42L42_SPDIF_CTL3, 0x00 }, 156 { CS42L42_SPDIF_CTL4, 0x42 }, 157 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 158 { CS42L42_ASP_TX_CH_EN, 0x00 }, 159 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 160 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 161 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 162 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 163 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 164 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 165 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 166 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 167 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 168 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 169 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 170 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 171 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 172 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 173 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 174 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 175 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 176 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 177 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 178 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 179 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 180 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 181 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 182 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 183 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 184 { CS42L42_SUB_REVID, 0x03 }, 185 }; 186 187 static bool cs42l42_readable_register(struct device *dev, unsigned int reg) 188 { 189 switch (reg) { 190 case CS42L42_PAGE_REGISTER: 191 case CS42L42_DEVID_AB: 192 case CS42L42_DEVID_CD: 193 case CS42L42_DEVID_E: 194 case CS42L42_FABID: 195 case CS42L42_REVID: 196 case CS42L42_FRZ_CTL: 197 case CS42L42_SRC_CTL: 198 case CS42L42_MCLK_STATUS: 199 case CS42L42_MCLK_CTL: 200 case CS42L42_SFTRAMP_RATE: 201 case CS42L42_I2C_DEBOUNCE: 202 case CS42L42_I2C_STRETCH: 203 case CS42L42_I2C_TIMEOUT: 204 case CS42L42_PWR_CTL1: 205 case CS42L42_PWR_CTL2: 206 case CS42L42_PWR_CTL3: 207 case CS42L42_RSENSE_CTL1: 208 case CS42L42_RSENSE_CTL2: 209 case CS42L42_OSC_SWITCH: 210 case CS42L42_OSC_SWITCH_STATUS: 211 case CS42L42_RSENSE_CTL3: 212 case CS42L42_TSENSE_CTL: 213 case CS42L42_TSRS_INT_DISABLE: 214 case CS42L42_TRSENSE_STATUS: 215 case CS42L42_HSDET_CTL1: 216 case CS42L42_HSDET_CTL2: 217 case CS42L42_HS_SWITCH_CTL: 218 case CS42L42_HS_DET_STATUS: 219 case CS42L42_HS_CLAMP_DISABLE: 220 case CS42L42_MCLK_SRC_SEL: 221 case CS42L42_SPDIF_CLK_CFG: 222 case CS42L42_FSYNC_PW_LOWER: 223 case CS42L42_FSYNC_PW_UPPER: 224 case CS42L42_FSYNC_P_LOWER: 225 case CS42L42_FSYNC_P_UPPER: 226 case CS42L42_ASP_CLK_CFG: 227 case CS42L42_ASP_FRM_CFG: 228 case CS42L42_FS_RATE_EN: 229 case CS42L42_IN_ASRC_CLK: 230 case CS42L42_OUT_ASRC_CLK: 231 case CS42L42_PLL_DIV_CFG1: 232 case CS42L42_ADC_OVFL_STATUS: 233 case CS42L42_MIXER_STATUS: 234 case CS42L42_SRC_STATUS: 235 case CS42L42_ASP_RX_STATUS: 236 case CS42L42_ASP_TX_STATUS: 237 case CS42L42_CODEC_STATUS: 238 case CS42L42_DET_INT_STATUS1: 239 case CS42L42_DET_INT_STATUS2: 240 case CS42L42_SRCPL_INT_STATUS: 241 case CS42L42_VPMON_STATUS: 242 case CS42L42_PLL_LOCK_STATUS: 243 case CS42L42_TSRS_PLUG_STATUS: 244 case CS42L42_ADC_OVFL_INT_MASK: 245 case CS42L42_MIXER_INT_MASK: 246 case CS42L42_SRC_INT_MASK: 247 case CS42L42_ASP_RX_INT_MASK: 248 case CS42L42_ASP_TX_INT_MASK: 249 case CS42L42_CODEC_INT_MASK: 250 case CS42L42_SRCPL_INT_MASK: 251 case CS42L42_VPMON_INT_MASK: 252 case CS42L42_PLL_LOCK_INT_MASK: 253 case CS42L42_TSRS_PLUG_INT_MASK: 254 case CS42L42_PLL_CTL1: 255 case CS42L42_PLL_DIV_FRAC0: 256 case CS42L42_PLL_DIV_FRAC1: 257 case CS42L42_PLL_DIV_FRAC2: 258 case CS42L42_PLL_DIV_INT: 259 case CS42L42_PLL_CTL3: 260 case CS42L42_PLL_CAL_RATIO: 261 case CS42L42_PLL_CTL4: 262 case CS42L42_LOAD_DET_RCSTAT: 263 case CS42L42_LOAD_DET_DONE: 264 case CS42L42_LOAD_DET_EN: 265 case CS42L42_HSBIAS_SC_AUTOCTL: 266 case CS42L42_WAKE_CTL: 267 case CS42L42_ADC_DISABLE_MUTE: 268 case CS42L42_TIPSENSE_CTL: 269 case CS42L42_MISC_DET_CTL: 270 case CS42L42_MIC_DET_CTL1: 271 case CS42L42_MIC_DET_CTL2: 272 case CS42L42_DET_STATUS1: 273 case CS42L42_DET_STATUS2: 274 case CS42L42_DET_INT1_MASK: 275 case CS42L42_DET_INT2_MASK: 276 case CS42L42_HS_BIAS_CTL: 277 case CS42L42_ADC_CTL: 278 case CS42L42_ADC_VOLUME: 279 case CS42L42_ADC_WNF_HPF_CTL: 280 case CS42L42_DAC_CTL1: 281 case CS42L42_DAC_CTL2: 282 case CS42L42_HP_CTL: 283 case CS42L42_CLASSH_CTL: 284 case CS42L42_MIXER_CHA_VOL: 285 case CS42L42_MIXER_ADC_VOL: 286 case CS42L42_MIXER_CHB_VOL: 287 case CS42L42_EQ_COEF_IN0: 288 case CS42L42_EQ_COEF_IN1: 289 case CS42L42_EQ_COEF_IN2: 290 case CS42L42_EQ_COEF_IN3: 291 case CS42L42_EQ_COEF_RW: 292 case CS42L42_EQ_COEF_OUT0: 293 case CS42L42_EQ_COEF_OUT1: 294 case CS42L42_EQ_COEF_OUT2: 295 case CS42L42_EQ_COEF_OUT3: 296 case CS42L42_EQ_INIT_STAT: 297 case CS42L42_EQ_START_FILT: 298 case CS42L42_EQ_MUTE_CTL: 299 case CS42L42_SP_RX_CH_SEL: 300 case CS42L42_SP_RX_ISOC_CTL: 301 case CS42L42_SP_RX_FS: 302 case CS42l42_SPDIF_CH_SEL: 303 case CS42L42_SP_TX_ISOC_CTL: 304 case CS42L42_SP_TX_FS: 305 case CS42L42_SPDIF_SW_CTL1: 306 case CS42L42_SRC_SDIN_FS: 307 case CS42L42_SRC_SDOUT_FS: 308 case CS42L42_SPDIF_CTL1: 309 case CS42L42_SPDIF_CTL2: 310 case CS42L42_SPDIF_CTL3: 311 case CS42L42_SPDIF_CTL4: 312 case CS42L42_ASP_TX_SZ_EN: 313 case CS42L42_ASP_TX_CH_EN: 314 case CS42L42_ASP_TX_CH_AP_RES: 315 case CS42L42_ASP_TX_CH1_BIT_MSB: 316 case CS42L42_ASP_TX_CH1_BIT_LSB: 317 case CS42L42_ASP_TX_HIZ_DLY_CFG: 318 case CS42L42_ASP_TX_CH2_BIT_MSB: 319 case CS42L42_ASP_TX_CH2_BIT_LSB: 320 case CS42L42_ASP_RX_DAI0_EN: 321 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 322 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 323 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 324 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 325 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 326 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 327 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 328 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 329 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 330 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 331 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 332 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 333 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 334 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 335 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 336 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 337 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 338 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 339 case CS42L42_SUB_REVID: 340 return true; 341 default: 342 return false; 343 } 344 } 345 346 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 347 { 348 switch (reg) { 349 case CS42L42_DEVID_AB: 350 case CS42L42_DEVID_CD: 351 case CS42L42_DEVID_E: 352 case CS42L42_MCLK_STATUS: 353 case CS42L42_TRSENSE_STATUS: 354 case CS42L42_HS_DET_STATUS: 355 case CS42L42_ADC_OVFL_STATUS: 356 case CS42L42_MIXER_STATUS: 357 case CS42L42_SRC_STATUS: 358 case CS42L42_ASP_RX_STATUS: 359 case CS42L42_ASP_TX_STATUS: 360 case CS42L42_CODEC_STATUS: 361 case CS42L42_DET_INT_STATUS1: 362 case CS42L42_DET_INT_STATUS2: 363 case CS42L42_SRCPL_INT_STATUS: 364 case CS42L42_VPMON_STATUS: 365 case CS42L42_PLL_LOCK_STATUS: 366 case CS42L42_TSRS_PLUG_STATUS: 367 case CS42L42_LOAD_DET_RCSTAT: 368 case CS42L42_LOAD_DET_DONE: 369 case CS42L42_DET_STATUS1: 370 case CS42L42_DET_STATUS2: 371 return true; 372 default: 373 return false; 374 } 375 } 376 377 static const struct regmap_range_cfg cs42l42_page_range = { 378 .name = "Pages", 379 .range_min = 0, 380 .range_max = CS42L42_MAX_REGISTER, 381 .selector_reg = CS42L42_PAGE_REGISTER, 382 .selector_mask = 0xff, 383 .selector_shift = 0, 384 .window_start = 0, 385 .window_len = 256, 386 }; 387 388 static const struct regmap_config cs42l42_regmap = { 389 .reg_bits = 8, 390 .val_bits = 8, 391 392 .readable_reg = cs42l42_readable_register, 393 .volatile_reg = cs42l42_volatile_register, 394 395 .ranges = &cs42l42_page_range, 396 .num_ranges = 1, 397 398 .max_register = CS42L42_MAX_REGISTER, 399 .reg_defaults = cs42l42_reg_defaults, 400 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 401 .cache_type = REGCACHE_RBTREE, 402 403 .use_single_read = true, 404 .use_single_write = true, 405 }; 406 407 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false); 408 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 409 410 static const char * const cs42l42_hpf_freq_text[] = { 411 "1.86Hz", "120Hz", "235Hz", "466Hz" 412 }; 413 414 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 415 CS42L42_ADC_HPF_CF_SHIFT, 416 cs42l42_hpf_freq_text); 417 418 static const char * const cs42l42_wnf3_freq_text[] = { 419 "160Hz", "180Hz", "200Hz", "220Hz", 420 "240Hz", "260Hz", "280Hz", "300Hz" 421 }; 422 423 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 424 CS42L42_ADC_WNF_CF_SHIFT, 425 cs42l42_wnf3_freq_text); 426 427 static const char * const cs42l42_wnf05_freq_text[] = { 428 "280Hz", "315Hz", "350Hz", "385Hz", 429 "420Hz", "455Hz", "490Hz", "525Hz" 430 }; 431 432 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 433 CS42L42_ADC_WNF_CF_SHIFT, 434 cs42l42_wnf05_freq_text); 435 436 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 437 /* ADC Volume and Filter Controls */ 438 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 439 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false), 440 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 441 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 442 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 443 CS42L42_ADC_INV_SHIFT, true, false), 444 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 445 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 446 SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME, 447 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv), 448 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 449 CS42L42_ADC_WNF_EN_SHIFT, true, false), 450 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 451 CS42L42_ADC_HPF_EN_SHIFT, true, false), 452 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 453 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 454 SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum), 455 456 /* DAC Volume and Filter Controls */ 457 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 458 CS42L42_DACA_INV_SHIFT, true, false), 459 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 460 CS42L42_DACB_INV_SHIFT, true, false), 461 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 462 CS42L42_DAC_HPF_EN_SHIFT, true, false), 463 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 464 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 465 0x3f, 1, mixer_tlv) 466 }; 467 468 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 469 /* Playback Path */ 470 SND_SOC_DAPM_OUTPUT("HP"), 471 SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1), 472 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 473 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH1_SHIFT, 0), 474 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH2_SHIFT, 0), 475 476 /* Playback Requirements */ 477 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 478 479 /* Capture Path */ 480 SND_SOC_DAPM_INPUT("HS"), 481 SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1), 482 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 483 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 484 485 /* Capture Requirements */ 486 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 487 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 488 489 /* Playback/Capture Requirements */ 490 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 491 }; 492 493 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 494 /* Playback Path */ 495 {"HP", NULL, "DAC"}, 496 {"DAC", NULL, "MIXER"}, 497 {"MIXER", NULL, "SDIN1"}, 498 {"MIXER", NULL, "SDIN2"}, 499 {"SDIN1", NULL, "Playback"}, 500 {"SDIN2", NULL, "Playback"}, 501 502 /* Playback Requirements */ 503 {"SDIN1", NULL, "ASP DAI0"}, 504 {"SDIN2", NULL, "ASP DAI0"}, 505 {"SDIN1", NULL, "SCLK"}, 506 {"SDIN2", NULL, "SCLK"}, 507 508 /* Capture Path */ 509 {"ADC", NULL, "HS"}, 510 { "SDOUT1", NULL, "ADC" }, 511 { "SDOUT2", NULL, "ADC" }, 512 { "Capture", NULL, "SDOUT1" }, 513 { "Capture", NULL, "SDOUT2" }, 514 515 /* Capture Requirements */ 516 { "SDOUT1", NULL, "ASP DAO0" }, 517 { "SDOUT2", NULL, "ASP DAO0" }, 518 { "SDOUT1", NULL, "SCLK" }, 519 { "SDOUT2", NULL, "SCLK" }, 520 { "SDOUT1", NULL, "ASP TX EN" }, 521 { "SDOUT2", NULL, "ASP TX EN" }, 522 }; 523 524 static int cs42l42_component_probe(struct snd_soc_component *component) 525 { 526 struct cs42l42_private *cs42l42 = 527 (struct cs42l42_private *)snd_soc_component_get_drvdata(component); 528 struct snd_soc_card *crd = component->card; 529 int ret = 0; 530 531 cs42l42->component = component; 532 533 ret = snd_soc_card_jack_new(crd, "CS42L42 Headset", SND_JACK_HEADSET | SND_JACK_BTN_0 | 534 SND_JACK_BTN_1 | SND_JACK_BTN_2 | SND_JACK_BTN_3, 535 &cs42l42->jack, NULL, 0); 536 if (ret < 0) 537 dev_err(component->dev, "Cannot create CS42L42 Headset: %d\n", ret); 538 539 return ret; 540 } 541 542 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = { 543 .probe = cs42l42_component_probe, 544 .dapm_widgets = cs42l42_dapm_widgets, 545 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 546 .dapm_routes = cs42l42_audio_map, 547 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 548 .controls = cs42l42_snd_controls, 549 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 550 .idle_bias_on = 1, 551 .endianness = 1, 552 .non_legacy_dai_naming = 1, 553 }; 554 555 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 556 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 557 { 558 .reg = CS42L42_OSC_SWITCH, 559 .def = CS42L42_SCLK_PRESENT_MASK, 560 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 561 }, 562 }; 563 564 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 565 static const struct reg_sequence cs42l42_to_osc_seq[] = { 566 { 567 .reg = CS42L42_OSC_SWITCH, 568 .def = 0, 569 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 570 }, 571 }; 572 573 struct cs42l42_pll_params { 574 u32 sclk; 575 u8 mclk_div; 576 u8 mclk_src_sel; 577 u8 sclk_prediv; 578 u8 pll_div_int; 579 u32 pll_div_frac; 580 u8 pll_mode; 581 u8 pll_divout; 582 u32 mclk_int; 583 u8 pll_cal_ratio; 584 }; 585 586 /* 587 * Common PLL Settings for given SCLK 588 * Table 4-5 from the Datasheet 589 */ 590 static const struct cs42l42_pll_params pll_ratio_table[] = { 591 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 }, 592 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 }, 593 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 }, 594 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 }, 595 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 }, 596 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 }, 597 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 }, 598 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 }, 599 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 }, 600 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 }, 601 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 }, 602 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 }, 603 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 }, 604 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 }, 605 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 } 606 }; 607 608 static int cs42l42_pll_config(struct snd_soc_component *component) 609 { 610 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 611 int i; 612 u32 clk; 613 u32 fsync; 614 615 if (!cs42l42->sclk) 616 clk = cs42l42->bclk; 617 else 618 clk = cs42l42->sclk; 619 620 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 621 if (pll_ratio_table[i].sclk == clk) { 622 /* Configure the internal sample rate */ 623 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 624 CS42L42_INTERNAL_FS_MASK, 625 ((pll_ratio_table[i].mclk_int != 626 12000000) && 627 (pll_ratio_table[i].mclk_int != 628 24000000)) << 629 CS42L42_INTERNAL_FS_SHIFT); 630 /* Set the MCLK src (PLL or SCLK) and the divide 631 * ratio 632 */ 633 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL, 634 CS42L42_MCLK_SRC_SEL_MASK | 635 CS42L42_MCLKDIV_MASK, 636 (pll_ratio_table[i].mclk_src_sel 637 << CS42L42_MCLK_SRC_SEL_SHIFT) | 638 (pll_ratio_table[i].mclk_div << 639 CS42L42_MCLKDIV_SHIFT)); 640 /* Set up the LRCLK */ 641 fsync = clk / cs42l42->srate; 642 if (((fsync * cs42l42->srate) != clk) 643 || ((fsync % 2) != 0)) { 644 dev_err(component->dev, 645 "Unsupported sclk %d/sample rate %d\n", 646 clk, 647 cs42l42->srate); 648 return -EINVAL; 649 } 650 /* Set the LRCLK period */ 651 snd_soc_component_update_bits(component, 652 CS42L42_FSYNC_P_LOWER, 653 CS42L42_FSYNC_PERIOD_MASK, 654 CS42L42_FRAC0_VAL(fsync - 1) << 655 CS42L42_FSYNC_PERIOD_SHIFT); 656 snd_soc_component_update_bits(component, 657 CS42L42_FSYNC_P_UPPER, 658 CS42L42_FSYNC_PERIOD_MASK, 659 CS42L42_FRAC1_VAL(fsync - 1) << 660 CS42L42_FSYNC_PERIOD_SHIFT); 661 /* Set the LRCLK to 50% duty cycle */ 662 fsync = fsync / 2; 663 snd_soc_component_update_bits(component, 664 CS42L42_FSYNC_PW_LOWER, 665 CS42L42_FSYNC_PULSE_WIDTH_MASK, 666 CS42L42_FRAC0_VAL(fsync - 1) << 667 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 668 snd_soc_component_update_bits(component, 669 CS42L42_FSYNC_PW_UPPER, 670 CS42L42_FSYNC_PULSE_WIDTH_MASK, 671 CS42L42_FRAC1_VAL(fsync - 1) << 672 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 673 snd_soc_component_update_bits(component, 674 CS42L42_ASP_FRM_CFG, 675 CS42L42_ASP_5050_MASK, 676 CS42L42_ASP_5050_MASK); 677 /* Set the frame delay to 1.0 SCLK clocks */ 678 snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG, 679 CS42L42_ASP_FSD_MASK, 680 CS42L42_ASP_FSD_1_0 << 681 CS42L42_ASP_FSD_SHIFT); 682 /* Set the sample rates (96k or lower) */ 683 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN, 684 CS42L42_FS_EN_MASK, 685 (CS42L42_FS_EN_IASRC_96K | 686 CS42L42_FS_EN_OASRC_96K) << 687 CS42L42_FS_EN_SHIFT); 688 /* Set the input/output internal MCLK clock ~12 MHz */ 689 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK, 690 CS42L42_CLK_IASRC_SEL_MASK, 691 CS42L42_CLK_IASRC_SEL_12 << 692 CS42L42_CLK_IASRC_SEL_SHIFT); 693 snd_soc_component_update_bits(component, 694 CS42L42_OUT_ASRC_CLK, 695 CS42L42_CLK_OASRC_SEL_MASK, 696 CS42L42_CLK_OASRC_SEL_12 << 697 CS42L42_CLK_OASRC_SEL_SHIFT); 698 if (pll_ratio_table[i].mclk_src_sel == 0) { 699 /* Pass the clock straight through */ 700 snd_soc_component_update_bits(component, 701 CS42L42_PLL_CTL1, 702 CS42L42_PLL_START_MASK, 0); 703 } else { 704 /* Configure PLL per table 4-5 */ 705 snd_soc_component_update_bits(component, 706 CS42L42_PLL_DIV_CFG1, 707 CS42L42_SCLK_PREDIV_MASK, 708 pll_ratio_table[i].sclk_prediv 709 << CS42L42_SCLK_PREDIV_SHIFT); 710 snd_soc_component_update_bits(component, 711 CS42L42_PLL_DIV_INT, 712 CS42L42_PLL_DIV_INT_MASK, 713 pll_ratio_table[i].pll_div_int 714 << CS42L42_PLL_DIV_INT_SHIFT); 715 snd_soc_component_update_bits(component, 716 CS42L42_PLL_DIV_FRAC0, 717 CS42L42_PLL_DIV_FRAC_MASK, 718 CS42L42_FRAC0_VAL( 719 pll_ratio_table[i].pll_div_frac) 720 << CS42L42_PLL_DIV_FRAC_SHIFT); 721 snd_soc_component_update_bits(component, 722 CS42L42_PLL_DIV_FRAC1, 723 CS42L42_PLL_DIV_FRAC_MASK, 724 CS42L42_FRAC1_VAL( 725 pll_ratio_table[i].pll_div_frac) 726 << CS42L42_PLL_DIV_FRAC_SHIFT); 727 snd_soc_component_update_bits(component, 728 CS42L42_PLL_DIV_FRAC2, 729 CS42L42_PLL_DIV_FRAC_MASK, 730 CS42L42_FRAC2_VAL( 731 pll_ratio_table[i].pll_div_frac) 732 << CS42L42_PLL_DIV_FRAC_SHIFT); 733 snd_soc_component_update_bits(component, 734 CS42L42_PLL_CTL4, 735 CS42L42_PLL_MODE_MASK, 736 pll_ratio_table[i].pll_mode 737 << CS42L42_PLL_MODE_SHIFT); 738 snd_soc_component_update_bits(component, 739 CS42L42_PLL_CTL3, 740 CS42L42_PLL_DIVOUT_MASK, 741 pll_ratio_table[i].pll_divout 742 << CS42L42_PLL_DIVOUT_SHIFT); 743 snd_soc_component_update_bits(component, 744 CS42L42_PLL_CAL_RATIO, 745 CS42L42_PLL_CAL_RATIO_MASK, 746 pll_ratio_table[i].pll_cal_ratio 747 << CS42L42_PLL_CAL_RATIO_SHIFT); 748 } 749 return 0; 750 } 751 } 752 753 return -EINVAL; 754 } 755 756 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 757 { 758 struct snd_soc_component *component = codec_dai->component; 759 u32 asp_cfg_val = 0; 760 761 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 762 case SND_SOC_DAIFMT_CBS_CFM: 763 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 764 CS42L42_ASP_MODE_SHIFT; 765 break; 766 case SND_SOC_DAIFMT_CBS_CFS: 767 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 768 CS42L42_ASP_MODE_SHIFT; 769 break; 770 default: 771 return -EINVAL; 772 } 773 774 /* interface format */ 775 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 776 case SND_SOC_DAIFMT_I2S: 777 case SND_SOC_DAIFMT_LEFT_J: 778 break; 779 default: 780 return -EINVAL; 781 } 782 783 /* Bitclock/frame inversion */ 784 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 785 case SND_SOC_DAIFMT_NB_NF: 786 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 787 break; 788 case SND_SOC_DAIFMT_NB_IF: 789 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 790 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 791 break; 792 case SND_SOC_DAIFMT_IB_NF: 793 break; 794 case SND_SOC_DAIFMT_IB_IF: 795 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 796 break; 797 } 798 799 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 800 CS42L42_ASP_SCPOL_MASK | 801 CS42L42_ASP_LCPOL_MASK, 802 asp_cfg_val); 803 804 return 0; 805 } 806 807 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 808 struct snd_pcm_hw_params *params, 809 struct snd_soc_dai *dai) 810 { 811 struct snd_soc_component *component = dai->component; 812 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 813 unsigned int channels = params_channels(params); 814 unsigned int width = (params_width(params) / 8) - 1; 815 unsigned int val = 0; 816 817 cs42l42->srate = params_rate(params); 818 cs42l42->bclk = snd_soc_params_to_bclk(params); 819 820 switch(substream->stream) { 821 case SNDRV_PCM_STREAM_CAPTURE: 822 if (channels == 2) { 823 val |= CS42L42_ASP_TX_CH2_AP_MASK; 824 val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT; 825 } 826 val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT; 827 828 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 829 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 830 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 831 break; 832 case SNDRV_PCM_STREAM_PLAYBACK: 833 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 834 /* channel 1 on low LRCLK */ 835 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 836 CS42L42_ASP_RX_CH_AP_MASK | 837 CS42L42_ASP_RX_CH_RES_MASK, val); 838 /* Channel 2 on high LRCLK */ 839 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 840 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 841 CS42L42_ASP_RX_CH_AP_MASK | 842 CS42L42_ASP_RX_CH_RES_MASK, val); 843 break; 844 default: 845 break; 846 } 847 848 return cs42l42_pll_config(component); 849 } 850 851 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 852 int clk_id, unsigned int freq, int dir) 853 { 854 struct snd_soc_component *component = dai->component; 855 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 856 857 cs42l42->sclk = freq; 858 859 return 0; 860 } 861 862 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 863 { 864 struct snd_soc_component *component = dai->component; 865 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 866 unsigned int regval; 867 u8 fullScaleVol; 868 int ret; 869 870 if (mute) { 871 /* Mute the headphone */ 872 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 873 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 874 CS42L42_HP_ANA_AMUTE_MASK | 875 CS42L42_HP_ANA_BMUTE_MASK, 876 CS42L42_HP_ANA_AMUTE_MASK | 877 CS42L42_HP_ANA_BMUTE_MASK); 878 879 cs42l42->stream_use &= ~(1 << stream); 880 if(!cs42l42->stream_use) { 881 /* 882 * Switch to the internal oscillator. 883 * SCLK must remain running until after this clock switch. 884 * Without a source of clock the I2C bus doesn't work. 885 */ 886 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 887 ARRAY_SIZE(cs42l42_to_osc_seq)); 888 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 889 CS42L42_PLL_START_MASK, 0); 890 } 891 } else { 892 if (!cs42l42->stream_use) { 893 /* SCLK must be running before codec unmute */ 894 if ((cs42l42->bclk < 11289600) && (cs42l42->sclk < 11289600)) { 895 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 896 CS42L42_PLL_START_MASK, 1); 897 ret = regmap_read_poll_timeout(cs42l42->regmap, 898 CS42L42_PLL_LOCK_STATUS, 899 regval, 900 (regval & 1), 901 CS42L42_PLL_LOCK_POLL_US, 902 CS42L42_PLL_LOCK_TIMEOUT_US); 903 if (ret < 0) 904 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 905 } 906 907 /* Mark SCLK as present, turn off internal oscillator */ 908 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 909 ARRAY_SIZE(cs42l42_to_sclk_seq)); 910 } 911 cs42l42->stream_use |= 1 << stream; 912 913 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 914 /* Read the headphone load */ 915 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT); 916 if (((regval & CS42L42_RLA_STAT_MASK) >> CS42L42_RLA_STAT_SHIFT) == 917 CS42L42_RLA_STAT_15_OHM) { 918 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK; 919 } else { 920 fullScaleVol = 0; 921 } 922 923 /* Un-mute the headphone, set the full scale volume flag */ 924 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 925 CS42L42_HP_ANA_AMUTE_MASK | 926 CS42L42_HP_ANA_BMUTE_MASK | 927 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol); 928 } 929 } 930 931 return 0; 932 } 933 934 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 935 SNDRV_PCM_FMTBIT_S24_LE |\ 936 SNDRV_PCM_FMTBIT_S32_LE ) 937 938 939 static const struct snd_soc_dai_ops cs42l42_ops = { 940 .hw_params = cs42l42_pcm_hw_params, 941 .set_fmt = cs42l42_set_dai_fmt, 942 .set_sysclk = cs42l42_set_sysclk, 943 .mute_stream = cs42l42_mute_stream, 944 }; 945 946 static struct snd_soc_dai_driver cs42l42_dai = { 947 .name = "cs42l42", 948 .playback = { 949 .stream_name = "Playback", 950 .channels_min = 1, 951 .channels_max = 2, 952 .rates = SNDRV_PCM_RATE_8000_192000, 953 .formats = CS42L42_FORMATS, 954 }, 955 .capture = { 956 .stream_name = "Capture", 957 .channels_min = 1, 958 .channels_max = 2, 959 .rates = SNDRV_PCM_RATE_8000_192000, 960 .formats = CS42L42_FORMATS, 961 }, 962 .symmetric_rate = 1, 963 .symmetric_sample_bits = 1, 964 .ops = &cs42l42_ops, 965 }; 966 967 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 968 { 969 unsigned int hs_det_status; 970 unsigned int int_status; 971 972 /* Mask the auto detect interrupt */ 973 regmap_update_bits(cs42l42->regmap, 974 CS42L42_CODEC_INT_MASK, 975 CS42L42_PDN_DONE_MASK | 976 CS42L42_HSDET_AUTO_DONE_MASK, 977 (1 << CS42L42_PDN_DONE_SHIFT) | 978 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 979 980 /* Set hs detect to automatic, disabled mode */ 981 regmap_update_bits(cs42l42->regmap, 982 CS42L42_HSDET_CTL2, 983 CS42L42_HSDET_CTRL_MASK | 984 CS42L42_HSDET_SET_MASK | 985 CS42L42_HSBIAS_REF_MASK | 986 CS42L42_HSDET_AUTO_TIME_MASK, 987 (2 << CS42L42_HSDET_CTRL_SHIFT) | 988 (2 << CS42L42_HSDET_SET_SHIFT) | 989 (0 << CS42L42_HSBIAS_REF_SHIFT) | 990 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 991 992 /* Read and save the hs detection result */ 993 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 994 995 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 996 CS42L42_HSDET_TYPE_SHIFT; 997 998 /* Set up button detection */ 999 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1000 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1001 /* Set auto HS bias settings to default */ 1002 regmap_update_bits(cs42l42->regmap, 1003 CS42L42_HSBIAS_SC_AUTOCTL, 1004 CS42L42_HSBIAS_SENSE_EN_MASK | 1005 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1006 CS42L42_TIP_SENSE_EN_MASK | 1007 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1008 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1009 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1010 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1011 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1012 1013 /* Set up hs detect level sensitivity */ 1014 regmap_update_bits(cs42l42->regmap, 1015 CS42L42_MIC_DET_CTL1, 1016 CS42L42_LATCH_TO_VP_MASK | 1017 CS42L42_EVENT_STAT_SEL_MASK | 1018 CS42L42_HS_DET_LEVEL_MASK, 1019 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1020 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1021 (cs42l42->bias_thresholds[0] << 1022 CS42L42_HS_DET_LEVEL_SHIFT)); 1023 1024 /* Set auto HS bias settings to default */ 1025 regmap_update_bits(cs42l42->regmap, 1026 CS42L42_HSBIAS_SC_AUTOCTL, 1027 CS42L42_HSBIAS_SENSE_EN_MASK | 1028 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1029 CS42L42_TIP_SENSE_EN_MASK | 1030 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1031 (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1032 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1033 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1034 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1035 1036 /* Turn on level detect circuitry */ 1037 regmap_update_bits(cs42l42->regmap, 1038 CS42L42_MISC_DET_CTL, 1039 CS42L42_DETECT_MODE_MASK | 1040 CS42L42_HSBIAS_CTL_MASK | 1041 CS42L42_PDN_MIC_LVL_DET_MASK, 1042 (0 << CS42L42_DETECT_MODE_SHIFT) | 1043 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1044 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1045 1046 msleep(cs42l42->btn_det_init_dbnce); 1047 1048 /* Clear any button interrupts before unmasking them */ 1049 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1050 &int_status); 1051 1052 /* Unmask button detect interrupts */ 1053 regmap_update_bits(cs42l42->regmap, 1054 CS42L42_DET_INT2_MASK, 1055 CS42L42_M_DETECT_TF_MASK | 1056 CS42L42_M_DETECT_FT_MASK | 1057 CS42L42_M_HSBIAS_HIZ_MASK | 1058 CS42L42_M_SHORT_RLS_MASK | 1059 CS42L42_M_SHORT_DET_MASK, 1060 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1061 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1062 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1063 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1064 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1065 } else { 1066 /* Make sure button detect and HS bias circuits are off */ 1067 regmap_update_bits(cs42l42->regmap, 1068 CS42L42_MISC_DET_CTL, 1069 CS42L42_DETECT_MODE_MASK | 1070 CS42L42_HSBIAS_CTL_MASK | 1071 CS42L42_PDN_MIC_LVL_DET_MASK, 1072 (0 << CS42L42_DETECT_MODE_SHIFT) | 1073 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1074 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1075 } 1076 1077 regmap_update_bits(cs42l42->regmap, 1078 CS42L42_DAC_CTL2, 1079 CS42L42_HPOUT_PULLDOWN_MASK | 1080 CS42L42_HPOUT_LOAD_MASK | 1081 CS42L42_HPOUT_CLAMP_MASK | 1082 CS42L42_DAC_HPF_EN_MASK | 1083 CS42L42_DAC_MON_EN_MASK, 1084 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1085 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1086 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1087 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1088 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1089 1090 /* Unmask tip sense interrupts */ 1091 regmap_update_bits(cs42l42->regmap, 1092 CS42L42_TSRS_PLUG_INT_MASK, 1093 CS42L42_RS_PLUG_MASK | 1094 CS42L42_RS_UNPLUG_MASK | 1095 CS42L42_TS_PLUG_MASK | 1096 CS42L42_TS_UNPLUG_MASK, 1097 (1 << CS42L42_RS_PLUG_SHIFT) | 1098 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1099 (0 << CS42L42_TS_PLUG_SHIFT) | 1100 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1101 } 1102 1103 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1104 { 1105 /* Mask tip sense interrupts */ 1106 regmap_update_bits(cs42l42->regmap, 1107 CS42L42_TSRS_PLUG_INT_MASK, 1108 CS42L42_RS_PLUG_MASK | 1109 CS42L42_RS_UNPLUG_MASK | 1110 CS42L42_TS_PLUG_MASK | 1111 CS42L42_TS_UNPLUG_MASK, 1112 (1 << CS42L42_RS_PLUG_SHIFT) | 1113 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1114 (1 << CS42L42_TS_PLUG_SHIFT) | 1115 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1116 1117 /* Make sure button detect and HS bias circuits are off */ 1118 regmap_update_bits(cs42l42->regmap, 1119 CS42L42_MISC_DET_CTL, 1120 CS42L42_DETECT_MODE_MASK | 1121 CS42L42_HSBIAS_CTL_MASK | 1122 CS42L42_PDN_MIC_LVL_DET_MASK, 1123 (0 << CS42L42_DETECT_MODE_SHIFT) | 1124 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1125 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1126 1127 /* Set auto HS bias settings to default */ 1128 regmap_update_bits(cs42l42->regmap, 1129 CS42L42_HSBIAS_SC_AUTOCTL, 1130 CS42L42_HSBIAS_SENSE_EN_MASK | 1131 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1132 CS42L42_TIP_SENSE_EN_MASK | 1133 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1134 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1135 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1136 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1137 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1138 1139 /* Set hs detect to manual, disabled mode */ 1140 regmap_update_bits(cs42l42->regmap, 1141 CS42L42_HSDET_CTL2, 1142 CS42L42_HSDET_CTRL_MASK | 1143 CS42L42_HSDET_SET_MASK | 1144 CS42L42_HSBIAS_REF_MASK | 1145 CS42L42_HSDET_AUTO_TIME_MASK, 1146 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1147 (2 << CS42L42_HSDET_SET_SHIFT) | 1148 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1149 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1150 1151 regmap_update_bits(cs42l42->regmap, 1152 CS42L42_DAC_CTL2, 1153 CS42L42_HPOUT_PULLDOWN_MASK | 1154 CS42L42_HPOUT_LOAD_MASK | 1155 CS42L42_HPOUT_CLAMP_MASK | 1156 CS42L42_DAC_HPF_EN_MASK | 1157 CS42L42_DAC_MON_EN_MASK, 1158 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1159 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1160 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1161 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1162 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1163 1164 /* Power up HS bias to 2.7V */ 1165 regmap_update_bits(cs42l42->regmap, 1166 CS42L42_MISC_DET_CTL, 1167 CS42L42_DETECT_MODE_MASK | 1168 CS42L42_HSBIAS_CTL_MASK | 1169 CS42L42_PDN_MIC_LVL_DET_MASK, 1170 (0 << CS42L42_DETECT_MODE_SHIFT) | 1171 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1172 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1173 1174 /* Wait for HS bias to ramp up */ 1175 msleep(cs42l42->hs_bias_ramp_time); 1176 1177 /* Unmask auto detect interrupt */ 1178 regmap_update_bits(cs42l42->regmap, 1179 CS42L42_CODEC_INT_MASK, 1180 CS42L42_PDN_DONE_MASK | 1181 CS42L42_HSDET_AUTO_DONE_MASK, 1182 (1 << CS42L42_PDN_DONE_SHIFT) | 1183 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1184 1185 /* Set hs detect to automatic, enabled mode */ 1186 regmap_update_bits(cs42l42->regmap, 1187 CS42L42_HSDET_CTL2, 1188 CS42L42_HSDET_CTRL_MASK | 1189 CS42L42_HSDET_SET_MASK | 1190 CS42L42_HSBIAS_REF_MASK | 1191 CS42L42_HSDET_AUTO_TIME_MASK, 1192 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1193 (2 << CS42L42_HSDET_SET_SHIFT) | 1194 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1195 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1196 } 1197 1198 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1199 { 1200 /* Mask button detect interrupts */ 1201 regmap_update_bits(cs42l42->regmap, 1202 CS42L42_DET_INT2_MASK, 1203 CS42L42_M_DETECT_TF_MASK | 1204 CS42L42_M_DETECT_FT_MASK | 1205 CS42L42_M_HSBIAS_HIZ_MASK | 1206 CS42L42_M_SHORT_RLS_MASK | 1207 CS42L42_M_SHORT_DET_MASK, 1208 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1209 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1210 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1211 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1212 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1213 1214 /* Ground HS bias */ 1215 regmap_update_bits(cs42l42->regmap, 1216 CS42L42_MISC_DET_CTL, 1217 CS42L42_DETECT_MODE_MASK | 1218 CS42L42_HSBIAS_CTL_MASK | 1219 CS42L42_PDN_MIC_LVL_DET_MASK, 1220 (0 << CS42L42_DETECT_MODE_SHIFT) | 1221 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1222 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1223 1224 /* Set auto HS bias settings to default */ 1225 regmap_update_bits(cs42l42->regmap, 1226 CS42L42_HSBIAS_SC_AUTOCTL, 1227 CS42L42_HSBIAS_SENSE_EN_MASK | 1228 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1229 CS42L42_TIP_SENSE_EN_MASK | 1230 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1231 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1232 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1233 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1234 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1235 1236 /* Set hs detect to manual, disabled mode */ 1237 regmap_update_bits(cs42l42->regmap, 1238 CS42L42_HSDET_CTL2, 1239 CS42L42_HSDET_CTRL_MASK | 1240 CS42L42_HSDET_SET_MASK | 1241 CS42L42_HSBIAS_REF_MASK | 1242 CS42L42_HSDET_AUTO_TIME_MASK, 1243 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1244 (2 << CS42L42_HSDET_SET_SHIFT) | 1245 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1246 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1247 } 1248 1249 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1250 { 1251 int bias_level; 1252 unsigned int detect_status; 1253 1254 /* Mask button detect interrupts */ 1255 regmap_update_bits(cs42l42->regmap, 1256 CS42L42_DET_INT2_MASK, 1257 CS42L42_M_DETECT_TF_MASK | 1258 CS42L42_M_DETECT_FT_MASK | 1259 CS42L42_M_HSBIAS_HIZ_MASK | 1260 CS42L42_M_SHORT_RLS_MASK | 1261 CS42L42_M_SHORT_DET_MASK, 1262 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1263 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1264 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1265 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1266 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1267 1268 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1269 cs42l42->btn_det_event_dbnce * 2000); 1270 1271 /* Test all 4 level detect biases */ 1272 bias_level = 1; 1273 do { 1274 /* Adjust button detect level sensitivity */ 1275 regmap_update_bits(cs42l42->regmap, 1276 CS42L42_MIC_DET_CTL1, 1277 CS42L42_LATCH_TO_VP_MASK | 1278 CS42L42_EVENT_STAT_SEL_MASK | 1279 CS42L42_HS_DET_LEVEL_MASK, 1280 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1281 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1282 (cs42l42->bias_thresholds[bias_level] << 1283 CS42L42_HS_DET_LEVEL_SHIFT)); 1284 1285 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1286 &detect_status); 1287 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1288 (++bias_level < CS42L42_NUM_BIASES)); 1289 1290 switch (bias_level) { 1291 case 1: /* Function C button press */ 1292 bias_level = SND_JACK_BTN_2; 1293 dev_dbg(cs42l42->component->dev, "Function C button press\n"); 1294 break; 1295 case 2: /* Function B button press */ 1296 bias_level = SND_JACK_BTN_1; 1297 dev_dbg(cs42l42->component->dev, "Function B button press\n"); 1298 break; 1299 case 3: /* Function D button press */ 1300 bias_level = SND_JACK_BTN_3; 1301 dev_dbg(cs42l42->component->dev, "Function D button press\n"); 1302 break; 1303 case 4: /* Function A button press */ 1304 bias_level = SND_JACK_BTN_0; 1305 dev_dbg(cs42l42->component->dev, "Function A button press\n"); 1306 break; 1307 default: 1308 bias_level = 0; 1309 break; 1310 } 1311 1312 /* Set button detect level sensitivity back to default */ 1313 regmap_update_bits(cs42l42->regmap, 1314 CS42L42_MIC_DET_CTL1, 1315 CS42L42_LATCH_TO_VP_MASK | 1316 CS42L42_EVENT_STAT_SEL_MASK | 1317 CS42L42_HS_DET_LEVEL_MASK, 1318 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1319 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1320 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1321 1322 /* Clear any button interrupts before unmasking them */ 1323 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1324 &detect_status); 1325 1326 /* Unmask button detect interrupts */ 1327 regmap_update_bits(cs42l42->regmap, 1328 CS42L42_DET_INT2_MASK, 1329 CS42L42_M_DETECT_TF_MASK | 1330 CS42L42_M_DETECT_FT_MASK | 1331 CS42L42_M_HSBIAS_HIZ_MASK | 1332 CS42L42_M_SHORT_RLS_MASK | 1333 CS42L42_M_SHORT_DET_MASK, 1334 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1335 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1336 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1337 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1338 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1339 1340 return bias_level; 1341 } 1342 1343 struct cs42l42_irq_params { 1344 u16 status_addr; 1345 u16 mask_addr; 1346 u8 mask; 1347 }; 1348 1349 static const struct cs42l42_irq_params irq_params_table[] = { 1350 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1351 CS42L42_ADC_OVFL_VAL_MASK}, 1352 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1353 CS42L42_MIXER_VAL_MASK}, 1354 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1355 CS42L42_SRC_VAL_MASK}, 1356 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1357 CS42L42_ASP_RX_VAL_MASK}, 1358 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1359 CS42L42_ASP_TX_VAL_MASK}, 1360 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1361 CS42L42_CODEC_VAL_MASK}, 1362 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1363 CS42L42_DET_INT_VAL1_MASK}, 1364 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1365 CS42L42_DET_INT_VAL2_MASK}, 1366 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1367 CS42L42_SRCPL_VAL_MASK}, 1368 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1369 CS42L42_VPMON_VAL_MASK}, 1370 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1371 CS42L42_PLL_LOCK_VAL_MASK}, 1372 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1373 CS42L42_TSRS_PLUG_VAL_MASK} 1374 }; 1375 1376 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1377 { 1378 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1379 struct snd_soc_component *component = cs42l42->component; 1380 unsigned int stickies[12]; 1381 unsigned int masks[12]; 1382 unsigned int current_plug_status; 1383 unsigned int current_button_status; 1384 unsigned int i; 1385 int report = 0; 1386 1387 1388 /* Read sticky registers to clear interurpt */ 1389 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1390 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1391 &(stickies[i])); 1392 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1393 &(masks[i])); 1394 stickies[i] = stickies[i] & (~masks[i]) & 1395 irq_params_table[i].mask; 1396 } 1397 1398 /* Read tip sense status before handling type detect */ 1399 current_plug_status = (stickies[11] & 1400 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1401 CS42L42_TS_PLUG_SHIFT; 1402 1403 /* Read button sense status */ 1404 current_button_status = stickies[7] & 1405 (CS42L42_M_DETECT_TF_MASK | 1406 CS42L42_M_DETECT_FT_MASK | 1407 CS42L42_M_HSBIAS_HIZ_MASK); 1408 1409 /* Check auto-detect status */ 1410 if ((~masks[5]) & irq_params_table[5].mask) { 1411 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1412 cs42l42_process_hs_type_detect(cs42l42); 1413 switch(cs42l42->hs_type){ 1414 case CS42L42_PLUG_CTIA: 1415 case CS42L42_PLUG_OMTP: 1416 snd_soc_jack_report(&cs42l42->jack, SND_JACK_HEADSET, 1417 SND_JACK_HEADSET); 1418 break; 1419 case CS42L42_PLUG_HEADPHONE: 1420 snd_soc_jack_report(&cs42l42->jack, SND_JACK_HEADPHONE, 1421 SND_JACK_HEADPHONE); 1422 break; 1423 default: 1424 break; 1425 } 1426 dev_dbg(component->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1427 } 1428 } 1429 1430 /* Check tip sense status */ 1431 if ((~masks[11]) & irq_params_table[11].mask) { 1432 switch (current_plug_status) { 1433 case CS42L42_TS_PLUG: 1434 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1435 cs42l42->plug_state = CS42L42_TS_PLUG; 1436 cs42l42_init_hs_type_detect(cs42l42); 1437 } 1438 break; 1439 1440 case CS42L42_TS_UNPLUG: 1441 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1442 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1443 cs42l42_cancel_hs_type_detect(cs42l42); 1444 1445 switch(cs42l42->hs_type){ 1446 case CS42L42_PLUG_CTIA: 1447 case CS42L42_PLUG_OMTP: 1448 snd_soc_jack_report(&cs42l42->jack, 0, SND_JACK_HEADSET); 1449 break; 1450 case CS42L42_PLUG_HEADPHONE: 1451 snd_soc_jack_report(&cs42l42->jack, 0, SND_JACK_HEADPHONE); 1452 break; 1453 default: 1454 break; 1455 } 1456 dev_dbg(component->dev, "Unplug event\n"); 1457 } 1458 break; 1459 1460 default: 1461 if (cs42l42->plug_state != CS42L42_TS_TRANS) 1462 cs42l42->plug_state = CS42L42_TS_TRANS; 1463 } 1464 } 1465 1466 /* Check button detect status */ 1467 if ((~masks[7]) & irq_params_table[7].mask) { 1468 if (!(current_button_status & 1469 CS42L42_M_HSBIAS_HIZ_MASK)) { 1470 1471 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1472 dev_dbg(component->dev, "Button released\n"); 1473 report = 0; 1474 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1475 report = cs42l42_handle_button_press(cs42l42); 1476 1477 } 1478 snd_soc_jack_report(&cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1479 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1480 } 1481 } 1482 1483 return IRQ_HANDLED; 1484 } 1485 1486 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1487 { 1488 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1489 CS42L42_ADC_OVFL_MASK, 1490 (1 << CS42L42_ADC_OVFL_SHIFT)); 1491 1492 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1493 CS42L42_MIX_CHB_OVFL_MASK | 1494 CS42L42_MIX_CHA_OVFL_MASK | 1495 CS42L42_EQ_OVFL_MASK | 1496 CS42L42_EQ_BIQUAD_OVFL_MASK, 1497 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1498 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1499 (1 << CS42L42_EQ_OVFL_SHIFT) | 1500 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1501 1502 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1503 CS42L42_SRC_ILK_MASK | 1504 CS42L42_SRC_OLK_MASK | 1505 CS42L42_SRC_IUNLK_MASK | 1506 CS42L42_SRC_OUNLK_MASK, 1507 (1 << CS42L42_SRC_ILK_SHIFT) | 1508 (1 << CS42L42_SRC_OLK_SHIFT) | 1509 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1510 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1511 1512 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1513 CS42L42_ASPRX_NOLRCK_MASK | 1514 CS42L42_ASPRX_EARLY_MASK | 1515 CS42L42_ASPRX_LATE_MASK | 1516 CS42L42_ASPRX_ERROR_MASK | 1517 CS42L42_ASPRX_OVLD_MASK, 1518 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1519 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1520 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1521 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1522 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1523 1524 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1525 CS42L42_ASPTX_NOLRCK_MASK | 1526 CS42L42_ASPTX_EARLY_MASK | 1527 CS42L42_ASPTX_LATE_MASK | 1528 CS42L42_ASPTX_SMERROR_MASK, 1529 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1530 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1531 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1532 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1533 1534 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1535 CS42L42_PDN_DONE_MASK | 1536 CS42L42_HSDET_AUTO_DONE_MASK, 1537 (1 << CS42L42_PDN_DONE_SHIFT) | 1538 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1539 1540 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1541 CS42L42_SRCPL_ADC_LK_MASK | 1542 CS42L42_SRCPL_DAC_LK_MASK | 1543 CS42L42_SRCPL_ADC_UNLK_MASK | 1544 CS42L42_SRCPL_DAC_UNLK_MASK, 1545 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1546 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1547 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1548 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1549 1550 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1551 CS42L42_TIP_SENSE_UNPLUG_MASK | 1552 CS42L42_TIP_SENSE_PLUG_MASK | 1553 CS42L42_HSBIAS_SENSE_MASK, 1554 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1555 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1556 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1557 1558 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1559 CS42L42_M_DETECT_TF_MASK | 1560 CS42L42_M_DETECT_FT_MASK | 1561 CS42L42_M_HSBIAS_HIZ_MASK | 1562 CS42L42_M_SHORT_RLS_MASK | 1563 CS42L42_M_SHORT_DET_MASK, 1564 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1565 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1566 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1567 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1568 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1569 1570 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1571 CS42L42_VPMON_MASK, 1572 (1 << CS42L42_VPMON_SHIFT)); 1573 1574 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1575 CS42L42_PLL_LOCK_MASK, 1576 (1 << CS42L42_PLL_LOCK_SHIFT)); 1577 1578 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1579 CS42L42_RS_PLUG_MASK | 1580 CS42L42_RS_UNPLUG_MASK | 1581 CS42L42_TS_PLUG_MASK | 1582 CS42L42_TS_UNPLUG_MASK, 1583 (1 << CS42L42_RS_PLUG_SHIFT) | 1584 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1585 (0 << CS42L42_TS_PLUG_SHIFT) | 1586 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1587 } 1588 1589 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1590 { 1591 unsigned int reg; 1592 1593 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1594 1595 /* Latch analog controls to VP power domain */ 1596 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1597 CS42L42_LATCH_TO_VP_MASK | 1598 CS42L42_EVENT_STAT_SEL_MASK | 1599 CS42L42_HS_DET_LEVEL_MASK, 1600 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1601 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1602 (cs42l42->bias_thresholds[0] << 1603 CS42L42_HS_DET_LEVEL_SHIFT)); 1604 1605 /* Remove ground noise-suppression clamps */ 1606 regmap_update_bits(cs42l42->regmap, 1607 CS42L42_HS_CLAMP_DISABLE, 1608 CS42L42_HS_CLAMP_DISABLE_MASK, 1609 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1610 1611 /* Enable the tip sense circuit */ 1612 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1613 CS42L42_TIP_SENSE_CTRL_MASK | 1614 CS42L42_TIP_SENSE_INV_MASK | 1615 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1616 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1617 (0 << CS42L42_TIP_SENSE_INV_SHIFT) | 1618 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1619 1620 /* Save the initial status of the tip sense */ 1621 regmap_read(cs42l42->regmap, 1622 CS42L42_TSRS_PLUG_STATUS, 1623 ®); 1624 cs42l42->plug_state = (((char) reg) & 1625 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1626 CS42L42_TS_PLUG_SHIFT; 1627 } 1628 1629 static const unsigned int threshold_defaults[] = { 1630 CS42L42_HS_DET_LEVEL_15, 1631 CS42L42_HS_DET_LEVEL_8, 1632 CS42L42_HS_DET_LEVEL_4, 1633 CS42L42_HS_DET_LEVEL_1 1634 }; 1635 1636 static int cs42l42_handle_device_data(struct i2c_client *i2c_client, 1637 struct cs42l42_private *cs42l42) 1638 { 1639 struct device_node *np = i2c_client->dev.of_node; 1640 unsigned int val; 1641 unsigned int thresholds[CS42L42_NUM_BIASES]; 1642 int ret; 1643 int i; 1644 1645 ret = of_property_read_u32(np, "cirrus,ts-inv", &val); 1646 1647 if (!ret) { 1648 switch (val) { 1649 case CS42L42_TS_INV_EN: 1650 case CS42L42_TS_INV_DIS: 1651 cs42l42->ts_inv = val; 1652 break; 1653 default: 1654 dev_err(&i2c_client->dev, 1655 "Wrong cirrus,ts-inv DT value %d\n", 1656 val); 1657 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1658 } 1659 } else { 1660 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1661 } 1662 1663 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1664 CS42L42_TS_INV_MASK, 1665 (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT)); 1666 1667 ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val); 1668 1669 if (!ret) { 1670 switch (val) { 1671 case CS42L42_TS_DBNCE_0: 1672 case CS42L42_TS_DBNCE_125: 1673 case CS42L42_TS_DBNCE_250: 1674 case CS42L42_TS_DBNCE_500: 1675 case CS42L42_TS_DBNCE_750: 1676 case CS42L42_TS_DBNCE_1000: 1677 case CS42L42_TS_DBNCE_1250: 1678 case CS42L42_TS_DBNCE_1500: 1679 cs42l42->ts_dbnc_rise = val; 1680 break; 1681 default: 1682 dev_err(&i2c_client->dev, 1683 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1684 val); 1685 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1686 } 1687 } else { 1688 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1689 } 1690 1691 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1692 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1693 (cs42l42->ts_dbnc_rise << 1694 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1695 1696 ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val); 1697 1698 if (!ret) { 1699 switch (val) { 1700 case CS42L42_TS_DBNCE_0: 1701 case CS42L42_TS_DBNCE_125: 1702 case CS42L42_TS_DBNCE_250: 1703 case CS42L42_TS_DBNCE_500: 1704 case CS42L42_TS_DBNCE_750: 1705 case CS42L42_TS_DBNCE_1000: 1706 case CS42L42_TS_DBNCE_1250: 1707 case CS42L42_TS_DBNCE_1500: 1708 cs42l42->ts_dbnc_fall = val; 1709 break; 1710 default: 1711 dev_err(&i2c_client->dev, 1712 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1713 val); 1714 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1715 } 1716 } else { 1717 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1718 } 1719 1720 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1721 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1722 (cs42l42->ts_dbnc_fall << 1723 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1724 1725 ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val); 1726 1727 if (!ret) { 1728 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1729 cs42l42->btn_det_init_dbnce = val; 1730 else { 1731 dev_err(&i2c_client->dev, 1732 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1733 val); 1734 cs42l42->btn_det_init_dbnce = 1735 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1736 } 1737 } else { 1738 cs42l42->btn_det_init_dbnce = 1739 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1740 } 1741 1742 ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val); 1743 1744 if (!ret) { 1745 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 1746 cs42l42->btn_det_event_dbnce = val; 1747 else { 1748 dev_err(&i2c_client->dev, 1749 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 1750 cs42l42->btn_det_event_dbnce = 1751 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1752 } 1753 } else { 1754 cs42l42->btn_det_event_dbnce = 1755 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1756 } 1757 1758 ret = of_property_read_u32_array(np, "cirrus,bias-lvls", 1759 (u32 *)thresholds, CS42L42_NUM_BIASES); 1760 1761 if (!ret) { 1762 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 1763 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 1764 cs42l42->bias_thresholds[i] = thresholds[i]; 1765 else { 1766 dev_err(&i2c_client->dev, 1767 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 1768 thresholds[i]); 1769 cs42l42->bias_thresholds[i] = 1770 threshold_defaults[i]; 1771 } 1772 } 1773 } else { 1774 for (i = 0; i < CS42L42_NUM_BIASES; i++) 1775 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1776 } 1777 1778 ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val); 1779 1780 if (!ret) { 1781 switch (val) { 1782 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 1783 cs42l42->hs_bias_ramp_rate = val; 1784 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 1785 break; 1786 case CS42L42_HSBIAS_RAMP_FAST: 1787 cs42l42->hs_bias_ramp_rate = val; 1788 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 1789 break; 1790 case CS42L42_HSBIAS_RAMP_SLOW: 1791 cs42l42->hs_bias_ramp_rate = val; 1792 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1793 break; 1794 case CS42L42_HSBIAS_RAMP_SLOWEST: 1795 cs42l42->hs_bias_ramp_rate = val; 1796 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 1797 break; 1798 default: 1799 dev_err(&i2c_client->dev, 1800 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 1801 val); 1802 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1803 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1804 } 1805 } else { 1806 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1807 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1808 } 1809 1810 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 1811 CS42L42_HSBIAS_RAMP_MASK, 1812 (cs42l42->hs_bias_ramp_rate << 1813 CS42L42_HSBIAS_RAMP_SHIFT)); 1814 1815 return 0; 1816 } 1817 1818 static int cs42l42_i2c_probe(struct i2c_client *i2c_client, 1819 const struct i2c_device_id *id) 1820 { 1821 struct cs42l42_private *cs42l42; 1822 int ret, i; 1823 unsigned int devid = 0; 1824 unsigned int reg; 1825 1826 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private), 1827 GFP_KERNEL); 1828 if (!cs42l42) 1829 return -ENOMEM; 1830 1831 i2c_set_clientdata(i2c_client, cs42l42); 1832 1833 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap); 1834 if (IS_ERR(cs42l42->regmap)) { 1835 ret = PTR_ERR(cs42l42->regmap); 1836 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1837 return ret; 1838 } 1839 1840 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 1841 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 1842 1843 ret = devm_regulator_bulk_get(&i2c_client->dev, 1844 ARRAY_SIZE(cs42l42->supplies), 1845 cs42l42->supplies); 1846 if (ret != 0) { 1847 dev_err(&i2c_client->dev, 1848 "Failed to request supplies: %d\n", ret); 1849 return ret; 1850 } 1851 1852 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1853 cs42l42->supplies); 1854 if (ret != 0) { 1855 dev_err(&i2c_client->dev, 1856 "Failed to enable supplies: %d\n", ret); 1857 return ret; 1858 } 1859 1860 /* Reset the Device */ 1861 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 1862 "reset", GPIOD_OUT_LOW); 1863 if (IS_ERR(cs42l42->reset_gpio)) { 1864 ret = PTR_ERR(cs42l42->reset_gpio); 1865 goto err_disable; 1866 } 1867 1868 if (cs42l42->reset_gpio) { 1869 dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); 1870 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1871 } 1872 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 1873 1874 /* Request IRQ */ 1875 ret = devm_request_threaded_irq(&i2c_client->dev, 1876 i2c_client->irq, 1877 NULL, cs42l42_irq_thread, 1878 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 1879 "cs42l42", cs42l42); 1880 1881 if (ret != 0) 1882 dev_err(&i2c_client->dev, 1883 "Failed to request IRQ: %d\n", ret); 1884 1885 /* initialize codec */ 1886 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, ®); 1887 devid = (reg & 0xFF) << 12; 1888 1889 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, ®); 1890 devid |= (reg & 0xFF) << 4; 1891 1892 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, ®); 1893 devid |= (reg & 0xF0) >> 4; 1894 1895 if (devid != CS42L42_CHIP_ID) { 1896 ret = -ENODEV; 1897 dev_err(&i2c_client->dev, 1898 "CS42L42 Device ID (%X). Expected %X\n", 1899 devid, CS42L42_CHIP_ID); 1900 goto err_disable; 1901 } 1902 1903 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 1904 if (ret < 0) { 1905 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1906 goto err_disable; 1907 } 1908 1909 dev_info(&i2c_client->dev, 1910 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); 1911 1912 /* Power up the codec */ 1913 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 1914 CS42L42_ASP_DAO_PDN_MASK | 1915 CS42L42_ASP_DAI_PDN_MASK | 1916 CS42L42_MIXER_PDN_MASK | 1917 CS42L42_EQ_PDN_MASK | 1918 CS42L42_HP_PDN_MASK | 1919 CS42L42_ADC_PDN_MASK | 1920 CS42L42_PDN_ALL_MASK, 1921 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 1922 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 1923 (1 << CS42L42_MIXER_PDN_SHIFT) | 1924 (1 << CS42L42_EQ_PDN_SHIFT) | 1925 (1 << CS42L42_HP_PDN_SHIFT) | 1926 (1 << CS42L42_ADC_PDN_SHIFT) | 1927 (0 << CS42L42_PDN_ALL_SHIFT)); 1928 1929 if (i2c_client->dev.of_node) { 1930 ret = cs42l42_handle_device_data(i2c_client, cs42l42); 1931 if (ret != 0) 1932 goto err_disable; 1933 } 1934 1935 /* Setup headset detection */ 1936 cs42l42_setup_hs_type_detect(cs42l42); 1937 1938 /* Mask/Unmask Interrupts */ 1939 cs42l42_set_interrupt_masks(cs42l42); 1940 1941 /* Register codec for machine driver */ 1942 ret = devm_snd_soc_register_component(&i2c_client->dev, 1943 &soc_component_dev_cs42l42, &cs42l42_dai, 1); 1944 if (ret < 0) 1945 goto err_disable; 1946 return 0; 1947 1948 err_disable: 1949 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1950 cs42l42->supplies); 1951 return ret; 1952 } 1953 1954 static int cs42l42_i2c_remove(struct i2c_client *i2c_client) 1955 { 1956 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client); 1957 1958 devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42); 1959 pm_runtime_suspend(&i2c_client->dev); 1960 pm_runtime_disable(&i2c_client->dev); 1961 1962 return 0; 1963 } 1964 1965 #ifdef CONFIG_PM 1966 static int cs42l42_runtime_suspend(struct device *dev) 1967 { 1968 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1969 1970 regcache_cache_only(cs42l42->regmap, true); 1971 regcache_mark_dirty(cs42l42->regmap); 1972 1973 /* Hold down reset */ 1974 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 1975 1976 /* remove power */ 1977 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1978 cs42l42->supplies); 1979 1980 return 0; 1981 } 1982 1983 static int cs42l42_runtime_resume(struct device *dev) 1984 { 1985 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1986 int ret; 1987 1988 /* Enable power */ 1989 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1990 cs42l42->supplies); 1991 if (ret != 0) { 1992 dev_err(dev, "Failed to enable supplies: %d\n", 1993 ret); 1994 return ret; 1995 } 1996 1997 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1998 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 1999 2000 regcache_cache_only(cs42l42->regmap, false); 2001 regcache_sync(cs42l42->regmap); 2002 2003 return 0; 2004 } 2005 #endif 2006 2007 static const struct dev_pm_ops cs42l42_runtime_pm = { 2008 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume, 2009 NULL) 2010 }; 2011 2012 static const struct of_device_id cs42l42_of_match[] = { 2013 { .compatible = "cirrus,cs42l42", }, 2014 {}, 2015 }; 2016 MODULE_DEVICE_TABLE(of, cs42l42_of_match); 2017 2018 2019 static const struct i2c_device_id cs42l42_id[] = { 2020 {"cs42l42", 0}, 2021 {} 2022 }; 2023 2024 MODULE_DEVICE_TABLE(i2c, cs42l42_id); 2025 2026 static struct i2c_driver cs42l42_i2c_driver = { 2027 .driver = { 2028 .name = "cs42l42", 2029 .pm = &cs42l42_runtime_pm, 2030 .of_match_table = cs42l42_of_match, 2031 }, 2032 .id_table = cs42l42_id, 2033 .probe = cs42l42_i2c_probe, 2034 .remove = cs42l42_i2c_remove, 2035 }; 2036 2037 module_i2c_driver(cs42l42_i2c_driver); 2038 2039 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2040 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2041 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2042 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2043 MODULE_LICENSE("GPL"); 2044