1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/i2c.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/acpi.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/of_device.h> 28 #include <linux/pm_runtime.h> 29 #include <sound/core.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc.h> 33 #include <sound/soc-dapm.h> 34 #include <sound/initval.h> 35 #include <sound/tlv.h> 36 #include <dt-bindings/sound/cs42l42.h> 37 38 #include "cs42l42.h" 39 #include "cirrus_legacy.h" 40 41 static const struct reg_default cs42l42_reg_defaults[] = { 42 { CS42L42_FRZ_CTL, 0x00 }, 43 { CS42L42_SRC_CTL, 0x10 }, 44 { CS42L42_MCLK_STATUS, 0x02 }, 45 { CS42L42_MCLK_CTL, 0x02 }, 46 { CS42L42_SFTRAMP_RATE, 0xA4 }, 47 { CS42L42_I2C_DEBOUNCE, 0x88 }, 48 { CS42L42_I2C_STRETCH, 0x03 }, 49 { CS42L42_I2C_TIMEOUT, 0xB7 }, 50 { CS42L42_PWR_CTL1, 0xFF }, 51 { CS42L42_PWR_CTL2, 0x84 }, 52 { CS42L42_PWR_CTL3, 0x20 }, 53 { CS42L42_RSENSE_CTL1, 0x40 }, 54 { CS42L42_RSENSE_CTL2, 0x00 }, 55 { CS42L42_OSC_SWITCH, 0x00 }, 56 { CS42L42_OSC_SWITCH_STATUS, 0x05 }, 57 { CS42L42_RSENSE_CTL3, 0x1B }, 58 { CS42L42_TSENSE_CTL, 0x1B }, 59 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 60 { CS42L42_TRSENSE_STATUS, 0x00 }, 61 { CS42L42_HSDET_CTL1, 0x77 }, 62 { CS42L42_HSDET_CTL2, 0x00 }, 63 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 64 { CS42L42_HS_DET_STATUS, 0x00 }, 65 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 66 { CS42L42_MCLK_SRC_SEL, 0x00 }, 67 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 68 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 69 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 70 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 71 { CS42L42_FSYNC_P_UPPER, 0x00 }, 72 { CS42L42_ASP_CLK_CFG, 0x00 }, 73 { CS42L42_ASP_FRM_CFG, 0x10 }, 74 { CS42L42_FS_RATE_EN, 0x00 }, 75 { CS42L42_IN_ASRC_CLK, 0x00 }, 76 { CS42L42_OUT_ASRC_CLK, 0x00 }, 77 { CS42L42_PLL_DIV_CFG1, 0x00 }, 78 { CS42L42_ADC_OVFL_STATUS, 0x00 }, 79 { CS42L42_MIXER_STATUS, 0x00 }, 80 { CS42L42_SRC_STATUS, 0x00 }, 81 { CS42L42_ASP_RX_STATUS, 0x00 }, 82 { CS42L42_ASP_TX_STATUS, 0x00 }, 83 { CS42L42_CODEC_STATUS, 0x00 }, 84 { CS42L42_DET_INT_STATUS1, 0x00 }, 85 { CS42L42_DET_INT_STATUS2, 0x00 }, 86 { CS42L42_SRCPL_INT_STATUS, 0x00 }, 87 { CS42L42_VPMON_STATUS, 0x00 }, 88 { CS42L42_PLL_LOCK_STATUS, 0x00 }, 89 { CS42L42_TSRS_PLUG_STATUS, 0x00 }, 90 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 91 { CS42L42_MIXER_INT_MASK, 0x0F }, 92 { CS42L42_SRC_INT_MASK, 0x0F }, 93 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 94 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 95 { CS42L42_CODEC_INT_MASK, 0x03 }, 96 { CS42L42_SRCPL_INT_MASK, 0xFF }, 97 { CS42L42_VPMON_INT_MASK, 0x01 }, 98 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 99 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 100 { CS42L42_PLL_CTL1, 0x00 }, 101 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 102 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 103 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 104 { CS42L42_PLL_DIV_INT, 0x40 }, 105 { CS42L42_PLL_CTL3, 0x10 }, 106 { CS42L42_PLL_CAL_RATIO, 0x80 }, 107 { CS42L42_PLL_CTL4, 0x03 }, 108 { CS42L42_LOAD_DET_RCSTAT, 0x00 }, 109 { CS42L42_LOAD_DET_DONE, 0x00 }, 110 { CS42L42_LOAD_DET_EN, 0x00 }, 111 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 112 { CS42L42_WAKE_CTL, 0xC0 }, 113 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 114 { CS42L42_TIPSENSE_CTL, 0x02 }, 115 { CS42L42_MISC_DET_CTL, 0x03 }, 116 { CS42L42_MIC_DET_CTL1, 0x1F }, 117 { CS42L42_MIC_DET_CTL2, 0x2F }, 118 { CS42L42_DET_STATUS1, 0x00 }, 119 { CS42L42_DET_STATUS2, 0x00 }, 120 { CS42L42_DET_INT1_MASK, 0xE0 }, 121 { CS42L42_DET_INT2_MASK, 0xFF }, 122 { CS42L42_HS_BIAS_CTL, 0xC2 }, 123 { CS42L42_ADC_CTL, 0x00 }, 124 { CS42L42_ADC_VOLUME, 0x00 }, 125 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 126 { CS42L42_DAC_CTL1, 0x00 }, 127 { CS42L42_DAC_CTL2, 0x02 }, 128 { CS42L42_HP_CTL, 0x0D }, 129 { CS42L42_CLASSH_CTL, 0x07 }, 130 { CS42L42_MIXER_CHA_VOL, 0x3F }, 131 { CS42L42_MIXER_ADC_VOL, 0x3F }, 132 { CS42L42_MIXER_CHB_VOL, 0x3F }, 133 { CS42L42_EQ_COEF_IN0, 0x22 }, 134 { CS42L42_EQ_COEF_IN1, 0x00 }, 135 { CS42L42_EQ_COEF_IN2, 0x00 }, 136 { CS42L42_EQ_COEF_IN3, 0x00 }, 137 { CS42L42_EQ_COEF_RW, 0x00 }, 138 { CS42L42_EQ_COEF_OUT0, 0x00 }, 139 { CS42L42_EQ_COEF_OUT1, 0x00 }, 140 { CS42L42_EQ_COEF_OUT2, 0x00 }, 141 { CS42L42_EQ_COEF_OUT3, 0x00 }, 142 { CS42L42_EQ_INIT_STAT, 0x00 }, 143 { CS42L42_EQ_START_FILT, 0x00 }, 144 { CS42L42_EQ_MUTE_CTL, 0x00 }, 145 { CS42L42_SP_RX_CH_SEL, 0x04 }, 146 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 147 { CS42L42_SP_RX_FS, 0x8C }, 148 { CS42l42_SPDIF_CH_SEL, 0x0E }, 149 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 150 { CS42L42_SP_TX_FS, 0xCC }, 151 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 152 { CS42L42_SRC_SDIN_FS, 0x40 }, 153 { CS42L42_SRC_SDOUT_FS, 0x40 }, 154 { CS42L42_SPDIF_CTL1, 0x01 }, 155 { CS42L42_SPDIF_CTL2, 0x00 }, 156 { CS42L42_SPDIF_CTL3, 0x00 }, 157 { CS42L42_SPDIF_CTL4, 0x42 }, 158 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 159 { CS42L42_ASP_TX_CH_EN, 0x00 }, 160 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 161 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 162 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 163 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 164 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 165 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 166 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 167 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 168 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 169 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 170 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 171 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 172 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 173 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 174 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 175 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 176 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 177 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 178 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 179 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 180 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 181 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 182 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 183 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 184 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 185 { CS42L42_SUB_REVID, 0x03 }, 186 }; 187 188 static bool cs42l42_readable_register(struct device *dev, unsigned int reg) 189 { 190 switch (reg) { 191 case CS42L42_PAGE_REGISTER: 192 case CS42L42_DEVID_AB: 193 case CS42L42_DEVID_CD: 194 case CS42L42_DEVID_E: 195 case CS42L42_FABID: 196 case CS42L42_REVID: 197 case CS42L42_FRZ_CTL: 198 case CS42L42_SRC_CTL: 199 case CS42L42_MCLK_STATUS: 200 case CS42L42_MCLK_CTL: 201 case CS42L42_SFTRAMP_RATE: 202 case CS42L42_I2C_DEBOUNCE: 203 case CS42L42_I2C_STRETCH: 204 case CS42L42_I2C_TIMEOUT: 205 case CS42L42_PWR_CTL1: 206 case CS42L42_PWR_CTL2: 207 case CS42L42_PWR_CTL3: 208 case CS42L42_RSENSE_CTL1: 209 case CS42L42_RSENSE_CTL2: 210 case CS42L42_OSC_SWITCH: 211 case CS42L42_OSC_SWITCH_STATUS: 212 case CS42L42_RSENSE_CTL3: 213 case CS42L42_TSENSE_CTL: 214 case CS42L42_TSRS_INT_DISABLE: 215 case CS42L42_TRSENSE_STATUS: 216 case CS42L42_HSDET_CTL1: 217 case CS42L42_HSDET_CTL2: 218 case CS42L42_HS_SWITCH_CTL: 219 case CS42L42_HS_DET_STATUS: 220 case CS42L42_HS_CLAMP_DISABLE: 221 case CS42L42_MCLK_SRC_SEL: 222 case CS42L42_SPDIF_CLK_CFG: 223 case CS42L42_FSYNC_PW_LOWER: 224 case CS42L42_FSYNC_PW_UPPER: 225 case CS42L42_FSYNC_P_LOWER: 226 case CS42L42_FSYNC_P_UPPER: 227 case CS42L42_ASP_CLK_CFG: 228 case CS42L42_ASP_FRM_CFG: 229 case CS42L42_FS_RATE_EN: 230 case CS42L42_IN_ASRC_CLK: 231 case CS42L42_OUT_ASRC_CLK: 232 case CS42L42_PLL_DIV_CFG1: 233 case CS42L42_ADC_OVFL_STATUS: 234 case CS42L42_MIXER_STATUS: 235 case CS42L42_SRC_STATUS: 236 case CS42L42_ASP_RX_STATUS: 237 case CS42L42_ASP_TX_STATUS: 238 case CS42L42_CODEC_STATUS: 239 case CS42L42_DET_INT_STATUS1: 240 case CS42L42_DET_INT_STATUS2: 241 case CS42L42_SRCPL_INT_STATUS: 242 case CS42L42_VPMON_STATUS: 243 case CS42L42_PLL_LOCK_STATUS: 244 case CS42L42_TSRS_PLUG_STATUS: 245 case CS42L42_ADC_OVFL_INT_MASK: 246 case CS42L42_MIXER_INT_MASK: 247 case CS42L42_SRC_INT_MASK: 248 case CS42L42_ASP_RX_INT_MASK: 249 case CS42L42_ASP_TX_INT_MASK: 250 case CS42L42_CODEC_INT_MASK: 251 case CS42L42_SRCPL_INT_MASK: 252 case CS42L42_VPMON_INT_MASK: 253 case CS42L42_PLL_LOCK_INT_MASK: 254 case CS42L42_TSRS_PLUG_INT_MASK: 255 case CS42L42_PLL_CTL1: 256 case CS42L42_PLL_DIV_FRAC0: 257 case CS42L42_PLL_DIV_FRAC1: 258 case CS42L42_PLL_DIV_FRAC2: 259 case CS42L42_PLL_DIV_INT: 260 case CS42L42_PLL_CTL3: 261 case CS42L42_PLL_CAL_RATIO: 262 case CS42L42_PLL_CTL4: 263 case CS42L42_LOAD_DET_RCSTAT: 264 case CS42L42_LOAD_DET_DONE: 265 case CS42L42_LOAD_DET_EN: 266 case CS42L42_HSBIAS_SC_AUTOCTL: 267 case CS42L42_WAKE_CTL: 268 case CS42L42_ADC_DISABLE_MUTE: 269 case CS42L42_TIPSENSE_CTL: 270 case CS42L42_MISC_DET_CTL: 271 case CS42L42_MIC_DET_CTL1: 272 case CS42L42_MIC_DET_CTL2: 273 case CS42L42_DET_STATUS1: 274 case CS42L42_DET_STATUS2: 275 case CS42L42_DET_INT1_MASK: 276 case CS42L42_DET_INT2_MASK: 277 case CS42L42_HS_BIAS_CTL: 278 case CS42L42_ADC_CTL: 279 case CS42L42_ADC_VOLUME: 280 case CS42L42_ADC_WNF_HPF_CTL: 281 case CS42L42_DAC_CTL1: 282 case CS42L42_DAC_CTL2: 283 case CS42L42_HP_CTL: 284 case CS42L42_CLASSH_CTL: 285 case CS42L42_MIXER_CHA_VOL: 286 case CS42L42_MIXER_ADC_VOL: 287 case CS42L42_MIXER_CHB_VOL: 288 case CS42L42_EQ_COEF_IN0: 289 case CS42L42_EQ_COEF_IN1: 290 case CS42L42_EQ_COEF_IN2: 291 case CS42L42_EQ_COEF_IN3: 292 case CS42L42_EQ_COEF_RW: 293 case CS42L42_EQ_COEF_OUT0: 294 case CS42L42_EQ_COEF_OUT1: 295 case CS42L42_EQ_COEF_OUT2: 296 case CS42L42_EQ_COEF_OUT3: 297 case CS42L42_EQ_INIT_STAT: 298 case CS42L42_EQ_START_FILT: 299 case CS42L42_EQ_MUTE_CTL: 300 case CS42L42_SP_RX_CH_SEL: 301 case CS42L42_SP_RX_ISOC_CTL: 302 case CS42L42_SP_RX_FS: 303 case CS42l42_SPDIF_CH_SEL: 304 case CS42L42_SP_TX_ISOC_CTL: 305 case CS42L42_SP_TX_FS: 306 case CS42L42_SPDIF_SW_CTL1: 307 case CS42L42_SRC_SDIN_FS: 308 case CS42L42_SRC_SDOUT_FS: 309 case CS42L42_SPDIF_CTL1: 310 case CS42L42_SPDIF_CTL2: 311 case CS42L42_SPDIF_CTL3: 312 case CS42L42_SPDIF_CTL4: 313 case CS42L42_ASP_TX_SZ_EN: 314 case CS42L42_ASP_TX_CH_EN: 315 case CS42L42_ASP_TX_CH_AP_RES: 316 case CS42L42_ASP_TX_CH1_BIT_MSB: 317 case CS42L42_ASP_TX_CH1_BIT_LSB: 318 case CS42L42_ASP_TX_HIZ_DLY_CFG: 319 case CS42L42_ASP_TX_CH2_BIT_MSB: 320 case CS42L42_ASP_TX_CH2_BIT_LSB: 321 case CS42L42_ASP_RX_DAI0_EN: 322 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 323 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 324 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 325 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 326 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 327 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 328 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 329 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 330 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 331 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 332 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 333 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 334 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 335 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 336 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 337 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 338 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 339 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 340 case CS42L42_SUB_REVID: 341 return true; 342 default: 343 return false; 344 } 345 } 346 347 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 348 { 349 switch (reg) { 350 case CS42L42_DEVID_AB: 351 case CS42L42_DEVID_CD: 352 case CS42L42_DEVID_E: 353 case CS42L42_MCLK_STATUS: 354 case CS42L42_TRSENSE_STATUS: 355 case CS42L42_HS_DET_STATUS: 356 case CS42L42_ADC_OVFL_STATUS: 357 case CS42L42_MIXER_STATUS: 358 case CS42L42_SRC_STATUS: 359 case CS42L42_ASP_RX_STATUS: 360 case CS42L42_ASP_TX_STATUS: 361 case CS42L42_CODEC_STATUS: 362 case CS42L42_DET_INT_STATUS1: 363 case CS42L42_DET_INT_STATUS2: 364 case CS42L42_SRCPL_INT_STATUS: 365 case CS42L42_VPMON_STATUS: 366 case CS42L42_PLL_LOCK_STATUS: 367 case CS42L42_TSRS_PLUG_STATUS: 368 case CS42L42_LOAD_DET_RCSTAT: 369 case CS42L42_LOAD_DET_DONE: 370 case CS42L42_DET_STATUS1: 371 case CS42L42_DET_STATUS2: 372 return true; 373 default: 374 return false; 375 } 376 } 377 378 static const struct regmap_range_cfg cs42l42_page_range = { 379 .name = "Pages", 380 .range_min = 0, 381 .range_max = CS42L42_MAX_REGISTER, 382 .selector_reg = CS42L42_PAGE_REGISTER, 383 .selector_mask = 0xff, 384 .selector_shift = 0, 385 .window_start = 0, 386 .window_len = 256, 387 }; 388 389 static const struct regmap_config cs42l42_regmap = { 390 .reg_bits = 8, 391 .val_bits = 8, 392 393 .readable_reg = cs42l42_readable_register, 394 .volatile_reg = cs42l42_volatile_register, 395 396 .ranges = &cs42l42_page_range, 397 .num_ranges = 1, 398 399 .max_register = CS42L42_MAX_REGISTER, 400 .reg_defaults = cs42l42_reg_defaults, 401 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 402 .cache_type = REGCACHE_RBTREE, 403 404 .use_single_read = true, 405 .use_single_write = true, 406 }; 407 408 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false); 409 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 410 411 static const char * const cs42l42_hpf_freq_text[] = { 412 "1.86Hz", "120Hz", "235Hz", "466Hz" 413 }; 414 415 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 416 CS42L42_ADC_HPF_CF_SHIFT, 417 cs42l42_hpf_freq_text); 418 419 static const char * const cs42l42_wnf3_freq_text[] = { 420 "160Hz", "180Hz", "200Hz", "220Hz", 421 "240Hz", "260Hz", "280Hz", "300Hz" 422 }; 423 424 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 425 CS42L42_ADC_WNF_CF_SHIFT, 426 cs42l42_wnf3_freq_text); 427 428 static const char * const cs42l42_wnf05_freq_text[] = { 429 "280Hz", "315Hz", "350Hz", "385Hz", 430 "420Hz", "455Hz", "490Hz", "525Hz" 431 }; 432 433 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 434 CS42L42_ADC_WNF_CF_SHIFT, 435 cs42l42_wnf05_freq_text); 436 437 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 438 /* ADC Volume and Filter Controls */ 439 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 440 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false), 441 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 442 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 443 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 444 CS42L42_ADC_INV_SHIFT, true, false), 445 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 446 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 447 SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME, 448 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv), 449 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 450 CS42L42_ADC_WNF_EN_SHIFT, true, false), 451 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 452 CS42L42_ADC_HPF_EN_SHIFT, true, false), 453 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 454 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 455 SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum), 456 457 /* DAC Volume and Filter Controls */ 458 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 459 CS42L42_DACA_INV_SHIFT, true, false), 460 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 461 CS42L42_DACB_INV_SHIFT, true, false), 462 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 463 CS42L42_DAC_HPF_EN_SHIFT, true, false), 464 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 465 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 466 0x3f, 1, mixer_tlv) 467 }; 468 469 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 470 /* Playback Path */ 471 SND_SOC_DAPM_OUTPUT("HP"), 472 SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1), 473 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 474 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH1_SHIFT, 0), 475 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH2_SHIFT, 0), 476 477 /* Playback Requirements */ 478 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 479 480 /* Capture Path */ 481 SND_SOC_DAPM_INPUT("HS"), 482 SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1), 483 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 484 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 485 486 /* Capture Requirements */ 487 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 488 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 489 490 /* Playback/Capture Requirements */ 491 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 492 }; 493 494 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 495 /* Playback Path */ 496 {"HP", NULL, "DAC"}, 497 {"DAC", NULL, "MIXER"}, 498 {"MIXER", NULL, "SDIN1"}, 499 {"MIXER", NULL, "SDIN2"}, 500 {"SDIN1", NULL, "Playback"}, 501 {"SDIN2", NULL, "Playback"}, 502 503 /* Playback Requirements */ 504 {"SDIN1", NULL, "ASP DAI0"}, 505 {"SDIN2", NULL, "ASP DAI0"}, 506 {"SDIN1", NULL, "SCLK"}, 507 {"SDIN2", NULL, "SCLK"}, 508 509 /* Capture Path */ 510 {"ADC", NULL, "HS"}, 511 { "SDOUT1", NULL, "ADC" }, 512 { "SDOUT2", NULL, "ADC" }, 513 { "Capture", NULL, "SDOUT1" }, 514 { "Capture", NULL, "SDOUT2" }, 515 516 /* Capture Requirements */ 517 { "SDOUT1", NULL, "ASP DAO0" }, 518 { "SDOUT2", NULL, "ASP DAO0" }, 519 { "SDOUT1", NULL, "SCLK" }, 520 { "SDOUT2", NULL, "SCLK" }, 521 { "SDOUT1", NULL, "ASP TX EN" }, 522 { "SDOUT2", NULL, "ASP TX EN" }, 523 }; 524 525 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) 526 { 527 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 528 529 cs42l42->jack = jk; 530 531 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 532 CS42L42_RS_PLUG_MASK | CS42L42_RS_UNPLUG_MASK | 533 CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK, 534 (1 << CS42L42_RS_PLUG_SHIFT) | (1 << CS42L42_RS_UNPLUG_SHIFT) | 535 (0 << CS42L42_TS_PLUG_SHIFT) | (0 << CS42L42_TS_UNPLUG_SHIFT)); 536 537 return 0; 538 } 539 540 static int cs42l42_component_probe(struct snd_soc_component *component) 541 { 542 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 543 544 cs42l42->component = component; 545 546 return 0; 547 } 548 549 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = { 550 .probe = cs42l42_component_probe, 551 .set_jack = cs42l42_set_jack, 552 .dapm_widgets = cs42l42_dapm_widgets, 553 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 554 .dapm_routes = cs42l42_audio_map, 555 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 556 .controls = cs42l42_snd_controls, 557 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 558 .idle_bias_on = 1, 559 .endianness = 1, 560 .non_legacy_dai_naming = 1, 561 }; 562 563 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 564 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 565 { 566 .reg = CS42L42_OSC_SWITCH, 567 .def = CS42L42_SCLK_PRESENT_MASK, 568 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 569 }, 570 }; 571 572 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 573 static const struct reg_sequence cs42l42_to_osc_seq[] = { 574 { 575 .reg = CS42L42_OSC_SWITCH, 576 .def = 0, 577 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 578 }, 579 }; 580 581 struct cs42l42_pll_params { 582 u32 sclk; 583 u8 mclk_div; 584 u8 mclk_src_sel; 585 u8 sclk_prediv; 586 u8 pll_div_int; 587 u32 pll_div_frac; 588 u8 pll_mode; 589 u8 pll_divout; 590 u32 mclk_int; 591 u8 pll_cal_ratio; 592 u8 n; 593 }; 594 595 /* 596 * Common PLL Settings for given SCLK 597 * Table 4-5 from the Datasheet 598 */ 599 static const struct cs42l42_pll_params pll_ratio_table[] = { 600 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2}, 601 { 2304000, 0, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2}, 602 { 2400000, 0, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 603 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 604 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 605 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 606 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1}, 607 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1}, 608 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 609 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 610 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 611 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0, 1}, 612 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0, 1}, 613 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0, 1}, 614 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0, 1}, 615 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0, 1}, 616 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0, 1} 617 }; 618 619 static int cs42l42_pll_config(struct snd_soc_component *component) 620 { 621 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 622 int i; 623 u32 clk; 624 u32 fsync; 625 626 if (!cs42l42->sclk) 627 clk = cs42l42->bclk; 628 else 629 clk = cs42l42->sclk; 630 631 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 632 if (pll_ratio_table[i].sclk == clk) { 633 /* Configure the internal sample rate */ 634 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 635 CS42L42_INTERNAL_FS_MASK, 636 ((pll_ratio_table[i].mclk_int != 637 12000000) && 638 (pll_ratio_table[i].mclk_int != 639 24000000)) << 640 CS42L42_INTERNAL_FS_SHIFT); 641 /* Set the MCLK src (PLL or SCLK) and the divide 642 * ratio 643 */ 644 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL, 645 CS42L42_MCLK_SRC_SEL_MASK | 646 CS42L42_MCLKDIV_MASK, 647 (pll_ratio_table[i].mclk_src_sel 648 << CS42L42_MCLK_SRC_SEL_SHIFT) | 649 (pll_ratio_table[i].mclk_div << 650 CS42L42_MCLKDIV_SHIFT)); 651 /* Set up the LRCLK */ 652 fsync = clk / cs42l42->srate; 653 if (((fsync * cs42l42->srate) != clk) 654 || ((fsync % 2) != 0)) { 655 dev_err(component->dev, 656 "Unsupported sclk %d/sample rate %d\n", 657 clk, 658 cs42l42->srate); 659 return -EINVAL; 660 } 661 /* Set the LRCLK period */ 662 snd_soc_component_update_bits(component, 663 CS42L42_FSYNC_P_LOWER, 664 CS42L42_FSYNC_PERIOD_MASK, 665 CS42L42_FRAC0_VAL(fsync - 1) << 666 CS42L42_FSYNC_PERIOD_SHIFT); 667 snd_soc_component_update_bits(component, 668 CS42L42_FSYNC_P_UPPER, 669 CS42L42_FSYNC_PERIOD_MASK, 670 CS42L42_FRAC1_VAL(fsync - 1) << 671 CS42L42_FSYNC_PERIOD_SHIFT); 672 /* Set the LRCLK to 50% duty cycle */ 673 fsync = fsync / 2; 674 snd_soc_component_update_bits(component, 675 CS42L42_FSYNC_PW_LOWER, 676 CS42L42_FSYNC_PULSE_WIDTH_MASK, 677 CS42L42_FRAC0_VAL(fsync - 1) << 678 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 679 snd_soc_component_update_bits(component, 680 CS42L42_FSYNC_PW_UPPER, 681 CS42L42_FSYNC_PULSE_WIDTH_MASK, 682 CS42L42_FRAC1_VAL(fsync - 1) << 683 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 684 snd_soc_component_update_bits(component, 685 CS42L42_ASP_FRM_CFG, 686 CS42L42_ASP_5050_MASK, 687 CS42L42_ASP_5050_MASK); 688 /* Set the frame delay to 1.0 SCLK clocks */ 689 snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG, 690 CS42L42_ASP_FSD_MASK, 691 CS42L42_ASP_FSD_1_0 << 692 CS42L42_ASP_FSD_SHIFT); 693 /* Set the sample rates (96k or lower) */ 694 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN, 695 CS42L42_FS_EN_MASK, 696 (CS42L42_FS_EN_IASRC_96K | 697 CS42L42_FS_EN_OASRC_96K) << 698 CS42L42_FS_EN_SHIFT); 699 /* Set the input/output internal MCLK clock ~12 MHz */ 700 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK, 701 CS42L42_CLK_IASRC_SEL_MASK, 702 CS42L42_CLK_IASRC_SEL_12 << 703 CS42L42_CLK_IASRC_SEL_SHIFT); 704 snd_soc_component_update_bits(component, 705 CS42L42_OUT_ASRC_CLK, 706 CS42L42_CLK_OASRC_SEL_MASK, 707 CS42L42_CLK_OASRC_SEL_12 << 708 CS42L42_CLK_OASRC_SEL_SHIFT); 709 if (pll_ratio_table[i].mclk_src_sel == 0) { 710 /* Pass the clock straight through */ 711 snd_soc_component_update_bits(component, 712 CS42L42_PLL_CTL1, 713 CS42L42_PLL_START_MASK, 0); 714 } else { 715 /* Configure PLL per table 4-5 */ 716 snd_soc_component_update_bits(component, 717 CS42L42_PLL_DIV_CFG1, 718 CS42L42_SCLK_PREDIV_MASK, 719 pll_ratio_table[i].sclk_prediv 720 << CS42L42_SCLK_PREDIV_SHIFT); 721 snd_soc_component_update_bits(component, 722 CS42L42_PLL_DIV_INT, 723 CS42L42_PLL_DIV_INT_MASK, 724 pll_ratio_table[i].pll_div_int 725 << CS42L42_PLL_DIV_INT_SHIFT); 726 snd_soc_component_update_bits(component, 727 CS42L42_PLL_DIV_FRAC0, 728 CS42L42_PLL_DIV_FRAC_MASK, 729 CS42L42_FRAC0_VAL( 730 pll_ratio_table[i].pll_div_frac) 731 << CS42L42_PLL_DIV_FRAC_SHIFT); 732 snd_soc_component_update_bits(component, 733 CS42L42_PLL_DIV_FRAC1, 734 CS42L42_PLL_DIV_FRAC_MASK, 735 CS42L42_FRAC1_VAL( 736 pll_ratio_table[i].pll_div_frac) 737 << CS42L42_PLL_DIV_FRAC_SHIFT); 738 snd_soc_component_update_bits(component, 739 CS42L42_PLL_DIV_FRAC2, 740 CS42L42_PLL_DIV_FRAC_MASK, 741 CS42L42_FRAC2_VAL( 742 pll_ratio_table[i].pll_div_frac) 743 << CS42L42_PLL_DIV_FRAC_SHIFT); 744 snd_soc_component_update_bits(component, 745 CS42L42_PLL_CTL4, 746 CS42L42_PLL_MODE_MASK, 747 pll_ratio_table[i].pll_mode 748 << CS42L42_PLL_MODE_SHIFT); 749 snd_soc_component_update_bits(component, 750 CS42L42_PLL_CTL3, 751 CS42L42_PLL_DIVOUT_MASK, 752 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n) 753 << CS42L42_PLL_DIVOUT_SHIFT); 754 if (pll_ratio_table[i].n != 1) 755 cs42l42->pll_divout = pll_ratio_table[i].pll_divout; 756 else 757 cs42l42->pll_divout = 0; 758 snd_soc_component_update_bits(component, 759 CS42L42_PLL_CAL_RATIO, 760 CS42L42_PLL_CAL_RATIO_MASK, 761 pll_ratio_table[i].pll_cal_ratio 762 << CS42L42_PLL_CAL_RATIO_SHIFT); 763 } 764 return 0; 765 } 766 } 767 768 return -EINVAL; 769 } 770 771 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 772 { 773 struct snd_soc_component *component = codec_dai->component; 774 u32 asp_cfg_val = 0; 775 776 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 777 case SND_SOC_DAIFMT_CBS_CFM: 778 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 779 CS42L42_ASP_MODE_SHIFT; 780 break; 781 case SND_SOC_DAIFMT_CBS_CFS: 782 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 783 CS42L42_ASP_MODE_SHIFT; 784 break; 785 default: 786 return -EINVAL; 787 } 788 789 /* interface format */ 790 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 791 case SND_SOC_DAIFMT_I2S: 792 case SND_SOC_DAIFMT_LEFT_J: 793 break; 794 default: 795 return -EINVAL; 796 } 797 798 /* Bitclock/frame inversion */ 799 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 800 case SND_SOC_DAIFMT_NB_NF: 801 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 802 break; 803 case SND_SOC_DAIFMT_NB_IF: 804 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 805 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 806 break; 807 case SND_SOC_DAIFMT_IB_NF: 808 break; 809 case SND_SOC_DAIFMT_IB_IF: 810 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 811 break; 812 } 813 814 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 815 CS42L42_ASP_SCPOL_MASK | 816 CS42L42_ASP_LCPOL_MASK, 817 asp_cfg_val); 818 819 return 0; 820 } 821 822 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 823 struct snd_pcm_hw_params *params, 824 struct snd_soc_dai *dai) 825 { 826 struct snd_soc_component *component = dai->component; 827 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 828 unsigned int channels = params_channels(params); 829 unsigned int width = (params_width(params) / 8) - 1; 830 unsigned int val = 0; 831 832 cs42l42->srate = params_rate(params); 833 cs42l42->bclk = snd_soc_params_to_bclk(params); 834 835 switch(substream->stream) { 836 case SNDRV_PCM_STREAM_CAPTURE: 837 if (channels == 2) { 838 val |= CS42L42_ASP_TX_CH2_AP_MASK; 839 val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT; 840 } 841 val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT; 842 843 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 844 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 845 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 846 break; 847 case SNDRV_PCM_STREAM_PLAYBACK: 848 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 849 /* channel 1 on low LRCLK */ 850 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 851 CS42L42_ASP_RX_CH_AP_MASK | 852 CS42L42_ASP_RX_CH_RES_MASK, val); 853 /* Channel 2 on high LRCLK */ 854 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 855 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 856 CS42L42_ASP_RX_CH_AP_MASK | 857 CS42L42_ASP_RX_CH_RES_MASK, val); 858 break; 859 default: 860 break; 861 } 862 863 return cs42l42_pll_config(component); 864 } 865 866 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 867 int clk_id, unsigned int freq, int dir) 868 { 869 struct snd_soc_component *component = dai->component; 870 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 871 872 cs42l42->sclk = freq; 873 874 return 0; 875 } 876 877 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 878 { 879 struct snd_soc_component *component = dai->component; 880 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 881 unsigned int regval; 882 u8 fullScaleVol; 883 int ret; 884 885 if (mute) { 886 /* Mute the headphone */ 887 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 888 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 889 CS42L42_HP_ANA_AMUTE_MASK | 890 CS42L42_HP_ANA_BMUTE_MASK, 891 CS42L42_HP_ANA_AMUTE_MASK | 892 CS42L42_HP_ANA_BMUTE_MASK); 893 894 cs42l42->stream_use &= ~(1 << stream); 895 if(!cs42l42->stream_use) { 896 /* 897 * Switch to the internal oscillator. 898 * SCLK must remain running until after this clock switch. 899 * Without a source of clock the I2C bus doesn't work. 900 */ 901 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 902 ARRAY_SIZE(cs42l42_to_osc_seq)); 903 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 904 CS42L42_PLL_START_MASK, 0); 905 } 906 } else { 907 if (!cs42l42->stream_use) { 908 /* SCLK must be running before codec unmute */ 909 if ((cs42l42->bclk < 11289600) && (cs42l42->sclk < 11289600)) { 910 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 911 CS42L42_PLL_START_MASK, 1); 912 913 if (cs42l42->pll_divout) { 914 usleep_range(CS42L42_PLL_DIVOUT_TIME_US, 915 CS42L42_PLL_DIVOUT_TIME_US * 2); 916 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3, 917 CS42L42_PLL_DIVOUT_MASK, 918 cs42l42->pll_divout << 919 CS42L42_PLL_DIVOUT_SHIFT); 920 } 921 922 ret = regmap_read_poll_timeout(cs42l42->regmap, 923 CS42L42_PLL_LOCK_STATUS, 924 regval, 925 (regval & 1), 926 CS42L42_PLL_LOCK_POLL_US, 927 CS42L42_PLL_LOCK_TIMEOUT_US); 928 if (ret < 0) 929 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 930 } 931 932 /* Mark SCLK as present, turn off internal oscillator */ 933 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 934 ARRAY_SIZE(cs42l42_to_sclk_seq)); 935 } 936 cs42l42->stream_use |= 1 << stream; 937 938 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 939 /* Read the headphone load */ 940 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT); 941 if (((regval & CS42L42_RLA_STAT_MASK) >> CS42L42_RLA_STAT_SHIFT) == 942 CS42L42_RLA_STAT_15_OHM) { 943 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK; 944 } else { 945 fullScaleVol = 0; 946 } 947 948 /* Un-mute the headphone, set the full scale volume flag */ 949 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 950 CS42L42_HP_ANA_AMUTE_MASK | 951 CS42L42_HP_ANA_BMUTE_MASK | 952 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol); 953 } 954 } 955 956 return 0; 957 } 958 959 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 960 SNDRV_PCM_FMTBIT_S24_LE |\ 961 SNDRV_PCM_FMTBIT_S32_LE ) 962 963 964 static const struct snd_soc_dai_ops cs42l42_ops = { 965 .hw_params = cs42l42_pcm_hw_params, 966 .set_fmt = cs42l42_set_dai_fmt, 967 .set_sysclk = cs42l42_set_sysclk, 968 .mute_stream = cs42l42_mute_stream, 969 }; 970 971 static struct snd_soc_dai_driver cs42l42_dai = { 972 .name = "cs42l42", 973 .playback = { 974 .stream_name = "Playback", 975 .channels_min = 1, 976 .channels_max = 2, 977 .rates = SNDRV_PCM_RATE_8000_192000, 978 .formats = CS42L42_FORMATS, 979 }, 980 .capture = { 981 .stream_name = "Capture", 982 .channels_min = 1, 983 .channels_max = 2, 984 .rates = SNDRV_PCM_RATE_8000_192000, 985 .formats = CS42L42_FORMATS, 986 }, 987 .symmetric_rate = 1, 988 .symmetric_sample_bits = 1, 989 .ops = &cs42l42_ops, 990 }; 991 992 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 993 { 994 unsigned int hs_det_status; 995 unsigned int int_status; 996 997 /* Mask the auto detect interrupt */ 998 regmap_update_bits(cs42l42->regmap, 999 CS42L42_CODEC_INT_MASK, 1000 CS42L42_PDN_DONE_MASK | 1001 CS42L42_HSDET_AUTO_DONE_MASK, 1002 (1 << CS42L42_PDN_DONE_SHIFT) | 1003 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1004 1005 /* Set hs detect to automatic, disabled mode */ 1006 regmap_update_bits(cs42l42->regmap, 1007 CS42L42_HSDET_CTL2, 1008 CS42L42_HSDET_CTRL_MASK | 1009 CS42L42_HSDET_SET_MASK | 1010 CS42L42_HSBIAS_REF_MASK | 1011 CS42L42_HSDET_AUTO_TIME_MASK, 1012 (2 << CS42L42_HSDET_CTRL_SHIFT) | 1013 (2 << CS42L42_HSDET_SET_SHIFT) | 1014 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1015 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1016 1017 /* Read and save the hs detection result */ 1018 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1019 1020 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 1021 CS42L42_HSDET_TYPE_SHIFT; 1022 1023 /* Set up button detection */ 1024 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1025 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1026 /* Set auto HS bias settings to default */ 1027 regmap_update_bits(cs42l42->regmap, 1028 CS42L42_HSBIAS_SC_AUTOCTL, 1029 CS42L42_HSBIAS_SENSE_EN_MASK | 1030 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1031 CS42L42_TIP_SENSE_EN_MASK | 1032 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1033 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1034 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1035 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1036 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1037 1038 /* Set up hs detect level sensitivity */ 1039 regmap_update_bits(cs42l42->regmap, 1040 CS42L42_MIC_DET_CTL1, 1041 CS42L42_LATCH_TO_VP_MASK | 1042 CS42L42_EVENT_STAT_SEL_MASK | 1043 CS42L42_HS_DET_LEVEL_MASK, 1044 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1045 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1046 (cs42l42->bias_thresholds[0] << 1047 CS42L42_HS_DET_LEVEL_SHIFT)); 1048 1049 /* Set auto HS bias settings to default */ 1050 regmap_update_bits(cs42l42->regmap, 1051 CS42L42_HSBIAS_SC_AUTOCTL, 1052 CS42L42_HSBIAS_SENSE_EN_MASK | 1053 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1054 CS42L42_TIP_SENSE_EN_MASK | 1055 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1056 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1057 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1058 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1059 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1060 1061 /* Turn on level detect circuitry */ 1062 regmap_update_bits(cs42l42->regmap, 1063 CS42L42_MISC_DET_CTL, 1064 CS42L42_DETECT_MODE_MASK | 1065 CS42L42_HSBIAS_CTL_MASK | 1066 CS42L42_PDN_MIC_LVL_DET_MASK, 1067 (0 << CS42L42_DETECT_MODE_SHIFT) | 1068 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1069 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1070 1071 msleep(cs42l42->btn_det_init_dbnce); 1072 1073 /* Clear any button interrupts before unmasking them */ 1074 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1075 &int_status); 1076 1077 /* Unmask button detect interrupts */ 1078 regmap_update_bits(cs42l42->regmap, 1079 CS42L42_DET_INT2_MASK, 1080 CS42L42_M_DETECT_TF_MASK | 1081 CS42L42_M_DETECT_FT_MASK | 1082 CS42L42_M_HSBIAS_HIZ_MASK | 1083 CS42L42_M_SHORT_RLS_MASK | 1084 CS42L42_M_SHORT_DET_MASK, 1085 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1086 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1087 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1088 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1089 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1090 } else { 1091 /* Make sure button detect and HS bias circuits are off */ 1092 regmap_update_bits(cs42l42->regmap, 1093 CS42L42_MISC_DET_CTL, 1094 CS42L42_DETECT_MODE_MASK | 1095 CS42L42_HSBIAS_CTL_MASK | 1096 CS42L42_PDN_MIC_LVL_DET_MASK, 1097 (0 << CS42L42_DETECT_MODE_SHIFT) | 1098 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1099 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1100 } 1101 1102 regmap_update_bits(cs42l42->regmap, 1103 CS42L42_DAC_CTL2, 1104 CS42L42_HPOUT_PULLDOWN_MASK | 1105 CS42L42_HPOUT_LOAD_MASK | 1106 CS42L42_HPOUT_CLAMP_MASK | 1107 CS42L42_DAC_HPF_EN_MASK | 1108 CS42L42_DAC_MON_EN_MASK, 1109 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1110 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1111 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1112 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1113 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1114 1115 /* Unmask tip sense interrupts */ 1116 regmap_update_bits(cs42l42->regmap, 1117 CS42L42_TSRS_PLUG_INT_MASK, 1118 CS42L42_RS_PLUG_MASK | 1119 CS42L42_RS_UNPLUG_MASK | 1120 CS42L42_TS_PLUG_MASK | 1121 CS42L42_TS_UNPLUG_MASK, 1122 (1 << CS42L42_RS_PLUG_SHIFT) | 1123 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1124 (0 << CS42L42_TS_PLUG_SHIFT) | 1125 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1126 } 1127 1128 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1129 { 1130 /* Mask tip sense interrupts */ 1131 regmap_update_bits(cs42l42->regmap, 1132 CS42L42_TSRS_PLUG_INT_MASK, 1133 CS42L42_RS_PLUG_MASK | 1134 CS42L42_RS_UNPLUG_MASK | 1135 CS42L42_TS_PLUG_MASK | 1136 CS42L42_TS_UNPLUG_MASK, 1137 (1 << CS42L42_RS_PLUG_SHIFT) | 1138 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1139 (1 << CS42L42_TS_PLUG_SHIFT) | 1140 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1141 1142 /* Make sure button detect and HS bias circuits are off */ 1143 regmap_update_bits(cs42l42->regmap, 1144 CS42L42_MISC_DET_CTL, 1145 CS42L42_DETECT_MODE_MASK | 1146 CS42L42_HSBIAS_CTL_MASK | 1147 CS42L42_PDN_MIC_LVL_DET_MASK, 1148 (0 << CS42L42_DETECT_MODE_SHIFT) | 1149 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1150 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1151 1152 /* Set auto HS bias settings to default */ 1153 regmap_update_bits(cs42l42->regmap, 1154 CS42L42_HSBIAS_SC_AUTOCTL, 1155 CS42L42_HSBIAS_SENSE_EN_MASK | 1156 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1157 CS42L42_TIP_SENSE_EN_MASK | 1158 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1159 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1160 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1161 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1162 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1163 1164 /* Set hs detect to manual, disabled mode */ 1165 regmap_update_bits(cs42l42->regmap, 1166 CS42L42_HSDET_CTL2, 1167 CS42L42_HSDET_CTRL_MASK | 1168 CS42L42_HSDET_SET_MASK | 1169 CS42L42_HSBIAS_REF_MASK | 1170 CS42L42_HSDET_AUTO_TIME_MASK, 1171 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1172 (2 << CS42L42_HSDET_SET_SHIFT) | 1173 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1174 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1175 1176 regmap_update_bits(cs42l42->regmap, 1177 CS42L42_DAC_CTL2, 1178 CS42L42_HPOUT_PULLDOWN_MASK | 1179 CS42L42_HPOUT_LOAD_MASK | 1180 CS42L42_HPOUT_CLAMP_MASK | 1181 CS42L42_DAC_HPF_EN_MASK | 1182 CS42L42_DAC_MON_EN_MASK, 1183 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1184 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1185 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1186 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1187 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1188 1189 /* Power up HS bias to 2.7V */ 1190 regmap_update_bits(cs42l42->regmap, 1191 CS42L42_MISC_DET_CTL, 1192 CS42L42_DETECT_MODE_MASK | 1193 CS42L42_HSBIAS_CTL_MASK | 1194 CS42L42_PDN_MIC_LVL_DET_MASK, 1195 (0 << CS42L42_DETECT_MODE_SHIFT) | 1196 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1197 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1198 1199 /* Wait for HS bias to ramp up */ 1200 msleep(cs42l42->hs_bias_ramp_time); 1201 1202 /* Unmask auto detect interrupt */ 1203 regmap_update_bits(cs42l42->regmap, 1204 CS42L42_CODEC_INT_MASK, 1205 CS42L42_PDN_DONE_MASK | 1206 CS42L42_HSDET_AUTO_DONE_MASK, 1207 (1 << CS42L42_PDN_DONE_SHIFT) | 1208 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1209 1210 /* Set hs detect to automatic, enabled mode */ 1211 regmap_update_bits(cs42l42->regmap, 1212 CS42L42_HSDET_CTL2, 1213 CS42L42_HSDET_CTRL_MASK | 1214 CS42L42_HSDET_SET_MASK | 1215 CS42L42_HSBIAS_REF_MASK | 1216 CS42L42_HSDET_AUTO_TIME_MASK, 1217 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1218 (2 << CS42L42_HSDET_SET_SHIFT) | 1219 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1220 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1221 } 1222 1223 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1224 { 1225 /* Mask button detect interrupts */ 1226 regmap_update_bits(cs42l42->regmap, 1227 CS42L42_DET_INT2_MASK, 1228 CS42L42_M_DETECT_TF_MASK | 1229 CS42L42_M_DETECT_FT_MASK | 1230 CS42L42_M_HSBIAS_HIZ_MASK | 1231 CS42L42_M_SHORT_RLS_MASK | 1232 CS42L42_M_SHORT_DET_MASK, 1233 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1234 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1235 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1236 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1237 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1238 1239 /* Ground HS bias */ 1240 regmap_update_bits(cs42l42->regmap, 1241 CS42L42_MISC_DET_CTL, 1242 CS42L42_DETECT_MODE_MASK | 1243 CS42L42_HSBIAS_CTL_MASK | 1244 CS42L42_PDN_MIC_LVL_DET_MASK, 1245 (0 << CS42L42_DETECT_MODE_SHIFT) | 1246 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1247 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1248 1249 /* Set auto HS bias settings to default */ 1250 regmap_update_bits(cs42l42->regmap, 1251 CS42L42_HSBIAS_SC_AUTOCTL, 1252 CS42L42_HSBIAS_SENSE_EN_MASK | 1253 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1254 CS42L42_TIP_SENSE_EN_MASK | 1255 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1256 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1257 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1258 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1259 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1260 1261 /* Set hs detect to manual, disabled mode */ 1262 regmap_update_bits(cs42l42->regmap, 1263 CS42L42_HSDET_CTL2, 1264 CS42L42_HSDET_CTRL_MASK | 1265 CS42L42_HSDET_SET_MASK | 1266 CS42L42_HSBIAS_REF_MASK | 1267 CS42L42_HSDET_AUTO_TIME_MASK, 1268 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1269 (2 << CS42L42_HSDET_SET_SHIFT) | 1270 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1271 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1272 } 1273 1274 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1275 { 1276 int bias_level; 1277 unsigned int detect_status; 1278 1279 /* Mask button detect interrupts */ 1280 regmap_update_bits(cs42l42->regmap, 1281 CS42L42_DET_INT2_MASK, 1282 CS42L42_M_DETECT_TF_MASK | 1283 CS42L42_M_DETECT_FT_MASK | 1284 CS42L42_M_HSBIAS_HIZ_MASK | 1285 CS42L42_M_SHORT_RLS_MASK | 1286 CS42L42_M_SHORT_DET_MASK, 1287 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1288 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1289 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1290 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1291 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1292 1293 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1294 cs42l42->btn_det_event_dbnce * 2000); 1295 1296 /* Test all 4 level detect biases */ 1297 bias_level = 1; 1298 do { 1299 /* Adjust button detect level sensitivity */ 1300 regmap_update_bits(cs42l42->regmap, 1301 CS42L42_MIC_DET_CTL1, 1302 CS42L42_LATCH_TO_VP_MASK | 1303 CS42L42_EVENT_STAT_SEL_MASK | 1304 CS42L42_HS_DET_LEVEL_MASK, 1305 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1306 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1307 (cs42l42->bias_thresholds[bias_level] << 1308 CS42L42_HS_DET_LEVEL_SHIFT)); 1309 1310 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1311 &detect_status); 1312 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1313 (++bias_level < CS42L42_NUM_BIASES)); 1314 1315 switch (bias_level) { 1316 case 1: /* Function C button press */ 1317 bias_level = SND_JACK_BTN_2; 1318 dev_dbg(cs42l42->component->dev, "Function C button press\n"); 1319 break; 1320 case 2: /* Function B button press */ 1321 bias_level = SND_JACK_BTN_1; 1322 dev_dbg(cs42l42->component->dev, "Function B button press\n"); 1323 break; 1324 case 3: /* Function D button press */ 1325 bias_level = SND_JACK_BTN_3; 1326 dev_dbg(cs42l42->component->dev, "Function D button press\n"); 1327 break; 1328 case 4: /* Function A button press */ 1329 bias_level = SND_JACK_BTN_0; 1330 dev_dbg(cs42l42->component->dev, "Function A button press\n"); 1331 break; 1332 default: 1333 bias_level = 0; 1334 break; 1335 } 1336 1337 /* Set button detect level sensitivity back to default */ 1338 regmap_update_bits(cs42l42->regmap, 1339 CS42L42_MIC_DET_CTL1, 1340 CS42L42_LATCH_TO_VP_MASK | 1341 CS42L42_EVENT_STAT_SEL_MASK | 1342 CS42L42_HS_DET_LEVEL_MASK, 1343 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1344 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1345 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1346 1347 /* Clear any button interrupts before unmasking them */ 1348 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1349 &detect_status); 1350 1351 /* Unmask button detect interrupts */ 1352 regmap_update_bits(cs42l42->regmap, 1353 CS42L42_DET_INT2_MASK, 1354 CS42L42_M_DETECT_TF_MASK | 1355 CS42L42_M_DETECT_FT_MASK | 1356 CS42L42_M_HSBIAS_HIZ_MASK | 1357 CS42L42_M_SHORT_RLS_MASK | 1358 CS42L42_M_SHORT_DET_MASK, 1359 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1360 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1361 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1362 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1363 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1364 1365 return bias_level; 1366 } 1367 1368 struct cs42l42_irq_params { 1369 u16 status_addr; 1370 u16 mask_addr; 1371 u8 mask; 1372 }; 1373 1374 static const struct cs42l42_irq_params irq_params_table[] = { 1375 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1376 CS42L42_ADC_OVFL_VAL_MASK}, 1377 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1378 CS42L42_MIXER_VAL_MASK}, 1379 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1380 CS42L42_SRC_VAL_MASK}, 1381 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1382 CS42L42_ASP_RX_VAL_MASK}, 1383 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1384 CS42L42_ASP_TX_VAL_MASK}, 1385 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1386 CS42L42_CODEC_VAL_MASK}, 1387 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1388 CS42L42_DET_INT_VAL1_MASK}, 1389 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1390 CS42L42_DET_INT_VAL2_MASK}, 1391 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1392 CS42L42_SRCPL_VAL_MASK}, 1393 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1394 CS42L42_VPMON_VAL_MASK}, 1395 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1396 CS42L42_PLL_LOCK_VAL_MASK}, 1397 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1398 CS42L42_TSRS_PLUG_VAL_MASK} 1399 }; 1400 1401 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1402 { 1403 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1404 struct snd_soc_component *component = cs42l42->component; 1405 unsigned int stickies[12]; 1406 unsigned int masks[12]; 1407 unsigned int current_plug_status; 1408 unsigned int current_button_status; 1409 unsigned int i; 1410 int report = 0; 1411 1412 1413 /* Read sticky registers to clear interurpt */ 1414 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1415 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1416 &(stickies[i])); 1417 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1418 &(masks[i])); 1419 stickies[i] = stickies[i] & (~masks[i]) & 1420 irq_params_table[i].mask; 1421 } 1422 1423 /* Read tip sense status before handling type detect */ 1424 current_plug_status = (stickies[11] & 1425 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1426 CS42L42_TS_PLUG_SHIFT; 1427 1428 /* Read button sense status */ 1429 current_button_status = stickies[7] & 1430 (CS42L42_M_DETECT_TF_MASK | 1431 CS42L42_M_DETECT_FT_MASK | 1432 CS42L42_M_HSBIAS_HIZ_MASK); 1433 1434 /* Check auto-detect status */ 1435 if ((~masks[5]) & irq_params_table[5].mask) { 1436 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1437 cs42l42_process_hs_type_detect(cs42l42); 1438 switch(cs42l42->hs_type){ 1439 case CS42L42_PLUG_CTIA: 1440 case CS42L42_PLUG_OMTP: 1441 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET, 1442 SND_JACK_HEADSET); 1443 break; 1444 case CS42L42_PLUG_HEADPHONE: 1445 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE, 1446 SND_JACK_HEADPHONE); 1447 break; 1448 default: 1449 break; 1450 } 1451 dev_dbg(component->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1452 } 1453 } 1454 1455 /* Check tip sense status */ 1456 if ((~masks[11]) & irq_params_table[11].mask) { 1457 switch (current_plug_status) { 1458 case CS42L42_TS_PLUG: 1459 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1460 cs42l42->plug_state = CS42L42_TS_PLUG; 1461 cs42l42_init_hs_type_detect(cs42l42); 1462 } 1463 break; 1464 1465 case CS42L42_TS_UNPLUG: 1466 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1467 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1468 cs42l42_cancel_hs_type_detect(cs42l42); 1469 1470 switch(cs42l42->hs_type){ 1471 case CS42L42_PLUG_CTIA: 1472 case CS42L42_PLUG_OMTP: 1473 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADSET); 1474 break; 1475 case CS42L42_PLUG_HEADPHONE: 1476 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADPHONE); 1477 break; 1478 default: 1479 break; 1480 } 1481 snd_soc_jack_report(cs42l42->jack, 0, 1482 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1483 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1484 1485 dev_dbg(component->dev, "Unplug event\n"); 1486 } 1487 break; 1488 1489 default: 1490 if (cs42l42->plug_state != CS42L42_TS_TRANS) 1491 cs42l42->plug_state = CS42L42_TS_TRANS; 1492 } 1493 } 1494 1495 /* Check button detect status */ 1496 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) { 1497 if (!(current_button_status & 1498 CS42L42_M_HSBIAS_HIZ_MASK)) { 1499 1500 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1501 dev_dbg(component->dev, "Button released\n"); 1502 report = 0; 1503 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1504 report = cs42l42_handle_button_press(cs42l42); 1505 1506 } 1507 snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1508 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1509 } 1510 } 1511 1512 return IRQ_HANDLED; 1513 } 1514 1515 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1516 { 1517 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1518 CS42L42_ADC_OVFL_MASK, 1519 (1 << CS42L42_ADC_OVFL_SHIFT)); 1520 1521 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1522 CS42L42_MIX_CHB_OVFL_MASK | 1523 CS42L42_MIX_CHA_OVFL_MASK | 1524 CS42L42_EQ_OVFL_MASK | 1525 CS42L42_EQ_BIQUAD_OVFL_MASK, 1526 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1527 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1528 (1 << CS42L42_EQ_OVFL_SHIFT) | 1529 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1530 1531 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1532 CS42L42_SRC_ILK_MASK | 1533 CS42L42_SRC_OLK_MASK | 1534 CS42L42_SRC_IUNLK_MASK | 1535 CS42L42_SRC_OUNLK_MASK, 1536 (1 << CS42L42_SRC_ILK_SHIFT) | 1537 (1 << CS42L42_SRC_OLK_SHIFT) | 1538 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1539 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1540 1541 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1542 CS42L42_ASPRX_NOLRCK_MASK | 1543 CS42L42_ASPRX_EARLY_MASK | 1544 CS42L42_ASPRX_LATE_MASK | 1545 CS42L42_ASPRX_ERROR_MASK | 1546 CS42L42_ASPRX_OVLD_MASK, 1547 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1548 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1549 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1550 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1551 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1552 1553 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1554 CS42L42_ASPTX_NOLRCK_MASK | 1555 CS42L42_ASPTX_EARLY_MASK | 1556 CS42L42_ASPTX_LATE_MASK | 1557 CS42L42_ASPTX_SMERROR_MASK, 1558 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1559 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1560 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1561 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1562 1563 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1564 CS42L42_PDN_DONE_MASK | 1565 CS42L42_HSDET_AUTO_DONE_MASK, 1566 (1 << CS42L42_PDN_DONE_SHIFT) | 1567 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1568 1569 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1570 CS42L42_SRCPL_ADC_LK_MASK | 1571 CS42L42_SRCPL_DAC_LK_MASK | 1572 CS42L42_SRCPL_ADC_UNLK_MASK | 1573 CS42L42_SRCPL_DAC_UNLK_MASK, 1574 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1575 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1576 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1577 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1578 1579 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1580 CS42L42_TIP_SENSE_UNPLUG_MASK | 1581 CS42L42_TIP_SENSE_PLUG_MASK | 1582 CS42L42_HSBIAS_SENSE_MASK, 1583 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1584 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1585 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1586 1587 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1588 CS42L42_M_DETECT_TF_MASK | 1589 CS42L42_M_DETECT_FT_MASK | 1590 CS42L42_M_HSBIAS_HIZ_MASK | 1591 CS42L42_M_SHORT_RLS_MASK | 1592 CS42L42_M_SHORT_DET_MASK, 1593 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1594 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1595 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1596 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1597 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1598 1599 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1600 CS42L42_VPMON_MASK, 1601 (1 << CS42L42_VPMON_SHIFT)); 1602 1603 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1604 CS42L42_PLL_LOCK_MASK, 1605 (1 << CS42L42_PLL_LOCK_SHIFT)); 1606 1607 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1608 CS42L42_RS_PLUG_MASK | 1609 CS42L42_RS_UNPLUG_MASK | 1610 CS42L42_TS_PLUG_MASK | 1611 CS42L42_TS_UNPLUG_MASK, 1612 (1 << CS42L42_RS_PLUG_SHIFT) | 1613 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1614 (1 << CS42L42_TS_PLUG_SHIFT) | 1615 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1616 } 1617 1618 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1619 { 1620 unsigned int reg; 1621 1622 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1623 1624 /* Latch analog controls to VP power domain */ 1625 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1626 CS42L42_LATCH_TO_VP_MASK | 1627 CS42L42_EVENT_STAT_SEL_MASK | 1628 CS42L42_HS_DET_LEVEL_MASK, 1629 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1630 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1631 (cs42l42->bias_thresholds[0] << 1632 CS42L42_HS_DET_LEVEL_SHIFT)); 1633 1634 /* Remove ground noise-suppression clamps */ 1635 regmap_update_bits(cs42l42->regmap, 1636 CS42L42_HS_CLAMP_DISABLE, 1637 CS42L42_HS_CLAMP_DISABLE_MASK, 1638 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1639 1640 /* Enable the tip sense circuit */ 1641 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1642 CS42L42_TIP_SENSE_CTRL_MASK | 1643 CS42L42_TIP_SENSE_INV_MASK | 1644 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1645 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1646 (0 << CS42L42_TIP_SENSE_INV_SHIFT) | 1647 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1648 1649 /* Save the initial status of the tip sense */ 1650 regmap_read(cs42l42->regmap, 1651 CS42L42_TSRS_PLUG_STATUS, 1652 ®); 1653 cs42l42->plug_state = (((char) reg) & 1654 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1655 CS42L42_TS_PLUG_SHIFT; 1656 } 1657 1658 static const unsigned int threshold_defaults[] = { 1659 CS42L42_HS_DET_LEVEL_15, 1660 CS42L42_HS_DET_LEVEL_8, 1661 CS42L42_HS_DET_LEVEL_4, 1662 CS42L42_HS_DET_LEVEL_1 1663 }; 1664 1665 static int cs42l42_handle_device_data(struct device *dev, 1666 struct cs42l42_private *cs42l42) 1667 { 1668 unsigned int val; 1669 u32 thresholds[CS42L42_NUM_BIASES]; 1670 int ret; 1671 int i; 1672 1673 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val); 1674 if (!ret) { 1675 switch (val) { 1676 case CS42L42_TS_INV_EN: 1677 case CS42L42_TS_INV_DIS: 1678 cs42l42->ts_inv = val; 1679 break; 1680 default: 1681 dev_err(dev, 1682 "Wrong cirrus,ts-inv DT value %d\n", 1683 val); 1684 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1685 } 1686 } else { 1687 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1688 } 1689 1690 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1691 CS42L42_TS_INV_MASK, 1692 (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT)); 1693 1694 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val); 1695 if (!ret) { 1696 switch (val) { 1697 case CS42L42_TS_DBNCE_0: 1698 case CS42L42_TS_DBNCE_125: 1699 case CS42L42_TS_DBNCE_250: 1700 case CS42L42_TS_DBNCE_500: 1701 case CS42L42_TS_DBNCE_750: 1702 case CS42L42_TS_DBNCE_1000: 1703 case CS42L42_TS_DBNCE_1250: 1704 case CS42L42_TS_DBNCE_1500: 1705 cs42l42->ts_dbnc_rise = val; 1706 break; 1707 default: 1708 dev_err(dev, 1709 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1710 val); 1711 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1712 } 1713 } else { 1714 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1715 } 1716 1717 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1718 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1719 (cs42l42->ts_dbnc_rise << 1720 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1721 1722 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val); 1723 if (!ret) { 1724 switch (val) { 1725 case CS42L42_TS_DBNCE_0: 1726 case CS42L42_TS_DBNCE_125: 1727 case CS42L42_TS_DBNCE_250: 1728 case CS42L42_TS_DBNCE_500: 1729 case CS42L42_TS_DBNCE_750: 1730 case CS42L42_TS_DBNCE_1000: 1731 case CS42L42_TS_DBNCE_1250: 1732 case CS42L42_TS_DBNCE_1500: 1733 cs42l42->ts_dbnc_fall = val; 1734 break; 1735 default: 1736 dev_err(dev, 1737 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1738 val); 1739 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1740 } 1741 } else { 1742 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1743 } 1744 1745 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1746 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1747 (cs42l42->ts_dbnc_fall << 1748 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1749 1750 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val); 1751 if (!ret) { 1752 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1753 cs42l42->btn_det_init_dbnce = val; 1754 else { 1755 dev_err(dev, 1756 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1757 val); 1758 cs42l42->btn_det_init_dbnce = 1759 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1760 } 1761 } else { 1762 cs42l42->btn_det_init_dbnce = 1763 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1764 } 1765 1766 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val); 1767 if (!ret) { 1768 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 1769 cs42l42->btn_det_event_dbnce = val; 1770 else { 1771 dev_err(dev, 1772 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 1773 cs42l42->btn_det_event_dbnce = 1774 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1775 } 1776 } else { 1777 cs42l42->btn_det_event_dbnce = 1778 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1779 } 1780 1781 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls", 1782 thresholds, ARRAY_SIZE(thresholds)); 1783 if (!ret) { 1784 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 1785 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 1786 cs42l42->bias_thresholds[i] = thresholds[i]; 1787 else { 1788 dev_err(dev, 1789 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 1790 thresholds[i]); 1791 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1792 } 1793 } 1794 } else { 1795 for (i = 0; i < CS42L42_NUM_BIASES; i++) 1796 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1797 } 1798 1799 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val); 1800 if (!ret) { 1801 switch (val) { 1802 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 1803 cs42l42->hs_bias_ramp_rate = val; 1804 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 1805 break; 1806 case CS42L42_HSBIAS_RAMP_FAST: 1807 cs42l42->hs_bias_ramp_rate = val; 1808 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 1809 break; 1810 case CS42L42_HSBIAS_RAMP_SLOW: 1811 cs42l42->hs_bias_ramp_rate = val; 1812 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1813 break; 1814 case CS42L42_HSBIAS_RAMP_SLOWEST: 1815 cs42l42->hs_bias_ramp_rate = val; 1816 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 1817 break; 1818 default: 1819 dev_err(dev, 1820 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 1821 val); 1822 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1823 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1824 } 1825 } else { 1826 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1827 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1828 } 1829 1830 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 1831 CS42L42_HSBIAS_RAMP_MASK, 1832 (cs42l42->hs_bias_ramp_rate << 1833 CS42L42_HSBIAS_RAMP_SHIFT)); 1834 1835 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable")) 1836 cs42l42->hs_bias_sense_en = 0; 1837 else 1838 cs42l42->hs_bias_sense_en = 1; 1839 1840 return 0; 1841 } 1842 1843 static int cs42l42_i2c_probe(struct i2c_client *i2c_client, 1844 const struct i2c_device_id *id) 1845 { 1846 struct cs42l42_private *cs42l42; 1847 int ret, i, devid; 1848 unsigned int reg; 1849 1850 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private), 1851 GFP_KERNEL); 1852 if (!cs42l42) 1853 return -ENOMEM; 1854 1855 i2c_set_clientdata(i2c_client, cs42l42); 1856 1857 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap); 1858 if (IS_ERR(cs42l42->regmap)) { 1859 ret = PTR_ERR(cs42l42->regmap); 1860 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1861 return ret; 1862 } 1863 1864 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 1865 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 1866 1867 ret = devm_regulator_bulk_get(&i2c_client->dev, 1868 ARRAY_SIZE(cs42l42->supplies), 1869 cs42l42->supplies); 1870 if (ret != 0) { 1871 dev_err(&i2c_client->dev, 1872 "Failed to request supplies: %d\n", ret); 1873 return ret; 1874 } 1875 1876 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1877 cs42l42->supplies); 1878 if (ret != 0) { 1879 dev_err(&i2c_client->dev, 1880 "Failed to enable supplies: %d\n", ret); 1881 return ret; 1882 } 1883 1884 /* Reset the Device */ 1885 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 1886 "reset", GPIOD_OUT_LOW); 1887 if (IS_ERR(cs42l42->reset_gpio)) { 1888 ret = PTR_ERR(cs42l42->reset_gpio); 1889 goto err_disable; 1890 } 1891 1892 if (cs42l42->reset_gpio) { 1893 dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); 1894 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1895 } 1896 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 1897 1898 /* Request IRQ */ 1899 ret = devm_request_threaded_irq(&i2c_client->dev, 1900 i2c_client->irq, 1901 NULL, cs42l42_irq_thread, 1902 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 1903 "cs42l42", cs42l42); 1904 1905 if (ret != 0) 1906 dev_err(&i2c_client->dev, 1907 "Failed to request IRQ: %d\n", ret); 1908 1909 /* initialize codec */ 1910 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB); 1911 if (devid < 0) { 1912 ret = devid; 1913 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret); 1914 goto err_disable; 1915 } 1916 1917 if (devid != CS42L42_CHIP_ID) { 1918 ret = -ENODEV; 1919 dev_err(&i2c_client->dev, 1920 "CS42L42 Device ID (%X). Expected %X\n", 1921 devid, CS42L42_CHIP_ID); 1922 goto err_disable; 1923 } 1924 1925 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 1926 if (ret < 0) { 1927 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1928 goto err_disable; 1929 } 1930 1931 dev_info(&i2c_client->dev, 1932 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); 1933 1934 /* Power up the codec */ 1935 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 1936 CS42L42_ASP_DAO_PDN_MASK | 1937 CS42L42_ASP_DAI_PDN_MASK | 1938 CS42L42_MIXER_PDN_MASK | 1939 CS42L42_EQ_PDN_MASK | 1940 CS42L42_HP_PDN_MASK | 1941 CS42L42_ADC_PDN_MASK | 1942 CS42L42_PDN_ALL_MASK, 1943 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 1944 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 1945 (1 << CS42L42_MIXER_PDN_SHIFT) | 1946 (1 << CS42L42_EQ_PDN_SHIFT) | 1947 (1 << CS42L42_HP_PDN_SHIFT) | 1948 (1 << CS42L42_ADC_PDN_SHIFT) | 1949 (0 << CS42L42_PDN_ALL_SHIFT)); 1950 1951 ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42); 1952 if (ret != 0) 1953 goto err_disable; 1954 1955 /* Setup headset detection */ 1956 cs42l42_setup_hs_type_detect(cs42l42); 1957 1958 /* Mask/Unmask Interrupts */ 1959 cs42l42_set_interrupt_masks(cs42l42); 1960 1961 /* Register codec for machine driver */ 1962 ret = devm_snd_soc_register_component(&i2c_client->dev, 1963 &soc_component_dev_cs42l42, &cs42l42_dai, 1); 1964 if (ret < 0) 1965 goto err_disable; 1966 return 0; 1967 1968 err_disable: 1969 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1970 cs42l42->supplies); 1971 return ret; 1972 } 1973 1974 static int cs42l42_i2c_remove(struct i2c_client *i2c_client) 1975 { 1976 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client); 1977 1978 devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42); 1979 pm_runtime_suspend(&i2c_client->dev); 1980 pm_runtime_disable(&i2c_client->dev); 1981 1982 return 0; 1983 } 1984 1985 #ifdef CONFIG_PM 1986 static int cs42l42_runtime_suspend(struct device *dev) 1987 { 1988 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1989 1990 regcache_cache_only(cs42l42->regmap, true); 1991 regcache_mark_dirty(cs42l42->regmap); 1992 1993 /* Hold down reset */ 1994 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 1995 1996 /* remove power */ 1997 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1998 cs42l42->supplies); 1999 2000 return 0; 2001 } 2002 2003 static int cs42l42_runtime_resume(struct device *dev) 2004 { 2005 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2006 int ret; 2007 2008 /* Enable power */ 2009 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 2010 cs42l42->supplies); 2011 if (ret != 0) { 2012 dev_err(dev, "Failed to enable supplies: %d\n", 2013 ret); 2014 return ret; 2015 } 2016 2017 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2018 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2019 2020 regcache_cache_only(cs42l42->regmap, false); 2021 regcache_sync(cs42l42->regmap); 2022 2023 return 0; 2024 } 2025 #endif 2026 2027 static const struct dev_pm_ops cs42l42_runtime_pm = { 2028 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume, 2029 NULL) 2030 }; 2031 2032 #ifdef CONFIG_OF 2033 static const struct of_device_id cs42l42_of_match[] = { 2034 { .compatible = "cirrus,cs42l42", }, 2035 {} 2036 }; 2037 MODULE_DEVICE_TABLE(of, cs42l42_of_match); 2038 #endif 2039 2040 #ifdef CONFIG_ACPI 2041 static const struct acpi_device_id cs42l42_acpi_match[] = { 2042 {"10134242", 0,}, 2043 {} 2044 }; 2045 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match); 2046 #endif 2047 2048 static const struct i2c_device_id cs42l42_id[] = { 2049 {"cs42l42", 0}, 2050 {} 2051 }; 2052 2053 MODULE_DEVICE_TABLE(i2c, cs42l42_id); 2054 2055 static struct i2c_driver cs42l42_i2c_driver = { 2056 .driver = { 2057 .name = "cs42l42", 2058 .pm = &cs42l42_runtime_pm, 2059 .of_match_table = of_match_ptr(cs42l42_of_match), 2060 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match), 2061 }, 2062 .id_table = cs42l42_id, 2063 .probe = cs42l42_i2c_probe, 2064 .remove = cs42l42_i2c_remove, 2065 }; 2066 2067 module_i2c_driver(cs42l42_i2c_driver); 2068 2069 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2070 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2071 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2072 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2073 MODULE_LICENSE("GPL"); 2074