1 // SPDX-License-Identifier: GPL-2.0-only 2 // cs42l42-sdw.c -- CS42L42 ALSA SoC audio driver SoundWire driver 3 // 4 // Copyright (C) 2022 Cirrus Logic, Inc. and 5 // Cirrus Logic International Semiconductor Ltd. 6 7 #include <linux/acpi.h> 8 #include <linux/device.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/of_irq.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/soundwire/sdw.h> 15 #include <linux/soundwire/sdw_registers.h> 16 #include <linux/soundwire/sdw_type.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/sdw.h> 20 #include <sound/soc.h> 21 22 #include "cs42l42.h" 23 24 #define CS42L42_SDW_CAPTURE_PORT 1 25 #define CS42L42_SDW_PLAYBACK_PORT 2 26 27 /* Register addresses are offset when sent over SoundWire */ 28 #define CS42L42_SDW_ADDR_OFFSET 0x8000 29 30 #define CS42L42_SDW_MEM_ACCESS_STATUS 0xd0 31 #define CS42L42_SDW_MEM_READ_DATA 0xd8 32 33 #define CS42L42_SDW_LAST_LATE BIT(3) 34 #define CS42L42_SDW_CMD_IN_PROGRESS BIT(2) 35 #define CS42L42_SDW_RDATA_RDY BIT(0) 36 37 #define CS42L42_DELAYED_READ_POLL_US 1 38 #define CS42L42_DELAYED_READ_TIMEOUT_US 100 39 40 static const struct snd_soc_dapm_route cs42l42_sdw_audio_map[] = { 41 /* Playback Path */ 42 { "HP", NULL, "MIXER" }, 43 { "MIXER", NULL, "DACSRC" }, 44 { "DACSRC", NULL, "Playback" }, 45 46 /* Capture Path */ 47 { "ADCSRC", NULL, "HS" }, 48 { "Capture", NULL, "ADCSRC" }, 49 }; 50 51 static int cs42l42_sdw_dai_startup(struct snd_pcm_substream *substream, 52 struct snd_soc_dai *dai) 53 { 54 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component); 55 56 if (!cs42l42->init_done) 57 return -ENODEV; 58 59 return 0; 60 } 61 62 static int cs42l42_sdw_dai_hw_params(struct snd_pcm_substream *substream, 63 struct snd_pcm_hw_params *params, 64 struct snd_soc_dai *dai) 65 { 66 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component); 67 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 68 struct sdw_stream_config stream_config = {0}; 69 struct sdw_port_config port_config = {0}; 70 int ret; 71 72 if (!sdw_stream) 73 return -EINVAL; 74 75 /* Needed for PLL configuration when we are notified of new bus config */ 76 cs42l42->sample_rate = params_rate(params); 77 78 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 79 80 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 81 port_config.num = CS42L42_SDW_PLAYBACK_PORT; 82 else 83 port_config.num = CS42L42_SDW_CAPTURE_PORT; 84 85 ret = sdw_stream_add_slave(cs42l42->sdw_peripheral, &stream_config, &port_config, 1, 86 sdw_stream); 87 if (ret) { 88 dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret); 89 return ret; 90 } 91 92 cs42l42_src_config(dai->component, params_rate(params)); 93 94 return 0; 95 } 96 97 static int cs42l42_sdw_dai_prepare(struct snd_pcm_substream *substream, 98 struct snd_soc_dai *dai) 99 { 100 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component); 101 102 dev_dbg(dai->dev, "dai_prepare: sclk=%u rate=%u\n", cs42l42->sclk, cs42l42->sample_rate); 103 104 if (!cs42l42->sclk || !cs42l42->sample_rate) 105 return -EINVAL; 106 107 /* 108 * At this point we know the sample rate from hw_params, and the SWIRE_CLK from bus_config() 109 * callback. This could only fail if the ACPI or machine driver are misconfigured to allow 110 * an unsupported SWIRE_CLK and sample_rate combination. 111 */ 112 113 return cs42l42_pll_config(dai->component, cs42l42->sclk, cs42l42->sample_rate); 114 } 115 116 static int cs42l42_sdw_dai_hw_free(struct snd_pcm_substream *substream, 117 struct snd_soc_dai *dai) 118 { 119 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component); 120 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 121 122 sdw_stream_remove_slave(cs42l42->sdw_peripheral, sdw_stream); 123 cs42l42->sample_rate = 0; 124 125 return 0; 126 } 127 128 static int cs42l42_sdw_port_prep(struct sdw_slave *slave, 129 struct sdw_prepare_ch *prepare_ch, 130 enum sdw_port_prep_ops state) 131 { 132 struct cs42l42_private *cs42l42 = dev_get_drvdata(&slave->dev); 133 unsigned int pdn_mask; 134 135 if (prepare_ch->num == CS42L42_SDW_PLAYBACK_PORT) 136 pdn_mask = CS42L42_HP_PDN_MASK; 137 else 138 pdn_mask = CS42L42_ADC_PDN_MASK; 139 140 if (state == SDW_OPS_PORT_PRE_PREP) { 141 dev_dbg(cs42l42->dev, "Prep Port pdn_mask:%x\n", pdn_mask); 142 regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask); 143 usleep_range(CS42L42_HP_ADC_EN_TIME_US, CS42L42_HP_ADC_EN_TIME_US + 1000); 144 } else if (state == SDW_OPS_PORT_POST_DEPREP) { 145 dev_dbg(cs42l42->dev, "Deprep Port pdn_mask:%x\n", pdn_mask); 146 regmap_set_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask); 147 } 148 149 return 0; 150 } 151 152 static int cs42l42_sdw_dai_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 153 int direction) 154 { 155 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 156 157 return 0; 158 } 159 160 static void cs42l42_sdw_dai_shutdown(struct snd_pcm_substream *substream, 161 struct snd_soc_dai *dai) 162 { 163 snd_soc_dai_set_dma_data(dai, substream, NULL); 164 } 165 166 static const struct snd_soc_dai_ops cs42l42_sdw_dai_ops = { 167 .startup = cs42l42_sdw_dai_startup, 168 .shutdown = cs42l42_sdw_dai_shutdown, 169 .hw_params = cs42l42_sdw_dai_hw_params, 170 .prepare = cs42l42_sdw_dai_prepare, 171 .hw_free = cs42l42_sdw_dai_hw_free, 172 .mute_stream = cs42l42_mute_stream, 173 .set_stream = cs42l42_sdw_dai_set_sdw_stream, 174 }; 175 176 static struct snd_soc_dai_driver cs42l42_sdw_dai = { 177 .name = "cs42l42-sdw", 178 .playback = { 179 .stream_name = "Playback", 180 .channels_min = 1, 181 .channels_max = 2, 182 /* Restrict which rates and formats are supported */ 183 .rates = SNDRV_PCM_RATE_8000_96000, 184 .formats = SNDRV_PCM_FMTBIT_S16_LE | 185 SNDRV_PCM_FMTBIT_S24_LE | 186 SNDRV_PCM_FMTBIT_S32_LE, 187 }, 188 .capture = { 189 .stream_name = "Capture", 190 .channels_min = 1, 191 .channels_max = 1, 192 /* Restrict which rates and formats are supported */ 193 .rates = SNDRV_PCM_RATE_8000_96000, 194 .formats = SNDRV_PCM_FMTBIT_S16_LE | 195 SNDRV_PCM_FMTBIT_S24_LE | 196 SNDRV_PCM_FMTBIT_S32_LE, 197 }, 198 .symmetric_rate = 1, 199 .ops = &cs42l42_sdw_dai_ops, 200 }; 201 202 static int cs42l42_sdw_poll_status(struct sdw_slave *peripheral, u8 mask, u8 match) 203 { 204 int ret, sdwret; 205 206 ret = read_poll_timeout(sdw_read_no_pm, sdwret, 207 (sdwret < 0) || ((sdwret & mask) == match), 208 CS42L42_DELAYED_READ_POLL_US, CS42L42_DELAYED_READ_TIMEOUT_US, 209 false, peripheral, CS42L42_SDW_MEM_ACCESS_STATUS); 210 if (ret == 0) 211 ret = sdwret; 212 213 if (ret < 0) 214 dev_err(&peripheral->dev, "MEM_ACCESS_STATUS & %#x for %#x fail: %d\n", 215 mask, match, ret); 216 217 return ret; 218 } 219 220 static int cs42l42_sdw_read(void *context, unsigned int reg, unsigned int *val) 221 { 222 struct sdw_slave *peripheral = context; 223 u8 data; 224 int ret; 225 226 reg += CS42L42_SDW_ADDR_OFFSET; 227 228 ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0); 229 if (ret < 0) 230 return ret; 231 232 ret = sdw_read_no_pm(peripheral, reg); 233 if (ret < 0) { 234 dev_err(&peripheral->dev, "Failed to issue read @0x%x: %d\n", reg, ret); 235 return ret; 236 } 237 238 data = (u8)ret; /* possible non-delayed read value */ 239 ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_ACCESS_STATUS); 240 if (ret < 0) { 241 dev_err(&peripheral->dev, "Failed to read MEM_ACCESS_STATUS: %d\n", ret); 242 return ret; 243 } 244 245 /* If read was not delayed we already have the result */ 246 if ((ret & CS42L42_SDW_LAST_LATE) == 0) { 247 *val = data; 248 return 0; 249 } 250 251 /* Poll for delayed read completion */ 252 if ((ret & CS42L42_SDW_RDATA_RDY) == 0) { 253 ret = cs42l42_sdw_poll_status(peripheral, 254 CS42L42_SDW_RDATA_RDY, CS42L42_SDW_RDATA_RDY); 255 if (ret < 0) 256 return ret; 257 } 258 259 ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_READ_DATA); 260 if (ret < 0) { 261 dev_err(&peripheral->dev, "Failed to read READ_DATA: %d\n", ret); 262 return ret; 263 } 264 265 *val = (u8)ret; 266 267 return 0; 268 } 269 270 static int cs42l42_sdw_write(void *context, unsigned int reg, unsigned int val) 271 { 272 struct sdw_slave *peripheral = context; 273 int ret; 274 275 ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0); 276 if (ret < 0) 277 return ret; 278 279 return sdw_write_no_pm(peripheral, reg + CS42L42_SDW_ADDR_OFFSET, (u8)val); 280 } 281 282 /* Initialise cs42l42 using SoundWire - this is only called once, during initialisation */ 283 static void cs42l42_sdw_init(struct sdw_slave *peripheral) 284 { 285 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev); 286 int ret; 287 288 regcache_cache_only(cs42l42->regmap, false); 289 290 ret = cs42l42_init(cs42l42); 291 if (ret < 0) { 292 regcache_cache_only(cs42l42->regmap, true); 293 goto err; 294 } 295 296 /* Write out any cached changes that happened between probe and attach */ 297 ret = regcache_sync(cs42l42->regmap); 298 if (ret < 0) 299 dev_warn(cs42l42->dev, "Failed to sync cache: %d\n", ret); 300 301 /* Disable internal logic that makes clock-stop conditional */ 302 regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL3, CS42L42_SW_CLK_STP_STAT_SEL_MASK); 303 304 err: 305 /* This cancels the pm_runtime_get_noresume() call from cs42l42_sdw_probe(). */ 306 pm_runtime_put_autosuspend(cs42l42->dev); 307 } 308 309 static int cs42l42_sdw_read_prop(struct sdw_slave *peripheral) 310 { 311 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev); 312 struct sdw_slave_prop *prop = &peripheral->prop; 313 struct sdw_dpn_prop *ports; 314 315 ports = devm_kcalloc(cs42l42->dev, 2, sizeof(*ports), GFP_KERNEL); 316 if (!ports) 317 return -ENOMEM; 318 319 prop->source_ports = BIT(CS42L42_SDW_CAPTURE_PORT); 320 prop->sink_ports = BIT(CS42L42_SDW_PLAYBACK_PORT); 321 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 322 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 323 324 /* DP1 - capture */ 325 ports[0].num = CS42L42_SDW_CAPTURE_PORT, 326 ports[0].type = SDW_DPN_FULL, 327 ports[0].ch_prep_timeout = 10, 328 prop->src_dpn_prop = &ports[0]; 329 330 /* DP2 - playback */ 331 ports[1].num = CS42L42_SDW_PLAYBACK_PORT, 332 ports[1].type = SDW_DPN_FULL, 333 ports[1].ch_prep_timeout = 10, 334 prop->sink_dpn_prop = &ports[1]; 335 336 return 0; 337 } 338 339 static int cs42l42_sdw_update_status(struct sdw_slave *peripheral, 340 enum sdw_slave_status status) 341 { 342 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev); 343 344 switch (status) { 345 case SDW_SLAVE_ATTACHED: 346 dev_dbg(cs42l42->dev, "ATTACHED\n"); 347 /* 348 * Initialise codec, this only needs to be done once. 349 * When resuming from suspend, resume callback will handle re-init of codec, 350 * using regcache_sync(). 351 */ 352 if (!cs42l42->init_done) 353 cs42l42_sdw_init(peripheral); 354 break; 355 case SDW_SLAVE_UNATTACHED: 356 dev_dbg(cs42l42->dev, "UNATTACHED\n"); 357 break; 358 default: 359 break; 360 } 361 362 return 0; 363 } 364 365 static int cs42l42_sdw_bus_config(struct sdw_slave *peripheral, 366 struct sdw_bus_params *params) 367 { 368 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev); 369 unsigned int new_sclk = params->curr_dr_freq / 2; 370 371 /* The cs42l42 cannot support a glitchless SWIRE_CLK change. */ 372 if ((new_sclk != cs42l42->sclk) && cs42l42->stream_use) { 373 dev_warn(cs42l42->dev, "Rejected SCLK change while audio active\n"); 374 return -EBUSY; 375 } 376 377 cs42l42->sclk = new_sclk; 378 379 dev_dbg(cs42l42->dev, "bus_config: sclk=%u c=%u r=%u\n", 380 cs42l42->sclk, params->col, params->row); 381 382 return 0; 383 } 384 385 static const struct sdw_slave_ops cs42l42_sdw_ops = { 386 /* No interrupt callback because only hardware INT is supported for Jack Detect in the CS42L42 */ 387 .read_prop = cs42l42_sdw_read_prop, 388 .update_status = cs42l42_sdw_update_status, 389 .bus_config = cs42l42_sdw_bus_config, 390 .port_prep = cs42l42_sdw_port_prep, 391 }; 392 393 static int __maybe_unused cs42l42_sdw_runtime_suspend(struct device *dev) 394 { 395 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 396 397 dev_dbg(dev, "Runtime suspend\n"); 398 399 if (!cs42l42->init_done) 400 return 0; 401 402 /* The host controller could suspend, which would mean no register access */ 403 regcache_cache_only(cs42l42->regmap, true); 404 405 return 0; 406 } 407 408 static const struct reg_sequence __maybe_unused cs42l42_soft_reboot_seq[] = { 409 REG_SEQ0(CS42L42_SOFT_RESET_REBOOT, 0x1e), 410 }; 411 412 static int __maybe_unused cs42l42_sdw_handle_unattach(struct cs42l42_private *cs42l42) 413 { 414 struct sdw_slave *peripheral = cs42l42->sdw_peripheral; 415 416 if (!peripheral->unattach_request) 417 return 0; 418 419 /* Cannot access registers until master re-attaches. */ 420 dev_dbg(&peripheral->dev, "Wait for initialization_complete\n"); 421 if (!wait_for_completion_timeout(&peripheral->initialization_complete, 422 msecs_to_jiffies(5000))) { 423 dev_err(&peripheral->dev, "initialization_complete timed out\n"); 424 return -ETIMEDOUT; 425 } 426 427 peripheral->unattach_request = 0; 428 429 /* 430 * After a bus reset there must be a reconfiguration reset to 431 * reinitialize the internal state of CS42L42. 432 */ 433 regmap_multi_reg_write_bypassed(cs42l42->regmap, 434 cs42l42_soft_reboot_seq, 435 ARRAY_SIZE(cs42l42_soft_reboot_seq)); 436 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 437 regcache_mark_dirty(cs42l42->regmap); 438 439 return 0; 440 } 441 442 static int __maybe_unused cs42l42_sdw_runtime_resume(struct device *dev) 443 { 444 static const unsigned int ts_dbnce_ms[] = { 0, 125, 250, 500, 750, 1000, 1250, 1500}; 445 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 446 unsigned int dbnce; 447 int ret; 448 449 dev_dbg(dev, "Runtime resume\n"); 450 451 if (!cs42l42->init_done) 452 return 0; 453 454 ret = cs42l42_sdw_handle_unattach(cs42l42); 455 if (ret < 0) { 456 return ret; 457 } else if (ret > 0) { 458 dbnce = max(cs42l42->ts_dbnc_rise, cs42l42->ts_dbnc_fall); 459 460 if (dbnce > 0) 461 msleep(ts_dbnce_ms[dbnce]); 462 } 463 464 regcache_cache_only(cs42l42->regmap, false); 465 466 /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */ 467 regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1); 468 regcache_sync(cs42l42->regmap); 469 470 return 0; 471 } 472 473 static int __maybe_unused cs42l42_sdw_resume(struct device *dev) 474 { 475 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 476 int ret; 477 478 dev_dbg(dev, "System resume\n"); 479 480 /* Power-up so it can re-enumerate */ 481 ret = cs42l42_resume(dev); 482 if (ret) 483 return ret; 484 485 /* Wait for re-attach */ 486 ret = cs42l42_sdw_handle_unattach(cs42l42); 487 if (ret < 0) 488 return ret; 489 490 cs42l42_resume_restore(dev); 491 492 return 0; 493 } 494 495 static int cs42l42_sdw_probe(struct sdw_slave *peripheral, const struct sdw_device_id *id) 496 { 497 struct snd_soc_component_driver *component_drv; 498 struct device *dev = &peripheral->dev; 499 struct cs42l42_private *cs42l42; 500 struct regmap_config *regmap_conf; 501 struct regmap *regmap; 502 int irq, ret; 503 504 cs42l42 = devm_kzalloc(dev, sizeof(*cs42l42), GFP_KERNEL); 505 if (!cs42l42) 506 return -ENOMEM; 507 508 if (has_acpi_companion(dev)) 509 irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0); 510 else 511 irq = of_irq_get(dev->of_node, 0); 512 513 if (irq == -ENOENT) 514 irq = 0; 515 else if (irq < 0) 516 return dev_err_probe(dev, irq, "Failed to get IRQ\n"); 517 518 regmap_conf = devm_kmemdup(dev, &cs42l42_regmap, sizeof(cs42l42_regmap), GFP_KERNEL); 519 if (!regmap_conf) 520 return -ENOMEM; 521 regmap_conf->reg_bits = 16; 522 regmap_conf->num_ranges = 0; 523 regmap_conf->reg_read = cs42l42_sdw_read; 524 regmap_conf->reg_write = cs42l42_sdw_write; 525 526 regmap = devm_regmap_init(dev, NULL, peripheral, regmap_conf); 527 if (IS_ERR(regmap)) 528 return dev_err_probe(dev, PTR_ERR(regmap), "Failed to allocate register map\n"); 529 530 /* Start in cache-only until device is enumerated */ 531 regcache_cache_only(regmap, true); 532 533 component_drv = devm_kmemdup(dev, 534 &cs42l42_soc_component, 535 sizeof(cs42l42_soc_component), 536 GFP_KERNEL); 537 if (!component_drv) 538 return -ENOMEM; 539 540 component_drv->dapm_routes = cs42l42_sdw_audio_map; 541 component_drv->num_dapm_routes = ARRAY_SIZE(cs42l42_sdw_audio_map); 542 543 cs42l42->dev = dev; 544 cs42l42->regmap = regmap; 545 cs42l42->sdw_peripheral = peripheral; 546 cs42l42->irq = irq; 547 cs42l42->devid = CS42L42_CHIP_ID; 548 549 /* 550 * pm_runtime is needed to control bus manager suspend, and to 551 * recover from an unattach_request when the manager suspends. 552 */ 553 pm_runtime_set_autosuspend_delay(cs42l42->dev, 3000); 554 pm_runtime_use_autosuspend(cs42l42->dev); 555 pm_runtime_mark_last_busy(cs42l42->dev); 556 pm_runtime_set_active(cs42l42->dev); 557 pm_runtime_get_noresume(cs42l42->dev); 558 pm_runtime_enable(cs42l42->dev); 559 560 ret = cs42l42_common_probe(cs42l42, component_drv, &cs42l42_sdw_dai); 561 if (ret < 0) 562 return ret; 563 564 return 0; 565 } 566 567 static int cs42l42_sdw_remove(struct sdw_slave *peripheral) 568 { 569 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev); 570 571 cs42l42_common_remove(cs42l42); 572 pm_runtime_disable(cs42l42->dev); 573 574 return 0; 575 } 576 577 static const struct dev_pm_ops cs42l42_sdw_pm = { 578 SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_sdw_resume) 579 SET_RUNTIME_PM_OPS(cs42l42_sdw_runtime_suspend, cs42l42_sdw_runtime_resume, NULL) 580 }; 581 582 static const struct sdw_device_id cs42l42_sdw_id[] = { 583 SDW_SLAVE_ENTRY(0x01FA, 0x4242, 0), 584 {}, 585 }; 586 MODULE_DEVICE_TABLE(sdw, cs42l42_sdw_id); 587 588 static struct sdw_driver cs42l42_sdw_driver = { 589 .driver = { 590 .name = "cs42l42-sdw", 591 .pm = &cs42l42_sdw_pm, 592 }, 593 .probe = cs42l42_sdw_probe, 594 .remove = cs42l42_sdw_remove, 595 .ops = &cs42l42_sdw_ops, 596 .id_table = cs42l42_sdw_id, 597 }; 598 599 module_sdw_driver(cs42l42_sdw_driver); 600 601 MODULE_DESCRIPTION("ASoC CS42L42 SoundWire driver"); 602 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 603 MODULE_LICENSE("GPL"); 604 MODULE_IMPORT_NS(SND_SOC_CS42L42_CORE); 605