1 /* 2 * CS4271 ASoC codec driver 3 * 4 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * This driver support CS4271 codec being master or slave, working 17 * in control port mode, connected either via SPI or I2C. 18 * The data format accepted is I2S or left-justified. 19 * DAPM support not implemented. 20 */ 21 22 #include <linux/module.h> 23 #include <linux/slab.h> 24 #include <linux/delay.h> 25 #include <linux/gpio.h> 26 #include <linux/i2c.h> 27 #include <linux/spi/spi.h> 28 #include <linux/of_device.h> 29 #include <linux/of_gpio.h> 30 #include <sound/pcm.h> 31 #include <sound/soc.h> 32 #include <sound/tlv.h> 33 #include <sound/cs4271.h> 34 35 #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 36 SNDRV_PCM_FMTBIT_S24_LE | \ 37 SNDRV_PCM_FMTBIT_S32_LE) 38 #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000 39 40 /* 41 * CS4271 registers 42 */ 43 #define CS4271_MODE1 0x01 /* Mode Control 1 */ 44 #define CS4271_DACCTL 0x02 /* DAC Control */ 45 #define CS4271_DACVOL 0x03 /* DAC Volume & Mixing Control */ 46 #define CS4271_VOLA 0x04 /* DAC Channel A Volume Control */ 47 #define CS4271_VOLB 0x05 /* DAC Channel B Volume Control */ 48 #define CS4271_ADCCTL 0x06 /* ADC Control */ 49 #define CS4271_MODE2 0x07 /* Mode Control 2 */ 50 #define CS4271_CHIPID 0x08 /* Chip ID */ 51 52 #define CS4271_FIRSTREG CS4271_MODE1 53 #define CS4271_LASTREG CS4271_MODE2 54 #define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1) 55 56 /* Bit masks for the CS4271 registers */ 57 #define CS4271_MODE1_MODE_MASK 0xC0 58 #define CS4271_MODE1_MODE_1X 0x00 59 #define CS4271_MODE1_MODE_2X 0x80 60 #define CS4271_MODE1_MODE_4X 0xC0 61 62 #define CS4271_MODE1_DIV_MASK 0x30 63 #define CS4271_MODE1_DIV_1 0x00 64 #define CS4271_MODE1_DIV_15 0x10 65 #define CS4271_MODE1_DIV_2 0x20 66 #define CS4271_MODE1_DIV_3 0x30 67 68 #define CS4271_MODE1_MASTER 0x08 69 70 #define CS4271_MODE1_DAC_DIF_MASK 0x07 71 #define CS4271_MODE1_DAC_DIF_LJ 0x00 72 #define CS4271_MODE1_DAC_DIF_I2S 0x01 73 #define CS4271_MODE1_DAC_DIF_RJ16 0x02 74 #define CS4271_MODE1_DAC_DIF_RJ24 0x03 75 #define CS4271_MODE1_DAC_DIF_RJ20 0x04 76 #define CS4271_MODE1_DAC_DIF_RJ18 0x05 77 78 #define CS4271_DACCTL_AMUTE 0x80 79 #define CS4271_DACCTL_IF_SLOW 0x40 80 81 #define CS4271_DACCTL_DEM_MASK 0x30 82 #define CS4271_DACCTL_DEM_DIS 0x00 83 #define CS4271_DACCTL_DEM_441 0x10 84 #define CS4271_DACCTL_DEM_48 0x20 85 #define CS4271_DACCTL_DEM_32 0x30 86 87 #define CS4271_DACCTL_SVRU 0x08 88 #define CS4271_DACCTL_SRD 0x04 89 #define CS4271_DACCTL_INVA 0x02 90 #define CS4271_DACCTL_INVB 0x01 91 92 #define CS4271_DACVOL_BEQUA 0x40 93 #define CS4271_DACVOL_SOFT 0x20 94 #define CS4271_DACVOL_ZEROC 0x10 95 96 #define CS4271_DACVOL_ATAPI_MASK 0x0F 97 #define CS4271_DACVOL_ATAPI_M_M 0x00 98 #define CS4271_DACVOL_ATAPI_M_BR 0x01 99 #define CS4271_DACVOL_ATAPI_M_BL 0x02 100 #define CS4271_DACVOL_ATAPI_M_BLR2 0x03 101 #define CS4271_DACVOL_ATAPI_AR_M 0x04 102 #define CS4271_DACVOL_ATAPI_AR_BR 0x05 103 #define CS4271_DACVOL_ATAPI_AR_BL 0x06 104 #define CS4271_DACVOL_ATAPI_AR_BLR2 0x07 105 #define CS4271_DACVOL_ATAPI_AL_M 0x08 106 #define CS4271_DACVOL_ATAPI_AL_BR 0x09 107 #define CS4271_DACVOL_ATAPI_AL_BL 0x0A 108 #define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B 109 #define CS4271_DACVOL_ATAPI_ALR2_M 0x0C 110 #define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D 111 #define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E 112 #define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F 113 114 #define CS4271_VOLA_MUTE 0x80 115 #define CS4271_VOLA_VOL_MASK 0x7F 116 #define CS4271_VOLB_MUTE 0x80 117 #define CS4271_VOLB_VOL_MASK 0x7F 118 119 #define CS4271_ADCCTL_DITHER16 0x20 120 121 #define CS4271_ADCCTL_ADC_DIF_MASK 0x10 122 #define CS4271_ADCCTL_ADC_DIF_LJ 0x00 123 #define CS4271_ADCCTL_ADC_DIF_I2S 0x10 124 125 #define CS4271_ADCCTL_MUTEA 0x08 126 #define CS4271_ADCCTL_MUTEB 0x04 127 #define CS4271_ADCCTL_HPFDA 0x02 128 #define CS4271_ADCCTL_HPFDB 0x01 129 130 #define CS4271_MODE2_LOOP 0x10 131 #define CS4271_MODE2_MUTECAEQUB 0x08 132 #define CS4271_MODE2_FREEZE 0x04 133 #define CS4271_MODE2_CPEN 0x02 134 #define CS4271_MODE2_PDN 0x01 135 136 #define CS4271_CHIPID_PART_MASK 0xF0 137 #define CS4271_CHIPID_REV_MASK 0x0F 138 139 /* 140 * Default CS4271 power-up configuration 141 * Array contains non-existing in hw register at address 0 142 * Array do not include Chip ID, as codec driver does not use 143 * registers read operations at all 144 */ 145 static const struct reg_default cs4271_reg_defaults[] = { 146 { CS4271_MODE1, 0, }, 147 { CS4271_DACCTL, CS4271_DACCTL_AMUTE, }, 148 { CS4271_DACVOL, CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, }, 149 { CS4271_VOLA, 0, }, 150 { CS4271_VOLB, 0, }, 151 { CS4271_ADCCTL, 0, }, 152 { CS4271_MODE2, 0, }, 153 }; 154 155 static bool cs4271_volatile_reg(struct device *dev, unsigned int reg) 156 { 157 return reg == CS4271_CHIPID; 158 } 159 160 struct cs4271_private { 161 /* SND_SOC_I2C or SND_SOC_SPI */ 162 unsigned int mclk; 163 bool master; 164 bool deemph; 165 struct regmap *regmap; 166 /* Current sample rate for de-emphasis control */ 167 int rate; 168 /* GPIO driving Reset pin, if any */ 169 int gpio_nreset; 170 /* GPIO that disable serial bus, if any */ 171 int gpio_disable; 172 /* enable soft reset workaround */ 173 bool enable_soft_reset; 174 }; 175 176 /* 177 * @freq is the desired MCLK rate 178 * MCLK rate should (c) be the sample rate, multiplied by one of the 179 * ratios listed in cs4271_mclk_fs_ratios table 180 */ 181 static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai, 182 int clk_id, unsigned int freq, int dir) 183 { 184 struct snd_soc_codec *codec = codec_dai->codec; 185 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 186 187 cs4271->mclk = freq; 188 return 0; 189 } 190 191 static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai, 192 unsigned int format) 193 { 194 struct snd_soc_codec *codec = codec_dai->codec; 195 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 196 unsigned int val = 0; 197 int ret; 198 199 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 200 case SND_SOC_DAIFMT_CBS_CFS: 201 cs4271->master = 0; 202 break; 203 case SND_SOC_DAIFMT_CBM_CFM: 204 cs4271->master = 1; 205 val |= CS4271_MODE1_MASTER; 206 break; 207 default: 208 dev_err(codec->dev, "Invalid DAI format\n"); 209 return -EINVAL; 210 } 211 212 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 213 case SND_SOC_DAIFMT_LEFT_J: 214 val |= CS4271_MODE1_DAC_DIF_LJ; 215 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL, 216 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ); 217 if (ret < 0) 218 return ret; 219 break; 220 case SND_SOC_DAIFMT_I2S: 221 val |= CS4271_MODE1_DAC_DIF_I2S; 222 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL, 223 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S); 224 if (ret < 0) 225 return ret; 226 break; 227 default: 228 dev_err(codec->dev, "Invalid DAI format\n"); 229 return -EINVAL; 230 } 231 232 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1, 233 CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val); 234 if (ret < 0) 235 return ret; 236 return 0; 237 } 238 239 static int cs4271_deemph[] = {0, 44100, 48000, 32000}; 240 241 static int cs4271_set_deemph(struct snd_soc_codec *codec) 242 { 243 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 244 int i, ret; 245 int val = CS4271_DACCTL_DEM_DIS; 246 247 if (cs4271->deemph) { 248 /* Find closest de-emphasis freq */ 249 val = 1; 250 for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++) 251 if (abs(cs4271_deemph[i] - cs4271->rate) < 252 abs(cs4271_deemph[val] - cs4271->rate)) 253 val = i; 254 val <<= 4; 255 } 256 257 ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL, 258 CS4271_DACCTL_DEM_MASK, val); 259 if (ret < 0) 260 return ret; 261 return 0; 262 } 263 264 static int cs4271_get_deemph(struct snd_kcontrol *kcontrol, 265 struct snd_ctl_elem_value *ucontrol) 266 { 267 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 268 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 269 270 ucontrol->value.enumerated.item[0] = cs4271->deemph; 271 return 0; 272 } 273 274 static int cs4271_put_deemph(struct snd_kcontrol *kcontrol, 275 struct snd_ctl_elem_value *ucontrol) 276 { 277 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 278 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 279 280 cs4271->deemph = ucontrol->value.enumerated.item[0]; 281 return cs4271_set_deemph(codec); 282 } 283 284 struct cs4271_clk_cfg { 285 bool master; /* codec mode */ 286 u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */ 287 unsigned short ratio; /* MCLK / sample rate */ 288 u8 ratio_mask; /* ratio bit mask for Master mode */ 289 }; 290 291 static struct cs4271_clk_cfg cs4271_clk_tab[] = { 292 {1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, 293 {1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15}, 294 {1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2}, 295 {1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3}, 296 {1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, 297 {1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15}, 298 {1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2}, 299 {1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3}, 300 {1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, 301 {1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15}, 302 {1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2}, 303 {1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3}, 304 {0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, 305 {0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1}, 306 {0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1}, 307 {0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2}, 308 {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2}, 309 {0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, 310 {0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1}, 311 {0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1}, 312 {0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2}, 313 {0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2}, 314 {0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, 315 {0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1}, 316 {0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1}, 317 {0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2}, 318 {0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2}, 319 }; 320 321 #define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab) 322 323 static int cs4271_hw_params(struct snd_pcm_substream *substream, 324 struct snd_pcm_hw_params *params, 325 struct snd_soc_dai *dai) 326 { 327 struct snd_soc_codec *codec = dai->codec; 328 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 329 int i, ret; 330 unsigned int ratio, val; 331 332 if (cs4271->enable_soft_reset) { 333 /* 334 * Put the codec in soft reset and back again in case it's not 335 * currently streaming data. This way of bringing the codec in 336 * sync to the current clocks is not explicitly documented in 337 * the data sheet, but it seems to work fine, and in contrast 338 * to a read hardware reset, we don't have to sync back all 339 * registers every time. 340 */ 341 342 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 343 !dai->capture_active) || 344 (substream->stream == SNDRV_PCM_STREAM_CAPTURE && 345 !dai->playback_active)) { 346 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 347 CS4271_MODE2_PDN, 348 CS4271_MODE2_PDN); 349 if (ret < 0) 350 return ret; 351 352 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 353 CS4271_MODE2_PDN, 0); 354 if (ret < 0) 355 return ret; 356 } 357 } 358 359 cs4271->rate = params_rate(params); 360 361 /* Configure DAC */ 362 if (cs4271->rate < 50000) 363 val = CS4271_MODE1_MODE_1X; 364 else if (cs4271->rate < 100000) 365 val = CS4271_MODE1_MODE_2X; 366 else 367 val = CS4271_MODE1_MODE_4X; 368 369 ratio = cs4271->mclk / cs4271->rate; 370 for (i = 0; i < CS4171_NR_RATIOS; i++) 371 if ((cs4271_clk_tab[i].master == cs4271->master) && 372 (cs4271_clk_tab[i].speed_mode == val) && 373 (cs4271_clk_tab[i].ratio == ratio)) 374 break; 375 376 if (i == CS4171_NR_RATIOS) { 377 dev_err(codec->dev, "Invalid sample rate\n"); 378 return -EINVAL; 379 } 380 381 val |= cs4271_clk_tab[i].ratio_mask; 382 383 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1, 384 CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val); 385 if (ret < 0) 386 return ret; 387 388 return cs4271_set_deemph(codec); 389 } 390 391 static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 392 { 393 struct snd_soc_codec *codec = dai->codec; 394 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 395 int ret; 396 int val_a = 0; 397 int val_b = 0; 398 399 if (stream != SNDRV_PCM_STREAM_PLAYBACK) 400 return 0; 401 402 if (mute) { 403 val_a = CS4271_VOLA_MUTE; 404 val_b = CS4271_VOLB_MUTE; 405 } 406 407 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA, 408 CS4271_VOLA_MUTE, val_a); 409 if (ret < 0) 410 return ret; 411 412 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB, 413 CS4271_VOLB_MUTE, val_b); 414 if (ret < 0) 415 return ret; 416 417 return 0; 418 } 419 420 /* CS4271 controls */ 421 static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0); 422 423 static const struct snd_kcontrol_new cs4271_snd_controls[] = { 424 SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB, 425 0, 0x7F, 1, cs4271_dac_tlv), 426 SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0), 427 SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0), 428 SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0), 429 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0, 430 cs4271_get_deemph, cs4271_put_deemph), 431 SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0), 432 SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0), 433 SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0), 434 SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0), 435 SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0), 436 SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0), 437 SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1), 438 SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0), 439 SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1), 440 SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB, 441 7, 1, 1), 442 }; 443 444 static const struct snd_soc_dai_ops cs4271_dai_ops = { 445 .hw_params = cs4271_hw_params, 446 .set_sysclk = cs4271_set_dai_sysclk, 447 .set_fmt = cs4271_set_dai_fmt, 448 .mute_stream = cs4271_mute_stream, 449 }; 450 451 static struct snd_soc_dai_driver cs4271_dai = { 452 .name = "cs4271-hifi", 453 .playback = { 454 .stream_name = "Playback", 455 .channels_min = 2, 456 .channels_max = 2, 457 .rates = CS4271_PCM_RATES, 458 .formats = CS4271_PCM_FORMATS, 459 }, 460 .capture = { 461 .stream_name = "Capture", 462 .channels_min = 2, 463 .channels_max = 2, 464 .rates = CS4271_PCM_RATES, 465 .formats = CS4271_PCM_FORMATS, 466 }, 467 .ops = &cs4271_dai_ops, 468 .symmetric_rates = 1, 469 }; 470 471 #ifdef CONFIG_PM 472 static int cs4271_soc_suspend(struct snd_soc_codec *codec) 473 { 474 int ret; 475 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 476 477 /* Set power-down bit */ 478 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 479 CS4271_MODE2_PDN, CS4271_MODE2_PDN); 480 if (ret < 0) 481 return ret; 482 483 return 0; 484 } 485 486 static int cs4271_soc_resume(struct snd_soc_codec *codec) 487 { 488 int ret; 489 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 490 491 /* Restore codec state */ 492 ret = regcache_sync(cs4271->regmap); 493 if (ret < 0) 494 return ret; 495 496 /* then disable the power-down bit */ 497 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 498 CS4271_MODE2_PDN, 0); 499 if (ret < 0) 500 return ret; 501 502 return 0; 503 } 504 #else 505 #define cs4271_soc_suspend NULL 506 #define cs4271_soc_resume NULL 507 #endif /* CONFIG_PM */ 508 509 #ifdef CONFIG_OF 510 static const struct of_device_id cs4271_dt_ids[] = { 511 { .compatible = "cirrus,cs4271", }, 512 { } 513 }; 514 MODULE_DEVICE_TABLE(of, cs4271_dt_ids); 515 #endif 516 517 static int cs4271_probe(struct snd_soc_codec *codec) 518 { 519 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 520 struct cs4271_platform_data *cs4271plat = codec->dev->platform_data; 521 int ret; 522 int gpio_nreset = -EINVAL; 523 bool amutec_eq_bmutec = false; 524 525 #ifdef CONFIG_OF 526 if (of_match_device(cs4271_dt_ids, codec->dev)) { 527 gpio_nreset = of_get_named_gpio(codec->dev->of_node, 528 "reset-gpio", 0); 529 530 if (of_get_property(codec->dev->of_node, 531 "cirrus,amutec-eq-bmutec", NULL)) 532 amutec_eq_bmutec = true; 533 534 if (of_get_property(codec->dev->of_node, 535 "cirrus,enable-soft-reset", NULL)) 536 cs4271->enable_soft_reset = true; 537 } 538 #endif 539 540 if (cs4271plat) { 541 if (gpio_is_valid(cs4271plat->gpio_nreset)) 542 gpio_nreset = cs4271plat->gpio_nreset; 543 544 amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec; 545 cs4271->enable_soft_reset = cs4271plat->enable_soft_reset; 546 } 547 548 if (gpio_nreset >= 0) 549 if (devm_gpio_request(codec->dev, gpio_nreset, "CS4271 Reset")) 550 gpio_nreset = -EINVAL; 551 if (gpio_nreset >= 0) { 552 /* Reset codec */ 553 gpio_direction_output(gpio_nreset, 0); 554 udelay(1); 555 gpio_set_value(gpio_nreset, 1); 556 /* Give the codec time to wake up */ 557 udelay(1); 558 } 559 560 cs4271->gpio_nreset = gpio_nreset; 561 562 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 563 CS4271_MODE2_PDN | CS4271_MODE2_CPEN, 564 CS4271_MODE2_PDN | CS4271_MODE2_CPEN); 565 if (ret < 0) 566 return ret; 567 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 568 CS4271_MODE2_PDN, 0); 569 if (ret < 0) 570 return ret; 571 /* Power-up sequence requires 85 uS */ 572 udelay(85); 573 574 if (amutec_eq_bmutec) 575 regmap_update_bits(cs4271->regmap, CS4271_MODE2, 576 CS4271_MODE2_MUTECAEQUB, 577 CS4271_MODE2_MUTECAEQUB); 578 579 return snd_soc_add_codec_controls(codec, cs4271_snd_controls, 580 ARRAY_SIZE(cs4271_snd_controls)); 581 } 582 583 static int cs4271_remove(struct snd_soc_codec *codec) 584 { 585 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 586 587 if (gpio_is_valid(cs4271->gpio_nreset)) 588 /* Set codec to the reset state */ 589 gpio_set_value(cs4271->gpio_nreset, 0); 590 591 return 0; 592 }; 593 594 static struct snd_soc_codec_driver soc_codec_dev_cs4271 = { 595 .probe = cs4271_probe, 596 .remove = cs4271_remove, 597 .suspend = cs4271_soc_suspend, 598 .resume = cs4271_soc_resume, 599 }; 600 601 #if defined(CONFIG_SPI_MASTER) 602 603 static const struct regmap_config cs4271_spi_regmap = { 604 .reg_bits = 16, 605 .val_bits = 8, 606 .max_register = CS4271_LASTREG, 607 .read_flag_mask = 0x21, 608 .write_flag_mask = 0x20, 609 610 .reg_defaults = cs4271_reg_defaults, 611 .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults), 612 .cache_type = REGCACHE_RBTREE, 613 614 .volatile_reg = cs4271_volatile_reg, 615 }; 616 617 static int cs4271_spi_probe(struct spi_device *spi) 618 { 619 struct cs4271_private *cs4271; 620 621 cs4271 = devm_kzalloc(&spi->dev, sizeof(*cs4271), GFP_KERNEL); 622 if (!cs4271) 623 return -ENOMEM; 624 625 spi_set_drvdata(spi, cs4271); 626 cs4271->regmap = devm_regmap_init_spi(spi, &cs4271_spi_regmap); 627 if (IS_ERR(cs4271->regmap)) 628 return PTR_ERR(cs4271->regmap); 629 630 return snd_soc_register_codec(&spi->dev, &soc_codec_dev_cs4271, 631 &cs4271_dai, 1); 632 } 633 634 static int cs4271_spi_remove(struct spi_device *spi) 635 { 636 snd_soc_unregister_codec(&spi->dev); 637 return 0; 638 } 639 640 static struct spi_driver cs4271_spi_driver = { 641 .driver = { 642 .name = "cs4271", 643 .owner = THIS_MODULE, 644 .of_match_table = of_match_ptr(cs4271_dt_ids), 645 }, 646 .probe = cs4271_spi_probe, 647 .remove = cs4271_spi_remove, 648 }; 649 #endif /* defined(CONFIG_SPI_MASTER) */ 650 651 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 652 static const struct i2c_device_id cs4271_i2c_id[] = { 653 {"cs4271", 0}, 654 {} 655 }; 656 MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id); 657 658 static const struct regmap_config cs4271_i2c_regmap = { 659 .reg_bits = 8, 660 .val_bits = 8, 661 .max_register = CS4271_LASTREG, 662 663 .reg_defaults = cs4271_reg_defaults, 664 .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults), 665 .cache_type = REGCACHE_RBTREE, 666 667 .volatile_reg = cs4271_volatile_reg, 668 }; 669 670 static int cs4271_i2c_probe(struct i2c_client *client, 671 const struct i2c_device_id *id) 672 { 673 struct cs4271_private *cs4271; 674 675 cs4271 = devm_kzalloc(&client->dev, sizeof(*cs4271), GFP_KERNEL); 676 if (!cs4271) 677 return -ENOMEM; 678 679 i2c_set_clientdata(client, cs4271); 680 cs4271->regmap = devm_regmap_init_i2c(client, &cs4271_i2c_regmap); 681 if (IS_ERR(cs4271->regmap)) 682 return PTR_ERR(cs4271->regmap); 683 684 return snd_soc_register_codec(&client->dev, &soc_codec_dev_cs4271, 685 &cs4271_dai, 1); 686 } 687 688 static int cs4271_i2c_remove(struct i2c_client *client) 689 { 690 snd_soc_unregister_codec(&client->dev); 691 return 0; 692 } 693 694 static struct i2c_driver cs4271_i2c_driver = { 695 .driver = { 696 .name = "cs4271", 697 .owner = THIS_MODULE, 698 .of_match_table = of_match_ptr(cs4271_dt_ids), 699 }, 700 .id_table = cs4271_i2c_id, 701 .probe = cs4271_i2c_probe, 702 .remove = cs4271_i2c_remove, 703 }; 704 #endif /* defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) */ 705 706 /* 707 * We only register our serial bus driver here without 708 * assignment to particular chip. So if any of the below 709 * fails, there is some problem with I2C or SPI subsystem. 710 * In most cases this module will be compiled with support 711 * of only one serial bus. 712 */ 713 static int __init cs4271_modinit(void) 714 { 715 int ret; 716 717 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 718 ret = i2c_add_driver(&cs4271_i2c_driver); 719 if (ret) { 720 pr_err("Failed to register CS4271 I2C driver: %d\n", ret); 721 return ret; 722 } 723 #endif 724 725 #if defined(CONFIG_SPI_MASTER) 726 ret = spi_register_driver(&cs4271_spi_driver); 727 if (ret) { 728 pr_err("Failed to register CS4271 SPI driver: %d\n", ret); 729 return ret; 730 } 731 #endif 732 733 return 0; 734 } 735 module_init(cs4271_modinit); 736 737 static void __exit cs4271_modexit(void) 738 { 739 #if defined(CONFIG_SPI_MASTER) 740 spi_unregister_driver(&cs4271_spi_driver); 741 #endif 742 743 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 744 i2c_del_driver(&cs4271_i2c_driver); 745 #endif 746 } 747 module_exit(cs4271_modexit); 748 749 MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>"); 750 MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver"); 751 MODULE_LICENSE("GPL"); 752