1 /* 2 * CS4271 ASoC codec driver 3 * 4 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * This driver support CS4271 codec being master or slave, working 17 * in control port mode, connected either via SPI or I2C. 18 * The data format accepted is I2S or left-justified. 19 * DAPM support not implemented. 20 */ 21 22 #include <linux/module.h> 23 #include <linux/slab.h> 24 #include <linux/delay.h> 25 #include <linux/gpio.h> 26 #include <linux/i2c.h> 27 #include <linux/spi/spi.h> 28 #include <linux/of_device.h> 29 #include <linux/of_gpio.h> 30 #include <sound/pcm.h> 31 #include <sound/soc.h> 32 #include <sound/tlv.h> 33 #include <sound/cs4271.h> 34 35 #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 36 SNDRV_PCM_FMTBIT_S24_LE | \ 37 SNDRV_PCM_FMTBIT_S32_LE) 38 #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000 39 40 /* 41 * CS4271 registers 42 */ 43 #define CS4271_MODE1 0x01 /* Mode Control 1 */ 44 #define CS4271_DACCTL 0x02 /* DAC Control */ 45 #define CS4271_DACVOL 0x03 /* DAC Volume & Mixing Control */ 46 #define CS4271_VOLA 0x04 /* DAC Channel A Volume Control */ 47 #define CS4271_VOLB 0x05 /* DAC Channel B Volume Control */ 48 #define CS4271_ADCCTL 0x06 /* ADC Control */ 49 #define CS4271_MODE2 0x07 /* Mode Control 2 */ 50 #define CS4271_CHIPID 0x08 /* Chip ID */ 51 52 #define CS4271_FIRSTREG CS4271_MODE1 53 #define CS4271_LASTREG CS4271_MODE2 54 #define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1) 55 56 /* Bit masks for the CS4271 registers */ 57 #define CS4271_MODE1_MODE_MASK 0xC0 58 #define CS4271_MODE1_MODE_1X 0x00 59 #define CS4271_MODE1_MODE_2X 0x80 60 #define CS4271_MODE1_MODE_4X 0xC0 61 62 #define CS4271_MODE1_DIV_MASK 0x30 63 #define CS4271_MODE1_DIV_1 0x00 64 #define CS4271_MODE1_DIV_15 0x10 65 #define CS4271_MODE1_DIV_2 0x20 66 #define CS4271_MODE1_DIV_3 0x30 67 68 #define CS4271_MODE1_MASTER 0x08 69 70 #define CS4271_MODE1_DAC_DIF_MASK 0x07 71 #define CS4271_MODE1_DAC_DIF_LJ 0x00 72 #define CS4271_MODE1_DAC_DIF_I2S 0x01 73 #define CS4271_MODE1_DAC_DIF_RJ16 0x02 74 #define CS4271_MODE1_DAC_DIF_RJ24 0x03 75 #define CS4271_MODE1_DAC_DIF_RJ20 0x04 76 #define CS4271_MODE1_DAC_DIF_RJ18 0x05 77 78 #define CS4271_DACCTL_AMUTE 0x80 79 #define CS4271_DACCTL_IF_SLOW 0x40 80 81 #define CS4271_DACCTL_DEM_MASK 0x30 82 #define CS4271_DACCTL_DEM_DIS 0x00 83 #define CS4271_DACCTL_DEM_441 0x10 84 #define CS4271_DACCTL_DEM_48 0x20 85 #define CS4271_DACCTL_DEM_32 0x30 86 87 #define CS4271_DACCTL_SVRU 0x08 88 #define CS4271_DACCTL_SRD 0x04 89 #define CS4271_DACCTL_INVA 0x02 90 #define CS4271_DACCTL_INVB 0x01 91 92 #define CS4271_DACVOL_BEQUA 0x40 93 #define CS4271_DACVOL_SOFT 0x20 94 #define CS4271_DACVOL_ZEROC 0x10 95 96 #define CS4271_DACVOL_ATAPI_MASK 0x0F 97 #define CS4271_DACVOL_ATAPI_M_M 0x00 98 #define CS4271_DACVOL_ATAPI_M_BR 0x01 99 #define CS4271_DACVOL_ATAPI_M_BL 0x02 100 #define CS4271_DACVOL_ATAPI_M_BLR2 0x03 101 #define CS4271_DACVOL_ATAPI_AR_M 0x04 102 #define CS4271_DACVOL_ATAPI_AR_BR 0x05 103 #define CS4271_DACVOL_ATAPI_AR_BL 0x06 104 #define CS4271_DACVOL_ATAPI_AR_BLR2 0x07 105 #define CS4271_DACVOL_ATAPI_AL_M 0x08 106 #define CS4271_DACVOL_ATAPI_AL_BR 0x09 107 #define CS4271_DACVOL_ATAPI_AL_BL 0x0A 108 #define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B 109 #define CS4271_DACVOL_ATAPI_ALR2_M 0x0C 110 #define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D 111 #define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E 112 #define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F 113 114 #define CS4271_VOLA_MUTE 0x80 115 #define CS4271_VOLA_VOL_MASK 0x7F 116 #define CS4271_VOLB_MUTE 0x80 117 #define CS4271_VOLB_VOL_MASK 0x7F 118 119 #define CS4271_ADCCTL_DITHER16 0x20 120 121 #define CS4271_ADCCTL_ADC_DIF_MASK 0x10 122 #define CS4271_ADCCTL_ADC_DIF_LJ 0x00 123 #define CS4271_ADCCTL_ADC_DIF_I2S 0x10 124 125 #define CS4271_ADCCTL_MUTEA 0x08 126 #define CS4271_ADCCTL_MUTEB 0x04 127 #define CS4271_ADCCTL_HPFDA 0x02 128 #define CS4271_ADCCTL_HPFDB 0x01 129 130 #define CS4271_MODE2_LOOP 0x10 131 #define CS4271_MODE2_MUTECAEQUB 0x08 132 #define CS4271_MODE2_FREEZE 0x04 133 #define CS4271_MODE2_CPEN 0x02 134 #define CS4271_MODE2_PDN 0x01 135 136 #define CS4271_CHIPID_PART_MASK 0xF0 137 #define CS4271_CHIPID_REV_MASK 0x0F 138 139 /* 140 * Default CS4271 power-up configuration 141 * Array contains non-existing in hw register at address 0 142 * Array do not include Chip ID, as codec driver does not use 143 * registers read operations at all 144 */ 145 static const struct reg_default cs4271_reg_defaults[] = { 146 { CS4271_MODE1, 0, }, 147 { CS4271_DACCTL, CS4271_DACCTL_AMUTE, }, 148 { CS4271_DACVOL, CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, }, 149 { CS4271_VOLA, 0, }, 150 { CS4271_VOLB, 0, }, 151 { CS4271_ADCCTL, 0, }, 152 { CS4271_MODE2, 0, }, 153 }; 154 155 static bool cs4271_volatile_reg(struct device *dev, unsigned int reg) 156 { 157 return reg == CS4271_CHIPID; 158 } 159 160 struct cs4271_private { 161 /* SND_SOC_I2C or SND_SOC_SPI */ 162 unsigned int mclk; 163 bool master; 164 bool deemph; 165 struct regmap *regmap; 166 /* Current sample rate for de-emphasis control */ 167 int rate; 168 /* GPIO driving Reset pin, if any */ 169 int gpio_nreset; 170 /* GPIO that disable serial bus, if any */ 171 int gpio_disable; 172 /* enable soft reset workaround */ 173 bool enable_soft_reset; 174 }; 175 176 static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = { 177 SND_SOC_DAPM_INPUT("AINA"), 178 SND_SOC_DAPM_INPUT("AINB"), 179 180 SND_SOC_DAPM_OUTPUT("AOUTA+"), 181 SND_SOC_DAPM_OUTPUT("AOUTA-"), 182 SND_SOC_DAPM_OUTPUT("AOUTB+"), 183 SND_SOC_DAPM_OUTPUT("AOUTB-"), 184 }; 185 186 static const struct snd_soc_dapm_route cs4271_dapm_routes[] = { 187 { "Capture", NULL, "AINA" }, 188 { "Capture", NULL, "AINB" }, 189 190 { "AOUTA+", NULL, "Playback" }, 191 { "AOUTA-", NULL, "Playback" }, 192 { "AOUTB+", NULL, "Playback" }, 193 { "AOUTB-", NULL, "Playback" }, 194 }; 195 196 /* 197 * @freq is the desired MCLK rate 198 * MCLK rate should (c) be the sample rate, multiplied by one of the 199 * ratios listed in cs4271_mclk_fs_ratios table 200 */ 201 static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai, 202 int clk_id, unsigned int freq, int dir) 203 { 204 struct snd_soc_codec *codec = codec_dai->codec; 205 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 206 207 cs4271->mclk = freq; 208 return 0; 209 } 210 211 static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai, 212 unsigned int format) 213 { 214 struct snd_soc_codec *codec = codec_dai->codec; 215 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 216 unsigned int val = 0; 217 int ret; 218 219 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 220 case SND_SOC_DAIFMT_CBS_CFS: 221 cs4271->master = 0; 222 break; 223 case SND_SOC_DAIFMT_CBM_CFM: 224 cs4271->master = 1; 225 val |= CS4271_MODE1_MASTER; 226 break; 227 default: 228 dev_err(codec->dev, "Invalid DAI format\n"); 229 return -EINVAL; 230 } 231 232 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 233 case SND_SOC_DAIFMT_LEFT_J: 234 val |= CS4271_MODE1_DAC_DIF_LJ; 235 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL, 236 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ); 237 if (ret < 0) 238 return ret; 239 break; 240 case SND_SOC_DAIFMT_I2S: 241 val |= CS4271_MODE1_DAC_DIF_I2S; 242 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL, 243 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S); 244 if (ret < 0) 245 return ret; 246 break; 247 default: 248 dev_err(codec->dev, "Invalid DAI format\n"); 249 return -EINVAL; 250 } 251 252 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1, 253 CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val); 254 if (ret < 0) 255 return ret; 256 return 0; 257 } 258 259 static int cs4271_deemph[] = {0, 44100, 48000, 32000}; 260 261 static int cs4271_set_deemph(struct snd_soc_codec *codec) 262 { 263 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 264 int i, ret; 265 int val = CS4271_DACCTL_DEM_DIS; 266 267 if (cs4271->deemph) { 268 /* Find closest de-emphasis freq */ 269 val = 1; 270 for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++) 271 if (abs(cs4271_deemph[i] - cs4271->rate) < 272 abs(cs4271_deemph[val] - cs4271->rate)) 273 val = i; 274 val <<= 4; 275 } 276 277 ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL, 278 CS4271_DACCTL_DEM_MASK, val); 279 if (ret < 0) 280 return ret; 281 return 0; 282 } 283 284 static int cs4271_get_deemph(struct snd_kcontrol *kcontrol, 285 struct snd_ctl_elem_value *ucontrol) 286 { 287 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 288 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 289 290 ucontrol->value.enumerated.item[0] = cs4271->deemph; 291 return 0; 292 } 293 294 static int cs4271_put_deemph(struct snd_kcontrol *kcontrol, 295 struct snd_ctl_elem_value *ucontrol) 296 { 297 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 298 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 299 300 cs4271->deemph = ucontrol->value.enumerated.item[0]; 301 return cs4271_set_deemph(codec); 302 } 303 304 struct cs4271_clk_cfg { 305 bool master; /* codec mode */ 306 u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */ 307 unsigned short ratio; /* MCLK / sample rate */ 308 u8 ratio_mask; /* ratio bit mask for Master mode */ 309 }; 310 311 static struct cs4271_clk_cfg cs4271_clk_tab[] = { 312 {1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, 313 {1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15}, 314 {1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2}, 315 {1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3}, 316 {1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, 317 {1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15}, 318 {1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2}, 319 {1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3}, 320 {1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, 321 {1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15}, 322 {1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2}, 323 {1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3}, 324 {0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, 325 {0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1}, 326 {0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1}, 327 {0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2}, 328 {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2}, 329 {0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, 330 {0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1}, 331 {0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1}, 332 {0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2}, 333 {0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2}, 334 {0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, 335 {0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1}, 336 {0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1}, 337 {0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2}, 338 {0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2}, 339 }; 340 341 #define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab) 342 343 static int cs4271_hw_params(struct snd_pcm_substream *substream, 344 struct snd_pcm_hw_params *params, 345 struct snd_soc_dai *dai) 346 { 347 struct snd_soc_codec *codec = dai->codec; 348 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 349 int i, ret; 350 unsigned int ratio, val; 351 352 if (cs4271->enable_soft_reset) { 353 /* 354 * Put the codec in soft reset and back again in case it's not 355 * currently streaming data. This way of bringing the codec in 356 * sync to the current clocks is not explicitly documented in 357 * the data sheet, but it seems to work fine, and in contrast 358 * to a read hardware reset, we don't have to sync back all 359 * registers every time. 360 */ 361 362 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 363 !dai->capture_active) || 364 (substream->stream == SNDRV_PCM_STREAM_CAPTURE && 365 !dai->playback_active)) { 366 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 367 CS4271_MODE2_PDN, 368 CS4271_MODE2_PDN); 369 if (ret < 0) 370 return ret; 371 372 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 373 CS4271_MODE2_PDN, 0); 374 if (ret < 0) 375 return ret; 376 } 377 } 378 379 cs4271->rate = params_rate(params); 380 381 /* Configure DAC */ 382 if (cs4271->rate < 50000) 383 val = CS4271_MODE1_MODE_1X; 384 else if (cs4271->rate < 100000) 385 val = CS4271_MODE1_MODE_2X; 386 else 387 val = CS4271_MODE1_MODE_4X; 388 389 ratio = cs4271->mclk / cs4271->rate; 390 for (i = 0; i < CS4171_NR_RATIOS; i++) 391 if ((cs4271_clk_tab[i].master == cs4271->master) && 392 (cs4271_clk_tab[i].speed_mode == val) && 393 (cs4271_clk_tab[i].ratio == ratio)) 394 break; 395 396 if (i == CS4171_NR_RATIOS) { 397 dev_err(codec->dev, "Invalid sample rate\n"); 398 return -EINVAL; 399 } 400 401 val |= cs4271_clk_tab[i].ratio_mask; 402 403 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1, 404 CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val); 405 if (ret < 0) 406 return ret; 407 408 return cs4271_set_deemph(codec); 409 } 410 411 static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 412 { 413 struct snd_soc_codec *codec = dai->codec; 414 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 415 int ret; 416 int val_a = 0; 417 int val_b = 0; 418 419 if (stream != SNDRV_PCM_STREAM_PLAYBACK) 420 return 0; 421 422 if (mute) { 423 val_a = CS4271_VOLA_MUTE; 424 val_b = CS4271_VOLB_MUTE; 425 } 426 427 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA, 428 CS4271_VOLA_MUTE, val_a); 429 if (ret < 0) 430 return ret; 431 432 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB, 433 CS4271_VOLB_MUTE, val_b); 434 if (ret < 0) 435 return ret; 436 437 return 0; 438 } 439 440 /* CS4271 controls */ 441 static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0); 442 443 static const struct snd_kcontrol_new cs4271_snd_controls[] = { 444 SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB, 445 0, 0x7F, 1, cs4271_dac_tlv), 446 SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0), 447 SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0), 448 SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0), 449 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0, 450 cs4271_get_deemph, cs4271_put_deemph), 451 SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0), 452 SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0), 453 SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0), 454 SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0), 455 SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0), 456 SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0), 457 SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1), 458 SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0), 459 SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1), 460 SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB, 461 7, 1, 1), 462 }; 463 464 static const struct snd_soc_dai_ops cs4271_dai_ops = { 465 .hw_params = cs4271_hw_params, 466 .set_sysclk = cs4271_set_dai_sysclk, 467 .set_fmt = cs4271_set_dai_fmt, 468 .mute_stream = cs4271_mute_stream, 469 }; 470 471 static struct snd_soc_dai_driver cs4271_dai = { 472 .name = "cs4271-hifi", 473 .playback = { 474 .stream_name = "Playback", 475 .channels_min = 2, 476 .channels_max = 2, 477 .rates = CS4271_PCM_RATES, 478 .formats = CS4271_PCM_FORMATS, 479 }, 480 .capture = { 481 .stream_name = "Capture", 482 .channels_min = 2, 483 .channels_max = 2, 484 .rates = CS4271_PCM_RATES, 485 .formats = CS4271_PCM_FORMATS, 486 }, 487 .ops = &cs4271_dai_ops, 488 .symmetric_rates = 1, 489 }; 490 491 #ifdef CONFIG_PM 492 static int cs4271_soc_suspend(struct snd_soc_codec *codec) 493 { 494 int ret; 495 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 496 497 /* Set power-down bit */ 498 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 499 CS4271_MODE2_PDN, CS4271_MODE2_PDN); 500 if (ret < 0) 501 return ret; 502 503 return 0; 504 } 505 506 static int cs4271_soc_resume(struct snd_soc_codec *codec) 507 { 508 int ret; 509 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 510 511 /* Restore codec state */ 512 ret = regcache_sync(cs4271->regmap); 513 if (ret < 0) 514 return ret; 515 516 /* then disable the power-down bit */ 517 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 518 CS4271_MODE2_PDN, 0); 519 if (ret < 0) 520 return ret; 521 522 return 0; 523 } 524 #else 525 #define cs4271_soc_suspend NULL 526 #define cs4271_soc_resume NULL 527 #endif /* CONFIG_PM */ 528 529 #ifdef CONFIG_OF 530 static const struct of_device_id cs4271_dt_ids[] = { 531 { .compatible = "cirrus,cs4271", }, 532 { } 533 }; 534 MODULE_DEVICE_TABLE(of, cs4271_dt_ids); 535 #endif 536 537 static int cs4271_probe(struct snd_soc_codec *codec) 538 { 539 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 540 struct cs4271_platform_data *cs4271plat = codec->dev->platform_data; 541 int ret; 542 int gpio_nreset = -EINVAL; 543 bool amutec_eq_bmutec = false; 544 545 #ifdef CONFIG_OF 546 if (of_match_device(cs4271_dt_ids, codec->dev)) { 547 gpio_nreset = of_get_named_gpio(codec->dev->of_node, 548 "reset-gpio", 0); 549 550 if (of_get_property(codec->dev->of_node, 551 "cirrus,amutec-eq-bmutec", NULL)) 552 amutec_eq_bmutec = true; 553 554 if (of_get_property(codec->dev->of_node, 555 "cirrus,enable-soft-reset", NULL)) 556 cs4271->enable_soft_reset = true; 557 } 558 #endif 559 560 if (cs4271plat) { 561 if (gpio_is_valid(cs4271plat->gpio_nreset)) 562 gpio_nreset = cs4271plat->gpio_nreset; 563 564 amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec; 565 cs4271->enable_soft_reset = cs4271plat->enable_soft_reset; 566 } 567 568 if (gpio_nreset >= 0) 569 if (devm_gpio_request(codec->dev, gpio_nreset, "CS4271 Reset")) 570 gpio_nreset = -EINVAL; 571 if (gpio_nreset >= 0) { 572 /* Reset codec */ 573 gpio_direction_output(gpio_nreset, 0); 574 udelay(1); 575 gpio_set_value(gpio_nreset, 1); 576 /* Give the codec time to wake up */ 577 udelay(1); 578 } 579 580 cs4271->gpio_nreset = gpio_nreset; 581 582 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 583 CS4271_MODE2_PDN | CS4271_MODE2_CPEN, 584 CS4271_MODE2_PDN | CS4271_MODE2_CPEN); 585 if (ret < 0) 586 return ret; 587 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 588 CS4271_MODE2_PDN, 0); 589 if (ret < 0) 590 return ret; 591 /* Power-up sequence requires 85 uS */ 592 udelay(85); 593 594 if (amutec_eq_bmutec) 595 regmap_update_bits(cs4271->regmap, CS4271_MODE2, 596 CS4271_MODE2_MUTECAEQUB, 597 CS4271_MODE2_MUTECAEQUB); 598 599 return 0; 600 } 601 602 static int cs4271_remove(struct snd_soc_codec *codec) 603 { 604 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 605 606 if (gpio_is_valid(cs4271->gpio_nreset)) 607 /* Set codec to the reset state */ 608 gpio_set_value(cs4271->gpio_nreset, 0); 609 610 return 0; 611 }; 612 613 static struct snd_soc_codec_driver soc_codec_dev_cs4271 = { 614 .probe = cs4271_probe, 615 .remove = cs4271_remove, 616 .suspend = cs4271_soc_suspend, 617 .resume = cs4271_soc_resume, 618 619 .controls = cs4271_snd_controls, 620 .num_controls = ARRAY_SIZE(cs4271_snd_controls), 621 .dapm_widgets = cs4271_dapm_widgets, 622 .num_dapm_widgets = ARRAY_SIZE(cs4271_dapm_widgets), 623 .dapm_routes = cs4271_dapm_routes, 624 .num_dapm_routes = ARRAY_SIZE(cs4271_dapm_routes), 625 }; 626 627 #if defined(CONFIG_SPI_MASTER) 628 629 static const struct regmap_config cs4271_spi_regmap = { 630 .reg_bits = 16, 631 .val_bits = 8, 632 .max_register = CS4271_LASTREG, 633 .read_flag_mask = 0x21, 634 .write_flag_mask = 0x20, 635 636 .reg_defaults = cs4271_reg_defaults, 637 .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults), 638 .cache_type = REGCACHE_RBTREE, 639 640 .volatile_reg = cs4271_volatile_reg, 641 }; 642 643 static int cs4271_spi_probe(struct spi_device *spi) 644 { 645 struct cs4271_private *cs4271; 646 647 cs4271 = devm_kzalloc(&spi->dev, sizeof(*cs4271), GFP_KERNEL); 648 if (!cs4271) 649 return -ENOMEM; 650 651 spi_set_drvdata(spi, cs4271); 652 cs4271->regmap = devm_regmap_init_spi(spi, &cs4271_spi_regmap); 653 if (IS_ERR(cs4271->regmap)) 654 return PTR_ERR(cs4271->regmap); 655 656 return snd_soc_register_codec(&spi->dev, &soc_codec_dev_cs4271, 657 &cs4271_dai, 1); 658 } 659 660 static int cs4271_spi_remove(struct spi_device *spi) 661 { 662 snd_soc_unregister_codec(&spi->dev); 663 return 0; 664 } 665 666 static struct spi_driver cs4271_spi_driver = { 667 .driver = { 668 .name = "cs4271", 669 .owner = THIS_MODULE, 670 .of_match_table = of_match_ptr(cs4271_dt_ids), 671 }, 672 .probe = cs4271_spi_probe, 673 .remove = cs4271_spi_remove, 674 }; 675 #endif /* defined(CONFIG_SPI_MASTER) */ 676 677 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 678 static const struct i2c_device_id cs4271_i2c_id[] = { 679 {"cs4271", 0}, 680 {} 681 }; 682 MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id); 683 684 static const struct regmap_config cs4271_i2c_regmap = { 685 .reg_bits = 8, 686 .val_bits = 8, 687 .max_register = CS4271_LASTREG, 688 689 .reg_defaults = cs4271_reg_defaults, 690 .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults), 691 .cache_type = REGCACHE_RBTREE, 692 693 .volatile_reg = cs4271_volatile_reg, 694 }; 695 696 static int cs4271_i2c_probe(struct i2c_client *client, 697 const struct i2c_device_id *id) 698 { 699 struct cs4271_private *cs4271; 700 701 cs4271 = devm_kzalloc(&client->dev, sizeof(*cs4271), GFP_KERNEL); 702 if (!cs4271) 703 return -ENOMEM; 704 705 i2c_set_clientdata(client, cs4271); 706 cs4271->regmap = devm_regmap_init_i2c(client, &cs4271_i2c_regmap); 707 if (IS_ERR(cs4271->regmap)) 708 return PTR_ERR(cs4271->regmap); 709 710 return snd_soc_register_codec(&client->dev, &soc_codec_dev_cs4271, 711 &cs4271_dai, 1); 712 } 713 714 static int cs4271_i2c_remove(struct i2c_client *client) 715 { 716 snd_soc_unregister_codec(&client->dev); 717 return 0; 718 } 719 720 static struct i2c_driver cs4271_i2c_driver = { 721 .driver = { 722 .name = "cs4271", 723 .owner = THIS_MODULE, 724 .of_match_table = of_match_ptr(cs4271_dt_ids), 725 }, 726 .id_table = cs4271_i2c_id, 727 .probe = cs4271_i2c_probe, 728 .remove = cs4271_i2c_remove, 729 }; 730 #endif /* defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) */ 731 732 /* 733 * We only register our serial bus driver here without 734 * assignment to particular chip. So if any of the below 735 * fails, there is some problem with I2C or SPI subsystem. 736 * In most cases this module will be compiled with support 737 * of only one serial bus. 738 */ 739 static int __init cs4271_modinit(void) 740 { 741 int ret; 742 743 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 744 ret = i2c_add_driver(&cs4271_i2c_driver); 745 if (ret) { 746 pr_err("Failed to register CS4271 I2C driver: %d\n", ret); 747 return ret; 748 } 749 #endif 750 751 #if defined(CONFIG_SPI_MASTER) 752 ret = spi_register_driver(&cs4271_spi_driver); 753 if (ret) { 754 pr_err("Failed to register CS4271 SPI driver: %d\n", ret); 755 return ret; 756 } 757 #endif 758 759 return 0; 760 } 761 module_init(cs4271_modinit); 762 763 static void __exit cs4271_modexit(void) 764 { 765 #if defined(CONFIG_SPI_MASTER) 766 spi_unregister_driver(&cs4271_spi_driver); 767 #endif 768 769 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 770 i2c_del_driver(&cs4271_i2c_driver); 771 #endif 772 } 773 module_exit(cs4271_modexit); 774 775 MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>"); 776 MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver"); 777 MODULE_LICENSE("GPL"); 778