1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs4265.c -- CS4265 ALSA SoC audio driver 4 * 5 * Copyright 2014 Cirrus Logic, Inc. 6 * 7 * Author: Paul Handrigan <paul.handrigan@cirrus.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/kernel.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/i2c.h> 17 #include <linux/input.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <linux/platform_device.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/soc-dapm.h> 26 #include <sound/initval.h> 27 #include <sound/tlv.h> 28 #include "cs4265.h" 29 30 struct cs4265_private { 31 struct regmap *regmap; 32 struct gpio_desc *reset_gpio; 33 u8 format; 34 u32 sysclk; 35 }; 36 37 static const struct reg_default cs4265_reg_defaults[] = { 38 { CS4265_PWRCTL, 0x0F }, 39 { CS4265_DAC_CTL, 0x08 }, 40 { CS4265_ADC_CTL, 0x00 }, 41 { CS4265_MCLK_FREQ, 0x00 }, 42 { CS4265_SIG_SEL, 0x40 }, 43 { CS4265_CHB_PGA_CTL, 0x00 }, 44 { CS4265_CHA_PGA_CTL, 0x00 }, 45 { CS4265_ADC_CTL2, 0x19 }, 46 { CS4265_DAC_CHA_VOL, 0x00 }, 47 { CS4265_DAC_CHB_VOL, 0x00 }, 48 { CS4265_DAC_CTL2, 0xC0 }, 49 { CS4265_SPDIF_CTL1, 0x00 }, 50 { CS4265_SPDIF_CTL2, 0x00 }, 51 { CS4265_INT_MASK, 0x00 }, 52 { CS4265_STATUS_MODE_MSB, 0x00 }, 53 { CS4265_STATUS_MODE_LSB, 0x00 }, 54 }; 55 56 static bool cs4265_readable_register(struct device *dev, unsigned int reg) 57 { 58 switch (reg) { 59 case CS4265_CHIP_ID ... CS4265_MAX_REGISTER: 60 return true; 61 default: 62 return false; 63 } 64 } 65 66 static bool cs4265_volatile_register(struct device *dev, unsigned int reg) 67 { 68 switch (reg) { 69 case CS4265_INT_STATUS: 70 return true; 71 default: 72 return false; 73 } 74 } 75 76 static DECLARE_TLV_DB_SCALE(pga_tlv, -1200, 50, 0); 77 78 static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 0); 79 80 static const char * const digital_input_mux_text[] = { 81 "SDIN1", "SDIN2" 82 }; 83 84 static SOC_ENUM_SINGLE_DECL(digital_input_mux_enum, CS4265_SIG_SEL, 7, 85 digital_input_mux_text); 86 87 static const struct snd_kcontrol_new digital_input_mux = 88 SOC_DAPM_ENUM("Digital Input Mux", digital_input_mux_enum); 89 90 static const char * const mic_linein_text[] = { 91 "MIC", "LINEIN" 92 }; 93 94 static SOC_ENUM_SINGLE_DECL(mic_linein_enum, CS4265_ADC_CTL2, 0, 95 mic_linein_text); 96 97 static const char * const cam_mode_text[] = { 98 "One Byte", "Two Byte" 99 }; 100 101 static SOC_ENUM_SINGLE_DECL(cam_mode_enum, CS4265_SPDIF_CTL1, 5, 102 cam_mode_text); 103 104 static const char * const cam_mono_stereo_text[] = { 105 "Stereo", "Mono" 106 }; 107 108 static SOC_ENUM_SINGLE_DECL(spdif_mono_stereo_enum, CS4265_SPDIF_CTL2, 2, 109 cam_mono_stereo_text); 110 111 static const char * const mono_select_text[] = { 112 "Channel A", "Channel B" 113 }; 114 115 static SOC_ENUM_SINGLE_DECL(spdif_mono_select_enum, CS4265_SPDIF_CTL2, 0, 116 mono_select_text); 117 118 static const struct snd_kcontrol_new mic_linein_mux = 119 SOC_DAPM_ENUM("ADC Input Capture Mux", mic_linein_enum); 120 121 static const struct snd_kcontrol_new loopback_ctl = 122 SOC_DAPM_SINGLE("Switch", CS4265_SIG_SEL, 1, 1, 0); 123 124 static const struct snd_kcontrol_new spdif_switch = 125 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 0, 0); 126 127 static const struct snd_kcontrol_new dac_switch = 128 SOC_DAPM_SINGLE("Switch", CS4265_PWRCTL, 1, 1, 0); 129 130 static const struct snd_kcontrol_new cs4265_snd_controls[] = { 131 132 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS4265_CHA_PGA_CTL, 133 CS4265_CHB_PGA_CTL, 0, 0x28, 0x30, pga_tlv), 134 SOC_DOUBLE_R_TLV("DAC Volume", CS4265_DAC_CHA_VOL, 135 CS4265_DAC_CHB_VOL, 0, 0xFF, 1, dac_tlv), 136 SOC_SINGLE("De-emp 44.1kHz Switch", CS4265_DAC_CTL, 1, 137 1, 0), 138 SOC_SINGLE("DAC INV Switch", CS4265_DAC_CTL2, 5, 139 1, 0), 140 SOC_SINGLE("DAC Zero Cross Switch", CS4265_DAC_CTL2, 6, 141 1, 0), 142 SOC_SINGLE("DAC Soft Ramp Switch", CS4265_DAC_CTL2, 7, 143 1, 0), 144 SOC_SINGLE("ADC HPF Switch", CS4265_ADC_CTL, 1, 145 1, 0), 146 SOC_SINGLE("ADC Zero Cross Switch", CS4265_ADC_CTL2, 3, 147 1, 1), 148 SOC_SINGLE("ADC Soft Ramp Switch", CS4265_ADC_CTL2, 7, 149 1, 0), 150 SOC_SINGLE("E to F Buffer Disable Switch", CS4265_SPDIF_CTL1, 151 6, 1, 0), 152 SOC_ENUM("C Data Access", cam_mode_enum), 153 SOC_SINGLE("SPDIF Switch", CS4265_SPDIF_CTL2, 5, 1, 1), 154 SOC_SINGLE("Validity Bit Control Switch", CS4265_SPDIF_CTL2, 155 3, 1, 0), 156 SOC_ENUM("SPDIF Mono/Stereo", spdif_mono_stereo_enum), 157 SOC_SINGLE("MMTLR Data Switch", CS4265_SPDIF_CTL2, 0, 1, 0), 158 SOC_ENUM("Mono Channel Select", spdif_mono_select_enum), 159 SND_SOC_BYTES("C Data Buffer", CS4265_C_DATA_BUFF, 24), 160 }; 161 162 static const struct snd_soc_dapm_widget cs4265_dapm_widgets[] = { 163 164 SND_SOC_DAPM_INPUT("LINEINL"), 165 SND_SOC_DAPM_INPUT("LINEINR"), 166 SND_SOC_DAPM_INPUT("MICL"), 167 SND_SOC_DAPM_INPUT("MICR"), 168 169 SND_SOC_DAPM_AIF_OUT("DOUT", NULL, 0, 170 SND_SOC_NOPM, 0, 0), 171 SND_SOC_DAPM_AIF_OUT("SPDIFOUT", NULL, 0, 172 SND_SOC_NOPM, 0, 0), 173 174 SND_SOC_DAPM_MUX("ADC Mux", SND_SOC_NOPM, 0, 0, &mic_linein_mux), 175 176 SND_SOC_DAPM_ADC("ADC", NULL, CS4265_PWRCTL, 2, 1), 177 SND_SOC_DAPM_PGA("Pre-amp MIC", CS4265_PWRCTL, 3, 178 1, NULL, 0), 179 180 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 181 0, 0, &digital_input_mux), 182 183 SND_SOC_DAPM_MIXER("SDIN1 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 184 SND_SOC_DAPM_MIXER("SDIN2 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 185 SND_SOC_DAPM_MIXER("SPDIF Transmitter", SND_SOC_NOPM, 0, 0, NULL, 0), 186 187 SND_SOC_DAPM_SWITCH("Loopback", SND_SOC_NOPM, 0, 0, 188 &loopback_ctl), 189 SND_SOC_DAPM_SWITCH("SPDIF", SND_SOC_NOPM, 0, 0, 190 &spdif_switch), 191 SND_SOC_DAPM_SWITCH("DAC", CS4265_PWRCTL, 1, 1, 192 &dac_switch), 193 194 SND_SOC_DAPM_AIF_IN("DIN1", NULL, 0, 195 SND_SOC_NOPM, 0, 0), 196 SND_SOC_DAPM_AIF_IN("DIN2", NULL, 0, 197 SND_SOC_NOPM, 0, 0), 198 SND_SOC_DAPM_AIF_IN("TXIN", NULL, 0, 199 CS4265_SPDIF_CTL2, 5, 1), 200 201 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 202 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 203 204 }; 205 206 static const struct snd_soc_dapm_route cs4265_audio_map[] = { 207 208 {"DIN1", NULL, "DAI1 Playback"}, 209 {"DIN2", NULL, "DAI2 Playback"}, 210 {"SDIN1 Input Mixer", NULL, "DIN1"}, 211 {"SDIN2 Input Mixer", NULL, "DIN2"}, 212 {"Input Mux", "SDIN1", "SDIN1 Input Mixer"}, 213 {"Input Mux", "SDIN2", "SDIN2 Input Mixer"}, 214 {"DAC", "Switch", "Input Mux"}, 215 {"SPDIF", "Switch", "Input Mux"}, 216 {"LINEOUTL", NULL, "DAC"}, 217 {"LINEOUTR", NULL, "DAC"}, 218 {"SPDIFOUT", NULL, "SPDIF"}, 219 220 {"Pre-amp MIC", NULL, "MICL"}, 221 {"Pre-amp MIC", NULL, "MICR"}, 222 {"ADC Mux", "MIC", "Pre-amp MIC"}, 223 {"ADC Mux", "LINEIN", "LINEINL"}, 224 {"ADC Mux", "LINEIN", "LINEINR"}, 225 {"ADC", NULL, "ADC Mux"}, 226 {"DOUT", NULL, "ADC"}, 227 {"DAI1 Capture", NULL, "DOUT"}, 228 {"DAI2 Capture", NULL, "DOUT"}, 229 230 /* Loopback */ 231 {"Loopback", "Switch", "ADC"}, 232 {"DAC", NULL, "Loopback"}, 233 }; 234 235 struct cs4265_clk_para { 236 u32 mclk; 237 u32 rate; 238 u8 fm_mode; /* values 1, 2, or 4 */ 239 u8 mclkdiv; 240 }; 241 242 static const struct cs4265_clk_para clk_map_table[] = { 243 /*32k*/ 244 {8192000, 32000, 0, 0}, 245 {12288000, 32000, 0, 1}, 246 {16384000, 32000, 0, 2}, 247 {24576000, 32000, 0, 3}, 248 {32768000, 32000, 0, 4}, 249 250 /*44.1k*/ 251 {11289600, 44100, 0, 0}, 252 {16934400, 44100, 0, 1}, 253 {22579200, 44100, 0, 2}, 254 {33868000, 44100, 0, 3}, 255 {45158400, 44100, 0, 4}, 256 257 /*48k*/ 258 {12288000, 48000, 0, 0}, 259 {18432000, 48000, 0, 1}, 260 {24576000, 48000, 0, 2}, 261 {36864000, 48000, 0, 3}, 262 {49152000, 48000, 0, 4}, 263 264 /*64k*/ 265 {8192000, 64000, 1, 0}, 266 {12288000, 64000, 1, 1}, 267 {16934400, 64000, 1, 2}, 268 {24576000, 64000, 1, 3}, 269 {32768000, 64000, 1, 4}, 270 271 /* 88.2k */ 272 {11289600, 88200, 1, 0}, 273 {16934400, 88200, 1, 1}, 274 {22579200, 88200, 1, 2}, 275 {33868000, 88200, 1, 3}, 276 {45158400, 88200, 1, 4}, 277 278 /* 96k */ 279 {12288000, 96000, 1, 0}, 280 {18432000, 96000, 1, 1}, 281 {24576000, 96000, 1, 2}, 282 {36864000, 96000, 1, 3}, 283 {49152000, 96000, 1, 4}, 284 285 /* 128k */ 286 {8192000, 128000, 2, 0}, 287 {12288000, 128000, 2, 1}, 288 {16934400, 128000, 2, 2}, 289 {24576000, 128000, 2, 3}, 290 {32768000, 128000, 2, 4}, 291 292 /* 176.4k */ 293 {11289600, 176400, 2, 0}, 294 {16934400, 176400, 2, 1}, 295 {22579200, 176400, 2, 2}, 296 {33868000, 176400, 2, 3}, 297 {49152000, 176400, 2, 4}, 298 299 /* 192k */ 300 {12288000, 192000, 2, 0}, 301 {18432000, 192000, 2, 1}, 302 {24576000, 192000, 2, 2}, 303 {36864000, 192000, 2, 3}, 304 {49152000, 192000, 2, 4}, 305 }; 306 307 static int cs4265_get_clk_index(int mclk, int rate) 308 { 309 int i; 310 311 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) { 312 if (clk_map_table[i].rate == rate && 313 clk_map_table[i].mclk == mclk) 314 return i; 315 } 316 return -EINVAL; 317 } 318 319 static int cs4265_set_sysclk(struct snd_soc_dai *codec_dai, int clk_id, 320 unsigned int freq, int dir) 321 { 322 struct snd_soc_component *component = codec_dai->component; 323 struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component); 324 int i; 325 326 if (clk_id != 0) { 327 dev_err(component->dev, "Invalid clk_id %d\n", clk_id); 328 return -EINVAL; 329 } 330 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) { 331 if (clk_map_table[i].mclk == freq) { 332 cs4265->sysclk = freq; 333 return 0; 334 } 335 } 336 cs4265->sysclk = 0; 337 dev_err(component->dev, "Invalid freq parameter %d\n", freq); 338 return -EINVAL; 339 } 340 341 static int cs4265_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 342 { 343 struct snd_soc_component *component = codec_dai->component; 344 struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component); 345 u8 iface = 0; 346 347 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 348 case SND_SOC_DAIFMT_CBM_CFM: 349 snd_soc_component_update_bits(component, CS4265_ADC_CTL, 350 CS4265_ADC_MASTER, 351 CS4265_ADC_MASTER); 352 break; 353 case SND_SOC_DAIFMT_CBS_CFS: 354 snd_soc_component_update_bits(component, CS4265_ADC_CTL, 355 CS4265_ADC_MASTER, 356 0); 357 break; 358 default: 359 return -EINVAL; 360 } 361 362 /* interface format */ 363 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 364 case SND_SOC_DAIFMT_I2S: 365 iface |= SND_SOC_DAIFMT_I2S; 366 break; 367 case SND_SOC_DAIFMT_RIGHT_J: 368 iface |= SND_SOC_DAIFMT_RIGHT_J; 369 break; 370 case SND_SOC_DAIFMT_LEFT_J: 371 iface |= SND_SOC_DAIFMT_LEFT_J; 372 break; 373 default: 374 return -EINVAL; 375 } 376 377 cs4265->format = iface; 378 return 0; 379 } 380 381 static int cs4265_digital_mute(struct snd_soc_dai *dai, int mute) 382 { 383 struct snd_soc_component *component = dai->component; 384 385 if (mute) { 386 snd_soc_component_update_bits(component, CS4265_DAC_CTL, 387 CS4265_DAC_CTL_MUTE, 388 CS4265_DAC_CTL_MUTE); 389 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2, 390 CS4265_SPDIF_CTL2_MUTE, 391 CS4265_SPDIF_CTL2_MUTE); 392 } else { 393 snd_soc_component_update_bits(component, CS4265_DAC_CTL, 394 CS4265_DAC_CTL_MUTE, 395 0); 396 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2, 397 CS4265_SPDIF_CTL2_MUTE, 398 0); 399 } 400 return 0; 401 } 402 403 static int cs4265_pcm_hw_params(struct snd_pcm_substream *substream, 404 struct snd_pcm_hw_params *params, 405 struct snd_soc_dai *dai) 406 { 407 struct snd_soc_component *component = dai->component; 408 struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component); 409 int index; 410 411 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && 412 ((cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK) 413 == SND_SOC_DAIFMT_RIGHT_J)) 414 return -EINVAL; 415 416 index = cs4265_get_clk_index(cs4265->sysclk, params_rate(params)); 417 if (index >= 0) { 418 snd_soc_component_update_bits(component, CS4265_ADC_CTL, 419 CS4265_ADC_FM, clk_map_table[index].fm_mode << 6); 420 snd_soc_component_update_bits(component, CS4265_MCLK_FREQ, 421 CS4265_MCLK_FREQ_MASK, 422 clk_map_table[index].mclkdiv << 4); 423 424 } else { 425 dev_err(component->dev, "can't get correct mclk\n"); 426 return -EINVAL; 427 } 428 429 switch (cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK) { 430 case SND_SOC_DAIFMT_I2S: 431 snd_soc_component_update_bits(component, CS4265_DAC_CTL, 432 CS4265_DAC_CTL_DIF, (1 << 4)); 433 snd_soc_component_update_bits(component, CS4265_ADC_CTL, 434 CS4265_ADC_DIF, (1 << 4)); 435 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2, 436 CS4265_SPDIF_CTL2_DIF, (1 << 6)); 437 break; 438 case SND_SOC_DAIFMT_RIGHT_J: 439 if (params_width(params) == 16) { 440 snd_soc_component_update_bits(component, CS4265_DAC_CTL, 441 CS4265_DAC_CTL_DIF, (2 << 4)); 442 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2, 443 CS4265_SPDIF_CTL2_DIF, (2 << 6)); 444 } else { 445 snd_soc_component_update_bits(component, CS4265_DAC_CTL, 446 CS4265_DAC_CTL_DIF, (3 << 4)); 447 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2, 448 CS4265_SPDIF_CTL2_DIF, (3 << 6)); 449 } 450 break; 451 case SND_SOC_DAIFMT_LEFT_J: 452 snd_soc_component_update_bits(component, CS4265_DAC_CTL, 453 CS4265_DAC_CTL_DIF, 0); 454 snd_soc_component_update_bits(component, CS4265_ADC_CTL, 455 CS4265_ADC_DIF, 0); 456 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2, 457 CS4265_SPDIF_CTL2_DIF, 0); 458 459 break; 460 default: 461 return -EINVAL; 462 } 463 return 0; 464 } 465 466 static int cs4265_set_bias_level(struct snd_soc_component *component, 467 enum snd_soc_bias_level level) 468 { 469 switch (level) { 470 case SND_SOC_BIAS_ON: 471 break; 472 case SND_SOC_BIAS_PREPARE: 473 snd_soc_component_update_bits(component, CS4265_PWRCTL, 474 CS4265_PWRCTL_PDN, 0); 475 break; 476 case SND_SOC_BIAS_STANDBY: 477 snd_soc_component_update_bits(component, CS4265_PWRCTL, 478 CS4265_PWRCTL_PDN, 479 CS4265_PWRCTL_PDN); 480 break; 481 case SND_SOC_BIAS_OFF: 482 snd_soc_component_update_bits(component, CS4265_PWRCTL, 483 CS4265_PWRCTL_PDN, 484 CS4265_PWRCTL_PDN); 485 break; 486 } 487 return 0; 488 } 489 490 #define CS4265_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 491 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ 492 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \ 493 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000) 494 495 #define CS4265_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \ 496 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE | \ 497 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE) 498 499 static const struct snd_soc_dai_ops cs4265_ops = { 500 .hw_params = cs4265_pcm_hw_params, 501 .digital_mute = cs4265_digital_mute, 502 .set_fmt = cs4265_set_fmt, 503 .set_sysclk = cs4265_set_sysclk, 504 }; 505 506 static struct snd_soc_dai_driver cs4265_dai[] = { 507 { 508 .name = "cs4265-dai1", 509 .playback = { 510 .stream_name = "DAI1 Playback", 511 .channels_min = 1, 512 .channels_max = 2, 513 .rates = CS4265_RATES, 514 .formats = CS4265_FORMATS, 515 }, 516 .capture = { 517 .stream_name = "DAI1 Capture", 518 .channels_min = 1, 519 .channels_max = 2, 520 .rates = CS4265_RATES, 521 .formats = CS4265_FORMATS, 522 }, 523 .ops = &cs4265_ops, 524 }, 525 { 526 .name = "cs4265-dai2", 527 .playback = { 528 .stream_name = "DAI2 Playback", 529 .channels_min = 1, 530 .channels_max = 2, 531 .rates = CS4265_RATES, 532 .formats = CS4265_FORMATS, 533 }, 534 .capture = { 535 .stream_name = "DAI2 Capture", 536 .channels_min = 1, 537 .channels_max = 2, 538 .rates = CS4265_RATES, 539 .formats = CS4265_FORMATS, 540 }, 541 .ops = &cs4265_ops, 542 }, 543 }; 544 545 static const struct snd_soc_component_driver soc_component_cs4265 = { 546 .set_bias_level = cs4265_set_bias_level, 547 .controls = cs4265_snd_controls, 548 .num_controls = ARRAY_SIZE(cs4265_snd_controls), 549 .dapm_widgets = cs4265_dapm_widgets, 550 .num_dapm_widgets = ARRAY_SIZE(cs4265_dapm_widgets), 551 .dapm_routes = cs4265_audio_map, 552 .num_dapm_routes = ARRAY_SIZE(cs4265_audio_map), 553 .idle_bias_on = 1, 554 .use_pmdown_time = 1, 555 .endianness = 1, 556 .non_legacy_dai_naming = 1, 557 }; 558 559 static const struct regmap_config cs4265_regmap = { 560 .reg_bits = 8, 561 .val_bits = 8, 562 563 .max_register = CS4265_MAX_REGISTER, 564 .reg_defaults = cs4265_reg_defaults, 565 .num_reg_defaults = ARRAY_SIZE(cs4265_reg_defaults), 566 .readable_reg = cs4265_readable_register, 567 .volatile_reg = cs4265_volatile_register, 568 .cache_type = REGCACHE_RBTREE, 569 }; 570 571 static int cs4265_i2c_probe(struct i2c_client *i2c_client, 572 const struct i2c_device_id *id) 573 { 574 struct cs4265_private *cs4265; 575 int ret = 0; 576 unsigned int devid = 0; 577 unsigned int reg; 578 579 cs4265 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs4265_private), 580 GFP_KERNEL); 581 if (cs4265 == NULL) 582 return -ENOMEM; 583 584 cs4265->regmap = devm_regmap_init_i2c(i2c_client, &cs4265_regmap); 585 if (IS_ERR(cs4265->regmap)) { 586 ret = PTR_ERR(cs4265->regmap); 587 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 588 return ret; 589 } 590 591 cs4265->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 592 "reset", GPIOD_OUT_LOW); 593 if (IS_ERR(cs4265->reset_gpio)) 594 return PTR_ERR(cs4265->reset_gpio); 595 596 if (cs4265->reset_gpio) { 597 mdelay(1); 598 gpiod_set_value_cansleep(cs4265->reset_gpio, 1); 599 } 600 601 i2c_set_clientdata(i2c_client, cs4265); 602 603 ret = regmap_read(cs4265->regmap, CS4265_CHIP_ID, ®); 604 devid = reg & CS4265_CHIP_ID_MASK; 605 if (devid != CS4265_CHIP_ID_VAL) { 606 ret = -ENODEV; 607 dev_err(&i2c_client->dev, 608 "CS4265 Device ID (%X). Expected %X\n", 609 devid, CS4265_CHIP_ID); 610 return ret; 611 } 612 dev_info(&i2c_client->dev, 613 "CS4265 Version %x\n", 614 reg & CS4265_REV_ID_MASK); 615 616 regmap_write(cs4265->regmap, CS4265_PWRCTL, 0x0F); 617 618 ret = devm_snd_soc_register_component(&i2c_client->dev, 619 &soc_component_cs4265, cs4265_dai, 620 ARRAY_SIZE(cs4265_dai)); 621 return ret; 622 } 623 624 static const struct of_device_id cs4265_of_match[] = { 625 { .compatible = "cirrus,cs4265", }, 626 { } 627 }; 628 MODULE_DEVICE_TABLE(of, cs4265_of_match); 629 630 static const struct i2c_device_id cs4265_id[] = { 631 { "cs4265", 0 }, 632 { } 633 }; 634 MODULE_DEVICE_TABLE(i2c, cs4265_id); 635 636 static struct i2c_driver cs4265_i2c_driver = { 637 .driver = { 638 .name = "cs4265", 639 .of_match_table = cs4265_of_match, 640 }, 641 .id_table = cs4265_id, 642 .probe = cs4265_i2c_probe, 643 }; 644 645 module_i2c_driver(cs4265_i2c_driver); 646 647 MODULE_DESCRIPTION("ASoC CS4265 driver"); 648 MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>"); 649 MODULE_LICENSE("GPL"); 650