1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cirrus Logic CS35L56 smart amp 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/acpi.h> 9 #include <linux/completion.h> 10 #include <linux/debugfs.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/interrupt.h> 15 #include <linux/math.h> 16 #include <linux/module.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/slab.h> 22 #include <linux/soundwire/sdw.h> 23 #include <linux/types.h> 24 #include <linux/workqueue.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dapm.h> 29 #include <sound/tlv.h> 30 31 #include "wm_adsp.h" 32 #include "cs35l56.h" 33 34 static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w, 35 struct snd_kcontrol *kcontrol, int event); 36 37 static int cs35l56_mbox_send(struct cs35l56_private *cs35l56, unsigned int command) 38 { 39 unsigned int val; 40 int ret; 41 42 regmap_write(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 43 ret = regmap_read_poll_timeout(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 44 val, (val == 0), 45 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 46 if (ret) { 47 dev_warn(cs35l56->dev, "MBOX command %#x failed: %d\n", command, ret); 48 return ret; 49 } 50 51 return 0; 52 } 53 54 static void cs35l56_wait_dsp_ready(struct cs35l56_private *cs35l56) 55 { 56 /* Wait for patching to complete */ 57 flush_work(&cs35l56->dsp_work); 58 } 59 60 static int cs35l56_dspwait_get_volsw(struct snd_kcontrol *kcontrol, 61 struct snd_ctl_elem_value *ucontrol) 62 { 63 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 64 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 65 66 cs35l56_wait_dsp_ready(cs35l56); 67 return snd_soc_get_volsw(kcontrol, ucontrol); 68 } 69 70 static int cs35l56_dspwait_put_volsw(struct snd_kcontrol *kcontrol, 71 struct snd_ctl_elem_value *ucontrol) 72 { 73 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 74 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 75 76 cs35l56_wait_dsp_ready(cs35l56); 77 return snd_soc_put_volsw(kcontrol, ucontrol); 78 } 79 80 static DECLARE_TLV_DB_SCALE(vol_tlv, -10000, 25, 0); 81 82 static const struct snd_kcontrol_new cs35l56_controls[] = { 83 SOC_SINGLE_EXT("Speaker Switch", 84 CS35L56_MAIN_RENDER_USER_MUTE, 0, 1, 1, 85 cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw), 86 SOC_SINGLE_S_EXT_TLV("Speaker Volume", 87 CS35L56_MAIN_RENDER_USER_VOLUME, 88 6, -400, 400, 9, 0, 89 cs35l56_dspwait_get_volsw, 90 cs35l56_dspwait_put_volsw, 91 vol_tlv), 92 SOC_SINGLE_EXT("Posture Number", CS35L56_MAIN_POSTURE_NUMBER, 93 0, 255, 0, 94 cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw), 95 }; 96 97 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx1_enum, 98 CS35L56_ASP1TX1_INPUT, 99 0, CS35L56_ASP_TXn_SRC_MASK, 100 cs35l56_tx_input_texts, 101 cs35l56_tx_input_values); 102 103 static const struct snd_kcontrol_new asp1_tx1_mux = 104 SOC_DAPM_ENUM("ASP1TX1 SRC", cs35l56_asp1tx1_enum); 105 106 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx2_enum, 107 CS35L56_ASP1TX2_INPUT, 108 0, CS35L56_ASP_TXn_SRC_MASK, 109 cs35l56_tx_input_texts, 110 cs35l56_tx_input_values); 111 112 static const struct snd_kcontrol_new asp1_tx2_mux = 113 SOC_DAPM_ENUM("ASP1TX2 SRC", cs35l56_asp1tx2_enum); 114 115 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx3_enum, 116 CS35L56_ASP1TX3_INPUT, 117 0, CS35L56_ASP_TXn_SRC_MASK, 118 cs35l56_tx_input_texts, 119 cs35l56_tx_input_values); 120 121 static const struct snd_kcontrol_new asp1_tx3_mux = 122 SOC_DAPM_ENUM("ASP1TX3 SRC", cs35l56_asp1tx3_enum); 123 124 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx4_enum, 125 CS35L56_ASP1TX4_INPUT, 126 0, CS35L56_ASP_TXn_SRC_MASK, 127 cs35l56_tx_input_texts, 128 cs35l56_tx_input_values); 129 130 static const struct snd_kcontrol_new asp1_tx4_mux = 131 SOC_DAPM_ENUM("ASP1TX4 SRC", cs35l56_asp1tx4_enum); 132 133 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx1_enum, 134 CS35L56_SWIRE_DP3_CH1_INPUT, 135 0, CS35L56_SWIRETXn_SRC_MASK, 136 cs35l56_tx_input_texts, 137 cs35l56_tx_input_values); 138 139 static const struct snd_kcontrol_new sdw1_tx1_mux = 140 SOC_DAPM_ENUM("SDW1TX1 SRC", cs35l56_sdw1tx1_enum); 141 142 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx2_enum, 143 CS35L56_SWIRE_DP3_CH2_INPUT, 144 0, CS35L56_SWIRETXn_SRC_MASK, 145 cs35l56_tx_input_texts, 146 cs35l56_tx_input_values); 147 148 static const struct snd_kcontrol_new sdw1_tx2_mux = 149 SOC_DAPM_ENUM("SDW1TX2 SRC", cs35l56_sdw1tx2_enum); 150 151 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx3_enum, 152 CS35L56_SWIRE_DP3_CH3_INPUT, 153 0, CS35L56_SWIRETXn_SRC_MASK, 154 cs35l56_tx_input_texts, 155 cs35l56_tx_input_values); 156 157 static const struct snd_kcontrol_new sdw1_tx3_mux = 158 SOC_DAPM_ENUM("SDW1TX3 SRC", cs35l56_sdw1tx3_enum); 159 160 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx4_enum, 161 CS35L56_SWIRE_DP3_CH4_INPUT, 162 0, CS35L56_SWIRETXn_SRC_MASK, 163 cs35l56_tx_input_texts, 164 cs35l56_tx_input_values); 165 166 static const struct snd_kcontrol_new sdw1_tx4_mux = 167 SOC_DAPM_ENUM("SDW1TX4 SRC", cs35l56_sdw1tx4_enum); 168 169 static int cs35l56_play_event(struct snd_soc_dapm_widget *w, 170 struct snd_kcontrol *kcontrol, int event) 171 { 172 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 173 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 174 unsigned int val; 175 int ret; 176 177 dev_dbg(cs35l56->dev, "play: %d\n", event); 178 179 switch (event) { 180 case SND_SOC_DAPM_PRE_PMU: 181 /* Don't wait for ACK, we check in POST_PMU that it completed */ 182 return regmap_write(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 183 CS35L56_MBOX_CMD_AUDIO_PLAY); 184 case SND_SOC_DAPM_POST_PMU: 185 /* Wait for firmware to enter PS0 power state */ 186 ret = regmap_read_poll_timeout(cs35l56->regmap, 187 CS35L56_TRANSDUCER_ACTUAL_PS, 188 val, (val == CS35L56_PS0), 189 CS35L56_PS0_POLL_US, 190 CS35L56_PS0_TIMEOUT_US); 191 if (ret) 192 dev_err(cs35l56->dev, "PS0 wait failed: %d\n", ret); 193 return ret; 194 case SND_SOC_DAPM_POST_PMD: 195 return cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_AUDIO_PAUSE); 196 default: 197 return 0; 198 } 199 } 200 201 static const struct snd_soc_dapm_widget cs35l56_dapm_widgets[] = { 202 SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_B", 0, 0), 203 SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_AMP", 0, 0), 204 205 SND_SOC_DAPM_SUPPLY("PLAY", SND_SOC_NOPM, 0, 0, cs35l56_play_event, 206 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 207 208 SND_SOC_DAPM_OUT_DRV("AMP", SND_SOC_NOPM, 0, 0, NULL, 0), 209 SND_SOC_DAPM_OUTPUT("SPK"), 210 211 SND_SOC_DAPM_PGA_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, cs35l56_dsp_event, 212 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 213 214 SND_SOC_DAPM_AIF_IN("ASP1RX1", NULL, 0, CS35L56_ASP1_ENABLES1, 215 CS35L56_ASP_RX1_EN_SHIFT, 0), 216 SND_SOC_DAPM_AIF_IN("ASP1RX2", NULL, 1, CS35L56_ASP1_ENABLES1, 217 CS35L56_ASP_RX2_EN_SHIFT, 0), 218 SND_SOC_DAPM_AIF_OUT("ASP1TX1", NULL, 0, CS35L56_ASP1_ENABLES1, 219 CS35L56_ASP_TX1_EN_SHIFT, 0), 220 SND_SOC_DAPM_AIF_OUT("ASP1TX2", NULL, 1, CS35L56_ASP1_ENABLES1, 221 CS35L56_ASP_TX2_EN_SHIFT, 0), 222 SND_SOC_DAPM_AIF_OUT("ASP1TX3", NULL, 2, CS35L56_ASP1_ENABLES1, 223 CS35L56_ASP_TX3_EN_SHIFT, 0), 224 SND_SOC_DAPM_AIF_OUT("ASP1TX4", NULL, 3, CS35L56_ASP1_ENABLES1, 225 CS35L56_ASP_TX4_EN_SHIFT, 0), 226 227 SND_SOC_DAPM_MUX("ASP1 TX1 Source", SND_SOC_NOPM, 0, 0, &asp1_tx1_mux), 228 SND_SOC_DAPM_MUX("ASP1 TX2 Source", SND_SOC_NOPM, 0, 0, &asp1_tx2_mux), 229 SND_SOC_DAPM_MUX("ASP1 TX3 Source", SND_SOC_NOPM, 0, 0, &asp1_tx3_mux), 230 SND_SOC_DAPM_MUX("ASP1 TX4 Source", SND_SOC_NOPM, 0, 0, &asp1_tx4_mux), 231 232 SND_SOC_DAPM_MUX("SDW1 TX1 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx1_mux), 233 SND_SOC_DAPM_MUX("SDW1 TX2 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx2_mux), 234 SND_SOC_DAPM_MUX("SDW1 TX3 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx3_mux), 235 SND_SOC_DAPM_MUX("SDW1 TX4 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx4_mux), 236 237 SND_SOC_DAPM_SIGGEN("VMON ADC"), 238 SND_SOC_DAPM_SIGGEN("IMON ADC"), 239 SND_SOC_DAPM_SIGGEN("ERRVOL ADC"), 240 SND_SOC_DAPM_SIGGEN("CLASSH ADC"), 241 SND_SOC_DAPM_SIGGEN("VDDBMON ADC"), 242 SND_SOC_DAPM_SIGGEN("VBSTMON ADC"), 243 SND_SOC_DAPM_SIGGEN("TEMPMON ADC"), 244 }; 245 246 #define CS35L56_SRC_ROUTE(name) \ 247 { name" Source", "ASP1RX1", "ASP1RX1" }, \ 248 { name" Source", "ASP1RX2", "ASP1RX2" }, \ 249 { name" Source", "VMON", "VMON ADC" }, \ 250 { name" Source", "IMON", "IMON ADC" }, \ 251 { name" Source", "ERRVOL", "ERRVOL ADC" }, \ 252 { name" Source", "CLASSH", "CLASSH ADC" }, \ 253 { name" Source", "VDDBMON", "VDDBMON ADC" }, \ 254 { name" Source", "VBSTMON", "VBSTMON ADC" }, \ 255 { name" Source", "DSP1TX1", "DSP1" }, \ 256 { name" Source", "DSP1TX2", "DSP1" }, \ 257 { name" Source", "DSP1TX3", "DSP1" }, \ 258 { name" Source", "DSP1TX4", "DSP1" }, \ 259 { name" Source", "DSP1TX5", "DSP1" }, \ 260 { name" Source", "DSP1TX6", "DSP1" }, \ 261 { name" Source", "DSP1TX7", "DSP1" }, \ 262 { name" Source", "DSP1TX8", "DSP1" }, \ 263 { name" Source", "TEMPMON", "TEMPMON ADC" }, \ 264 { name" Source", "INTERPOLATOR", "AMP" }, \ 265 { name" Source", "SDW1RX1", "SDW1 Playback" }, \ 266 { name" Source", "SDW1RX2", "SDW1 Playback" }, 267 268 static const struct snd_soc_dapm_route cs35l56_audio_map[] = { 269 { "AMP", NULL, "VDD_B" }, 270 { "AMP", NULL, "VDD_AMP" }, 271 272 { "ASP1 Playback", NULL, "PLAY" }, 273 { "SDW1 Playback", NULL, "PLAY" }, 274 275 { "ASP1RX1", NULL, "ASP1 Playback" }, 276 { "ASP1RX2", NULL, "ASP1 Playback" }, 277 { "DSP1", NULL, "ASP1RX1" }, 278 { "DSP1", NULL, "ASP1RX2" }, 279 { "DSP1", NULL, "SDW1 Playback" }, 280 { "AMP", NULL, "DSP1" }, 281 { "SPK", NULL, "AMP" }, 282 283 CS35L56_SRC_ROUTE("ASP1 TX1") 284 CS35L56_SRC_ROUTE("ASP1 TX2") 285 CS35L56_SRC_ROUTE("ASP1 TX3") 286 CS35L56_SRC_ROUTE("ASP1 TX4") 287 288 { "ASP1TX1", NULL, "ASP1 TX1 Source" }, 289 { "ASP1TX2", NULL, "ASP1 TX2 Source" }, 290 { "ASP1TX3", NULL, "ASP1 TX3 Source" }, 291 { "ASP1TX4", NULL, "ASP1 TX4 Source" }, 292 { "ASP1 Capture", NULL, "ASP1TX1" }, 293 { "ASP1 Capture", NULL, "ASP1TX2" }, 294 { "ASP1 Capture", NULL, "ASP1TX3" }, 295 { "ASP1 Capture", NULL, "ASP1TX4" }, 296 297 CS35L56_SRC_ROUTE("SDW1 TX1") 298 CS35L56_SRC_ROUTE("SDW1 TX2") 299 CS35L56_SRC_ROUTE("SDW1 TX3") 300 CS35L56_SRC_ROUTE("SDW1 TX4") 301 { "SDW1 Capture", NULL, "SDW1 TX1 Source" }, 302 { "SDW1 Capture", NULL, "SDW1 TX2 Source" }, 303 { "SDW1 Capture", NULL, "SDW1 TX3 Source" }, 304 { "SDW1 Capture", NULL, "SDW1 TX4 Source" }, 305 }; 306 307 static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w, 308 struct snd_kcontrol *kcontrol, int event) 309 { 310 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 311 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 312 313 dev_dbg(cs35l56->dev, "%s: %d\n", __func__, event); 314 315 return wm_adsp_event(w, kcontrol, event); 316 } 317 318 irqreturn_t cs35l56_irq(int irq, void *data) 319 { 320 struct cs35l56_private *cs35l56 = data; 321 unsigned int status1 = 0, status8 = 0, status20 = 0; 322 unsigned int mask1, mask8, mask20; 323 unsigned int val; 324 int rv; 325 326 irqreturn_t ret = IRQ_NONE; 327 328 if (!cs35l56->init_done) 329 return IRQ_NONE; 330 331 mutex_lock(&cs35l56->irq_lock); 332 333 rv = pm_runtime_resume_and_get(cs35l56->dev); 334 if (rv < 0) { 335 dev_err(cs35l56->dev, "irq: failed to get pm_runtime: %d\n", rv); 336 goto err_unlock; 337 } 338 339 regmap_read(cs35l56->regmap, CS35L56_IRQ1_STATUS, &val); 340 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 341 dev_dbg(cs35l56->dev, "Spurious IRQ: no pending interrupt\n"); 342 goto err; 343 } 344 345 /* Ack interrupts */ 346 regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_1, &status1); 347 regmap_read(cs35l56->regmap, CS35L56_IRQ1_MASK_1, &mask1); 348 status1 &= ~mask1; 349 regmap_write(cs35l56->regmap, CS35L56_IRQ1_EINT_1, status1); 350 351 regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_8, &status8); 352 regmap_read(cs35l56->regmap, CS35L56_IRQ1_MASK_8, &mask8); 353 status8 &= ~mask8; 354 regmap_write(cs35l56->regmap, CS35L56_IRQ1_EINT_8, status8); 355 356 regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_20, &status20); 357 regmap_read(cs35l56->regmap, CS35L56_IRQ1_MASK_20, &mask20); 358 status20 &= ~mask20; 359 /* We don't want EINT20 but they default to unmasked: force mask */ 360 regmap_write(cs35l56->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 361 362 dev_dbg(cs35l56->dev, "%s: %#x %#x\n", __func__, status1, status8); 363 364 /* Check to see if unmasked bits are active */ 365 if (!status1 && !status8 && !status20) 366 goto err; 367 368 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 369 dev_crit(cs35l56->dev, "Amp short error\n"); 370 371 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 372 dev_crit(cs35l56->dev, "Overtemp error\n"); 373 374 ret = IRQ_HANDLED; 375 376 err: 377 pm_runtime_put(cs35l56->dev); 378 err_unlock: 379 mutex_unlock(&cs35l56->irq_lock); 380 381 return ret; 382 } 383 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_CORE); 384 385 int cs35l56_irq_request(struct cs35l56_private *cs35l56, int irq) 386 { 387 int ret; 388 389 if (!irq) 390 return 0; 391 392 ret = devm_request_threaded_irq(cs35l56->dev, irq, NULL, cs35l56_irq, 393 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 394 "cs35l56", cs35l56); 395 if (!ret) 396 cs35l56->irq = irq; 397 else 398 dev_err(cs35l56->dev, "Failed to get IRQ: %d\n", ret); 399 400 return ret; 401 } 402 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_CORE); 403 404 static int cs35l56_asp_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 405 { 406 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(codec_dai->component); 407 unsigned int val; 408 409 dev_dbg(cs35l56->dev, "%s: %#x\n", __func__, fmt); 410 411 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 412 case SND_SOC_DAIFMT_CBC_CFC: 413 break; 414 default: 415 dev_err(cs35l56->dev, "Unsupported clock source mode\n"); 416 return -EINVAL; 417 } 418 419 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 420 case SND_SOC_DAIFMT_DSP_A: 421 val = CS35L56_ASP_FMT_DSP_A << CS35L56_ASP_FMT_SHIFT; 422 cs35l56->tdm_mode = true; 423 break; 424 case SND_SOC_DAIFMT_I2S: 425 val = CS35L56_ASP_FMT_I2S << CS35L56_ASP_FMT_SHIFT; 426 cs35l56->tdm_mode = false; 427 break; 428 default: 429 dev_err(cs35l56->dev, "Unsupported DAI format\n"); 430 return -EINVAL; 431 } 432 433 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 434 case SND_SOC_DAIFMT_NB_IF: 435 val |= CS35L56_ASP_FSYNC_INV_MASK; 436 break; 437 case SND_SOC_DAIFMT_IB_NF: 438 val |= CS35L56_ASP_BCLK_INV_MASK; 439 break; 440 case SND_SOC_DAIFMT_IB_IF: 441 val |= CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK; 442 break; 443 case SND_SOC_DAIFMT_NB_NF: 444 break; 445 default: 446 dev_err(cs35l56->dev, "Invalid clock invert\n"); 447 return -EINVAL; 448 } 449 450 regmap_update_bits(cs35l56->regmap, 451 CS35L56_ASP1_CONTROL2, 452 CS35L56_ASP_FMT_MASK | 453 CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK, 454 val); 455 456 /* Hi-Z DOUT in unused slots and when all TX are disabled */ 457 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL3, 458 CS35L56_ASP1_DOUT_HIZ_CTRL_MASK, 459 CS35L56_ASP_UNUSED_HIZ_OFF_HIZ); 460 461 return 0; 462 } 463 464 static void cs35l56_set_asp_slot_positions(struct cs35l56_private *cs35l56, 465 unsigned int reg, unsigned long mask) 466 { 467 unsigned int reg_val, channel_shift; 468 int bit_num; 469 470 /* Init all slots to 63 */ 471 switch (reg) { 472 case CS35L56_ASP1_FRAME_CONTROL1: 473 reg_val = 0x3f3f3f3f; 474 break; 475 case CS35L56_ASP1_FRAME_CONTROL5: 476 reg_val = 0x3f3f3f; 477 break; 478 } 479 480 /* Enable consecutive TX1..TXn for each of the slots set in mask */ 481 channel_shift = 0; 482 for_each_set_bit(bit_num, &mask, 32) { 483 reg_val &= ~(0x3f << channel_shift); 484 reg_val |= bit_num << channel_shift; 485 channel_shift += 8; 486 } 487 488 regmap_write(cs35l56->regmap, reg, reg_val); 489 } 490 491 static int cs35l56_asp_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 492 unsigned int rx_mask, int slots, int slot_width) 493 { 494 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 495 496 if ((slots == 0) || (slot_width == 0)) { 497 dev_dbg(cs35l56->dev, "tdm config cleared\n"); 498 cs35l56->asp_slot_width = 0; 499 cs35l56->asp_slot_count = 0; 500 return 0; 501 } 502 503 if (slot_width > (CS35L56_ASP_RX_WIDTH_MASK >> CS35L56_ASP_RX_WIDTH_SHIFT)) { 504 dev_err(cs35l56->dev, "tdm invalid slot width %d\n", slot_width); 505 return -EINVAL; 506 } 507 508 /* More than 32 slots would give an unsupportable BCLK frequency */ 509 if (slots > 32) { 510 dev_err(cs35l56->dev, "tdm invalid slot count %d\n", slots); 511 return -EINVAL; 512 } 513 514 cs35l56->asp_slot_width = (u8)slot_width; 515 cs35l56->asp_slot_count = (u8)slots; 516 517 // Note: rx/tx is from point of view of the CPU end 518 if (tx_mask == 0) 519 tx_mask = 0x3; // ASPRX1/RX2 in slots 0 and 1 520 521 if (rx_mask == 0) 522 rx_mask = 0xf; // ASPTX1..TX4 in slots 0..3 523 524 cs35l56_set_asp_slot_positions(cs35l56, CS35L56_ASP1_FRAME_CONTROL1, rx_mask); 525 cs35l56_set_asp_slot_positions(cs35l56, CS35L56_ASP1_FRAME_CONTROL5, tx_mask); 526 527 dev_dbg(cs35l56->dev, "tdm slot width: %u count: %u tx_mask: %#x rx_mask: %#x\n", 528 cs35l56->asp_slot_width, cs35l56->asp_slot_count, tx_mask, rx_mask); 529 530 return 0; 531 } 532 533 static int cs35l56_asp_dai_hw_params(struct snd_pcm_substream *substream, 534 struct snd_pcm_hw_params *params, 535 struct snd_soc_dai *dai) 536 { 537 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 538 unsigned int rate = params_rate(params); 539 u8 asp_width, asp_wl; 540 541 asp_wl = params_width(params); 542 if (cs35l56->asp_slot_width) 543 asp_width = cs35l56->asp_slot_width; 544 else 545 asp_width = asp_wl; 546 547 dev_dbg(cs35l56->dev, "%s: wl=%d, width=%d, rate=%d", __func__, asp_wl, asp_width, rate); 548 549 if (!cs35l56->sysclk_set) { 550 unsigned int slots = cs35l56->asp_slot_count; 551 unsigned int bclk_freq; 552 int freq_id; 553 554 if (slots == 0) { 555 slots = params_channels(params); 556 557 /* I2S always has an even number of slots */ 558 if (!cs35l56->tdm_mode) 559 slots = round_up(slots, 2); 560 } 561 562 bclk_freq = asp_width * slots * rate; 563 freq_id = cs35l56_get_bclk_freq_id(bclk_freq); 564 if (freq_id < 0) { 565 dev_err(cs35l56->dev, "%s: Invalid BCLK %u\n", __func__, bclk_freq); 566 return -EINVAL; 567 } 568 569 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL1, 570 CS35L56_ASP_BCLK_FREQ_MASK, 571 freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT); 572 } 573 574 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 575 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL2, 576 CS35L56_ASP_RX_WIDTH_MASK, asp_width << 577 CS35L56_ASP_RX_WIDTH_SHIFT); 578 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_DATA_CONTROL5, 579 CS35L56_ASP_RX_WL_MASK, asp_wl); 580 } else { 581 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL2, 582 CS35L56_ASP_TX_WIDTH_MASK, asp_width << 583 CS35L56_ASP_TX_WIDTH_SHIFT); 584 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_DATA_CONTROL1, 585 CS35L56_ASP_TX_WL_MASK, asp_wl); 586 } 587 588 return 0; 589 } 590 591 static int cs35l56_asp_dai_set_sysclk(struct snd_soc_dai *dai, 592 int clk_id, unsigned int freq, int dir) 593 { 594 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 595 int freq_id; 596 597 if (freq == 0) { 598 cs35l56->sysclk_set = false; 599 return 0; 600 } 601 602 freq_id = cs35l56_get_bclk_freq_id(freq); 603 if (freq_id < 0) 604 return freq_id; 605 606 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL1, 607 CS35L56_ASP_BCLK_FREQ_MASK, 608 freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT); 609 cs35l56->sysclk_set = true; 610 611 return 0; 612 } 613 614 static const struct snd_soc_dai_ops cs35l56_ops = { 615 .set_fmt = cs35l56_asp_dai_set_fmt, 616 .set_tdm_slot = cs35l56_asp_dai_set_tdm_slot, 617 .hw_params = cs35l56_asp_dai_hw_params, 618 .set_sysclk = cs35l56_asp_dai_set_sysclk, 619 }; 620 621 static void cs35l56_sdw_dai_shutdown(struct snd_pcm_substream *substream, 622 struct snd_soc_dai *dai) 623 { 624 snd_soc_dai_set_dma_data(dai, substream, NULL); 625 } 626 627 static int cs35l56_sdw_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 628 unsigned int rx_mask, int slots, int slot_width) 629 { 630 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 631 632 /* rx/tx are from point of view of the CPU end so opposite to our rx/tx */ 633 cs35l56->rx_mask = tx_mask; 634 cs35l56->tx_mask = rx_mask; 635 636 return 0; 637 } 638 639 static int cs35l56_sdw_dai_hw_params(struct snd_pcm_substream *substream, 640 struct snd_pcm_hw_params *params, 641 struct snd_soc_dai *dai) 642 { 643 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 644 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 645 struct sdw_stream_config sconfig; 646 struct sdw_port_config pconfig; 647 int ret; 648 649 dev_dbg(cs35l56->dev, "%s: rate %d\n", __func__, params_rate(params)); 650 651 if (!cs35l56->init_done) 652 return -ENODEV; 653 654 if (!sdw_stream) 655 return -EINVAL; 656 657 memset(&sconfig, 0, sizeof(sconfig)); 658 memset(&pconfig, 0, sizeof(pconfig)); 659 660 sconfig.frame_rate = params_rate(params); 661 sconfig.bps = snd_pcm_format_width(params_format(params)); 662 663 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 664 sconfig.direction = SDW_DATA_DIR_RX; 665 pconfig.num = CS35L56_SDW1_PLAYBACK_PORT; 666 pconfig.ch_mask = cs35l56->rx_mask; 667 } else { 668 sconfig.direction = SDW_DATA_DIR_TX; 669 pconfig.num = CS35L56_SDW1_CAPTURE_PORT; 670 pconfig.ch_mask = cs35l56->tx_mask; 671 } 672 673 if (pconfig.ch_mask == 0) { 674 sconfig.ch_count = params_channels(params); 675 pconfig.ch_mask = GENMASK(sconfig.ch_count - 1, 0); 676 } else { 677 sconfig.ch_count = hweight32(pconfig.ch_mask); 678 } 679 680 ret = sdw_stream_add_slave(cs35l56->sdw_peripheral, &sconfig, &pconfig, 681 1, sdw_stream); 682 if (ret) { 683 dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret); 684 return ret; 685 } 686 687 return 0; 688 } 689 690 static int cs35l56_sdw_dai_hw_free(struct snd_pcm_substream *substream, 691 struct snd_soc_dai *dai) 692 { 693 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 694 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 695 696 if (!cs35l56->sdw_peripheral) 697 return -EINVAL; 698 699 sdw_stream_remove_slave(cs35l56->sdw_peripheral, sdw_stream); 700 701 return 0; 702 } 703 704 static int cs35l56_sdw_dai_set_stream(struct snd_soc_dai *dai, 705 void *sdw_stream, int direction) 706 { 707 if (!sdw_stream) 708 return 0; 709 710 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 711 712 return 0; 713 } 714 715 static const struct snd_soc_dai_ops cs35l56_sdw_dai_ops = { 716 .set_tdm_slot = cs35l56_sdw_dai_set_tdm_slot, 717 .shutdown = cs35l56_sdw_dai_shutdown, 718 .hw_params = cs35l56_sdw_dai_hw_params, 719 .hw_free = cs35l56_sdw_dai_hw_free, 720 .set_stream = cs35l56_sdw_dai_set_stream, 721 }; 722 723 static struct snd_soc_dai_driver cs35l56_dai[] = { 724 { 725 .name = "cs35l56-asp1", 726 .id = 0, 727 .playback = { 728 .stream_name = "ASP1 Playback", 729 .channels_min = 1, 730 .channels_max = 2, 731 .rates = CS35L56_RATES, 732 .formats = CS35L56_RX_FORMATS, 733 }, 734 .capture = { 735 .stream_name = "ASP1 Capture", 736 .channels_min = 1, 737 .channels_max = 4, 738 .rates = CS35L56_RATES, 739 .formats = CS35L56_TX_FORMATS, 740 }, 741 .ops = &cs35l56_ops, 742 .symmetric_rate = 1, 743 .symmetric_sample_bits = 1, 744 }, 745 { 746 .name = "cs35l56-sdw1", 747 .id = 1, 748 .playback = { 749 .stream_name = "SDW1 Playback", 750 .channels_min = 1, 751 .channels_max = 2, 752 .rates = CS35L56_RATES, 753 .formats = CS35L56_RX_FORMATS, 754 }, 755 .capture = { 756 .stream_name = "SDW1 Capture", 757 .channels_min = 1, 758 .channels_max = 4, 759 .rates = CS35L56_RATES, 760 .formats = CS35L56_TX_FORMATS, 761 }, 762 .symmetric_rate = 1, 763 .ops = &cs35l56_sdw_dai_ops, 764 } 765 }; 766 767 static int cs35l56_wait_for_firmware_boot(struct cs35l56_private *cs35l56) 768 { 769 unsigned int reg; 770 unsigned int val; 771 int ret; 772 773 if (cs35l56->rev < CS35L56_REVID_B0) 774 reg = CS35L56_DSP1_HALO_STATE_A1; 775 else 776 reg = CS35L56_DSP1_HALO_STATE; 777 778 ret = regmap_read_poll_timeout(cs35l56->regmap, reg, 779 val, 780 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 781 CS35L56_HALO_STATE_POLL_US, 782 CS35L56_HALO_STATE_TIMEOUT_US); 783 784 if ((ret < 0) && (ret != -ETIMEDOUT)) { 785 dev_err(cs35l56->dev, "Failed to read HALO_STATE: %d\n", ret); 786 return ret; 787 } 788 789 if ((ret == -ETIMEDOUT) || (val != CS35L56_HALO_STATE_BOOT_DONE)) { 790 dev_err(cs35l56->dev, "Firmware boot fail: HALO_STATE=%#x\n", val); 791 return -EIO; 792 } 793 794 return 0; 795 } 796 797 static inline void cs35l56_wait_min_reset_pulse(void) 798 { 799 /* Satisfy minimum reset pulse width spec */ 800 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 801 } 802 803 static const struct reg_sequence cs35l56_system_reset_seq[] = { 804 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 805 }; 806 807 static void cs35l56_system_reset(struct cs35l56_private *cs35l56) 808 { 809 cs35l56->soft_resetting = true; 810 811 /* 812 * Must enter cache-only first so there can't be any more register 813 * accesses other than the controlled system reset sequence below. 814 */ 815 regcache_cache_only(cs35l56->regmap, true); 816 regmap_multi_reg_write_bypassed(cs35l56->regmap, 817 cs35l56_system_reset_seq, 818 ARRAY_SIZE(cs35l56_system_reset_seq)); 819 820 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 821 if (cs35l56->sdw_peripheral) 822 return; 823 824 usleep_range(CS35L56_CONTROL_PORT_READY_US, CS35L56_CONTROL_PORT_READY_US + 400); 825 regcache_cache_only(cs35l56->regmap, false); 826 } 827 828 static void cs35l56_dsp_work(struct work_struct *work) 829 { 830 struct cs35l56_private *cs35l56 = container_of(work, 831 struct cs35l56_private, 832 dsp_work); 833 unsigned int reg; 834 unsigned int val; 835 int ret = 0; 836 837 if (!cs35l56->init_done) 838 return; 839 840 cs35l56->dsp.part = devm_kasprintf(cs35l56->dev, GFP_KERNEL, "cs35l56%s-%02x", 841 cs35l56->secured ? "s" : "", cs35l56->rev); 842 843 if (!cs35l56->dsp.part) 844 return; 845 846 pm_runtime_get_sync(cs35l56->dev); 847 848 /* 849 * Disable SoundWire interrupts to prevent race with IRQ work. 850 * Setting sdw_irq_no_unmask prevents the handler re-enabling 851 * the SoundWire interrupt. 852 */ 853 if (cs35l56->sdw_peripheral) { 854 cs35l56->sdw_irq_no_unmask = true; 855 cancel_work_sync(&cs35l56->sdw_irq_work); 856 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0); 857 sdw_read_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1); 858 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF); 859 } 860 861 ret = cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_SHUTDOWN); 862 if (ret) 863 goto err; 864 865 if (cs35l56->rev < CS35L56_REVID_B0) 866 reg = CS35L56_DSP1_PM_CUR_STATE_A1; 867 else 868 reg = CS35L56_DSP1_PM_CUR_STATE; 869 870 ret = regmap_read_poll_timeout(cs35l56->regmap, reg, 871 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 872 CS35L56_HALO_STATE_POLL_US, 873 CS35L56_HALO_STATE_TIMEOUT_US); 874 if (ret < 0) 875 dev_err(cs35l56->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 876 val, ret); 877 878 /* Use wm_adsp to load and apply the firmware patch and coefficient files */ 879 ret = wm_adsp_power_up(&cs35l56->dsp); 880 if (ret) { 881 dev_dbg(cs35l56->dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret); 882 goto err; 883 } 884 885 mutex_lock(&cs35l56->irq_lock); 886 887 init_completion(&cs35l56->init_completion); 888 889 cs35l56_system_reset(cs35l56); 890 891 if (cs35l56->sdw_peripheral) { 892 /* 893 * The system-reset causes the CS35L56 to detach from the bus. 894 * Wait for the manager to re-enumerate the CS35L56 and 895 * cs35l56_init() to run again. 896 */ 897 if (!wait_for_completion_timeout(&cs35l56->init_completion, 898 msecs_to_jiffies(5000))) { 899 dev_err(cs35l56->dev, "%s: init_completion timed out (SDW)\n", __func__); 900 goto err_unlock; 901 } 902 } else if (cs35l56_init(cs35l56)) { 903 goto err_unlock; 904 } 905 906 regmap_clear_bits(cs35l56->regmap, CS35L56_PROTECTION_STATUS, CS35L56_FIRMWARE_MISSING); 907 cs35l56->fw_patched = true; 908 909 err_unlock: 910 mutex_unlock(&cs35l56->irq_lock); 911 err: 912 pm_runtime_mark_last_busy(cs35l56->dev); 913 pm_runtime_put_autosuspend(cs35l56->dev); 914 915 /* Re-enable SoundWire interrupts */ 916 if (cs35l56->sdw_peripheral) { 917 cs35l56->sdw_irq_no_unmask = false; 918 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 919 CS35L56_SDW_INT_MASK_CODEC_IRQ); 920 } 921 } 922 923 static int cs35l56_component_probe(struct snd_soc_component *component) 924 { 925 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 926 struct dentry *debugfs_root = component->debugfs_root; 927 928 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_tx_input_texts) != ARRAY_SIZE(cs35l56_tx_input_values)); 929 930 if (!wait_for_completion_timeout(&cs35l56->init_completion, 931 msecs_to_jiffies(5000))) { 932 dev_err(cs35l56->dev, "%s: init_completion timed out\n", __func__); 933 return -ENODEV; 934 } 935 936 cs35l56->component = component; 937 wm_adsp2_component_probe(&cs35l56->dsp, component); 938 939 debugfs_create_bool("init_done", 0444, debugfs_root, &cs35l56->init_done); 940 debugfs_create_bool("can_hibernate", 0444, debugfs_root, &cs35l56->can_hibernate); 941 debugfs_create_bool("fw_patched", 0444, debugfs_root, &cs35l56->fw_patched); 942 943 queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work); 944 945 return 0; 946 } 947 948 static void cs35l56_component_remove(struct snd_soc_component *component) 949 { 950 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 951 952 cancel_work_sync(&cs35l56->dsp_work); 953 } 954 955 static int cs35l56_set_bias_level(struct snd_soc_component *component, 956 enum snd_soc_bias_level level) 957 { 958 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 959 960 switch (level) { 961 case SND_SOC_BIAS_STANDBY: 962 /* 963 * Wait for patching to complete when transitioning from 964 * BIAS_OFF to BIAS_STANDBY 965 */ 966 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 967 cs35l56_wait_dsp_ready(cs35l56); 968 969 break; 970 default: 971 break; 972 } 973 974 return 0; 975 } 976 977 static const struct snd_soc_component_driver soc_component_dev_cs35l56 = { 978 .probe = cs35l56_component_probe, 979 .remove = cs35l56_component_remove, 980 981 .dapm_widgets = cs35l56_dapm_widgets, 982 .num_dapm_widgets = ARRAY_SIZE(cs35l56_dapm_widgets), 983 .dapm_routes = cs35l56_audio_map, 984 .num_dapm_routes = ARRAY_SIZE(cs35l56_audio_map), 985 .controls = cs35l56_controls, 986 .num_controls = ARRAY_SIZE(cs35l56_controls), 987 988 .set_bias_level = cs35l56_set_bias_level, 989 990 .suspend_bias_off = 1, /* see cs35l56_system_resume() */ 991 }; 992 993 static const struct reg_sequence cs35l56_hibernate_seq[] = { 994 /* This must be the last register access */ 995 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_HIBERNATE_NOW), 996 }; 997 998 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = { 999 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP), 1000 }; 1001 1002 int cs35l56_runtime_suspend(struct device *dev) 1003 { 1004 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1005 unsigned int val; 1006 int ret; 1007 1008 if (!cs35l56->init_done) 1009 return 0; 1010 1011 /* Firmware must have entered a power-save state */ 1012 ret = regmap_read_poll_timeout(cs35l56->regmap, 1013 CS35L56_TRANSDUCER_ACTUAL_PS, 1014 val, (val >= CS35L56_PS3), 1015 CS35L56_PS3_POLL_US, 1016 CS35L56_PS3_TIMEOUT_US); 1017 if (ret) 1018 dev_warn(cs35l56->dev, "PS3 wait failed: %d\n", ret); 1019 1020 /* Clear BOOT_DONE so it can be used to detect a reboot */ 1021 regmap_write(cs35l56->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 1022 1023 if (!cs35l56->can_hibernate) { 1024 regcache_cache_only(cs35l56->regmap, true); 1025 dev_dbg(dev, "Suspended: no hibernate"); 1026 1027 return 0; 1028 } 1029 1030 /* 1031 * Enable auto-hibernate. If it is woken by some other wake source 1032 * it will automatically return to hibernate. 1033 */ 1034 cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE); 1035 1036 /* 1037 * Must enter cache-only first so there can't be any more register 1038 * accesses other than the controlled hibernate sequence below. 1039 */ 1040 regcache_cache_only(cs35l56->regmap, true); 1041 1042 regmap_multi_reg_write_bypassed(cs35l56->regmap, 1043 cs35l56_hibernate_seq, 1044 ARRAY_SIZE(cs35l56_hibernate_seq)); 1045 1046 dev_dbg(dev, "Suspended: hibernate"); 1047 1048 return 0; 1049 } 1050 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend, SND_SOC_CS35L56_CORE); 1051 1052 static int __maybe_unused cs35l56_runtime_resume_i2c_spi(struct device *dev) 1053 { 1054 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1055 1056 if (!cs35l56->init_done) 1057 return 0; 1058 1059 return cs35l56_runtime_resume_common(cs35l56); 1060 } 1061 1062 int cs35l56_runtime_resume_common(struct cs35l56_private *cs35l56) 1063 { 1064 unsigned int val; 1065 int ret; 1066 1067 if (!cs35l56->can_hibernate) 1068 goto out_sync; 1069 1070 if (!cs35l56->sdw_peripheral) { 1071 /* 1072 * Dummy transaction to trigger I2C/SPI auto-wake. This will NAK on I2C. 1073 * Must be done before releasing cache-only. 1074 */ 1075 regmap_multi_reg_write_bypassed(cs35l56->regmap, 1076 cs35l56_hibernate_wake_seq, 1077 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 1078 1079 usleep_range(CS35L56_CONTROL_PORT_READY_US, 1080 CS35L56_CONTROL_PORT_READY_US + 400); 1081 } 1082 1083 out_sync: 1084 regcache_cache_only(cs35l56->regmap, false); 1085 1086 ret = cs35l56_wait_for_firmware_boot(cs35l56); 1087 if (ret) { 1088 dev_err(cs35l56->dev, "Hibernate wake failed: %d\n", ret); 1089 goto err; 1090 } 1091 1092 ret = cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 1093 if (ret) 1094 goto err; 1095 1096 /* BOOT_DONE will be 1 if the amp reset */ 1097 regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_4, &val); 1098 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 1099 dev_dbg(cs35l56->dev, "Registers reset in suspend\n"); 1100 regcache_mark_dirty(cs35l56->regmap); 1101 } 1102 1103 regcache_sync(cs35l56->regmap); 1104 1105 dev_dbg(cs35l56->dev, "Resumed"); 1106 1107 return 0; 1108 1109 err: 1110 regmap_write(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 1111 CS35L56_MBOX_CMD_HIBERNATE_NOW); 1112 1113 regcache_cache_only(cs35l56->regmap, true); 1114 1115 return ret; 1116 } 1117 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_CORE); 1118 1119 static int cs35l56_is_fw_reload_needed(struct cs35l56_private *cs35l56) 1120 { 1121 unsigned int val; 1122 int ret; 1123 1124 /* Nothing to re-patch if we haven't done any patching yet. */ 1125 if (!cs35l56->fw_patched) 1126 return false; 1127 1128 /* 1129 * If we have control of RESET we will have asserted it so the firmware 1130 * will need re-patching. 1131 */ 1132 if (cs35l56->reset_gpio) 1133 return true; 1134 1135 /* 1136 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 1137 * can't be used here to test for memory retention. 1138 * Assume that tuning must be re-loaded. 1139 */ 1140 if (cs35l56->secured) 1141 return true; 1142 1143 ret = pm_runtime_resume_and_get(cs35l56->dev); 1144 if (ret) { 1145 dev_err(cs35l56->dev, "Failed to runtime_get: %d\n", ret); 1146 return ret; 1147 } 1148 1149 ret = regmap_read(cs35l56->regmap, CS35L56_PROTECTION_STATUS, &val); 1150 if (ret) 1151 dev_err(cs35l56->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 1152 else 1153 ret = !!(val & CS35L56_FIRMWARE_MISSING); 1154 1155 pm_runtime_put_autosuspend(cs35l56->dev); 1156 1157 return ret; 1158 } 1159 1160 int cs35l56_system_suspend(struct device *dev) 1161 { 1162 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1163 1164 dev_dbg(dev, "system_suspend\n"); 1165 1166 if (cs35l56->component) 1167 flush_work(&cs35l56->dsp_work); 1168 1169 /* 1170 * The interrupt line is normally shared, but after we start suspending 1171 * we can't check if our device is the source of an interrupt, and can't 1172 * clear it. Prevent this race by temporarily disabling the parent irq 1173 * until we reach _no_irq. 1174 */ 1175 if (cs35l56->irq) 1176 disable_irq(cs35l56->irq); 1177 1178 return pm_runtime_force_suspend(dev); 1179 } 1180 EXPORT_SYMBOL_GPL(cs35l56_system_suspend); 1181 1182 int cs35l56_system_suspend_late(struct device *dev) 1183 { 1184 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1185 1186 dev_dbg(dev, "system_suspend_late\n"); 1187 1188 /* 1189 * Assert RESET before removing supplies. 1190 * RESET is usually shared by all amps so it must not be asserted until 1191 * all driver instances have done their suspend() stage. 1192 */ 1193 if (cs35l56->reset_gpio) { 1194 gpiod_set_value_cansleep(cs35l56->reset_gpio, 0); 1195 cs35l56_wait_min_reset_pulse(); 1196 } 1197 1198 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1199 1200 return 0; 1201 } 1202 EXPORT_SYMBOL_GPL(cs35l56_system_suspend_late); 1203 1204 int cs35l56_system_suspend_no_irq(struct device *dev) 1205 { 1206 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1207 1208 dev_dbg(dev, "system_suspend_no_irq\n"); 1209 1210 /* Handlers are now disabled so the parent IRQ can safely be re-enabled. */ 1211 if (cs35l56->irq) 1212 enable_irq(cs35l56->irq); 1213 1214 return 0; 1215 } 1216 EXPORT_SYMBOL_GPL(cs35l56_system_suspend_no_irq); 1217 1218 int cs35l56_system_resume_no_irq(struct device *dev) 1219 { 1220 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1221 1222 dev_dbg(dev, "system_resume_no_irq\n"); 1223 1224 /* 1225 * WAKE interrupts unmask if the CS35L56 hibernates, which can cause 1226 * spurious interrupts, and the interrupt line is normally shared. 1227 * We can't check if our device is the source of an interrupt, and can't 1228 * clear it, until it has fully resumed. Prevent this race by temporarily 1229 * disabling the parent irq until we complete resume(). 1230 */ 1231 if (cs35l56->irq) 1232 disable_irq(cs35l56->irq); 1233 1234 return 0; 1235 } 1236 EXPORT_SYMBOL_GPL(cs35l56_system_resume_no_irq); 1237 1238 int cs35l56_system_resume_early(struct device *dev) 1239 { 1240 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1241 int ret; 1242 1243 dev_dbg(dev, "system_resume_early\n"); 1244 1245 /* Ensure a spec-compliant RESET pulse. */ 1246 if (cs35l56->reset_gpio) { 1247 gpiod_set_value_cansleep(cs35l56->reset_gpio, 0); 1248 cs35l56_wait_min_reset_pulse(); 1249 } 1250 1251 /* Enable supplies before releasing RESET. */ 1252 ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1253 if (ret) { 1254 dev_err(dev, "system_resume_early failed to enable supplies: %d\n", ret); 1255 return ret; 1256 } 1257 1258 /* Release shared RESET before drivers start resume(). */ 1259 gpiod_set_value_cansleep(cs35l56->reset_gpio, 1); 1260 1261 return 0; 1262 } 1263 EXPORT_SYMBOL_GPL(cs35l56_system_resume_early); 1264 1265 int cs35l56_system_resume(struct device *dev) 1266 { 1267 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1268 int ret; 1269 1270 dev_dbg(dev, "system_resume\n"); 1271 1272 /* Undo pm_runtime_force_suspend() before re-enabling the irq */ 1273 ret = pm_runtime_force_resume(dev); 1274 if (cs35l56->irq) 1275 enable_irq(cs35l56->irq); 1276 1277 if (ret) 1278 return ret; 1279 1280 /* Firmware won't have been loaded if the component hasn't probed */ 1281 if (!cs35l56->component) 1282 return 0; 1283 1284 ret = cs35l56_is_fw_reload_needed(cs35l56); 1285 dev_dbg(cs35l56->dev, "fw_reload_needed: %d\n", ret); 1286 if (ret < 1) 1287 return ret; 1288 1289 cs35l56->fw_patched = false; 1290 queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work); 1291 1292 /* 1293 * suspend_bias_off ensures we are now in BIAS_OFF so there will be 1294 * a BIAS_OFF->BIAS_STANDBY transition to complete dsp patching. 1295 */ 1296 1297 return 0; 1298 } 1299 EXPORT_SYMBOL_GPL(cs35l56_system_resume); 1300 1301 static int cs35l56_dsp_init(struct cs35l56_private *cs35l56) 1302 { 1303 struct wm_adsp *dsp; 1304 int ret; 1305 1306 cs35l56->dsp_wq = create_singlethread_workqueue("cs35l56-dsp"); 1307 if (!cs35l56->dsp_wq) 1308 return -ENOMEM; 1309 1310 INIT_WORK(&cs35l56->dsp_work, cs35l56_dsp_work); 1311 1312 dsp = &cs35l56->dsp; 1313 dsp->part = "cs35l56"; 1314 dsp->cs_dsp.num = 1; 1315 dsp->cs_dsp.type = WMFW_HALO; 1316 dsp->cs_dsp.rev = 0; 1317 dsp->fw = 12; 1318 dsp->cs_dsp.dev = cs35l56->dev; 1319 dsp->cs_dsp.regmap = cs35l56->regmap; 1320 dsp->cs_dsp.base = CS35L56_DSP1_CORE_BASE; 1321 dsp->cs_dsp.base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 1322 dsp->cs_dsp.mem = cs35l56_dsp1_regions; 1323 dsp->cs_dsp.num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 1324 dsp->cs_dsp.no_core_startstop = true; 1325 dsp->wmfw_optional = true; 1326 1327 dev_dbg(cs35l56->dev, "DSP system name: '%s'\n", dsp->system_name); 1328 1329 ret = wm_halo_init(dsp); 1330 if (ret != 0) { 1331 dev_err(cs35l56->dev, "wm_halo_init failed\n"); 1332 return ret; 1333 } 1334 1335 return 0; 1336 } 1337 1338 static int cs35l56_acpi_get_name(struct cs35l56_private *cs35l56) 1339 { 1340 acpi_handle handle = ACPI_HANDLE(cs35l56->dev); 1341 const char *sub; 1342 1343 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */ 1344 if (!handle) 1345 return 0; 1346 1347 sub = acpi_get_subsystem_id(handle); 1348 if (IS_ERR(sub)) { 1349 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */ 1350 if (PTR_ERR(sub) == -ENODATA) 1351 return 0; 1352 else 1353 return PTR_ERR(sub); 1354 } 1355 1356 cs35l56->dsp.system_name = sub; 1357 dev_dbg(cs35l56->dev, "Subsystem ID: %s\n", cs35l56->dsp.system_name); 1358 1359 return 0; 1360 } 1361 1362 int cs35l56_common_probe(struct cs35l56_private *cs35l56) 1363 { 1364 int ret; 1365 1366 init_completion(&cs35l56->init_completion); 1367 mutex_init(&cs35l56->irq_lock); 1368 1369 dev_set_drvdata(cs35l56->dev, cs35l56); 1370 1371 cs35l56_fill_supply_names(cs35l56->supplies); 1372 ret = devm_regulator_bulk_get(cs35l56->dev, ARRAY_SIZE(cs35l56->supplies), 1373 cs35l56->supplies); 1374 if (ret != 0) 1375 return dev_err_probe(cs35l56->dev, ret, "Failed to request supplies\n"); 1376 1377 /* Reset could be controlled by the BIOS or shared by multiple amps */ 1378 cs35l56->reset_gpio = devm_gpiod_get_optional(cs35l56->dev, "reset", GPIOD_OUT_LOW); 1379 if (IS_ERR(cs35l56->reset_gpio)) { 1380 ret = PTR_ERR(cs35l56->reset_gpio); 1381 /* 1382 * If RESET is shared the first amp to probe will grab the reset 1383 * line and reset all the amps 1384 */ 1385 if (ret != -EBUSY) 1386 return dev_err_probe(cs35l56->dev, ret, "Failed to get reset GPIO\n"); 1387 1388 dev_info(cs35l56->dev, "Reset GPIO busy, assume shared reset\n"); 1389 cs35l56->reset_gpio = NULL; 1390 } 1391 1392 ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1393 if (ret != 0) 1394 return dev_err_probe(cs35l56->dev, ret, "Failed to enable supplies\n"); 1395 1396 if (cs35l56->reset_gpio) { 1397 cs35l56_wait_min_reset_pulse(); 1398 gpiod_set_value_cansleep(cs35l56->reset_gpio, 1); 1399 } 1400 1401 ret = cs35l56_acpi_get_name(cs35l56); 1402 if (ret != 0) 1403 goto err; 1404 1405 ret = cs35l56_dsp_init(cs35l56); 1406 if (ret < 0) { 1407 dev_err_probe(cs35l56->dev, ret, "DSP init failed\n"); 1408 goto err; 1409 } 1410 1411 ret = devm_snd_soc_register_component(cs35l56->dev, 1412 &soc_component_dev_cs35l56, 1413 cs35l56_dai, ARRAY_SIZE(cs35l56_dai)); 1414 if (ret < 0) { 1415 dev_err_probe(cs35l56->dev, ret, "Register codec failed\n"); 1416 goto err; 1417 } 1418 1419 return 0; 1420 1421 err: 1422 gpiod_set_value_cansleep(cs35l56->reset_gpio, 0); 1423 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1424 1425 return ret; 1426 } 1427 EXPORT_SYMBOL_NS_GPL(cs35l56_common_probe, SND_SOC_CS35L56_CORE); 1428 1429 int cs35l56_init(struct cs35l56_private *cs35l56) 1430 { 1431 int ret; 1432 unsigned int devid, revid, otpid, secured; 1433 1434 /* 1435 * Check whether the actions associated with soft reset or one time 1436 * init need to be performed. 1437 */ 1438 if (cs35l56->soft_resetting) 1439 goto post_soft_reset; 1440 1441 if (cs35l56->init_done) 1442 return 0; 1443 1444 pm_runtime_set_autosuspend_delay(cs35l56->dev, 100); 1445 pm_runtime_use_autosuspend(cs35l56->dev); 1446 pm_runtime_set_active(cs35l56->dev); 1447 pm_runtime_enable(cs35l56->dev); 1448 1449 /* 1450 * If the system is not using a reset_gpio then issue a 1451 * dummy read to force a wakeup. 1452 */ 1453 if (!cs35l56->reset_gpio) 1454 regmap_read(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, &devid); 1455 1456 /* Wait for control port to be ready (datasheet tIRS). */ 1457 usleep_range(CS35L56_CONTROL_PORT_READY_US, 1458 CS35L56_CONTROL_PORT_READY_US + 400); 1459 1460 /* 1461 * The HALO_STATE register is in different locations on Ax and B0 1462 * devices so the REVID needs to be determined before waiting for the 1463 * firmware to boot. 1464 */ 1465 ret = regmap_read(cs35l56->regmap, CS35L56_REVID, &revid); 1466 if (ret < 0) { 1467 dev_err(cs35l56->dev, "Get Revision ID failed\n"); 1468 return ret; 1469 } 1470 cs35l56->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 1471 1472 ret = cs35l56_wait_for_firmware_boot(cs35l56); 1473 if (ret) 1474 return ret; 1475 1476 ret = regmap_read(cs35l56->regmap, CS35L56_DEVID, &devid); 1477 if (ret < 0) { 1478 dev_err(cs35l56->dev, "Get Device ID failed\n"); 1479 return ret; 1480 } 1481 devid &= CS35L56_DEVID_MASK; 1482 1483 switch (devid) { 1484 case 0x35A56: 1485 break; 1486 default: 1487 dev_err(cs35l56->dev, "Unknown device %x\n", devid); 1488 return ret; 1489 } 1490 1491 ret = regmap_read(cs35l56->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 1492 if (ret) { 1493 dev_err(cs35l56->dev, "Get Secure status failed\n"); 1494 return ret; 1495 } 1496 1497 /* When any bus is restricted treat the device as secured */ 1498 if (secured & CS35L56_RESTRICTED_MASK) 1499 cs35l56->secured = true; 1500 1501 ret = regmap_read(cs35l56->regmap, CS35L56_OTPID, &otpid); 1502 if (ret < 0) { 1503 dev_err(cs35l56->dev, "Get OTP ID failed\n"); 1504 return ret; 1505 } 1506 1507 dev_info(cs35l56->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d\n", 1508 cs35l56->secured ? "s" : "", cs35l56->rev, otpid); 1509 1510 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 1511 regmap_write(cs35l56->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 1512 regmap_update_bits(cs35l56->regmap, CS35L56_IRQ1_MASK_1, 1513 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 1514 0); 1515 regmap_update_bits(cs35l56->regmap, CS35L56_IRQ1_MASK_8, 1516 CS35L56_TEMP_ERR_EINT1_MASK, 1517 0); 1518 1519 if (!cs35l56->reset_gpio) { 1520 dev_dbg(cs35l56->dev, "No reset gpio: using soft reset\n"); 1521 cs35l56_system_reset(cs35l56); 1522 if (cs35l56->sdw_peripheral) { 1523 /* Keep alive while we wait for re-enumeration */ 1524 pm_runtime_get_noresume(cs35l56->dev); 1525 return 0; 1526 } 1527 } 1528 1529 post_soft_reset: 1530 if (cs35l56->soft_resetting) { 1531 cs35l56->soft_resetting = false; 1532 1533 /* Done re-enumerating after one-time init so release the keep-alive */ 1534 if (cs35l56->sdw_peripheral && !cs35l56->init_done) 1535 pm_runtime_put_noidle(cs35l56->dev); 1536 1537 regcache_mark_dirty(cs35l56->regmap); 1538 ret = cs35l56_wait_for_firmware_boot(cs35l56); 1539 if (ret) 1540 return ret; 1541 1542 dev_dbg(cs35l56->dev, "Firmware rebooted after soft reset\n"); 1543 } 1544 1545 /* Disable auto-hibernate so that runtime_pm has control */ 1546 ret = cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 1547 if (ret) 1548 return ret; 1549 1550 /* Populate soft registers in the regmap cache */ 1551 cs35l56_reread_firmware_registers(cs35l56->dev, cs35l56->regmap); 1552 1553 /* Registers could be dirty after soft reset or SoundWire enumeration */ 1554 regcache_sync(cs35l56->regmap); 1555 1556 cs35l56->init_done = true; 1557 complete(&cs35l56->init_completion); 1558 1559 return 0; 1560 } 1561 EXPORT_SYMBOL_NS_GPL(cs35l56_init, SND_SOC_CS35L56_CORE); 1562 1563 void cs35l56_remove(struct cs35l56_private *cs35l56) 1564 { 1565 cs35l56->init_done = false; 1566 1567 /* 1568 * WAKE IRQs unmask if CS35L56 hibernates so free the handler to 1569 * prevent it racing with remove(). 1570 */ 1571 if (cs35l56->irq) 1572 devm_free_irq(cs35l56->dev, cs35l56->irq, cs35l56); 1573 1574 flush_workqueue(cs35l56->dsp_wq); 1575 destroy_workqueue(cs35l56->dsp_wq); 1576 1577 pm_runtime_suspend(cs35l56->dev); 1578 pm_runtime_disable(cs35l56->dev); 1579 1580 regcache_cache_only(cs35l56->regmap, true); 1581 1582 kfree(cs35l56->dsp.system_name); 1583 1584 gpiod_set_value_cansleep(cs35l56->reset_gpio, 0); 1585 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1586 } 1587 EXPORT_SYMBOL_NS_GPL(cs35l56_remove, SND_SOC_CS35L56_CORE); 1588 1589 const struct dev_pm_ops cs35l56_pm_ops_i2c_spi = { 1590 SET_RUNTIME_PM_OPS(cs35l56_runtime_suspend, cs35l56_runtime_resume_i2c_spi, NULL) 1591 SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend, cs35l56_system_resume) 1592 LATE_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_late, cs35l56_system_resume_early) 1593 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_no_irq, cs35l56_system_resume_no_irq) 1594 }; 1595 EXPORT_SYMBOL_NS_GPL(cs35l56_pm_ops_i2c_spi, SND_SOC_CS35L56_CORE); 1596 1597 MODULE_DESCRIPTION("ASoC CS35L56 driver"); 1598 MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED); 1599 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1600 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1601 MODULE_LICENSE("GPL"); 1602