1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cirrus Logic CS35L56 smart amp 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/acpi.h> 9 #include <linux/completion.h> 10 #include <linux/debugfs.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/interrupt.h> 15 #include <linux/math.h> 16 #include <linux/module.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/slab.h> 22 #include <linux/soundwire/sdw.h> 23 #include <linux/types.h> 24 #include <linux/workqueue.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dapm.h> 29 #include <sound/tlv.h> 30 31 #include "wm_adsp.h" 32 #include "cs35l56.h" 33 34 static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w, 35 struct snd_kcontrol *kcontrol, int event); 36 37 static int cs35l56_mbox_send(struct cs35l56_private *cs35l56, unsigned int command) 38 { 39 unsigned int val; 40 int ret; 41 42 regmap_write(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 43 ret = regmap_read_poll_timeout(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 44 val, (val == 0), 45 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 46 if (ret) { 47 dev_warn(cs35l56->dev, "MBOX command %#x failed: %d\n", command, ret); 48 return ret; 49 } 50 51 return 0; 52 } 53 54 static void cs35l56_wait_dsp_ready(struct cs35l56_private *cs35l56) 55 { 56 /* Wait for patching to complete */ 57 flush_work(&cs35l56->dsp_work); 58 } 59 60 static int cs35l56_dspwait_get_volsw(struct snd_kcontrol *kcontrol, 61 struct snd_ctl_elem_value *ucontrol) 62 { 63 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 64 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 65 66 cs35l56_wait_dsp_ready(cs35l56); 67 return snd_soc_get_volsw(kcontrol, ucontrol); 68 } 69 70 static int cs35l56_dspwait_put_volsw(struct snd_kcontrol *kcontrol, 71 struct snd_ctl_elem_value *ucontrol) 72 { 73 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 74 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 75 76 cs35l56_wait_dsp_ready(cs35l56); 77 return snd_soc_put_volsw(kcontrol, ucontrol); 78 } 79 80 static DECLARE_TLV_DB_SCALE(vol_tlv, -10000, 25, 0); 81 82 static const struct snd_kcontrol_new cs35l56_controls[] = { 83 SOC_SINGLE_EXT("Speaker Switch", 84 CS35L56_MAIN_RENDER_USER_MUTE, 0, 1, 1, 85 cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw), 86 SOC_SINGLE_S_EXT_TLV("Speaker Volume", 87 CS35L56_MAIN_RENDER_USER_VOLUME, 88 6, -400, 400, 9, 0, 89 cs35l56_dspwait_get_volsw, 90 cs35l56_dspwait_put_volsw, 91 vol_tlv), 92 SOC_SINGLE_EXT("Posture Number", CS35L56_MAIN_POSTURE_NUMBER, 93 0, 255, 0, 94 cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw), 95 }; 96 97 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx1_enum, 98 CS35L56_ASP1TX1_INPUT, 99 0, CS35L56_ASP_TXn_SRC_MASK, 100 cs35l56_tx_input_texts, 101 cs35l56_tx_input_values); 102 103 static const struct snd_kcontrol_new asp1_tx1_mux = 104 SOC_DAPM_ENUM("ASP1TX1 SRC", cs35l56_asp1tx1_enum); 105 106 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx2_enum, 107 CS35L56_ASP1TX2_INPUT, 108 0, CS35L56_ASP_TXn_SRC_MASK, 109 cs35l56_tx_input_texts, 110 cs35l56_tx_input_values); 111 112 static const struct snd_kcontrol_new asp1_tx2_mux = 113 SOC_DAPM_ENUM("ASP1TX2 SRC", cs35l56_asp1tx2_enum); 114 115 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx3_enum, 116 CS35L56_ASP1TX3_INPUT, 117 0, CS35L56_ASP_TXn_SRC_MASK, 118 cs35l56_tx_input_texts, 119 cs35l56_tx_input_values); 120 121 static const struct snd_kcontrol_new asp1_tx3_mux = 122 SOC_DAPM_ENUM("ASP1TX3 SRC", cs35l56_asp1tx3_enum); 123 124 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx4_enum, 125 CS35L56_ASP1TX4_INPUT, 126 0, CS35L56_ASP_TXn_SRC_MASK, 127 cs35l56_tx_input_texts, 128 cs35l56_tx_input_values); 129 130 static const struct snd_kcontrol_new asp1_tx4_mux = 131 SOC_DAPM_ENUM("ASP1TX4 SRC", cs35l56_asp1tx4_enum); 132 133 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx1_enum, 134 CS35L56_SWIRE_DP3_CH1_INPUT, 135 0, CS35L56_SWIRETXn_SRC_MASK, 136 cs35l56_tx_input_texts, 137 cs35l56_tx_input_values); 138 139 static const struct snd_kcontrol_new sdw1_tx1_mux = 140 SOC_DAPM_ENUM("SDW1TX1 SRC", cs35l56_sdw1tx1_enum); 141 142 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx2_enum, 143 CS35L56_SWIRE_DP3_CH2_INPUT, 144 0, CS35L56_SWIRETXn_SRC_MASK, 145 cs35l56_tx_input_texts, 146 cs35l56_tx_input_values); 147 148 static const struct snd_kcontrol_new sdw1_tx2_mux = 149 SOC_DAPM_ENUM("SDW1TX2 SRC", cs35l56_sdw1tx2_enum); 150 151 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx3_enum, 152 CS35L56_SWIRE_DP3_CH3_INPUT, 153 0, CS35L56_SWIRETXn_SRC_MASK, 154 cs35l56_tx_input_texts, 155 cs35l56_tx_input_values); 156 157 static const struct snd_kcontrol_new sdw1_tx3_mux = 158 SOC_DAPM_ENUM("SDW1TX3 SRC", cs35l56_sdw1tx3_enum); 159 160 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx4_enum, 161 CS35L56_SWIRE_DP3_CH4_INPUT, 162 0, CS35L56_SWIRETXn_SRC_MASK, 163 cs35l56_tx_input_texts, 164 cs35l56_tx_input_values); 165 166 static const struct snd_kcontrol_new sdw1_tx4_mux = 167 SOC_DAPM_ENUM("SDW1TX4 SRC", cs35l56_sdw1tx4_enum); 168 169 static int cs35l56_play_event(struct snd_soc_dapm_widget *w, 170 struct snd_kcontrol *kcontrol, int event) 171 { 172 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 173 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 174 unsigned int val; 175 int ret; 176 177 dev_dbg(cs35l56->dev, "play: %d\n", event); 178 179 switch (event) { 180 case SND_SOC_DAPM_PRE_PMU: 181 /* Don't wait for ACK, we check in POST_PMU that it completed */ 182 return regmap_write(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 183 CS35L56_MBOX_CMD_AUDIO_PLAY); 184 case SND_SOC_DAPM_POST_PMU: 185 /* Wait for firmware to enter PS0 power state */ 186 ret = regmap_read_poll_timeout(cs35l56->regmap, 187 CS35L56_TRANSDUCER_ACTUAL_PS, 188 val, (val == CS35L56_PS0), 189 CS35L56_PS0_POLL_US, 190 CS35L56_PS0_TIMEOUT_US); 191 if (ret) 192 dev_err(cs35l56->dev, "PS0 wait failed: %d\n", ret); 193 return ret; 194 case SND_SOC_DAPM_POST_PMD: 195 return cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_AUDIO_PAUSE); 196 default: 197 return 0; 198 } 199 } 200 201 static const struct snd_soc_dapm_widget cs35l56_dapm_widgets[] = { 202 SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_B", 0, 0), 203 SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_AMP", 0, 0), 204 205 SND_SOC_DAPM_SUPPLY("PLAY", SND_SOC_NOPM, 0, 0, cs35l56_play_event, 206 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 207 208 SND_SOC_DAPM_OUT_DRV("AMP", SND_SOC_NOPM, 0, 0, NULL, 0), 209 SND_SOC_DAPM_OUTPUT("SPK"), 210 211 SND_SOC_DAPM_PGA_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, cs35l56_dsp_event, 212 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 213 214 SND_SOC_DAPM_AIF_IN("ASP1RX1", NULL, 0, CS35L56_ASP1_ENABLES1, 215 CS35L56_ASP_RX1_EN_SHIFT, 0), 216 SND_SOC_DAPM_AIF_IN("ASP1RX2", NULL, 1, CS35L56_ASP1_ENABLES1, 217 CS35L56_ASP_RX2_EN_SHIFT, 0), 218 SND_SOC_DAPM_AIF_OUT("ASP1TX1", NULL, 0, CS35L56_ASP1_ENABLES1, 219 CS35L56_ASP_TX1_EN_SHIFT, 0), 220 SND_SOC_DAPM_AIF_OUT("ASP1TX2", NULL, 1, CS35L56_ASP1_ENABLES1, 221 CS35L56_ASP_TX2_EN_SHIFT, 0), 222 SND_SOC_DAPM_AIF_OUT("ASP1TX3", NULL, 2, CS35L56_ASP1_ENABLES1, 223 CS35L56_ASP_TX3_EN_SHIFT, 0), 224 SND_SOC_DAPM_AIF_OUT("ASP1TX4", NULL, 3, CS35L56_ASP1_ENABLES1, 225 CS35L56_ASP_TX4_EN_SHIFT, 0), 226 227 SND_SOC_DAPM_MUX("ASP1 TX1 Source", SND_SOC_NOPM, 0, 0, &asp1_tx1_mux), 228 SND_SOC_DAPM_MUX("ASP1 TX2 Source", SND_SOC_NOPM, 0, 0, &asp1_tx2_mux), 229 SND_SOC_DAPM_MUX("ASP1 TX3 Source", SND_SOC_NOPM, 0, 0, &asp1_tx3_mux), 230 SND_SOC_DAPM_MUX("ASP1 TX4 Source", SND_SOC_NOPM, 0, 0, &asp1_tx4_mux), 231 232 SND_SOC_DAPM_MUX("SDW1 TX1 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx1_mux), 233 SND_SOC_DAPM_MUX("SDW1 TX2 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx2_mux), 234 SND_SOC_DAPM_MUX("SDW1 TX3 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx3_mux), 235 SND_SOC_DAPM_MUX("SDW1 TX4 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx4_mux), 236 237 SND_SOC_DAPM_SIGGEN("VMON ADC"), 238 SND_SOC_DAPM_SIGGEN("IMON ADC"), 239 SND_SOC_DAPM_SIGGEN("ERRVOL ADC"), 240 SND_SOC_DAPM_SIGGEN("CLASSH ADC"), 241 SND_SOC_DAPM_SIGGEN("VDDBMON ADC"), 242 SND_SOC_DAPM_SIGGEN("VBSTMON ADC"), 243 SND_SOC_DAPM_SIGGEN("TEMPMON ADC"), 244 }; 245 246 #define CS35L56_SRC_ROUTE(name) \ 247 { name" Source", "ASP1RX1", "ASP1RX1" }, \ 248 { name" Source", "ASP1RX2", "ASP1RX2" }, \ 249 { name" Source", "VMON", "VMON ADC" }, \ 250 { name" Source", "IMON", "IMON ADC" }, \ 251 { name" Source", "ERRVOL", "ERRVOL ADC" }, \ 252 { name" Source", "CLASSH", "CLASSH ADC" }, \ 253 { name" Source", "VDDBMON", "VDDBMON ADC" }, \ 254 { name" Source", "VBSTMON", "VBSTMON ADC" }, \ 255 { name" Source", "DSP1TX1", "DSP1" }, \ 256 { name" Source", "DSP1TX2", "DSP1" }, \ 257 { name" Source", "DSP1TX3", "DSP1" }, \ 258 { name" Source", "DSP1TX4", "DSP1" }, \ 259 { name" Source", "DSP1TX5", "DSP1" }, \ 260 { name" Source", "DSP1TX6", "DSP1" }, \ 261 { name" Source", "DSP1TX7", "DSP1" }, \ 262 { name" Source", "DSP1TX8", "DSP1" }, \ 263 { name" Source", "TEMPMON", "TEMPMON ADC" }, \ 264 { name" Source", "INTERPOLATOR", "AMP" }, \ 265 { name" Source", "SDW1RX1", "SDW1 Playback" }, \ 266 { name" Source", "SDW1RX2", "SDW1 Playback" }, 267 268 static const struct snd_soc_dapm_route cs35l56_audio_map[] = { 269 { "AMP", NULL, "VDD_B" }, 270 { "AMP", NULL, "VDD_AMP" }, 271 272 { "ASP1 Playback", NULL, "PLAY" }, 273 { "SDW1 Playback", NULL, "PLAY" }, 274 275 { "ASP1RX1", NULL, "ASP1 Playback" }, 276 { "ASP1RX2", NULL, "ASP1 Playback" }, 277 { "DSP1", NULL, "ASP1RX1" }, 278 { "DSP1", NULL, "ASP1RX2" }, 279 { "DSP1", NULL, "SDW1 Playback" }, 280 { "AMP", NULL, "DSP1" }, 281 { "SPK", NULL, "AMP" }, 282 283 CS35L56_SRC_ROUTE("ASP1 TX1") 284 CS35L56_SRC_ROUTE("ASP1 TX2") 285 CS35L56_SRC_ROUTE("ASP1 TX3") 286 CS35L56_SRC_ROUTE("ASP1 TX4") 287 288 { "ASP1TX1", NULL, "ASP1 TX1 Source" }, 289 { "ASP1TX2", NULL, "ASP1 TX2 Source" }, 290 { "ASP1TX3", NULL, "ASP1 TX3 Source" }, 291 { "ASP1TX4", NULL, "ASP1 TX4 Source" }, 292 { "ASP1 Capture", NULL, "ASP1TX1" }, 293 { "ASP1 Capture", NULL, "ASP1TX2" }, 294 { "ASP1 Capture", NULL, "ASP1TX3" }, 295 { "ASP1 Capture", NULL, "ASP1TX4" }, 296 297 CS35L56_SRC_ROUTE("SDW1 TX1") 298 CS35L56_SRC_ROUTE("SDW1 TX2") 299 CS35L56_SRC_ROUTE("SDW1 TX3") 300 CS35L56_SRC_ROUTE("SDW1 TX4") 301 { "SDW1 Capture", NULL, "SDW1 TX1 Source" }, 302 { "SDW1 Capture", NULL, "SDW1 TX2 Source" }, 303 { "SDW1 Capture", NULL, "SDW1 TX3 Source" }, 304 { "SDW1 Capture", NULL, "SDW1 TX4 Source" }, 305 }; 306 307 static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w, 308 struct snd_kcontrol *kcontrol, int event) 309 { 310 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 311 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 312 313 dev_dbg(cs35l56->dev, "%s: %d\n", __func__, event); 314 315 return wm_adsp_event(w, kcontrol, event); 316 } 317 318 irqreturn_t cs35l56_irq(int irq, void *data) 319 { 320 struct cs35l56_private *cs35l56 = data; 321 unsigned int status1 = 0, status8 = 0, status20 = 0; 322 unsigned int mask1, mask8, mask20; 323 unsigned int val; 324 int rv; 325 326 irqreturn_t ret = IRQ_NONE; 327 328 if (!cs35l56->init_done) 329 return IRQ_NONE; 330 331 mutex_lock(&cs35l56->irq_lock); 332 333 rv = pm_runtime_resume_and_get(cs35l56->dev); 334 if (rv < 0) { 335 dev_err(cs35l56->dev, "irq: failed to get pm_runtime: %d\n", rv); 336 goto err_unlock; 337 } 338 339 regmap_read(cs35l56->regmap, CS35L56_IRQ1_STATUS, &val); 340 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 341 dev_dbg(cs35l56->dev, "Spurious IRQ: no pending interrupt\n"); 342 goto err; 343 } 344 345 /* Ack interrupts */ 346 regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_1, &status1); 347 regmap_read(cs35l56->regmap, CS35L56_IRQ1_MASK_1, &mask1); 348 status1 &= ~mask1; 349 regmap_write(cs35l56->regmap, CS35L56_IRQ1_EINT_1, status1); 350 351 regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_8, &status8); 352 regmap_read(cs35l56->regmap, CS35L56_IRQ1_MASK_8, &mask8); 353 status8 &= ~mask8; 354 regmap_write(cs35l56->regmap, CS35L56_IRQ1_EINT_8, status8); 355 356 regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_20, &status20); 357 regmap_read(cs35l56->regmap, CS35L56_IRQ1_MASK_20, &mask20); 358 status20 &= ~mask20; 359 /* We don't want EINT20 but they default to unmasked: force mask */ 360 regmap_write(cs35l56->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 361 362 dev_dbg(cs35l56->dev, "%s: %#x %#x\n", __func__, status1, status8); 363 364 /* Check to see if unmasked bits are active */ 365 if (!status1 && !status8 && !status20) 366 goto err; 367 368 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 369 dev_crit(cs35l56->dev, "Amp short error\n"); 370 371 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 372 dev_crit(cs35l56->dev, "Overtemp error\n"); 373 374 ret = IRQ_HANDLED; 375 376 err: 377 pm_runtime_put(cs35l56->dev); 378 err_unlock: 379 mutex_unlock(&cs35l56->irq_lock); 380 381 return ret; 382 } 383 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_CORE); 384 385 int cs35l56_irq_request(struct cs35l56_private *cs35l56, int irq) 386 { 387 int ret; 388 389 if (!irq) 390 return 0; 391 392 ret = devm_request_threaded_irq(cs35l56->dev, irq, NULL, cs35l56_irq, 393 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 394 "cs35l56", cs35l56); 395 if (!ret) 396 cs35l56->irq = irq; 397 else 398 dev_err(cs35l56->dev, "Failed to get IRQ: %d\n", ret); 399 400 return ret; 401 } 402 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_CORE); 403 404 static int cs35l56_asp_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 405 { 406 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(codec_dai->component); 407 unsigned int val; 408 409 dev_dbg(cs35l56->dev, "%s: %#x\n", __func__, fmt); 410 411 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 412 case SND_SOC_DAIFMT_CBC_CFC: 413 break; 414 default: 415 dev_err(cs35l56->dev, "Unsupported clock source mode\n"); 416 return -EINVAL; 417 } 418 419 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 420 case SND_SOC_DAIFMT_DSP_A: 421 val = CS35L56_ASP_FMT_DSP_A << CS35L56_ASP_FMT_SHIFT; 422 cs35l56->tdm_mode = true; 423 break; 424 case SND_SOC_DAIFMT_I2S: 425 val = CS35L56_ASP_FMT_I2S << CS35L56_ASP_FMT_SHIFT; 426 cs35l56->tdm_mode = false; 427 break; 428 default: 429 dev_err(cs35l56->dev, "Unsupported DAI format\n"); 430 return -EINVAL; 431 } 432 433 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 434 case SND_SOC_DAIFMT_NB_IF: 435 val |= CS35L56_ASP_FSYNC_INV_MASK; 436 break; 437 case SND_SOC_DAIFMT_IB_NF: 438 val |= CS35L56_ASP_BCLK_INV_MASK; 439 break; 440 case SND_SOC_DAIFMT_IB_IF: 441 val |= CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK; 442 break; 443 case SND_SOC_DAIFMT_NB_NF: 444 break; 445 default: 446 dev_err(cs35l56->dev, "Invalid clock invert\n"); 447 return -EINVAL; 448 } 449 450 regmap_update_bits(cs35l56->regmap, 451 CS35L56_ASP1_CONTROL2, 452 CS35L56_ASP_FMT_MASK | 453 CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK, 454 val); 455 456 /* Hi-Z DOUT in unused slots and when all TX are disabled */ 457 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL3, 458 CS35L56_ASP1_DOUT_HIZ_CTRL_MASK, 459 CS35L56_ASP_UNUSED_HIZ_OFF_HIZ); 460 461 return 0; 462 } 463 464 static void cs35l56_set_asp_slot_positions(struct cs35l56_private *cs35l56, 465 unsigned int reg, unsigned long mask) 466 { 467 unsigned int reg_val, channel_shift; 468 int bit_num; 469 470 /* Init all slots to 63 */ 471 switch (reg) { 472 case CS35L56_ASP1_FRAME_CONTROL1: 473 reg_val = 0x3f3f3f3f; 474 break; 475 case CS35L56_ASP1_FRAME_CONTROL5: 476 reg_val = 0x3f3f3f; 477 break; 478 } 479 480 /* Enable consecutive TX1..TXn for each of the slots set in mask */ 481 channel_shift = 0; 482 for_each_set_bit(bit_num, &mask, 32) { 483 reg_val &= ~(0x3f << channel_shift); 484 reg_val |= bit_num << channel_shift; 485 channel_shift += 8; 486 } 487 488 regmap_write(cs35l56->regmap, reg, reg_val); 489 } 490 491 static int cs35l56_asp_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 492 unsigned int rx_mask, int slots, int slot_width) 493 { 494 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 495 496 if ((slots == 0) || (slot_width == 0)) { 497 dev_dbg(cs35l56->dev, "tdm config cleared\n"); 498 cs35l56->asp_slot_width = 0; 499 cs35l56->asp_slot_count = 0; 500 return 0; 501 } 502 503 if (slot_width > (CS35L56_ASP_RX_WIDTH_MASK >> CS35L56_ASP_RX_WIDTH_SHIFT)) { 504 dev_err(cs35l56->dev, "tdm invalid slot width %d\n", slot_width); 505 return -EINVAL; 506 } 507 508 /* More than 32 slots would give an unsupportable BCLK frequency */ 509 if (slots > 32) { 510 dev_err(cs35l56->dev, "tdm invalid slot count %d\n", slots); 511 return -EINVAL; 512 } 513 514 cs35l56->asp_slot_width = (u8)slot_width; 515 cs35l56->asp_slot_count = (u8)slots; 516 517 // Note: rx/tx is from point of view of the CPU end 518 if (tx_mask == 0) 519 tx_mask = 0x3; // ASPRX1/RX2 in slots 0 and 1 520 521 if (rx_mask == 0) 522 rx_mask = 0xf; // ASPTX1..TX4 in slots 0..3 523 524 cs35l56_set_asp_slot_positions(cs35l56, CS35L56_ASP1_FRAME_CONTROL1, rx_mask); 525 cs35l56_set_asp_slot_positions(cs35l56, CS35L56_ASP1_FRAME_CONTROL5, tx_mask); 526 527 dev_dbg(cs35l56->dev, "tdm slot width: %u count: %u tx_mask: %#x rx_mask: %#x\n", 528 cs35l56->asp_slot_width, cs35l56->asp_slot_count, tx_mask, rx_mask); 529 530 return 0; 531 } 532 533 static int cs35l56_asp_dai_hw_params(struct snd_pcm_substream *substream, 534 struct snd_pcm_hw_params *params, 535 struct snd_soc_dai *dai) 536 { 537 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 538 unsigned int rate = params_rate(params); 539 u8 asp_width, asp_wl; 540 541 asp_wl = params_width(params); 542 if (cs35l56->asp_slot_width) 543 asp_width = cs35l56->asp_slot_width; 544 else 545 asp_width = asp_wl; 546 547 dev_dbg(cs35l56->dev, "%s: wl=%d, width=%d, rate=%d", __func__, asp_wl, asp_width, rate); 548 549 if (!cs35l56->sysclk_set) { 550 unsigned int slots = cs35l56->asp_slot_count; 551 unsigned int bclk_freq; 552 int freq_id; 553 554 if (slots == 0) { 555 slots = params_channels(params); 556 557 /* I2S always has an even number of slots */ 558 if (!cs35l56->tdm_mode) 559 slots = round_up(slots, 2); 560 } 561 562 bclk_freq = asp_width * slots * rate; 563 freq_id = cs35l56_get_bclk_freq_id(bclk_freq); 564 if (freq_id < 0) { 565 dev_err(cs35l56->dev, "%s: Invalid BCLK %u\n", __func__, bclk_freq); 566 return -EINVAL; 567 } 568 569 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL1, 570 CS35L56_ASP_BCLK_FREQ_MASK, 571 freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT); 572 } 573 574 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 575 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL2, 576 CS35L56_ASP_RX_WIDTH_MASK, asp_width << 577 CS35L56_ASP_RX_WIDTH_SHIFT); 578 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_DATA_CONTROL5, 579 CS35L56_ASP_RX_WL_MASK, asp_wl); 580 } else { 581 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL2, 582 CS35L56_ASP_TX_WIDTH_MASK, asp_width << 583 CS35L56_ASP_TX_WIDTH_SHIFT); 584 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_DATA_CONTROL1, 585 CS35L56_ASP_TX_WL_MASK, asp_wl); 586 } 587 588 return 0; 589 } 590 591 static int cs35l56_asp_dai_set_sysclk(struct snd_soc_dai *dai, 592 int clk_id, unsigned int freq, int dir) 593 { 594 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 595 int freq_id; 596 597 if (freq == 0) { 598 cs35l56->sysclk_set = false; 599 return 0; 600 } 601 602 freq_id = cs35l56_get_bclk_freq_id(freq); 603 if (freq_id < 0) 604 return freq_id; 605 606 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL1, 607 CS35L56_ASP_BCLK_FREQ_MASK, 608 freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT); 609 cs35l56->sysclk_set = true; 610 611 return 0; 612 } 613 614 static const struct snd_soc_dai_ops cs35l56_ops = { 615 .set_fmt = cs35l56_asp_dai_set_fmt, 616 .set_tdm_slot = cs35l56_asp_dai_set_tdm_slot, 617 .hw_params = cs35l56_asp_dai_hw_params, 618 .set_sysclk = cs35l56_asp_dai_set_sysclk, 619 }; 620 621 static void cs35l56_sdw_dai_shutdown(struct snd_pcm_substream *substream, 622 struct snd_soc_dai *dai) 623 { 624 snd_soc_dai_set_dma_data(dai, substream, NULL); 625 } 626 627 static int cs35l56_sdw_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 628 unsigned int rx_mask, int slots, int slot_width) 629 { 630 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 631 632 /* rx/tx are from point of view of the CPU end so opposite to our rx/tx */ 633 cs35l56->rx_mask = tx_mask; 634 cs35l56->tx_mask = rx_mask; 635 636 return 0; 637 } 638 639 static int cs35l56_sdw_dai_hw_params(struct snd_pcm_substream *substream, 640 struct snd_pcm_hw_params *params, 641 struct snd_soc_dai *dai) 642 { 643 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 644 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 645 struct sdw_stream_config sconfig; 646 struct sdw_port_config pconfig; 647 int ret; 648 649 dev_dbg(cs35l56->dev, "%s: rate %d\n", __func__, params_rate(params)); 650 651 if (!cs35l56->init_done) 652 return -ENODEV; 653 654 if (!sdw_stream) 655 return -EINVAL; 656 657 memset(&sconfig, 0, sizeof(sconfig)); 658 memset(&pconfig, 0, sizeof(pconfig)); 659 660 sconfig.frame_rate = params_rate(params); 661 sconfig.bps = snd_pcm_format_width(params_format(params)); 662 663 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 664 sconfig.direction = SDW_DATA_DIR_RX; 665 pconfig.num = CS35L56_SDW1_PLAYBACK_PORT; 666 pconfig.ch_mask = cs35l56->rx_mask; 667 } else { 668 sconfig.direction = SDW_DATA_DIR_TX; 669 pconfig.num = CS35L56_SDW1_CAPTURE_PORT; 670 pconfig.ch_mask = cs35l56->tx_mask; 671 } 672 673 if (pconfig.ch_mask == 0) { 674 sconfig.ch_count = params_channels(params); 675 pconfig.ch_mask = GENMASK(sconfig.ch_count - 1, 0); 676 } else { 677 sconfig.ch_count = hweight32(pconfig.ch_mask); 678 } 679 680 ret = sdw_stream_add_slave(cs35l56->sdw_peripheral, &sconfig, &pconfig, 681 1, sdw_stream); 682 if (ret) { 683 dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret); 684 return ret; 685 } 686 687 return 0; 688 } 689 690 static int cs35l56_sdw_dai_hw_free(struct snd_pcm_substream *substream, 691 struct snd_soc_dai *dai) 692 { 693 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 694 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 695 696 if (!cs35l56->sdw_peripheral) 697 return -EINVAL; 698 699 sdw_stream_remove_slave(cs35l56->sdw_peripheral, sdw_stream); 700 701 return 0; 702 } 703 704 static int cs35l56_sdw_dai_set_stream(struct snd_soc_dai *dai, 705 void *sdw_stream, int direction) 706 { 707 if (!sdw_stream) 708 return 0; 709 710 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 711 712 return 0; 713 } 714 715 static const struct snd_soc_dai_ops cs35l56_sdw_dai_ops = { 716 .set_tdm_slot = cs35l56_sdw_dai_set_tdm_slot, 717 .shutdown = cs35l56_sdw_dai_shutdown, 718 .hw_params = cs35l56_sdw_dai_hw_params, 719 .hw_free = cs35l56_sdw_dai_hw_free, 720 .set_stream = cs35l56_sdw_dai_set_stream, 721 }; 722 723 static struct snd_soc_dai_driver cs35l56_dai[] = { 724 { 725 .name = "cs35l56-asp1", 726 .id = 0, 727 .playback = { 728 .stream_name = "ASP1 Playback", 729 .channels_min = 1, 730 .channels_max = 2, 731 .rates = CS35L56_RATES, 732 .formats = CS35L56_RX_FORMATS, 733 }, 734 .capture = { 735 .stream_name = "ASP1 Capture", 736 .channels_min = 1, 737 .channels_max = 4, 738 .rates = CS35L56_RATES, 739 .formats = CS35L56_TX_FORMATS, 740 }, 741 .ops = &cs35l56_ops, 742 .symmetric_rate = 1, 743 .symmetric_sample_bits = 1, 744 }, 745 { 746 .name = "cs35l56-sdw1", 747 .id = 1, 748 .playback = { 749 .stream_name = "SDW1 Playback", 750 .channels_min = 1, 751 .channels_max = 2, 752 .rates = CS35L56_RATES, 753 .formats = CS35L56_RX_FORMATS, 754 }, 755 .capture = { 756 .stream_name = "SDW1 Capture", 757 .channels_min = 1, 758 .channels_max = 4, 759 .rates = CS35L56_RATES, 760 .formats = CS35L56_TX_FORMATS, 761 }, 762 .symmetric_rate = 1, 763 .ops = &cs35l56_sdw_dai_ops, 764 } 765 }; 766 767 static int cs35l56_wait_for_firmware_boot(struct cs35l56_private *cs35l56) 768 { 769 unsigned int reg; 770 unsigned int val; 771 int ret; 772 773 if (cs35l56->rev < CS35L56_REVID_B0) 774 reg = CS35L56_DSP1_HALO_STATE_A1; 775 else 776 reg = CS35L56_DSP1_HALO_STATE; 777 778 ret = regmap_read_poll_timeout(cs35l56->regmap, reg, 779 val, 780 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 781 CS35L56_HALO_STATE_POLL_US, 782 CS35L56_HALO_STATE_TIMEOUT_US); 783 784 if ((ret < 0) && (ret != -ETIMEDOUT)) { 785 dev_err(cs35l56->dev, "Failed to read HALO_STATE: %d\n", ret); 786 return ret; 787 } 788 789 if ((ret == -ETIMEDOUT) || (val != CS35L56_HALO_STATE_BOOT_DONE)) { 790 dev_err(cs35l56->dev, "Firmware boot fail: HALO_STATE=%#x\n", val); 791 return -EIO; 792 } 793 794 return 0; 795 } 796 797 static inline void cs35l56_wait_min_reset_pulse(void) 798 { 799 /* Satisfy minimum reset pulse width spec */ 800 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 801 } 802 803 static const struct reg_sequence cs35l56_system_reset_seq[] = { 804 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 805 }; 806 807 static void cs35l56_system_reset(struct cs35l56_private *cs35l56) 808 { 809 cs35l56->soft_resetting = true; 810 811 /* 812 * Must enter cache-only first so there can't be any more register 813 * accesses other than the controlled system reset sequence below. 814 */ 815 regcache_cache_only(cs35l56->regmap, true); 816 regmap_multi_reg_write_bypassed(cs35l56->regmap, 817 cs35l56_system_reset_seq, 818 ARRAY_SIZE(cs35l56_system_reset_seq)); 819 820 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 821 if (cs35l56->sdw_peripheral) 822 return; 823 824 usleep_range(CS35L56_CONTROL_PORT_READY_US, CS35L56_CONTROL_PORT_READY_US + 400); 825 regcache_cache_only(cs35l56->regmap, false); 826 } 827 828 static void cs35l56_secure_patch(struct cs35l56_private *cs35l56) 829 { 830 int ret; 831 832 /* Use wm_adsp to load and apply the firmware patch and coefficient files */ 833 ret = wm_adsp_power_up(&cs35l56->dsp); 834 if (ret) 835 dev_dbg(cs35l56->dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret); 836 else 837 cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_AUDIO_REINIT); 838 } 839 840 static void cs35l56_patch(struct cs35l56_private *cs35l56) 841 { 842 unsigned int reg; 843 unsigned int val; 844 int ret; 845 846 /* 847 * Disable SoundWire interrupts to prevent race with IRQ work. 848 * Setting sdw_irq_no_unmask prevents the handler re-enabling 849 * the SoundWire interrupt. 850 */ 851 if (cs35l56->sdw_peripheral) { 852 cs35l56->sdw_irq_no_unmask = true; 853 cancel_work_sync(&cs35l56->sdw_irq_work); 854 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0); 855 sdw_read_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1); 856 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF); 857 } 858 859 ret = cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_SHUTDOWN); 860 if (ret) 861 goto err; 862 863 if (cs35l56->rev < CS35L56_REVID_B0) 864 reg = CS35L56_DSP1_PM_CUR_STATE_A1; 865 else 866 reg = CS35L56_DSP1_PM_CUR_STATE; 867 868 ret = regmap_read_poll_timeout(cs35l56->regmap, reg, 869 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 870 CS35L56_HALO_STATE_POLL_US, 871 CS35L56_HALO_STATE_TIMEOUT_US); 872 if (ret < 0) 873 dev_err(cs35l56->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 874 val, ret); 875 876 /* Use wm_adsp to load and apply the firmware patch and coefficient files */ 877 ret = wm_adsp_power_up(&cs35l56->dsp); 878 if (ret) { 879 dev_dbg(cs35l56->dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret); 880 goto err; 881 } 882 883 mutex_lock(&cs35l56->irq_lock); 884 885 init_completion(&cs35l56->init_completion); 886 887 cs35l56_system_reset(cs35l56); 888 889 if (cs35l56->sdw_peripheral) { 890 /* 891 * The system-reset causes the CS35L56 to detach from the bus. 892 * Wait for the manager to re-enumerate the CS35L56 and 893 * cs35l56_init() to run again. 894 */ 895 if (!wait_for_completion_timeout(&cs35l56->init_completion, 896 msecs_to_jiffies(5000))) { 897 dev_err(cs35l56->dev, "%s: init_completion timed out (SDW)\n", __func__); 898 goto err_unlock; 899 } 900 } else if (cs35l56_init(cs35l56)) { 901 goto err_unlock; 902 } 903 904 regmap_clear_bits(cs35l56->regmap, CS35L56_PROTECTION_STATUS, CS35L56_FIRMWARE_MISSING); 905 cs35l56->fw_patched = true; 906 907 err_unlock: 908 mutex_unlock(&cs35l56->irq_lock); 909 err: 910 /* Re-enable SoundWire interrupts */ 911 if (cs35l56->sdw_peripheral) { 912 cs35l56->sdw_irq_no_unmask = false; 913 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 914 CS35L56_SDW_INT_MASK_CODEC_IRQ); 915 } 916 } 917 918 static void cs35l56_dsp_work(struct work_struct *work) 919 { 920 struct cs35l56_private *cs35l56 = container_of(work, 921 struct cs35l56_private, 922 dsp_work); 923 924 if (!cs35l56->init_done) 925 return; 926 927 pm_runtime_get_sync(cs35l56->dev); 928 929 /* 930 * When the device is running in secure mode the firmware files can 931 * only contain insecure tunings and therefore we do not need to 932 * shutdown the firmware to apply them and can use the lower cost 933 * reinit sequence instead. 934 */ 935 if (cs35l56->secured) 936 cs35l56_secure_patch(cs35l56); 937 else 938 cs35l56_patch(cs35l56); 939 940 pm_runtime_mark_last_busy(cs35l56->dev); 941 pm_runtime_put_autosuspend(cs35l56->dev); 942 } 943 944 static int cs35l56_component_probe(struct snd_soc_component *component) 945 { 946 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 947 struct dentry *debugfs_root = component->debugfs_root; 948 949 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_tx_input_texts) != ARRAY_SIZE(cs35l56_tx_input_values)); 950 951 if (!wait_for_completion_timeout(&cs35l56->init_completion, 952 msecs_to_jiffies(5000))) { 953 dev_err(cs35l56->dev, "%s: init_completion timed out\n", __func__); 954 return -ENODEV; 955 } 956 957 cs35l56->component = component; 958 wm_adsp2_component_probe(&cs35l56->dsp, component); 959 960 debugfs_create_bool("init_done", 0444, debugfs_root, &cs35l56->init_done); 961 debugfs_create_bool("can_hibernate", 0444, debugfs_root, &cs35l56->can_hibernate); 962 debugfs_create_bool("fw_patched", 0444, debugfs_root, &cs35l56->fw_patched); 963 964 queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work); 965 966 return 0; 967 } 968 969 static void cs35l56_component_remove(struct snd_soc_component *component) 970 { 971 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 972 973 cancel_work_sync(&cs35l56->dsp_work); 974 } 975 976 static int cs35l56_set_bias_level(struct snd_soc_component *component, 977 enum snd_soc_bias_level level) 978 { 979 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 980 981 switch (level) { 982 case SND_SOC_BIAS_STANDBY: 983 /* 984 * Wait for patching to complete when transitioning from 985 * BIAS_OFF to BIAS_STANDBY 986 */ 987 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 988 cs35l56_wait_dsp_ready(cs35l56); 989 990 break; 991 default: 992 break; 993 } 994 995 return 0; 996 } 997 998 static const struct snd_soc_component_driver soc_component_dev_cs35l56 = { 999 .probe = cs35l56_component_probe, 1000 .remove = cs35l56_component_remove, 1001 1002 .dapm_widgets = cs35l56_dapm_widgets, 1003 .num_dapm_widgets = ARRAY_SIZE(cs35l56_dapm_widgets), 1004 .dapm_routes = cs35l56_audio_map, 1005 .num_dapm_routes = ARRAY_SIZE(cs35l56_audio_map), 1006 .controls = cs35l56_controls, 1007 .num_controls = ARRAY_SIZE(cs35l56_controls), 1008 1009 .set_bias_level = cs35l56_set_bias_level, 1010 1011 .suspend_bias_off = 1, /* see cs35l56_system_resume() */ 1012 }; 1013 1014 static const struct reg_sequence cs35l56_hibernate_seq[] = { 1015 /* This must be the last register access */ 1016 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_HIBERNATE_NOW), 1017 }; 1018 1019 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = { 1020 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP), 1021 }; 1022 1023 int cs35l56_runtime_suspend(struct device *dev) 1024 { 1025 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1026 unsigned int val; 1027 int ret; 1028 1029 if (!cs35l56->init_done) 1030 return 0; 1031 1032 /* Firmware must have entered a power-save state */ 1033 ret = regmap_read_poll_timeout(cs35l56->regmap, 1034 CS35L56_TRANSDUCER_ACTUAL_PS, 1035 val, (val >= CS35L56_PS3), 1036 CS35L56_PS3_POLL_US, 1037 CS35L56_PS3_TIMEOUT_US); 1038 if (ret) 1039 dev_warn(cs35l56->dev, "PS3 wait failed: %d\n", ret); 1040 1041 /* Clear BOOT_DONE so it can be used to detect a reboot */ 1042 regmap_write(cs35l56->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 1043 1044 if (!cs35l56->can_hibernate) { 1045 regcache_cache_only(cs35l56->regmap, true); 1046 dev_dbg(dev, "Suspended: no hibernate"); 1047 1048 return 0; 1049 } 1050 1051 /* 1052 * Enable auto-hibernate. If it is woken by some other wake source 1053 * it will automatically return to hibernate. 1054 */ 1055 cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE); 1056 1057 /* 1058 * Must enter cache-only first so there can't be any more register 1059 * accesses other than the controlled hibernate sequence below. 1060 */ 1061 regcache_cache_only(cs35l56->regmap, true); 1062 1063 regmap_multi_reg_write_bypassed(cs35l56->regmap, 1064 cs35l56_hibernate_seq, 1065 ARRAY_SIZE(cs35l56_hibernate_seq)); 1066 1067 dev_dbg(dev, "Suspended: hibernate"); 1068 1069 return 0; 1070 } 1071 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend, SND_SOC_CS35L56_CORE); 1072 1073 static int __maybe_unused cs35l56_runtime_resume_i2c_spi(struct device *dev) 1074 { 1075 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1076 1077 if (!cs35l56->init_done) 1078 return 0; 1079 1080 return cs35l56_runtime_resume_common(cs35l56); 1081 } 1082 1083 int cs35l56_runtime_resume_common(struct cs35l56_private *cs35l56) 1084 { 1085 unsigned int val; 1086 int ret; 1087 1088 if (!cs35l56->can_hibernate) 1089 goto out_sync; 1090 1091 if (!cs35l56->sdw_peripheral) { 1092 /* 1093 * Dummy transaction to trigger I2C/SPI auto-wake. This will NAK on I2C. 1094 * Must be done before releasing cache-only. 1095 */ 1096 regmap_multi_reg_write_bypassed(cs35l56->regmap, 1097 cs35l56_hibernate_wake_seq, 1098 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 1099 1100 usleep_range(CS35L56_CONTROL_PORT_READY_US, 1101 CS35L56_CONTROL_PORT_READY_US + 400); 1102 } 1103 1104 out_sync: 1105 regcache_cache_only(cs35l56->regmap, false); 1106 1107 ret = cs35l56_wait_for_firmware_boot(cs35l56); 1108 if (ret) { 1109 dev_err(cs35l56->dev, "Hibernate wake failed: %d\n", ret); 1110 goto err; 1111 } 1112 1113 ret = cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 1114 if (ret) 1115 goto err; 1116 1117 /* BOOT_DONE will be 1 if the amp reset */ 1118 regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_4, &val); 1119 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 1120 dev_dbg(cs35l56->dev, "Registers reset in suspend\n"); 1121 regcache_mark_dirty(cs35l56->regmap); 1122 } 1123 1124 regcache_sync(cs35l56->regmap); 1125 1126 dev_dbg(cs35l56->dev, "Resumed"); 1127 1128 return 0; 1129 1130 err: 1131 regmap_write(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 1132 CS35L56_MBOX_CMD_HIBERNATE_NOW); 1133 1134 regcache_cache_only(cs35l56->regmap, true); 1135 1136 return ret; 1137 } 1138 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_CORE); 1139 1140 static int cs35l56_is_fw_reload_needed(struct cs35l56_private *cs35l56) 1141 { 1142 unsigned int val; 1143 int ret; 1144 1145 /* Nothing to re-patch if we haven't done any patching yet. */ 1146 if (!cs35l56->fw_patched) 1147 return false; 1148 1149 /* 1150 * If we have control of RESET we will have asserted it so the firmware 1151 * will need re-patching. 1152 */ 1153 if (cs35l56->reset_gpio) 1154 return true; 1155 1156 /* 1157 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 1158 * can't be used here to test for memory retention. 1159 * Assume that tuning must be re-loaded. 1160 */ 1161 if (cs35l56->secured) 1162 return true; 1163 1164 ret = pm_runtime_resume_and_get(cs35l56->dev); 1165 if (ret) { 1166 dev_err(cs35l56->dev, "Failed to runtime_get: %d\n", ret); 1167 return ret; 1168 } 1169 1170 ret = regmap_read(cs35l56->regmap, CS35L56_PROTECTION_STATUS, &val); 1171 if (ret) 1172 dev_err(cs35l56->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 1173 else 1174 ret = !!(val & CS35L56_FIRMWARE_MISSING); 1175 1176 pm_runtime_put_autosuspend(cs35l56->dev); 1177 1178 return ret; 1179 } 1180 1181 int cs35l56_system_suspend(struct device *dev) 1182 { 1183 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1184 1185 dev_dbg(dev, "system_suspend\n"); 1186 1187 if (cs35l56->component) 1188 flush_work(&cs35l56->dsp_work); 1189 1190 /* 1191 * The interrupt line is normally shared, but after we start suspending 1192 * we can't check if our device is the source of an interrupt, and can't 1193 * clear it. Prevent this race by temporarily disabling the parent irq 1194 * until we reach _no_irq. 1195 */ 1196 if (cs35l56->irq) 1197 disable_irq(cs35l56->irq); 1198 1199 return pm_runtime_force_suspend(dev); 1200 } 1201 EXPORT_SYMBOL_GPL(cs35l56_system_suspend); 1202 1203 int cs35l56_system_suspend_late(struct device *dev) 1204 { 1205 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1206 1207 dev_dbg(dev, "system_suspend_late\n"); 1208 1209 /* 1210 * Assert RESET before removing supplies. 1211 * RESET is usually shared by all amps so it must not be asserted until 1212 * all driver instances have done their suspend() stage. 1213 */ 1214 if (cs35l56->reset_gpio) { 1215 gpiod_set_value_cansleep(cs35l56->reset_gpio, 0); 1216 cs35l56_wait_min_reset_pulse(); 1217 } 1218 1219 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1220 1221 return 0; 1222 } 1223 EXPORT_SYMBOL_GPL(cs35l56_system_suspend_late); 1224 1225 int cs35l56_system_suspend_no_irq(struct device *dev) 1226 { 1227 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1228 1229 dev_dbg(dev, "system_suspend_no_irq\n"); 1230 1231 /* Handlers are now disabled so the parent IRQ can safely be re-enabled. */ 1232 if (cs35l56->irq) 1233 enable_irq(cs35l56->irq); 1234 1235 return 0; 1236 } 1237 EXPORT_SYMBOL_GPL(cs35l56_system_suspend_no_irq); 1238 1239 int cs35l56_system_resume_no_irq(struct device *dev) 1240 { 1241 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1242 1243 dev_dbg(dev, "system_resume_no_irq\n"); 1244 1245 /* 1246 * WAKE interrupts unmask if the CS35L56 hibernates, which can cause 1247 * spurious interrupts, and the interrupt line is normally shared. 1248 * We can't check if our device is the source of an interrupt, and can't 1249 * clear it, until it has fully resumed. Prevent this race by temporarily 1250 * disabling the parent irq until we complete resume(). 1251 */ 1252 if (cs35l56->irq) 1253 disable_irq(cs35l56->irq); 1254 1255 return 0; 1256 } 1257 EXPORT_SYMBOL_GPL(cs35l56_system_resume_no_irq); 1258 1259 int cs35l56_system_resume_early(struct device *dev) 1260 { 1261 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1262 int ret; 1263 1264 dev_dbg(dev, "system_resume_early\n"); 1265 1266 /* Ensure a spec-compliant RESET pulse. */ 1267 if (cs35l56->reset_gpio) { 1268 gpiod_set_value_cansleep(cs35l56->reset_gpio, 0); 1269 cs35l56_wait_min_reset_pulse(); 1270 } 1271 1272 /* Enable supplies before releasing RESET. */ 1273 ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1274 if (ret) { 1275 dev_err(dev, "system_resume_early failed to enable supplies: %d\n", ret); 1276 return ret; 1277 } 1278 1279 /* Release shared RESET before drivers start resume(). */ 1280 gpiod_set_value_cansleep(cs35l56->reset_gpio, 1); 1281 1282 return 0; 1283 } 1284 EXPORT_SYMBOL_GPL(cs35l56_system_resume_early); 1285 1286 int cs35l56_system_resume(struct device *dev) 1287 { 1288 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 1289 int ret; 1290 1291 dev_dbg(dev, "system_resume\n"); 1292 1293 /* Undo pm_runtime_force_suspend() before re-enabling the irq */ 1294 ret = pm_runtime_force_resume(dev); 1295 if (cs35l56->irq) 1296 enable_irq(cs35l56->irq); 1297 1298 if (ret) 1299 return ret; 1300 1301 /* Firmware won't have been loaded if the component hasn't probed */ 1302 if (!cs35l56->component) 1303 return 0; 1304 1305 ret = cs35l56_is_fw_reload_needed(cs35l56); 1306 dev_dbg(cs35l56->dev, "fw_reload_needed: %d\n", ret); 1307 if (ret < 1) 1308 return ret; 1309 1310 cs35l56->fw_patched = false; 1311 queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work); 1312 1313 /* 1314 * suspend_bias_off ensures we are now in BIAS_OFF so there will be 1315 * a BIAS_OFF->BIAS_STANDBY transition to complete dsp patching. 1316 */ 1317 1318 return 0; 1319 } 1320 EXPORT_SYMBOL_GPL(cs35l56_system_resume); 1321 1322 static int cs35l56_dsp_init(struct cs35l56_private *cs35l56) 1323 { 1324 struct wm_adsp *dsp; 1325 int ret; 1326 1327 cs35l56->dsp_wq = create_singlethread_workqueue("cs35l56-dsp"); 1328 if (!cs35l56->dsp_wq) 1329 return -ENOMEM; 1330 1331 INIT_WORK(&cs35l56->dsp_work, cs35l56_dsp_work); 1332 1333 dsp = &cs35l56->dsp; 1334 dsp->part = "cs35l56"; 1335 dsp->cs_dsp.num = 1; 1336 dsp->cs_dsp.type = WMFW_HALO; 1337 dsp->cs_dsp.rev = 0; 1338 dsp->fw = 12; 1339 dsp->cs_dsp.dev = cs35l56->dev; 1340 dsp->cs_dsp.regmap = cs35l56->regmap; 1341 dsp->cs_dsp.base = CS35L56_DSP1_CORE_BASE; 1342 dsp->cs_dsp.base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 1343 dsp->cs_dsp.mem = cs35l56_dsp1_regions; 1344 dsp->cs_dsp.num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 1345 dsp->cs_dsp.no_core_startstop = true; 1346 dsp->wmfw_optional = true; 1347 1348 dev_dbg(cs35l56->dev, "DSP system name: '%s'\n", dsp->system_name); 1349 1350 ret = wm_halo_init(dsp); 1351 if (ret != 0) { 1352 dev_err(cs35l56->dev, "wm_halo_init failed\n"); 1353 return ret; 1354 } 1355 1356 return 0; 1357 } 1358 1359 static int cs35l56_acpi_get_name(struct cs35l56_private *cs35l56) 1360 { 1361 acpi_handle handle = ACPI_HANDLE(cs35l56->dev); 1362 const char *sub; 1363 1364 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */ 1365 if (!handle) 1366 return 0; 1367 1368 sub = acpi_get_subsystem_id(handle); 1369 if (IS_ERR(sub)) { 1370 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */ 1371 if (PTR_ERR(sub) == -ENODATA) 1372 return 0; 1373 else 1374 return PTR_ERR(sub); 1375 } 1376 1377 cs35l56->dsp.system_name = sub; 1378 dev_dbg(cs35l56->dev, "Subsystem ID: %s\n", cs35l56->dsp.system_name); 1379 1380 return 0; 1381 } 1382 1383 int cs35l56_common_probe(struct cs35l56_private *cs35l56) 1384 { 1385 int ret; 1386 1387 init_completion(&cs35l56->init_completion); 1388 mutex_init(&cs35l56->irq_lock); 1389 1390 dev_set_drvdata(cs35l56->dev, cs35l56); 1391 1392 cs35l56_fill_supply_names(cs35l56->supplies); 1393 ret = devm_regulator_bulk_get(cs35l56->dev, ARRAY_SIZE(cs35l56->supplies), 1394 cs35l56->supplies); 1395 if (ret != 0) 1396 return dev_err_probe(cs35l56->dev, ret, "Failed to request supplies\n"); 1397 1398 /* Reset could be controlled by the BIOS or shared by multiple amps */ 1399 cs35l56->reset_gpio = devm_gpiod_get_optional(cs35l56->dev, "reset", GPIOD_OUT_LOW); 1400 if (IS_ERR(cs35l56->reset_gpio)) { 1401 ret = PTR_ERR(cs35l56->reset_gpio); 1402 /* 1403 * If RESET is shared the first amp to probe will grab the reset 1404 * line and reset all the amps 1405 */ 1406 if (ret != -EBUSY) 1407 return dev_err_probe(cs35l56->dev, ret, "Failed to get reset GPIO\n"); 1408 1409 dev_info(cs35l56->dev, "Reset GPIO busy, assume shared reset\n"); 1410 cs35l56->reset_gpio = NULL; 1411 } 1412 1413 ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1414 if (ret != 0) 1415 return dev_err_probe(cs35l56->dev, ret, "Failed to enable supplies\n"); 1416 1417 if (cs35l56->reset_gpio) { 1418 cs35l56_wait_min_reset_pulse(); 1419 gpiod_set_value_cansleep(cs35l56->reset_gpio, 1); 1420 } 1421 1422 ret = cs35l56_acpi_get_name(cs35l56); 1423 if (ret != 0) 1424 goto err; 1425 1426 ret = cs35l56_dsp_init(cs35l56); 1427 if (ret < 0) { 1428 dev_err_probe(cs35l56->dev, ret, "DSP init failed\n"); 1429 goto err; 1430 } 1431 1432 ret = devm_snd_soc_register_component(cs35l56->dev, 1433 &soc_component_dev_cs35l56, 1434 cs35l56_dai, ARRAY_SIZE(cs35l56_dai)); 1435 if (ret < 0) { 1436 dev_err_probe(cs35l56->dev, ret, "Register codec failed\n"); 1437 goto err; 1438 } 1439 1440 return 0; 1441 1442 err: 1443 gpiod_set_value_cansleep(cs35l56->reset_gpio, 0); 1444 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1445 1446 return ret; 1447 } 1448 EXPORT_SYMBOL_NS_GPL(cs35l56_common_probe, SND_SOC_CS35L56_CORE); 1449 1450 int cs35l56_init(struct cs35l56_private *cs35l56) 1451 { 1452 int ret; 1453 unsigned int devid, revid, otpid, secured; 1454 1455 /* 1456 * Check whether the actions associated with soft reset or one time 1457 * init need to be performed. 1458 */ 1459 if (cs35l56->soft_resetting) 1460 goto post_soft_reset; 1461 1462 if (cs35l56->init_done) 1463 return 0; 1464 1465 pm_runtime_set_autosuspend_delay(cs35l56->dev, 100); 1466 pm_runtime_use_autosuspend(cs35l56->dev); 1467 pm_runtime_set_active(cs35l56->dev); 1468 pm_runtime_enable(cs35l56->dev); 1469 1470 /* 1471 * If the system is not using a reset_gpio then issue a 1472 * dummy read to force a wakeup. 1473 */ 1474 if (!cs35l56->reset_gpio) 1475 regmap_read(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, &devid); 1476 1477 /* Wait for control port to be ready (datasheet tIRS). */ 1478 usleep_range(CS35L56_CONTROL_PORT_READY_US, 1479 CS35L56_CONTROL_PORT_READY_US + 400); 1480 1481 /* 1482 * The HALO_STATE register is in different locations on Ax and B0 1483 * devices so the REVID needs to be determined before waiting for the 1484 * firmware to boot. 1485 */ 1486 ret = regmap_read(cs35l56->regmap, CS35L56_REVID, &revid); 1487 if (ret < 0) { 1488 dev_err(cs35l56->dev, "Get Revision ID failed\n"); 1489 return ret; 1490 } 1491 cs35l56->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 1492 1493 ret = cs35l56_wait_for_firmware_boot(cs35l56); 1494 if (ret) 1495 return ret; 1496 1497 ret = regmap_read(cs35l56->regmap, CS35L56_DEVID, &devid); 1498 if (ret < 0) { 1499 dev_err(cs35l56->dev, "Get Device ID failed\n"); 1500 return ret; 1501 } 1502 devid &= CS35L56_DEVID_MASK; 1503 1504 switch (devid) { 1505 case 0x35A56: 1506 break; 1507 default: 1508 dev_err(cs35l56->dev, "Unknown device %x\n", devid); 1509 return ret; 1510 } 1511 1512 ret = regmap_read(cs35l56->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 1513 if (ret) { 1514 dev_err(cs35l56->dev, "Get Secure status failed\n"); 1515 return ret; 1516 } 1517 1518 /* When any bus is restricted treat the device as secured */ 1519 if (secured & CS35L56_RESTRICTED_MASK) 1520 cs35l56->secured = true; 1521 1522 ret = regmap_read(cs35l56->regmap, CS35L56_OTPID, &otpid); 1523 if (ret < 0) { 1524 dev_err(cs35l56->dev, "Get OTP ID failed\n"); 1525 return ret; 1526 } 1527 1528 dev_info(cs35l56->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d\n", 1529 cs35l56->secured ? "s" : "", cs35l56->rev, otpid); 1530 1531 /* Populate the DSP information with the revision and security state */ 1532 cs35l56->dsp.part = devm_kasprintf(cs35l56->dev, GFP_KERNEL, "cs35l56%s-%02x", 1533 cs35l56->secured ? "s" : "", cs35l56->rev); 1534 if (!cs35l56->dsp.part) 1535 return -ENOMEM; 1536 1537 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 1538 regmap_write(cs35l56->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 1539 regmap_update_bits(cs35l56->regmap, CS35L56_IRQ1_MASK_1, 1540 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 1541 0); 1542 regmap_update_bits(cs35l56->regmap, CS35L56_IRQ1_MASK_8, 1543 CS35L56_TEMP_ERR_EINT1_MASK, 1544 0); 1545 1546 if (!cs35l56->reset_gpio) { 1547 dev_dbg(cs35l56->dev, "No reset gpio: using soft reset\n"); 1548 cs35l56_system_reset(cs35l56); 1549 if (cs35l56->sdw_peripheral) { 1550 /* Keep alive while we wait for re-enumeration */ 1551 pm_runtime_get_noresume(cs35l56->dev); 1552 return 0; 1553 } 1554 } 1555 1556 post_soft_reset: 1557 if (cs35l56->soft_resetting) { 1558 cs35l56->soft_resetting = false; 1559 1560 /* Done re-enumerating after one-time init so release the keep-alive */ 1561 if (cs35l56->sdw_peripheral && !cs35l56->init_done) 1562 pm_runtime_put_noidle(cs35l56->dev); 1563 1564 regcache_mark_dirty(cs35l56->regmap); 1565 ret = cs35l56_wait_for_firmware_boot(cs35l56); 1566 if (ret) 1567 return ret; 1568 1569 dev_dbg(cs35l56->dev, "Firmware rebooted after soft reset\n"); 1570 } 1571 1572 /* Disable auto-hibernate so that runtime_pm has control */ 1573 ret = cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 1574 if (ret) 1575 return ret; 1576 1577 /* Populate soft registers in the regmap cache */ 1578 cs35l56_reread_firmware_registers(cs35l56->dev, cs35l56->regmap); 1579 1580 /* Registers could be dirty after soft reset or SoundWire enumeration */ 1581 regcache_sync(cs35l56->regmap); 1582 1583 cs35l56->init_done = true; 1584 complete(&cs35l56->init_completion); 1585 1586 return 0; 1587 } 1588 EXPORT_SYMBOL_NS_GPL(cs35l56_init, SND_SOC_CS35L56_CORE); 1589 1590 void cs35l56_remove(struct cs35l56_private *cs35l56) 1591 { 1592 cs35l56->init_done = false; 1593 1594 /* 1595 * WAKE IRQs unmask if CS35L56 hibernates so free the handler to 1596 * prevent it racing with remove(). 1597 */ 1598 if (cs35l56->irq) 1599 devm_free_irq(cs35l56->dev, cs35l56->irq, cs35l56); 1600 1601 flush_workqueue(cs35l56->dsp_wq); 1602 destroy_workqueue(cs35l56->dsp_wq); 1603 1604 pm_runtime_suspend(cs35l56->dev); 1605 pm_runtime_disable(cs35l56->dev); 1606 1607 regcache_cache_only(cs35l56->regmap, true); 1608 1609 kfree(cs35l56->dsp.system_name); 1610 1611 gpiod_set_value_cansleep(cs35l56->reset_gpio, 0); 1612 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1613 } 1614 EXPORT_SYMBOL_NS_GPL(cs35l56_remove, SND_SOC_CS35L56_CORE); 1615 1616 const struct dev_pm_ops cs35l56_pm_ops_i2c_spi = { 1617 SET_RUNTIME_PM_OPS(cs35l56_runtime_suspend, cs35l56_runtime_resume_i2c_spi, NULL) 1618 SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend, cs35l56_system_resume) 1619 LATE_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_late, cs35l56_system_resume_early) 1620 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_no_irq, cs35l56_system_resume_no_irq) 1621 }; 1622 EXPORT_SYMBOL_NS_GPL(cs35l56_pm_ops_i2c_spi, SND_SOC_CS35L56_CORE); 1623 1624 MODULE_DESCRIPTION("ASoC CS35L56 driver"); 1625 MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED); 1626 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1627 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1628 MODULE_LICENSE("GPL"); 1629