1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/regmap.h> 9 #include <linux/regulator/consumer.h> 10 #include <linux/types.h> 11 12 #include "cs35l56.h" 13 14 static const struct reg_sequence cs35l56_patch[] = { 15 /* These are not reset by a soft-reset, so patch to defaults. */ 16 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 17 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 18 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 19 }; 20 21 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 22 { 23 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 24 ARRAY_SIZE(cs35l56_patch)); 25 } 26 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED); 27 28 static const struct reg_default cs35l56_reg_defaults[] = { 29 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 30 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 31 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 32 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 33 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 34 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 35 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 36 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 37 { CS35L56_ASP1TX1_INPUT, 0x00000018 }, 38 { CS35L56_ASP1TX2_INPUT, 0x00000019 }, 39 { CS35L56_ASP1TX3_INPUT, 0x00000020 }, 40 { CS35L56_ASP1TX4_INPUT, 0x00000028 }, 41 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 42 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 43 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 44 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 45 { CS35L56_IRQ1_CFG, 0x00000000 }, 46 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 47 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 48 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 49 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 50 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 51 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 52 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 53 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 54 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 55 }; 56 57 static bool cs35l56_is_dsp_memory(unsigned int reg) 58 { 59 switch (reg) { 60 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 61 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 62 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 63 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 64 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 65 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 66 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 67 return true; 68 default: 69 return false; 70 } 71 } 72 73 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 74 { 75 switch (reg) { 76 case CS35L56_DEVID: 77 case CS35L56_REVID: 78 case CS35L56_RELID: 79 case CS35L56_OTPID: 80 case CS35L56_SFT_RESET: 81 case CS35L56_GLOBAL_ENABLES: 82 case CS35L56_BLOCK_ENABLES: 83 case CS35L56_BLOCK_ENABLES2: 84 case CS35L56_REFCLK_INPUT: 85 case CS35L56_GLOBAL_SAMPLE_RATE: 86 case CS35L56_ASP1_ENABLES1: 87 case CS35L56_ASP1_CONTROL1: 88 case CS35L56_ASP1_CONTROL2: 89 case CS35L56_ASP1_CONTROL3: 90 case CS35L56_ASP1_FRAME_CONTROL1: 91 case CS35L56_ASP1_FRAME_CONTROL5: 92 case CS35L56_ASP1_DATA_CONTROL1: 93 case CS35L56_ASP1_DATA_CONTROL5: 94 case CS35L56_DACPCM1_INPUT: 95 case CS35L56_DACPCM2_INPUT: 96 case CS35L56_ASP1TX1_INPUT: 97 case CS35L56_ASP1TX2_INPUT: 98 case CS35L56_ASP1TX3_INPUT: 99 case CS35L56_ASP1TX4_INPUT: 100 case CS35L56_DSP1RX1_INPUT: 101 case CS35L56_DSP1RX2_INPUT: 102 case CS35L56_SWIRE_DP3_CH1_INPUT: 103 case CS35L56_SWIRE_DP3_CH2_INPUT: 104 case CS35L56_SWIRE_DP3_CH3_INPUT: 105 case CS35L56_SWIRE_DP3_CH4_INPUT: 106 case CS35L56_IRQ1_CFG: 107 case CS35L56_IRQ1_STATUS: 108 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 109 case CS35L56_IRQ1_EINT_18: 110 case CS35L56_IRQ1_EINT_20: 111 case CS35L56_IRQ1_MASK_1: 112 case CS35L56_IRQ1_MASK_2: 113 case CS35L56_IRQ1_MASK_4: 114 case CS35L56_IRQ1_MASK_8: 115 case CS35L56_IRQ1_MASK_18: 116 case CS35L56_IRQ1_MASK_20: 117 case CS35L56_DSP_VIRTUAL1_MBOX_1: 118 case CS35L56_DSP_VIRTUAL1_MBOX_2: 119 case CS35L56_DSP_VIRTUAL1_MBOX_3: 120 case CS35L56_DSP_VIRTUAL1_MBOX_4: 121 case CS35L56_DSP_VIRTUAL1_MBOX_5: 122 case CS35L56_DSP_VIRTUAL1_MBOX_6: 123 case CS35L56_DSP_VIRTUAL1_MBOX_7: 124 case CS35L56_DSP_VIRTUAL1_MBOX_8: 125 case CS35L56_DSP_RESTRICT_STS1: 126 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 127 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 128 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 129 case CS35L56_DSP1_SCRATCH1: 130 case CS35L56_DSP1_SCRATCH2: 131 case CS35L56_DSP1_SCRATCH3: 132 case CS35L56_DSP1_SCRATCH4: 133 return true; 134 default: 135 return cs35l56_is_dsp_memory(reg); 136 } 137 } 138 139 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 140 { 141 switch (reg) { 142 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 143 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 144 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 145 return true; 146 default: 147 return false; 148 } 149 } 150 151 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 152 { 153 switch (reg) { 154 case CS35L56_DEVID: 155 case CS35L56_REVID: 156 case CS35L56_RELID: 157 case CS35L56_OTPID: 158 case CS35L56_SFT_RESET: 159 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 160 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 161 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 162 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 163 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 164 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 165 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 166 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 167 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 168 case CS35L56_IRQ1_STATUS: 169 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 170 case CS35L56_IRQ1_EINT_18: 171 case CS35L56_IRQ1_EINT_20: 172 case CS35L56_DSP_VIRTUAL1_MBOX_1: 173 case CS35L56_DSP_VIRTUAL1_MBOX_2: 174 case CS35L56_DSP_VIRTUAL1_MBOX_3: 175 case CS35L56_DSP_VIRTUAL1_MBOX_4: 176 case CS35L56_DSP_VIRTUAL1_MBOX_5: 177 case CS35L56_DSP_VIRTUAL1_MBOX_6: 178 case CS35L56_DSP_VIRTUAL1_MBOX_7: 179 case CS35L56_DSP_VIRTUAL1_MBOX_8: 180 case CS35L56_DSP_RESTRICT_STS1: 181 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 182 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 183 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 184 case CS35L56_DSP1_SCRATCH1: 185 case CS35L56_DSP1_SCRATCH2: 186 case CS35L56_DSP1_SCRATCH3: 187 case CS35L56_DSP1_SCRATCH4: 188 return true; 189 case CS35L56_MAIN_RENDER_USER_MUTE: 190 case CS35L56_MAIN_RENDER_USER_VOLUME: 191 case CS35L56_MAIN_POSTURE_NUMBER: 192 return false; 193 default: 194 return cs35l56_is_dsp_memory(reg); 195 } 196 } 197 198 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 199 { 200 unsigned int val; 201 int ret; 202 203 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 204 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 205 val, (val == 0), 206 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 207 if (ret) { 208 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 209 return ret; 210 } 211 212 return 0; 213 } 214 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED); 215 216 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 217 { 218 int ret; 219 unsigned int reg; 220 unsigned int val; 221 222 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 223 if (ret) 224 return ret; 225 226 if (cs35l56_base->rev < CS35L56_REVID_B0) 227 reg = CS35L56_DSP1_PM_CUR_STATE_A1; 228 else 229 reg = CS35L56_DSP1_PM_CUR_STATE; 230 231 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg, 232 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 233 CS35L56_HALO_STATE_POLL_US, 234 CS35L56_HALO_STATE_TIMEOUT_US); 235 if (ret < 0) 236 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 237 val, ret); 238 return ret; 239 } 240 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED); 241 242 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 243 { 244 unsigned int reg; 245 unsigned int val; 246 int ret; 247 248 if (cs35l56_base->rev < CS35L56_REVID_B0) 249 reg = CS35L56_DSP1_HALO_STATE_A1; 250 else 251 reg = CS35L56_DSP1_HALO_STATE; 252 253 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg, 254 val, 255 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 256 CS35L56_HALO_STATE_POLL_US, 257 CS35L56_HALO_STATE_TIMEOUT_US); 258 259 if ((ret < 0) && (ret != -ETIMEDOUT)) { 260 dev_err(cs35l56_base->dev, "Failed to read HALO_STATE: %d\n", ret); 261 return ret; 262 } 263 264 if ((ret == -ETIMEDOUT) || (val != CS35L56_HALO_STATE_BOOT_DONE)) { 265 dev_err(cs35l56_base->dev, "Firmware boot fail: HALO_STATE=%#x\n", val); 266 return -EIO; 267 } 268 269 return 0; 270 } 271 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED); 272 273 void cs35l56_wait_control_port_ready(void) 274 { 275 /* Wait for control port to be ready (datasheet tIRS). */ 276 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 277 } 278 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED); 279 280 void cs35l56_wait_min_reset_pulse(void) 281 { 282 /* Satisfy minimum reset pulse width spec */ 283 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 284 } 285 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED); 286 287 static const struct reg_sequence cs35l56_system_reset_seq[] = { 288 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 289 }; 290 291 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 292 { 293 /* 294 * Must enter cache-only first so there can't be any more register 295 * accesses other than the controlled system reset sequence below. 296 */ 297 regcache_cache_only(cs35l56_base->regmap, true); 298 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 299 cs35l56_system_reset_seq, 300 ARRAY_SIZE(cs35l56_system_reset_seq)); 301 302 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 303 if (is_soundwire) 304 return; 305 306 cs35l56_wait_control_port_ready(); 307 regcache_cache_only(cs35l56_base->regmap, false); 308 } 309 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED); 310 311 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 312 { 313 int ret; 314 315 if (!irq) 316 return 0; 317 318 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 319 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 320 "cs35l56", cs35l56_base); 321 if (!ret) 322 cs35l56_base->irq = irq; 323 else 324 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 325 326 return ret; 327 } 328 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED); 329 330 irqreturn_t cs35l56_irq(int irq, void *data) 331 { 332 struct cs35l56_base *cs35l56_base = data; 333 unsigned int status1 = 0, status8 = 0, status20 = 0; 334 unsigned int mask1, mask8, mask20; 335 unsigned int val; 336 int rv; 337 338 irqreturn_t ret = IRQ_NONE; 339 340 if (!cs35l56_base->init_done) 341 return IRQ_NONE; 342 343 mutex_lock(&cs35l56_base->irq_lock); 344 345 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 346 if (rv < 0) { 347 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 348 goto err_unlock; 349 } 350 351 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 352 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 353 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 354 goto err; 355 } 356 357 /* Ack interrupts */ 358 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 359 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 360 status1 &= ~mask1; 361 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 362 363 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 364 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 365 status8 &= ~mask8; 366 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 367 368 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 369 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 370 status20 &= ~mask20; 371 /* We don't want EINT20 but they default to unmasked: force mask */ 372 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 373 374 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 375 376 /* Check to see if unmasked bits are active */ 377 if (!status1 && !status8 && !status20) 378 goto err; 379 380 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 381 dev_crit(cs35l56_base->dev, "Amp short error\n"); 382 383 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 384 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 385 386 ret = IRQ_HANDLED; 387 388 err: 389 pm_runtime_put(cs35l56_base->dev); 390 err_unlock: 391 mutex_unlock(&cs35l56_base->irq_lock); 392 393 return ret; 394 } 395 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED); 396 397 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 398 { 399 unsigned int val; 400 int ret; 401 402 /* Nothing to re-patch if we haven't done any patching yet. */ 403 if (!cs35l56_base->fw_patched) 404 return false; 405 406 /* 407 * If we have control of RESET we will have asserted it so the firmware 408 * will need re-patching. 409 */ 410 if (cs35l56_base->reset_gpio) 411 return true; 412 413 /* 414 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 415 * can't be used here to test for memory retention. 416 * Assume that tuning must be re-loaded. 417 */ 418 if (cs35l56_base->secured) 419 return true; 420 421 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 422 if (ret) { 423 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 424 return ret; 425 } 426 427 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val); 428 if (ret) 429 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 430 else 431 ret = !!(val & CS35L56_FIRMWARE_MISSING); 432 433 pm_runtime_put_autosuspend(cs35l56_base->dev); 434 435 return ret; 436 } 437 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED); 438 439 static const struct reg_sequence cs35l56_hibernate_seq[] = { 440 /* This must be the last register access */ 441 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_HIBERNATE_NOW), 442 }; 443 444 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = { 445 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP), 446 }; 447 448 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 449 { 450 unsigned int val; 451 int ret; 452 453 if (!cs35l56_base->init_done) 454 return 0; 455 456 /* Firmware must have entered a power-save state */ 457 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 458 CS35L56_TRANSDUCER_ACTUAL_PS, 459 val, (val >= CS35L56_PS3), 460 CS35L56_PS3_POLL_US, 461 CS35L56_PS3_TIMEOUT_US); 462 if (ret) 463 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 464 465 /* Clear BOOT_DONE so it can be used to detect a reboot */ 466 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 467 468 if (!cs35l56_base->can_hibernate) { 469 regcache_cache_only(cs35l56_base->regmap, true); 470 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 471 472 return 0; 473 } 474 475 /* 476 * Enable auto-hibernate. If it is woken by some other wake source 477 * it will automatically return to hibernate. 478 */ 479 cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE); 480 481 /* 482 * Must enter cache-only first so there can't be any more register 483 * accesses other than the controlled hibernate sequence below. 484 */ 485 regcache_cache_only(cs35l56_base->regmap, true); 486 487 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 488 cs35l56_hibernate_seq, 489 ARRAY_SIZE(cs35l56_hibernate_seq)); 490 491 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 492 493 return 0; 494 } 495 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED); 496 497 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 498 { 499 unsigned int val; 500 int ret; 501 502 if (!cs35l56_base->init_done) 503 return 0; 504 505 if (!cs35l56_base->can_hibernate) 506 goto out_sync; 507 508 if (!is_soundwire) { 509 /* 510 * Dummy transaction to trigger I2C/SPI auto-wake. This will NAK on I2C. 511 * Must be done before releasing cache-only. 512 */ 513 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 514 cs35l56_hibernate_wake_seq, 515 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 516 517 cs35l56_wait_control_port_ready(); 518 } 519 520 out_sync: 521 regcache_cache_only(cs35l56_base->regmap, false); 522 523 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 524 if (ret) { 525 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 526 goto err; 527 } 528 529 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 530 if (ret) 531 goto err; 532 533 /* BOOT_DONE will be 1 if the amp reset */ 534 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 535 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 536 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 537 regcache_mark_dirty(cs35l56_base->regmap); 538 } 539 540 regcache_sync(cs35l56_base->regmap); 541 542 dev_dbg(cs35l56_base->dev, "Resumed"); 543 544 return 0; 545 546 err: 547 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 548 CS35L56_MBOX_CMD_HIBERNATE_NOW); 549 550 regcache_cache_only(cs35l56_base->regmap, true); 551 552 return ret; 553 } 554 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED); 555 556 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 557 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 558 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 559 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 560 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 561 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 562 }; 563 564 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 565 { 566 cs_dsp->num = 1; 567 cs_dsp->type = WMFW_HALO; 568 cs_dsp->rev = 0; 569 cs_dsp->dev = cs35l56_base->dev; 570 cs_dsp->regmap = cs35l56_base->regmap; 571 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 572 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 573 cs_dsp->mem = cs35l56_dsp1_regions; 574 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 575 cs_dsp->no_core_startstop = true; 576 } 577 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED); 578 579 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 580 { 581 int ret; 582 unsigned int devid, revid, otpid, secured; 583 584 /* 585 * If the system is not using a reset_gpio then issue a 586 * dummy read to force a wakeup. 587 */ 588 if (!cs35l56_base->reset_gpio) 589 regmap_read(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, &devid); 590 591 cs35l56_wait_control_port_ready(); 592 593 /* 594 * The HALO_STATE register is in different locations on Ax and B0 595 * devices so the REVID needs to be determined before waiting for the 596 * firmware to boot. 597 */ 598 ret = regmap_read(cs35l56_base->regmap, CS35L56_REVID, &revid); 599 if (ret < 0) { 600 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 601 return ret; 602 } 603 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 604 605 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 606 if (ret) 607 return ret; 608 609 ret = regmap_read(cs35l56_base->regmap, CS35L56_DEVID, &devid); 610 if (ret < 0) { 611 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 612 return ret; 613 } 614 devid &= CS35L56_DEVID_MASK; 615 616 switch (devid) { 617 case 0x35A56: 618 break; 619 default: 620 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 621 return ret; 622 } 623 624 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 625 if (ret) { 626 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 627 return ret; 628 } 629 630 /* When any bus is restricted treat the device as secured */ 631 if (secured & CS35L56_RESTRICTED_MASK) 632 cs35l56_base->secured = true; 633 634 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 635 if (ret < 0) { 636 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 637 return ret; 638 } 639 640 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d\n", 641 cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid); 642 643 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 644 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 645 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 646 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 647 0); 648 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 649 CS35L56_TEMP_ERR_EINT1_MASK, 650 0); 651 652 return 0; 653 } 654 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED); 655 656 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 657 [0x0C] = 128000, 658 [0x0F] = 256000, 659 [0x11] = 384000, 660 [0x12] = 512000, 661 [0x15] = 768000, 662 [0x17] = 1024000, 663 [0x1A] = 1500000, 664 [0x1B] = 1536000, 665 [0x1C] = 2000000, 666 [0x1D] = 2048000, 667 [0x1E] = 2400000, 668 [0x20] = 3000000, 669 [0x21] = 3072000, 670 [0x23] = 4000000, 671 [0x24] = 4096000, 672 [0x25] = 4800000, 673 [0x27] = 6000000, 674 [0x28] = 6144000, 675 [0x29] = 6250000, 676 [0x2A] = 6400000, 677 [0x2E] = 8000000, 678 [0x2F] = 8192000, 679 [0x30] = 9600000, 680 [0x32] = 12000000, 681 [0x33] = 12288000, 682 [0x37] = 13500000, 683 [0x38] = 19200000, 684 [0x39] = 22579200, 685 [0x3B] = 24576000, 686 }; 687 688 int cs35l56_get_bclk_freq_id(unsigned int freq) 689 { 690 int i; 691 692 if (freq == 0) 693 return -EINVAL; 694 695 /* The BCLK frequency must be a valid PLL REFCLK */ 696 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 697 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 698 return i; 699 } 700 701 return -EINVAL; 702 } 703 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED); 704 705 static const char * const cs35l56_supplies[/* auto-sized */] = { 706 "VDD_P", 707 "VDD_IO", 708 "VDD_A", 709 }; 710 711 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 712 { 713 int i; 714 715 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 716 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 717 data[i].supply = cs35l56_supplies[i]; 718 } 719 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED); 720 721 const char * const cs35l56_tx_input_texts[] = { 722 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 723 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 724 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 725 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 726 }; 727 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED); 728 729 const unsigned int cs35l56_tx_input_values[] = { 730 CS35L56_INPUT_SRC_NONE, 731 CS35L56_INPUT_SRC_ASP1RX1, 732 CS35L56_INPUT_SRC_ASP1RX2, 733 CS35L56_INPUT_SRC_VMON, 734 CS35L56_INPUT_SRC_IMON, 735 CS35L56_INPUT_SRC_ERR_VOL, 736 CS35L56_INPUT_SRC_CLASSH, 737 CS35L56_INPUT_SRC_VDDBMON, 738 CS35L56_INPUT_SRC_VBSTMON, 739 CS35L56_INPUT_SRC_DSP1TX1, 740 CS35L56_INPUT_SRC_DSP1TX2, 741 CS35L56_INPUT_SRC_DSP1TX3, 742 CS35L56_INPUT_SRC_DSP1TX4, 743 CS35L56_INPUT_SRC_DSP1TX5, 744 CS35L56_INPUT_SRC_DSP1TX6, 745 CS35L56_INPUT_SRC_DSP1TX7, 746 CS35L56_INPUT_SRC_DSP1TX8, 747 CS35L56_INPUT_SRC_TEMPMON, 748 CS35L56_INPUT_SRC_INTERPOLATOR, 749 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 750 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 751 }; 752 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED); 753 754 struct regmap_config cs35l56_regmap_i2c = { 755 .reg_bits = 32, 756 .val_bits = 32, 757 .reg_stride = 4, 758 .reg_format_endian = REGMAP_ENDIAN_BIG, 759 .val_format_endian = REGMAP_ENDIAN_BIG, 760 .max_register = CS35L56_DSP1_PMEM_5114, 761 .reg_defaults = cs35l56_reg_defaults, 762 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 763 .volatile_reg = cs35l56_volatile_reg, 764 .readable_reg = cs35l56_readable_reg, 765 .precious_reg = cs35l56_precious_reg, 766 .cache_type = REGCACHE_MAPLE, 767 }; 768 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED); 769 770 struct regmap_config cs35l56_regmap_spi = { 771 .reg_bits = 32, 772 .val_bits = 32, 773 .pad_bits = 16, 774 .reg_stride = 4, 775 .reg_format_endian = REGMAP_ENDIAN_BIG, 776 .val_format_endian = REGMAP_ENDIAN_BIG, 777 .max_register = CS35L56_DSP1_PMEM_5114, 778 .reg_defaults = cs35l56_reg_defaults, 779 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 780 .volatile_reg = cs35l56_volatile_reg, 781 .readable_reg = cs35l56_readable_reg, 782 .precious_reg = cs35l56_precious_reg, 783 .cache_type = REGCACHE_MAPLE, 784 }; 785 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED); 786 787 struct regmap_config cs35l56_regmap_sdw = { 788 .reg_bits = 32, 789 .val_bits = 32, 790 .reg_stride = 4, 791 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 792 .val_format_endian = REGMAP_ENDIAN_BIG, 793 .max_register = CS35L56_DSP1_PMEM_5114, 794 .reg_defaults = cs35l56_reg_defaults, 795 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 796 .volatile_reg = cs35l56_volatile_reg, 797 .readable_reg = cs35l56_readable_reg, 798 .precious_reg = cs35l56_precious_reg, 799 .cache_type = REGCACHE_MAPLE, 800 }; 801 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED); 802 803 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 804 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 805 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 806 MODULE_LICENSE("GPL"); 807