1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l45.c - CS35L45 ALSA SoC audio driver 4 // 5 // Copyright 2019-2022 Cirrus Logic, Inc. 6 // 7 // Author: James Schulman <james.schulman@cirrus.com> 8 9 #include <linux/gpio/consumer.h> 10 #include <linux/module.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/property.h> 13 #include <linux/firmware.h> 14 #include <linux/regulator/consumer.h> 15 #include <sound/core.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc.h> 19 #include <sound/tlv.h> 20 21 #include "cs35l45.h" 22 23 static bool cs35l45_check_cspl_mbox_sts(const enum cs35l45_cspl_mboxcmd cmd, 24 enum cs35l45_cspl_mboxstate sts) 25 { 26 switch (cmd) { 27 case CSPL_MBOX_CMD_NONE: 28 case CSPL_MBOX_CMD_UNKNOWN_CMD: 29 return true; 30 case CSPL_MBOX_CMD_PAUSE: 31 case CSPL_MBOX_CMD_OUT_OF_HIBERNATE: 32 return (sts == CSPL_MBOX_STS_PAUSED); 33 case CSPL_MBOX_CMD_RESUME: 34 return (sts == CSPL_MBOX_STS_RUNNING); 35 case CSPL_MBOX_CMD_REINIT: 36 return (sts == CSPL_MBOX_STS_RUNNING); 37 case CSPL_MBOX_CMD_STOP_PRE_REINIT: 38 return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT); 39 case CSPL_MBOX_CMD_HIBERNATE: 40 return (sts == CSPL_MBOX_STS_HIBERNATE); 41 default: 42 return false; 43 } 44 } 45 46 static int cs35l45_set_cspl_mbox_cmd(struct cs35l45_private *cs35l45, 47 struct regmap *regmap, 48 const enum cs35l45_cspl_mboxcmd cmd) 49 { 50 unsigned int sts = 0, i; 51 int ret; 52 53 if (!cs35l45->dsp.cs_dsp.running) { 54 dev_err(cs35l45->dev, "DSP not running\n"); 55 return -EPERM; 56 } 57 58 // Set mailbox cmd 59 ret = regmap_write(regmap, CS35L45_DSP_VIRT1_MBOX_1, cmd); 60 if (ret < 0) { 61 if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE) 62 dev_err(cs35l45->dev, "Failed to write MBOX: %d\n", ret); 63 return ret; 64 } 65 66 // Read mailbox status and verify it is appropriate for the given cmd 67 for (i = 0; i < 5; i++) { 68 usleep_range(1000, 1100); 69 70 ret = regmap_read(regmap, CS35L45_DSP_MBOX_2, &sts); 71 if (ret < 0) { 72 dev_err(cs35l45->dev, "Failed to read MBOX STS: %d\n", ret); 73 continue; 74 } 75 76 if (!cs35l45_check_cspl_mbox_sts(cmd, sts)) 77 dev_dbg(cs35l45->dev, "[%u] cmd %u returned invalid sts %u", i, cmd, sts); 78 else 79 return 0; 80 } 81 82 if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE) 83 dev_err(cs35l45->dev, "Failed to set mailbox cmd %u (status %u)\n", cmd, sts); 84 85 return -ENOMSG; 86 } 87 88 static int cs35l45_global_en_ev(struct snd_soc_dapm_widget *w, 89 struct snd_kcontrol *kcontrol, int event) 90 { 91 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 92 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component); 93 94 dev_dbg(cs35l45->dev, "%s event : %x\n", __func__, event); 95 96 switch (event) { 97 case SND_SOC_DAPM_POST_PMU: 98 regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, 99 CS35L45_GLOBAL_EN_MASK); 100 101 usleep_range(CS35L45_POST_GLOBAL_EN_US, CS35L45_POST_GLOBAL_EN_US + 100); 102 break; 103 case SND_SOC_DAPM_PRE_PMD: 104 usleep_range(CS35L45_PRE_GLOBAL_DIS_US, CS35L45_PRE_GLOBAL_DIS_US + 100); 105 106 regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, 0); 107 break; 108 default: 109 break; 110 } 111 112 return 0; 113 } 114 115 static int cs35l45_dsp_preload_ev(struct snd_soc_dapm_widget *w, 116 struct snd_kcontrol *kcontrol, int event) 117 { 118 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 119 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component); 120 int ret; 121 122 switch (event) { 123 case SND_SOC_DAPM_PRE_PMU: 124 if (cs35l45->dsp.cs_dsp.booted) 125 return 0; 126 127 return wm_adsp_early_event(w, kcontrol, event); 128 case SND_SOC_DAPM_POST_PMU: 129 if (cs35l45->dsp.cs_dsp.running) 130 return 0; 131 132 regmap_set_bits(cs35l45->regmap, CS35L45_PWRMGT_CTL, 133 CS35L45_MEM_RDY_MASK); 134 135 return wm_adsp_event(w, kcontrol, event); 136 case SND_SOC_DAPM_PRE_PMD: 137 if (cs35l45->dsp.preloaded) 138 return 0; 139 140 if (cs35l45->dsp.cs_dsp.running) { 141 ret = wm_adsp_event(w, kcontrol, event); 142 if (ret) 143 return ret; 144 } 145 146 return wm_adsp_early_event(w, kcontrol, event); 147 default: 148 return 0; 149 } 150 } 151 152 static int cs35l45_dsp_audio_ev(struct snd_soc_dapm_widget *w, 153 struct snd_kcontrol *kcontrol, int event) 154 { 155 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 156 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component); 157 158 switch (event) { 159 case SND_SOC_DAPM_POST_PMU: 160 return cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap, 161 CSPL_MBOX_CMD_RESUME); 162 case SND_SOC_DAPM_PRE_PMD: 163 return cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap, 164 CSPL_MBOX_CMD_PAUSE); 165 default: 166 return 0; 167 } 168 169 return 0; 170 } 171 172 static const char * const cs35l45_asp_tx_txt[] = { 173 "Zero", "ASP_RX1", "ASP_RX2", 174 "VMON", "IMON", "ERR_VOL", 175 "VDD_BATTMON", "VDD_BSTMON", 176 "DSP_TX1", "DSP_TX2", 177 "Interpolator", "IL_TARGET", 178 }; 179 180 static const unsigned int cs35l45_asp_tx_val[] = { 181 CS35L45_PCM_SRC_ZERO, CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2, 182 CS35L45_PCM_SRC_VMON, CS35L45_PCM_SRC_IMON, CS35L45_PCM_SRC_ERR_VOL, 183 CS35L45_PCM_SRC_VDD_BATTMON, CS35L45_PCM_SRC_VDD_BSTMON, 184 CS35L45_PCM_SRC_DSP_TX1, CS35L45_PCM_SRC_DSP_TX2, 185 CS35L45_PCM_SRC_INTERPOLATOR, CS35L45_PCM_SRC_IL_TARGET, 186 }; 187 188 static const struct soc_enum cs35l45_asp_tx_enums[] = { 189 SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX1_INPUT, 0, CS35L45_PCM_SRC_MASK, 190 ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt, 191 cs35l45_asp_tx_val), 192 SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX2_INPUT, 0, CS35L45_PCM_SRC_MASK, 193 ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt, 194 cs35l45_asp_tx_val), 195 SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX3_INPUT, 0, CS35L45_PCM_SRC_MASK, 196 ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt, 197 cs35l45_asp_tx_val), 198 SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX4_INPUT, 0, CS35L45_PCM_SRC_MASK, 199 ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt, 200 cs35l45_asp_tx_val), 201 SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX5_INPUT, 0, CS35L45_PCM_SRC_MASK, 202 ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt, 203 cs35l45_asp_tx_val), 204 }; 205 206 static const char * const cs35l45_dsp_rx_txt[] = { 207 "Zero", "ASP_RX1", "ASP_RX2", 208 "VMON", "IMON", "ERR_VOL", 209 "CLASSH_TGT", "VDD_BATTMON", 210 "VDD_BSTMON", "TEMPMON", 211 }; 212 213 static const unsigned int cs35l45_dsp_rx_val[] = { 214 CS35L45_PCM_SRC_ZERO, CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2, 215 CS35L45_PCM_SRC_VMON, CS35L45_PCM_SRC_IMON, CS35L45_PCM_SRC_ERR_VOL, 216 CS35L45_PCM_SRC_CLASSH_TGT, CS35L45_PCM_SRC_VDD_BATTMON, 217 CS35L45_PCM_SRC_VDD_BSTMON, CS35L45_PCM_SRC_TEMPMON, 218 }; 219 220 static const struct soc_enum cs35l45_dsp_rx_enums[] = { 221 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX1_INPUT, 0, CS35L45_PCM_SRC_MASK, 222 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt, 223 cs35l45_dsp_rx_val), 224 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX2_INPUT, 0, CS35L45_PCM_SRC_MASK, 225 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt, 226 cs35l45_dsp_rx_val), 227 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX3_INPUT, 0, CS35L45_PCM_SRC_MASK, 228 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt, 229 cs35l45_dsp_rx_val), 230 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX4_INPUT, 0, CS35L45_PCM_SRC_MASK, 231 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt, 232 cs35l45_dsp_rx_val), 233 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX5_INPUT, 0, CS35L45_PCM_SRC_MASK, 234 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt, 235 cs35l45_dsp_rx_val), 236 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX6_INPUT, 0, CS35L45_PCM_SRC_MASK, 237 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt, 238 cs35l45_dsp_rx_val), 239 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX7_INPUT, 0, CS35L45_PCM_SRC_MASK, 240 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt, 241 cs35l45_dsp_rx_val), 242 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX8_INPUT, 0, CS35L45_PCM_SRC_MASK, 243 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt, 244 cs35l45_dsp_rx_val), 245 }; 246 247 static const char * const cs35l45_dac_txt[] = { 248 "Zero", "ASP_RX1", "ASP_RX2", "DSP_TX1", "DSP_TX2" 249 }; 250 251 static const unsigned int cs35l45_dac_val[] = { 252 CS35L45_PCM_SRC_ZERO, CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2, 253 CS35L45_PCM_SRC_DSP_TX1, CS35L45_PCM_SRC_DSP_TX2 254 }; 255 256 static const struct soc_enum cs35l45_dacpcm_enums[] = { 257 SOC_VALUE_ENUM_SINGLE(CS35L45_DACPCM1_INPUT, 0, CS35L45_PCM_SRC_MASK, 258 ARRAY_SIZE(cs35l45_dac_txt), cs35l45_dac_txt, 259 cs35l45_dac_val), 260 }; 261 262 static const struct snd_kcontrol_new cs35l45_asp_muxes[] = { 263 SOC_DAPM_ENUM("ASP_TX1 Source", cs35l45_asp_tx_enums[0]), 264 SOC_DAPM_ENUM("ASP_TX2 Source", cs35l45_asp_tx_enums[1]), 265 SOC_DAPM_ENUM("ASP_TX3 Source", cs35l45_asp_tx_enums[2]), 266 SOC_DAPM_ENUM("ASP_TX4 Source", cs35l45_asp_tx_enums[3]), 267 SOC_DAPM_ENUM("ASP_TX5 Source", cs35l45_asp_tx_enums[4]), 268 }; 269 270 static const struct snd_kcontrol_new cs35l45_dsp_muxes[] = { 271 SOC_DAPM_ENUM("DSP_RX1 Source", cs35l45_dsp_rx_enums[0]), 272 SOC_DAPM_ENUM("DSP_RX2 Source", cs35l45_dsp_rx_enums[1]), 273 SOC_DAPM_ENUM("DSP_RX3 Source", cs35l45_dsp_rx_enums[2]), 274 SOC_DAPM_ENUM("DSP_RX4 Source", cs35l45_dsp_rx_enums[3]), 275 SOC_DAPM_ENUM("DSP_RX5 Source", cs35l45_dsp_rx_enums[4]), 276 SOC_DAPM_ENUM("DSP_RX6 Source", cs35l45_dsp_rx_enums[5]), 277 SOC_DAPM_ENUM("DSP_RX7 Source", cs35l45_dsp_rx_enums[6]), 278 SOC_DAPM_ENUM("DSP_RX8 Source", cs35l45_dsp_rx_enums[7]), 279 }; 280 281 static const struct snd_kcontrol_new cs35l45_dac_muxes[] = { 282 SOC_DAPM_ENUM("DACPCM Source", cs35l45_dacpcm_enums[0]), 283 }; 284 285 static const struct snd_soc_dapm_widget cs35l45_dapm_widgets[] = { 286 SND_SOC_DAPM_SPK("DSP1 Preload", NULL), 287 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, 288 cs35l45_dsp_preload_ev, 289 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 290 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, 291 cs35l45_dsp_audio_ev, 292 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 293 SND_SOC_DAPM_SUPPLY("GLOBAL_EN", SND_SOC_NOPM, 0, 0, 294 cs35l45_global_en_ev, 295 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 296 SND_SOC_DAPM_SUPPLY("ASP_EN", CS35L45_BLOCK_ENABLES2, CS35L45_ASP_EN_SHIFT, 0, NULL, 0), 297 298 SND_SOC_DAPM_SIGGEN("VMON_SRC"), 299 SND_SOC_DAPM_SIGGEN("IMON_SRC"), 300 SND_SOC_DAPM_SIGGEN("VDD_BATTMON_SRC"), 301 SND_SOC_DAPM_SIGGEN("VDD_BSTMON_SRC"), 302 SND_SOC_DAPM_SIGGEN("ERR_VOL"), 303 SND_SOC_DAPM_SIGGEN("AMP_INTP"), 304 SND_SOC_DAPM_SIGGEN("IL_TARGET"), 305 SND_SOC_DAPM_ADC("VMON", NULL, CS35L45_BLOCK_ENABLES, CS35L45_VMON_EN_SHIFT, 0), 306 SND_SOC_DAPM_ADC("IMON", NULL, CS35L45_BLOCK_ENABLES, CS35L45_IMON_EN_SHIFT, 0), 307 SND_SOC_DAPM_ADC("VDD_BATTMON", NULL, CS35L45_BLOCK_ENABLES, 308 CS35L45_VDD_BATTMON_EN_SHIFT, 0), 309 SND_SOC_DAPM_ADC("VDD_BSTMON", NULL, CS35L45_BLOCK_ENABLES, 310 CS35L45_VDD_BSTMON_EN_SHIFT, 0), 311 312 SND_SOC_DAPM_AIF_IN("ASP_RX1", NULL, 0, CS35L45_ASP_ENABLES1, CS35L45_ASP_RX1_EN_SHIFT, 0), 313 SND_SOC_DAPM_AIF_IN("ASP_RX2", NULL, 1, CS35L45_ASP_ENABLES1, CS35L45_ASP_RX2_EN_SHIFT, 0), 314 315 SND_SOC_DAPM_AIF_OUT("ASP_TX1", NULL, 0, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX1_EN_SHIFT, 0), 316 SND_SOC_DAPM_AIF_OUT("ASP_TX2", NULL, 1, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX2_EN_SHIFT, 0), 317 SND_SOC_DAPM_AIF_OUT("ASP_TX3", NULL, 2, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX3_EN_SHIFT, 0), 318 SND_SOC_DAPM_AIF_OUT("ASP_TX4", NULL, 3, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX4_EN_SHIFT, 0), 319 SND_SOC_DAPM_AIF_OUT("ASP_TX5", NULL, 3, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX5_EN_SHIFT, 0), 320 321 SND_SOC_DAPM_MUX("ASP_TX1 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[0]), 322 SND_SOC_DAPM_MUX("ASP_TX2 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[1]), 323 SND_SOC_DAPM_MUX("ASP_TX3 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[2]), 324 SND_SOC_DAPM_MUX("ASP_TX4 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[3]), 325 SND_SOC_DAPM_MUX("ASP_TX5 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[4]), 326 327 SND_SOC_DAPM_MUX("DSP_RX1 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[0]), 328 SND_SOC_DAPM_MUX("DSP_RX2 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[1]), 329 SND_SOC_DAPM_MUX("DSP_RX3 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[2]), 330 SND_SOC_DAPM_MUX("DSP_RX4 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[3]), 331 SND_SOC_DAPM_MUX("DSP_RX5 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[4]), 332 SND_SOC_DAPM_MUX("DSP_RX6 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[5]), 333 SND_SOC_DAPM_MUX("DSP_RX7 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[6]), 334 SND_SOC_DAPM_MUX("DSP_RX8 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[7]), 335 336 SND_SOC_DAPM_MUX("DACPCM Source", SND_SOC_NOPM, 0, 0, &cs35l45_dac_muxes[0]), 337 338 SND_SOC_DAPM_OUT_DRV("AMP", SND_SOC_NOPM, 0, 0, NULL, 0), 339 340 SND_SOC_DAPM_OUTPUT("SPK"), 341 }; 342 343 #define CS35L45_ASP_MUX_ROUTE(name) \ 344 { name" Source", "ASP_RX1", "ASP_RX1" }, \ 345 { name" Source", "ASP_RX2", "ASP_RX2" }, \ 346 { name" Source", "DSP_TX1", "DSP1" }, \ 347 { name" Source", "DSP_TX2", "DSP1" }, \ 348 { name" Source", "VMON", "VMON" }, \ 349 { name" Source", "IMON", "IMON" }, \ 350 { name" Source", "ERR_VOL", "ERR_VOL" }, \ 351 { name" Source", "VDD_BATTMON", "VDD_BATTMON" }, \ 352 { name" Source", "VDD_BSTMON", "VDD_BSTMON" }, \ 353 { name" Source", "Interpolator", "AMP_INTP" }, \ 354 { name" Source", "IL_TARGET", "IL_TARGET" } 355 356 #define CS35L45_DSP_MUX_ROUTE(name) \ 357 { name" Source", "ASP_RX1", "ASP_RX1" }, \ 358 { name" Source", "ASP_RX2", "ASP_RX2" } 359 360 #define CS35L45_DAC_MUX_ROUTE(name) \ 361 { name" Source", "ASP_RX1", "ASP_RX1" }, \ 362 { name" Source", "ASP_RX2", "ASP_RX2" }, \ 363 { name" Source", "DSP_TX1", "DSP1" }, \ 364 { name" Source", "DSP_TX2", "DSP1" } 365 366 static const struct snd_soc_dapm_route cs35l45_dapm_routes[] = { 367 /* Feedback */ 368 { "VMON", NULL, "VMON_SRC" }, 369 { "IMON", NULL, "IMON_SRC" }, 370 { "VDD_BATTMON", NULL, "VDD_BATTMON_SRC" }, 371 { "VDD_BSTMON", NULL, "VDD_BSTMON_SRC" }, 372 373 { "Capture", NULL, "ASP_TX1"}, 374 { "Capture", NULL, "ASP_TX2"}, 375 { "Capture", NULL, "ASP_TX3"}, 376 { "Capture", NULL, "ASP_TX4"}, 377 { "Capture", NULL, "ASP_TX5"}, 378 { "ASP_TX1", NULL, "ASP_TX1 Source"}, 379 { "ASP_TX2", NULL, "ASP_TX2 Source"}, 380 { "ASP_TX3", NULL, "ASP_TX3 Source"}, 381 { "ASP_TX4", NULL, "ASP_TX4 Source"}, 382 { "ASP_TX5", NULL, "ASP_TX5 Source"}, 383 384 { "ASP_TX1", NULL, "ASP_EN" }, 385 { "ASP_TX2", NULL, "ASP_EN" }, 386 { "ASP_TX3", NULL, "ASP_EN" }, 387 { "ASP_TX4", NULL, "ASP_EN" }, 388 { "ASP_TX1", NULL, "GLOBAL_EN" }, 389 { "ASP_TX2", NULL, "GLOBAL_EN" }, 390 { "ASP_TX3", NULL, "GLOBAL_EN" }, 391 { "ASP_TX4", NULL, "GLOBAL_EN" }, 392 { "ASP_TX5", NULL, "GLOBAL_EN" }, 393 394 CS35L45_ASP_MUX_ROUTE("ASP_TX1"), 395 CS35L45_ASP_MUX_ROUTE("ASP_TX2"), 396 CS35L45_ASP_MUX_ROUTE("ASP_TX3"), 397 CS35L45_ASP_MUX_ROUTE("ASP_TX4"), 398 CS35L45_ASP_MUX_ROUTE("ASP_TX5"), 399 400 /* Playback */ 401 { "ASP_RX1", NULL, "Playback" }, 402 { "ASP_RX2", NULL, "Playback" }, 403 { "ASP_RX1", NULL, "ASP_EN" }, 404 { "ASP_RX2", NULL, "ASP_EN" }, 405 406 { "AMP", NULL, "DACPCM Source"}, 407 { "AMP", NULL, "GLOBAL_EN"}, 408 409 CS35L45_DSP_MUX_ROUTE("DSP_RX1"), 410 CS35L45_DSP_MUX_ROUTE("DSP_RX2"), 411 CS35L45_DSP_MUX_ROUTE("DSP_RX3"), 412 CS35L45_DSP_MUX_ROUTE("DSP_RX4"), 413 CS35L45_DSP_MUX_ROUTE("DSP_RX5"), 414 CS35L45_DSP_MUX_ROUTE("DSP_RX6"), 415 CS35L45_DSP_MUX_ROUTE("DSP_RX7"), 416 CS35L45_DSP_MUX_ROUTE("DSP_RX8"), 417 418 {"DSP1", NULL, "DSP_RX1 Source"}, 419 {"DSP1", NULL, "DSP_RX2 Source"}, 420 {"DSP1", NULL, "DSP_RX3 Source"}, 421 {"DSP1", NULL, "DSP_RX4 Source"}, 422 {"DSP1", NULL, "DSP_RX5 Source"}, 423 {"DSP1", NULL, "DSP_RX6 Source"}, 424 {"DSP1", NULL, "DSP_RX7 Source"}, 425 {"DSP1", NULL, "DSP_RX8 Source"}, 426 427 {"DSP1 Preload", NULL, "DSP1 Preloader"}, 428 {"DSP1", NULL, "DSP1 Preloader"}, 429 430 CS35L45_DAC_MUX_ROUTE("DACPCM"), 431 432 { "SPK", NULL, "AMP"}, 433 }; 434 435 static const DECLARE_TLV_DB_SCALE(cs35l45_dig_pcm_vol_tlv, -10225, 25, true); 436 437 static const struct snd_kcontrol_new cs35l45_controls[] = { 438 /* Ignore bit 0: it is beyond the resolution of TLV_DB_SCALE */ 439 SOC_SINGLE_S_TLV("Digital PCM Volume", 440 CS35L45_AMP_PCM_CONTROL, 441 CS35L45_AMP_VOL_PCM_SHIFT + 1, 442 -409, 48, 443 (CS35L45_AMP_VOL_PCM_WIDTH - 1) - 1, 444 0, cs35l45_dig_pcm_vol_tlv), 445 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), 446 WM_ADSP_FW_CONTROL("DSP1", 0), 447 }; 448 449 static int cs35l45_set_pll(struct cs35l45_private *cs35l45, unsigned int freq) 450 { 451 unsigned int val; 452 int freq_id; 453 454 freq_id = cs35l45_get_clk_freq_id(freq); 455 if (freq_id < 0) { 456 dev_err(cs35l45->dev, "Invalid freq: %u\n", freq); 457 return -EINVAL; 458 } 459 460 regmap_read(cs35l45->regmap, CS35L45_REFCLK_INPUT, &val); 461 val = (val & CS35L45_PLL_REFCLK_FREQ_MASK) >> CS35L45_PLL_REFCLK_FREQ_SHIFT; 462 if (val == freq_id) 463 return 0; 464 465 regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_OPEN_LOOP_MASK); 466 regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, 467 CS35L45_PLL_REFCLK_FREQ_MASK, 468 freq_id << CS35L45_PLL_REFCLK_FREQ_SHIFT); 469 regmap_clear_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_REFCLK_EN_MASK); 470 regmap_clear_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_OPEN_LOOP_MASK); 471 regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_REFCLK_EN_MASK); 472 473 return 0; 474 } 475 476 static int cs35l45_asp_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 477 { 478 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(codec_dai->component); 479 unsigned int asp_fmt, fsync_inv, bclk_inv; 480 481 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 482 case SND_SOC_DAIFMT_CBC_CFC: 483 break; 484 default: 485 dev_err(cs35l45->dev, "Invalid DAI clocking\n"); 486 return -EINVAL; 487 } 488 489 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 490 case SND_SOC_DAIFMT_DSP_A: 491 asp_fmt = CS35l45_ASP_FMT_DSP_A; 492 break; 493 case SND_SOC_DAIFMT_I2S: 494 asp_fmt = CS35L45_ASP_FMT_I2S; 495 break; 496 default: 497 dev_err(cs35l45->dev, "Invalid DAI format\n"); 498 return -EINVAL; 499 } 500 501 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 502 case SND_SOC_DAIFMT_NB_IF: 503 fsync_inv = 1; 504 bclk_inv = 0; 505 break; 506 case SND_SOC_DAIFMT_IB_NF: 507 fsync_inv = 0; 508 bclk_inv = 1; 509 break; 510 case SND_SOC_DAIFMT_IB_IF: 511 fsync_inv = 1; 512 bclk_inv = 1; 513 break; 514 case SND_SOC_DAIFMT_NB_NF: 515 fsync_inv = 0; 516 bclk_inv = 0; 517 break; 518 default: 519 dev_warn(cs35l45->dev, "Invalid DAI clock polarity\n"); 520 return -EINVAL; 521 } 522 523 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2, 524 CS35L45_ASP_FMT_MASK | 525 CS35L45_ASP_FSYNC_INV_MASK | 526 CS35L45_ASP_BCLK_INV_MASK, 527 (asp_fmt << CS35L45_ASP_FMT_SHIFT) | 528 (fsync_inv << CS35L45_ASP_FSYNC_INV_SHIFT) | 529 (bclk_inv << CS35L45_ASP_BCLK_INV_SHIFT)); 530 531 return 0; 532 } 533 534 static int cs35l45_asp_hw_params(struct snd_pcm_substream *substream, 535 struct snd_pcm_hw_params *params, 536 struct snd_soc_dai *dai) 537 { 538 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component); 539 unsigned int asp_width, asp_wl, global_fs, slot_multiple, asp_fmt; 540 int bclk; 541 542 switch (params_rate(params)) { 543 case 44100: 544 global_fs = CS35L45_44P100_KHZ; 545 break; 546 case 48000: 547 global_fs = CS35L45_48P0_KHZ; 548 break; 549 case 88200: 550 global_fs = CS35L45_88P200_KHZ; 551 break; 552 case 96000: 553 global_fs = CS35L45_96P0_KHZ; 554 break; 555 default: 556 dev_warn(cs35l45->dev, "Unsupported sample rate (%d)\n", 557 params_rate(params)); 558 return -EINVAL; 559 } 560 561 regmap_update_bits(cs35l45->regmap, CS35L45_GLOBAL_SAMPLE_RATE, 562 CS35L45_GLOBAL_FS_MASK, 563 global_fs << CS35L45_GLOBAL_FS_SHIFT); 564 565 asp_wl = params_width(params); 566 567 if (cs35l45->slot_width) 568 asp_width = cs35l45->slot_width; 569 else 570 asp_width = params_width(params); 571 572 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 573 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2, 574 CS35L45_ASP_WIDTH_RX_MASK, 575 asp_width << CS35L45_ASP_WIDTH_RX_SHIFT); 576 577 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_DATA_CONTROL5, 578 CS35L45_ASP_WL_MASK, 579 asp_wl << CS35L45_ASP_WL_SHIFT); 580 } else { 581 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2, 582 CS35L45_ASP_WIDTH_TX_MASK, 583 asp_width << CS35L45_ASP_WIDTH_TX_SHIFT); 584 585 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_DATA_CONTROL1, 586 CS35L45_ASP_WL_MASK, 587 asp_wl << CS35L45_ASP_WL_SHIFT); 588 } 589 590 if (cs35l45->sysclk_set) 591 return 0; 592 593 /* I2S always has an even number of channels */ 594 regmap_read(cs35l45->regmap, CS35L45_ASP_CONTROL2, &asp_fmt); 595 asp_fmt = (asp_fmt & CS35L45_ASP_FMT_MASK) >> CS35L45_ASP_FMT_SHIFT; 596 if (asp_fmt == CS35L45_ASP_FMT_I2S) 597 slot_multiple = 2; 598 else 599 slot_multiple = 1; 600 601 bclk = snd_soc_tdm_params_to_bclk(params, asp_width, 602 cs35l45->slot_count, slot_multiple); 603 604 return cs35l45_set_pll(cs35l45, bclk); 605 } 606 607 static int cs35l45_asp_set_tdm_slot(struct snd_soc_dai *dai, 608 unsigned int tx_mask, unsigned int rx_mask, 609 int slots, int slot_width) 610 { 611 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component); 612 613 if (slot_width && ((slot_width < 16) || (slot_width > 128))) 614 return -EINVAL; 615 616 cs35l45->slot_width = slot_width; 617 cs35l45->slot_count = slots; 618 619 return 0; 620 } 621 622 static int cs35l45_asp_set_sysclk(struct snd_soc_dai *dai, 623 int clk_id, unsigned int freq, int dir) 624 { 625 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component); 626 int ret; 627 628 if (clk_id != 0) { 629 dev_err(cs35l45->dev, "Invalid clk_id %d\n", clk_id); 630 return -EINVAL; 631 } 632 633 cs35l45->sysclk_set = false; 634 if (freq == 0) 635 return 0; 636 637 ret = cs35l45_set_pll(cs35l45, freq); 638 if (ret < 0) 639 return -EINVAL; 640 641 cs35l45->sysclk_set = true; 642 643 return 0; 644 } 645 646 static int cs35l45_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 647 { 648 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component); 649 unsigned int global_fs, val, hpf_tune; 650 651 if (mute) 652 return 0; 653 654 regmap_read(cs35l45->regmap, CS35L45_GLOBAL_SAMPLE_RATE, &global_fs); 655 global_fs = (global_fs & CS35L45_GLOBAL_FS_MASK) >> CS35L45_GLOBAL_FS_SHIFT; 656 switch (global_fs) { 657 case CS35L45_44P100_KHZ: 658 hpf_tune = CS35L45_HPF_44P1; 659 break; 660 case CS35L45_88P200_KHZ: 661 hpf_tune = CS35L45_HPF_88P2; 662 break; 663 default: 664 hpf_tune = CS35l45_HPF_DEFAULT; 665 break; 666 } 667 668 regmap_read(cs35l45->regmap, CS35L45_AMP_PCM_HPF_TST, &val); 669 if (val != hpf_tune) { 670 struct reg_sequence hpf_override_seq[] = { 671 { 0x00000040, 0x00000055 }, 672 { 0x00000040, 0x000000AA }, 673 { 0x00000044, 0x00000055 }, 674 { 0x00000044, 0x000000AA }, 675 { CS35L45_AMP_PCM_HPF_TST, hpf_tune }, 676 { 0x00000040, 0x00000000 }, 677 { 0x00000044, 0x00000000 }, 678 }; 679 regmap_multi_reg_write(cs35l45->regmap, hpf_override_seq, 680 ARRAY_SIZE(hpf_override_seq)); 681 } 682 683 return 0; 684 } 685 686 static const struct snd_soc_dai_ops cs35l45_asp_dai_ops = { 687 .set_fmt = cs35l45_asp_set_fmt, 688 .hw_params = cs35l45_asp_hw_params, 689 .set_tdm_slot = cs35l45_asp_set_tdm_slot, 690 .set_sysclk = cs35l45_asp_set_sysclk, 691 .mute_stream = cs35l45_mute_stream, 692 }; 693 694 static struct snd_soc_dai_driver cs35l45_dai[] = { 695 { 696 .name = "cs35l45", 697 .playback = { 698 .stream_name = "Playback", 699 .channels_min = 1, 700 .channels_max = 2, 701 .rates = CS35L45_RATES, 702 .formats = CS35L45_FORMATS, 703 }, 704 .capture = { 705 .stream_name = "Capture", 706 .channels_min = 1, 707 .channels_max = 5, 708 .rates = CS35L45_RATES, 709 .formats = CS35L45_FORMATS, 710 }, 711 .symmetric_rate = true, 712 .symmetric_sample_bits = true, 713 .ops = &cs35l45_asp_dai_ops, 714 }, 715 }; 716 717 static int cs35l45_component_probe(struct snd_soc_component *component) 718 { 719 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component); 720 721 return wm_adsp2_component_probe(&cs35l45->dsp, component); 722 } 723 724 static void cs35l45_component_remove(struct snd_soc_component *component) 725 { 726 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component); 727 728 wm_adsp2_component_remove(&cs35l45->dsp, component); 729 } 730 731 static const struct snd_soc_component_driver cs35l45_component = { 732 .probe = cs35l45_component_probe, 733 .remove = cs35l45_component_remove, 734 735 .dapm_widgets = cs35l45_dapm_widgets, 736 .num_dapm_widgets = ARRAY_SIZE(cs35l45_dapm_widgets), 737 738 .dapm_routes = cs35l45_dapm_routes, 739 .num_dapm_routes = ARRAY_SIZE(cs35l45_dapm_routes), 740 741 .controls = cs35l45_controls, 742 .num_controls = ARRAY_SIZE(cs35l45_controls), 743 744 .name = "cs35l45", 745 746 .endianness = 1, 747 }; 748 749 static void cs35l45_setup_hibernate(struct cs35l45_private *cs35l45) 750 { 751 unsigned int wksrc; 752 753 if (cs35l45->bus_type == CONTROL_BUS_I2C) 754 wksrc = CS35L45_WKSRC_I2C; 755 else 756 wksrc = CS35L45_WKSRC_SPI; 757 758 regmap_update_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL, 759 CS35L45_WKSRC_EN_MASK, 760 wksrc << CS35L45_WKSRC_EN_SHIFT); 761 762 regmap_set_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL, 763 CS35L45_UPDT_WKCTL_MASK); 764 765 regmap_update_bits(cs35l45->regmap, CS35L45_WKI2C_CTL, 766 CS35L45_WKI2C_ADDR_MASK, cs35l45->i2c_addr); 767 768 regmap_set_bits(cs35l45->regmap, CS35L45_WKI2C_CTL, 769 CS35L45_UPDT_WKI2C_MASK); 770 } 771 772 static int cs35l45_enter_hibernate(struct cs35l45_private *cs35l45) 773 { 774 dev_dbg(cs35l45->dev, "Enter hibernate\n"); 775 776 cs35l45_setup_hibernate(cs35l45); 777 778 regmap_set_bits(cs35l45->regmap, CS35L45_IRQ1_MASK_2, CS35L45_DSP_VIRT2_MBOX_MASK); 779 780 // Don't wait for ACK since bus activity would wake the device 781 regmap_write(cs35l45->regmap, CS35L45_DSP_VIRT1_MBOX_1, CSPL_MBOX_CMD_HIBERNATE); 782 783 return 0; 784 } 785 786 static int cs35l45_exit_hibernate(struct cs35l45_private *cs35l45) 787 { 788 const int wake_retries = 20; 789 const int sleep_retries = 5; 790 int ret, i, j; 791 792 for (i = 0; i < sleep_retries; i++) { 793 dev_dbg(cs35l45->dev, "Exit hibernate\n"); 794 795 for (j = 0; j < wake_retries; j++) { 796 ret = cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap, 797 CSPL_MBOX_CMD_OUT_OF_HIBERNATE); 798 if (!ret) { 799 dev_dbg(cs35l45->dev, "Wake success at cycle: %d\n", j); 800 regmap_clear_bits(cs35l45->regmap, CS35L45_IRQ1_MASK_2, 801 CS35L45_DSP_VIRT2_MBOX_MASK); 802 return 0; 803 } 804 usleep_range(100, 200); 805 } 806 807 dev_err(cs35l45->dev, "Wake failed, re-enter hibernate: %d\n", ret); 808 809 cs35l45_setup_hibernate(cs35l45); 810 } 811 812 dev_err(cs35l45->dev, "Timed out waking device\n"); 813 814 return -ETIMEDOUT; 815 } 816 817 static int cs35l45_runtime_suspend(struct device *dev) 818 { 819 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev); 820 821 if (!cs35l45->dsp.preloaded || !cs35l45->dsp.cs_dsp.running) 822 return 0; 823 824 cs35l45_enter_hibernate(cs35l45); 825 826 regcache_cache_only(cs35l45->regmap, true); 827 regcache_mark_dirty(cs35l45->regmap); 828 829 dev_dbg(cs35l45->dev, "Runtime suspended\n"); 830 831 return 0; 832 } 833 834 static int cs35l45_runtime_resume(struct device *dev) 835 { 836 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev); 837 int ret; 838 839 if (!cs35l45->dsp.preloaded || !cs35l45->dsp.cs_dsp.running) 840 return 0; 841 842 dev_dbg(cs35l45->dev, "Runtime resume\n"); 843 844 regcache_cache_only(cs35l45->regmap, false); 845 846 ret = cs35l45_exit_hibernate(cs35l45); 847 if (ret) 848 return ret; 849 850 ret = regcache_sync(cs35l45->regmap); 851 if (ret != 0) 852 dev_warn(cs35l45->dev, "regcache_sync failed: %d\n", ret); 853 854 /* Clear global error status */ 855 regmap_clear_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK); 856 regmap_set_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK); 857 regmap_clear_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK); 858 return ret; 859 } 860 861 static int cs35l45_sys_suspend(struct device *dev) 862 { 863 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev); 864 865 dev_dbg(cs35l45->dev, "System suspend, disabling IRQ\n"); 866 disable_irq(cs35l45->irq); 867 868 return 0; 869 } 870 871 static int cs35l45_sys_suspend_noirq(struct device *dev) 872 { 873 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev); 874 875 dev_dbg(cs35l45->dev, "Late system suspend, reenabling IRQ\n"); 876 enable_irq(cs35l45->irq); 877 878 return 0; 879 } 880 881 static int cs35l45_sys_resume_noirq(struct device *dev) 882 { 883 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev); 884 885 dev_dbg(cs35l45->dev, "Early system resume, disabling IRQ\n"); 886 disable_irq(cs35l45->irq); 887 888 return 0; 889 } 890 891 static int cs35l45_sys_resume(struct device *dev) 892 { 893 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev); 894 895 dev_dbg(cs35l45->dev, "System resume, reenabling IRQ\n"); 896 enable_irq(cs35l45->irq); 897 898 return 0; 899 } 900 901 static int cs35l45_apply_property_config(struct cs35l45_private *cs35l45) 902 { 903 struct device_node *node = cs35l45->dev->of_node; 904 unsigned int gpio_regs[] = {CS35L45_GPIO1_CTRL1, CS35L45_GPIO2_CTRL1, 905 CS35L45_GPIO3_CTRL1}; 906 unsigned int pad_regs[] = {CS35L45_SYNC_GPIO1, 907 CS35L45_INTB_GPIO2_MCLK_REF, CS35L45_GPIO3}; 908 struct device_node *child; 909 unsigned int val; 910 char of_name[32]; 911 int ret, i; 912 913 if (!node) 914 return 0; 915 916 for (i = 0; i < CS35L45_NUM_GPIOS; i++) { 917 sprintf(of_name, "cirrus,gpio-ctrl%d", i + 1); 918 child = of_get_child_by_name(node, of_name); 919 if (!child) 920 continue; 921 922 ret = of_property_read_u32(child, "gpio-dir", &val); 923 if (!ret) 924 regmap_update_bits(cs35l45->regmap, gpio_regs[i], 925 CS35L45_GPIO_DIR_MASK, 926 val << CS35L45_GPIO_DIR_SHIFT); 927 928 ret = of_property_read_u32(child, "gpio-lvl", &val); 929 if (!ret) 930 regmap_update_bits(cs35l45->regmap, gpio_regs[i], 931 CS35L45_GPIO_LVL_MASK, 932 val << CS35L45_GPIO_LVL_SHIFT); 933 934 ret = of_property_read_u32(child, "gpio-op-cfg", &val); 935 if (!ret) 936 regmap_update_bits(cs35l45->regmap, gpio_regs[i], 937 CS35L45_GPIO_OP_CFG_MASK, 938 val << CS35L45_GPIO_OP_CFG_SHIFT); 939 940 ret = of_property_read_u32(child, "gpio-pol", &val); 941 if (!ret) 942 regmap_update_bits(cs35l45->regmap, gpio_regs[i], 943 CS35L45_GPIO_POL_MASK, 944 val << CS35L45_GPIO_POL_SHIFT); 945 946 ret = of_property_read_u32(child, "gpio-ctrl", &val); 947 if (!ret) 948 regmap_update_bits(cs35l45->regmap, pad_regs[i], 949 CS35L45_GPIO_CTRL_MASK, 950 val << CS35L45_GPIO_CTRL_SHIFT); 951 952 ret = of_property_read_u32(child, "gpio-invert", &val); 953 if (!ret) { 954 regmap_update_bits(cs35l45->regmap, pad_regs[i], 955 CS35L45_GPIO_INVERT_MASK, 956 val << CS35L45_GPIO_INVERT_SHIFT); 957 if (i == 1) 958 cs35l45->irq_invert = val; 959 } 960 961 of_node_put(child); 962 } 963 964 if (device_property_read_u32(cs35l45->dev, 965 "cirrus,asp-sdout-hiz-ctrl", &val) == 0) { 966 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL3, 967 CS35L45_ASP_DOUT_HIZ_CTRL_MASK, 968 val << CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT); 969 } 970 971 return 0; 972 } 973 974 static int cs35l45_dsp_virt2_mbox3_irq_handle(struct cs35l45_private *cs35l45, 975 const unsigned int cmd, 976 unsigned int data) 977 { 978 static char *speak_status = "Unknown"; 979 980 switch (cmd) { 981 case EVENT_SPEAKER_STATUS: 982 switch (data) { 983 case 1: 984 speak_status = "All Clear"; 985 break; 986 case 2: 987 speak_status = "Open Circuit"; 988 break; 989 case 4: 990 speak_status = "Short Circuit"; 991 break; 992 } 993 994 dev_info(cs35l45->dev, "MBOX event (SPEAKER_STATUS): %s\n", 995 speak_status); 996 break; 997 case EVENT_BOOT_DONE: 998 dev_dbg(cs35l45->dev, "MBOX event (BOOT_DONE)\n"); 999 break; 1000 default: 1001 dev_err(cs35l45->dev, "MBOX event not supported %u\n", cmd); 1002 return -EINVAL; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static irqreturn_t cs35l45_dsp_virt2_mbox_cb(int irq, void *data) 1009 { 1010 struct cs35l45_private *cs35l45 = data; 1011 unsigned int mbox_val; 1012 int ret = 0; 1013 1014 ret = regmap_read(cs35l45->regmap, CS35L45_DSP_VIRT2_MBOX_3, &mbox_val); 1015 if (!ret && mbox_val) 1016 cs35l45_dsp_virt2_mbox3_irq_handle(cs35l45, mbox_val & CS35L45_MBOX3_CMD_MASK, 1017 (mbox_val & CS35L45_MBOX3_DATA_MASK) >> CS35L45_MBOX3_DATA_SHIFT); 1018 1019 /* Handle DSP trace log IRQ */ 1020 ret = regmap_read(cs35l45->regmap, CS35L45_DSP_VIRT2_MBOX_4, &mbox_val); 1021 if (!ret && mbox_val != 0) { 1022 dev_err(cs35l45->dev, "Spurious DSP MBOX4 IRQ\n"); 1023 } 1024 1025 return IRQ_RETVAL(ret); 1026 } 1027 1028 static irqreturn_t cs35l45_pll_unlock(int irq, void *data) 1029 { 1030 struct cs35l45_private *cs35l45 = data; 1031 1032 dev_dbg(cs35l45->dev, "PLL unlock detected!"); 1033 1034 return IRQ_HANDLED; 1035 } 1036 1037 static irqreturn_t cs35l45_pll_lock(int irq, void *data) 1038 { 1039 struct cs35l45_private *cs35l45 = data; 1040 1041 dev_dbg(cs35l45->dev, "PLL lock detected!"); 1042 1043 return IRQ_HANDLED; 1044 } 1045 1046 static irqreturn_t cs35l45_spk_safe_err(int irq, void *data); 1047 1048 static const struct cs35l45_irq cs35l45_irqs[] = { 1049 CS35L45_IRQ(AMP_SHORT_ERR, "Amplifier short error", cs35l45_spk_safe_err), 1050 CS35L45_IRQ(UVLO_VDDBATT_ERR, "VDDBATT undervoltage error", cs35l45_spk_safe_err), 1051 CS35L45_IRQ(BST_SHORT_ERR, "Boost inductor error", cs35l45_spk_safe_err), 1052 CS35L45_IRQ(BST_UVP_ERR, "Boost undervoltage error", cs35l45_spk_safe_err), 1053 CS35L45_IRQ(TEMP_ERR, "Overtemperature error", cs35l45_spk_safe_err), 1054 CS35L45_IRQ(AMP_CAL_ERR, "Amplifier calibration error", cs35l45_spk_safe_err), 1055 CS35L45_IRQ(UVLO_VDDLV_ERR, "LV threshold detector error", cs35l45_spk_safe_err), 1056 CS35L45_IRQ(GLOBAL_ERROR, "Global error", cs35l45_spk_safe_err), 1057 CS35L45_IRQ(DSP_WDT_EXPIRE, "DSP Watchdog Timer", cs35l45_spk_safe_err), 1058 CS35L45_IRQ(PLL_UNLOCK_FLAG_RISE, "PLL unlock", cs35l45_pll_unlock), 1059 CS35L45_IRQ(PLL_LOCK_FLAG, "PLL lock", cs35l45_pll_lock), 1060 CS35L45_IRQ(DSP_VIRT2_MBOX, "DSP virtual MBOX 2 write flag", cs35l45_dsp_virt2_mbox_cb), 1061 }; 1062 1063 static irqreturn_t cs35l45_spk_safe_err(int irq, void *data) 1064 { 1065 struct cs35l45_private *cs35l45 = data; 1066 int i; 1067 1068 i = irq - regmap_irq_get_virq(cs35l45->irq_data, 0); 1069 1070 if (i < 0 || i >= ARRAY_SIZE(cs35l45_irqs)) 1071 dev_err(cs35l45->dev, "Unspecified global error condition (%d) detected!\n", irq); 1072 else 1073 dev_err(cs35l45->dev, "%s condition detected!\n", cs35l45_irqs[i].name); 1074 1075 return IRQ_HANDLED; 1076 } 1077 1078 static const struct regmap_irq cs35l45_reg_irqs[] = { 1079 CS35L45_REG_IRQ(IRQ1_EINT_1, AMP_SHORT_ERR), 1080 CS35L45_REG_IRQ(IRQ1_EINT_1, UVLO_VDDBATT_ERR), 1081 CS35L45_REG_IRQ(IRQ1_EINT_1, BST_SHORT_ERR), 1082 CS35L45_REG_IRQ(IRQ1_EINT_1, BST_UVP_ERR), 1083 CS35L45_REG_IRQ(IRQ1_EINT_1, TEMP_ERR), 1084 CS35L45_REG_IRQ(IRQ1_EINT_3, AMP_CAL_ERR), 1085 CS35L45_REG_IRQ(IRQ1_EINT_18, UVLO_VDDLV_ERR), 1086 CS35L45_REG_IRQ(IRQ1_EINT_18, GLOBAL_ERROR), 1087 CS35L45_REG_IRQ(IRQ1_EINT_2, DSP_WDT_EXPIRE), 1088 CS35L45_REG_IRQ(IRQ1_EINT_3, PLL_UNLOCK_FLAG_RISE), 1089 CS35L45_REG_IRQ(IRQ1_EINT_3, PLL_LOCK_FLAG), 1090 CS35L45_REG_IRQ(IRQ1_EINT_2, DSP_VIRT2_MBOX), 1091 }; 1092 1093 static const struct regmap_irq_chip cs35l45_regmap_irq_chip = { 1094 .name = "cs35l45 IRQ1 Controller", 1095 .main_status = CS35L45_IRQ1_STATUS, 1096 .status_base = CS35L45_IRQ1_EINT_1, 1097 .mask_base = CS35L45_IRQ1_MASK_1, 1098 .ack_base = CS35L45_IRQ1_EINT_1, 1099 .num_regs = 18, 1100 .irqs = cs35l45_reg_irqs, 1101 .num_irqs = ARRAY_SIZE(cs35l45_reg_irqs), 1102 .runtime_pm = true, 1103 }; 1104 1105 static int cs35l45_initialize(struct cs35l45_private *cs35l45) 1106 { 1107 struct device *dev = cs35l45->dev; 1108 unsigned int dev_id[5]; 1109 unsigned int sts; 1110 int ret; 1111 1112 ret = regmap_read_poll_timeout(cs35l45->regmap, CS35L45_IRQ1_EINT_4, sts, 1113 (sts & CS35L45_OTP_BOOT_DONE_STS_MASK), 1114 1000, 5000); 1115 if (ret < 0) { 1116 dev_err(cs35l45->dev, "Timeout waiting for OTP boot\n"); 1117 return ret; 1118 } 1119 1120 ret = regmap_bulk_read(cs35l45->regmap, CS35L45_DEVID, dev_id, ARRAY_SIZE(dev_id)); 1121 if (ret) { 1122 dev_err(cs35l45->dev, "Get Device ID failed: %d\n", ret); 1123 return ret; 1124 } 1125 1126 switch (dev_id[0]) { 1127 case 0x35A450: 1128 case 0x35A460: 1129 break; 1130 default: 1131 dev_err(cs35l45->dev, "Bad DEVID 0x%x\n", dev_id[0]); 1132 return -ENODEV; 1133 } 1134 1135 dev_info(cs35l45->dev, "Cirrus Logic CS35L45: REVID %02X OTPID %02X\n", 1136 dev_id[1], dev_id[4]); 1137 1138 regmap_write(cs35l45->regmap, CS35L45_IRQ1_EINT_4, 1139 CS35L45_OTP_BOOT_DONE_STS_MASK | CS35L45_OTP_BUSY_MASK); 1140 1141 ret = cs35l45_apply_patch(cs35l45); 1142 if (ret < 0) { 1143 dev_err(dev, "Failed to apply init patch %d\n", ret); 1144 return ret; 1145 } 1146 1147 ret = cs35l45_apply_property_config(cs35l45); 1148 if (ret < 0) 1149 return ret; 1150 1151 return 0; 1152 } 1153 1154 static const struct reg_sequence cs35l45_fs_errata_patch[] = { 1155 {0x02B80080, 0x00000001}, 1156 {0x02B80088, 0x00000001}, 1157 {0x02B80090, 0x00000001}, 1158 {0x02B80098, 0x00000001}, 1159 {0x02B800A0, 0x00000001}, 1160 {0x02B800A8, 0x00000001}, 1161 {0x02B800B0, 0x00000001}, 1162 {0x02B800B8, 0x00000001}, 1163 {0x02B80280, 0x00000001}, 1164 {0x02B80288, 0x00000001}, 1165 {0x02B80290, 0x00000001}, 1166 {0x02B80298, 0x00000001}, 1167 {0x02B802A0, 0x00000001}, 1168 {0x02B802A8, 0x00000001}, 1169 {0x02B802B0, 0x00000001}, 1170 {0x02B802B8, 0x00000001}, 1171 }; 1172 1173 static const struct cs_dsp_region cs35l45_dsp1_regions[] = { 1174 { .type = WMFW_HALO_PM_PACKED, .base = CS35L45_DSP1_PMEM_0 }, 1175 { .type = WMFW_HALO_XM_PACKED, .base = CS35L45_DSP1_XMEM_PACK_0 }, 1176 { .type = WMFW_HALO_YM_PACKED, .base = CS35L45_DSP1_YMEM_PACK_0 }, 1177 {. type = WMFW_ADSP2_XM, .base = CS35L45_DSP1_XMEM_UNPACK24_0}, 1178 {. type = WMFW_ADSP2_YM, .base = CS35L45_DSP1_YMEM_UNPACK24_0}, 1179 }; 1180 1181 static int cs35l45_dsp_init(struct cs35l45_private *cs35l45) 1182 { 1183 struct wm_adsp *dsp = &cs35l45->dsp; 1184 int ret; 1185 1186 dsp->part = "cs35l45"; 1187 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */ 1188 dsp->toggle_preload = true; 1189 dsp->cs_dsp.num = 1; 1190 dsp->cs_dsp.type = WMFW_HALO; 1191 dsp->cs_dsp.rev = 0; 1192 dsp->cs_dsp.dev = cs35l45->dev; 1193 dsp->cs_dsp.regmap = cs35l45->regmap; 1194 dsp->cs_dsp.base = CS35L45_DSP1_CLOCK_FREQ; 1195 dsp->cs_dsp.base_sysinfo = CS35L45_DSP1_SYS_ID; 1196 dsp->cs_dsp.mem = cs35l45_dsp1_regions; 1197 dsp->cs_dsp.num_mems = ARRAY_SIZE(cs35l45_dsp1_regions); 1198 dsp->cs_dsp.lock_regions = 0xFFFFFFFF; 1199 1200 ret = wm_halo_init(dsp); 1201 1202 regmap_multi_reg_write(cs35l45->regmap, cs35l45_fs_errata_patch, 1203 ARRAY_SIZE(cs35l45_fs_errata_patch)); 1204 1205 return ret; 1206 } 1207 1208 int cs35l45_probe(struct cs35l45_private *cs35l45) 1209 { 1210 struct device *dev = cs35l45->dev; 1211 unsigned long irq_pol = IRQF_ONESHOT | IRQF_SHARED; 1212 int ret, i, irq; 1213 1214 cs35l45->vdd_batt = devm_regulator_get(dev, "vdd-batt"); 1215 if (IS_ERR(cs35l45->vdd_batt)) 1216 return dev_err_probe(dev, PTR_ERR(cs35l45->vdd_batt), 1217 "Failed to request vdd-batt\n"); 1218 1219 cs35l45->vdd_a = devm_regulator_get(dev, "vdd-a"); 1220 if (IS_ERR(cs35l45->vdd_a)) 1221 return dev_err_probe(dev, PTR_ERR(cs35l45->vdd_a), 1222 "Failed to request vdd-a\n"); 1223 1224 /* VDD_BATT must always be enabled before other supplies */ 1225 ret = regulator_enable(cs35l45->vdd_batt); 1226 if (ret < 0) 1227 return dev_err_probe(dev, ret, "Failed to enable vdd-batt\n"); 1228 1229 ret = regulator_enable(cs35l45->vdd_a); 1230 if (ret < 0) 1231 return dev_err_probe(dev, ret, "Failed to enable vdd-a\n"); 1232 1233 /* If reset is shared only one instance can claim it */ 1234 cs35l45->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1235 if (IS_ERR(cs35l45->reset_gpio)) { 1236 ret = PTR_ERR(cs35l45->reset_gpio); 1237 cs35l45->reset_gpio = NULL; 1238 if (ret == -EBUSY) { 1239 dev_dbg(dev, "Reset line busy, assuming shared reset\n"); 1240 } else { 1241 dev_err_probe(dev, ret, "Failed to get reset GPIO\n"); 1242 goto err; 1243 } 1244 } 1245 1246 if (cs35l45->reset_gpio) { 1247 usleep_range(CS35L45_RESET_HOLD_US, CS35L45_RESET_HOLD_US + 100); 1248 gpiod_set_value_cansleep(cs35l45->reset_gpio, 1); 1249 } 1250 1251 usleep_range(CS35L45_RESET_US, CS35L45_RESET_US + 100); 1252 1253 ret = cs35l45_initialize(cs35l45); 1254 if (ret < 0) 1255 goto err_reset; 1256 1257 ret = cs35l45_dsp_init(cs35l45); 1258 if (ret < 0) 1259 goto err_reset; 1260 1261 pm_runtime_set_autosuspend_delay(cs35l45->dev, 3000); 1262 pm_runtime_use_autosuspend(cs35l45->dev); 1263 pm_runtime_mark_last_busy(cs35l45->dev); 1264 pm_runtime_set_active(cs35l45->dev); 1265 pm_runtime_get_noresume(cs35l45->dev); 1266 pm_runtime_enable(cs35l45->dev); 1267 1268 if (cs35l45->irq) { 1269 if (cs35l45->irq_invert) 1270 irq_pol |= IRQF_TRIGGER_HIGH; 1271 else 1272 irq_pol |= IRQF_TRIGGER_LOW; 1273 1274 ret = devm_regmap_add_irq_chip(dev, cs35l45->regmap, cs35l45->irq, irq_pol, 0, 1275 &cs35l45_regmap_irq_chip, &cs35l45->irq_data); 1276 if (ret) { 1277 dev_err(dev, "Failed to register IRQ chip: %d\n", ret); 1278 goto err_dsp; 1279 } 1280 1281 for (i = 0; i < ARRAY_SIZE(cs35l45_irqs); i++) { 1282 irq = regmap_irq_get_virq(cs35l45->irq_data, cs35l45_irqs[i].irq); 1283 if (irq < 0) { 1284 dev_err(dev, "Failed to get %s\n", cs35l45_irqs[i].name); 1285 ret = irq; 1286 goto err_dsp; 1287 } 1288 1289 ret = devm_request_threaded_irq(dev, irq, NULL, cs35l45_irqs[i].handler, 1290 irq_pol, cs35l45_irqs[i].name, cs35l45); 1291 if (ret) { 1292 dev_err(dev, "Failed to request IRQ %s: %d\n", 1293 cs35l45_irqs[i].name, ret); 1294 goto err_dsp; 1295 } 1296 } 1297 } 1298 1299 ret = devm_snd_soc_register_component(dev, &cs35l45_component, 1300 cs35l45_dai, 1301 ARRAY_SIZE(cs35l45_dai)); 1302 if (ret < 0) 1303 goto err_dsp; 1304 1305 pm_runtime_put_autosuspend(cs35l45->dev); 1306 1307 return 0; 1308 1309 err_dsp: 1310 pm_runtime_disable(cs35l45->dev); 1311 pm_runtime_put_noidle(cs35l45->dev); 1312 wm_adsp2_remove(&cs35l45->dsp); 1313 1314 err_reset: 1315 gpiod_set_value_cansleep(cs35l45->reset_gpio, 0); 1316 err: 1317 regulator_disable(cs35l45->vdd_a); 1318 regulator_disable(cs35l45->vdd_batt); 1319 1320 return ret; 1321 } 1322 EXPORT_SYMBOL_NS_GPL(cs35l45_probe, SND_SOC_CS35L45); 1323 1324 void cs35l45_remove(struct cs35l45_private *cs35l45) 1325 { 1326 pm_runtime_get_sync(cs35l45->dev); 1327 pm_runtime_disable(cs35l45->dev); 1328 wm_adsp2_remove(&cs35l45->dsp); 1329 1330 gpiod_set_value_cansleep(cs35l45->reset_gpio, 0); 1331 1332 pm_runtime_put_noidle(cs35l45->dev); 1333 regulator_disable(cs35l45->vdd_a); 1334 /* VDD_BATT must be the last to power-off */ 1335 regulator_disable(cs35l45->vdd_batt); 1336 } 1337 EXPORT_SYMBOL_NS_GPL(cs35l45_remove, SND_SOC_CS35L45); 1338 1339 EXPORT_GPL_DEV_PM_OPS(cs35l45_pm_ops) = { 1340 RUNTIME_PM_OPS(cs35l45_runtime_suspend, cs35l45_runtime_resume, NULL) 1341 1342 SYSTEM_SLEEP_PM_OPS(cs35l45_sys_suspend, cs35l45_sys_resume) 1343 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l45_sys_suspend_noirq, cs35l45_sys_resume_noirq) 1344 }; 1345 1346 MODULE_DESCRIPTION("ASoC CS35L45 driver"); 1347 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 1348 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1349 MODULE_LICENSE("GPL"); 1350