1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 // 3 // cs35l45-tables.c -- CS35L45 ALSA SoC audio driver 4 // 5 // Copyright 2019-2022 Cirrus Logic, Inc. 6 // 7 // Author: James Schulman <james.schulman@cirrus.com> 8 9 #include <linux/module.h> 10 #include <linux/regmap.h> 11 12 #include "cs35l45.h" 13 14 static const struct reg_sequence cs35l45_patch[] = { 15 { 0x00000040, 0x00000055 }, 16 { 0x00000040, 0x000000AA }, 17 { 0x00000044, 0x00000055 }, 18 { 0x00000044, 0x000000AA }, 19 { 0x00006480, 0x0830500A }, 20 { 0x00007C60, 0x1000850B }, 21 { CS35L45_BOOST_OV_CFG, 0x007000D0 }, 22 { CS35L45_LDPM_CONFIG, 0x0001B636 }, 23 { 0x00002C08, 0x00000009 }, 24 { 0x00006850, 0x0A30FFC4 }, 25 { 0x00003820, 0x00040100 }, 26 { 0x00003824, 0x00000000 }, 27 { 0x00007CFC, 0x62870004 }, 28 { 0x00007C60, 0x1001850B }, 29 { 0x00000040, 0x00000000 }, 30 { 0x00000044, 0x00000000 }, 31 { CS35L45_BOOST_CCM_CFG, 0xF0000003 }, 32 { CS35L45_BOOST_DCM_CFG, 0x08710220 }, 33 { CS35L45_ERROR_RELEASE, 0x00200000 }, 34 }; 35 36 int cs35l45_apply_patch(struct cs35l45_private *cs35l45) 37 { 38 return regmap_register_patch(cs35l45->regmap, cs35l45_patch, 39 ARRAY_SIZE(cs35l45_patch)); 40 } 41 EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45); 42 43 static const struct reg_default cs35l45_defaults[] = { 44 { CS35L45_BLOCK_ENABLES, 0x00003323 }, 45 { CS35L45_BLOCK_ENABLES2, 0x00000010 }, 46 { CS35L45_SYNC_GPIO1, 0x00000007 }, 47 { CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 }, 48 { CS35L45_GPIO3, 0x00000005 }, 49 { CS35L45_REFCLK_INPUT, 0x00000510 }, 50 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 }, 51 { CS35L45_ASP_ENABLES1, 0x00000000 }, 52 { CS35L45_ASP_CONTROL1, 0x00000028 }, 53 { CS35L45_ASP_CONTROL2, 0x18180200 }, 54 { CS35L45_ASP_CONTROL3, 0x00000002 }, 55 { CS35L45_ASP_FRAME_CONTROL1, 0x03020100 }, 56 { CS35L45_ASP_FRAME_CONTROL2, 0x00000004 }, 57 { CS35L45_ASP_FRAME_CONTROL5, 0x00000100 }, 58 { CS35L45_ASP_DATA_CONTROL1, 0x00000018 }, 59 { CS35L45_ASP_DATA_CONTROL5, 0x00000018 }, 60 { CS35L45_DACPCM1_INPUT, 0x00000008 }, 61 { CS35L45_ASPTX1_INPUT, 0x00000018 }, 62 { CS35L45_ASPTX2_INPUT, 0x00000019 }, 63 { CS35L45_ASPTX3_INPUT, 0x00000020 }, 64 { CS35L45_ASPTX4_INPUT, 0x00000028 }, 65 { CS35L45_ASPTX5_INPUT, 0x00000048 }, 66 { CS35L45_AMP_PCM_CONTROL, 0x00100000 }, 67 { CS35L45_GPIO1_CTRL1, 0x81000001 }, 68 { CS35L45_GPIO2_CTRL1, 0x81000001 }, 69 { CS35L45_GPIO3_CTRL1, 0x81000001 }, 70 }; 71 72 static bool cs35l45_readable_reg(struct device *dev, unsigned int reg) 73 { 74 switch (reg) { 75 case CS35L45_DEVID ... CS35L45_OTPID: 76 case CS35L45_SFT_RESET: 77 case CS35L45_GLOBAL_ENABLES: 78 case CS35L45_BLOCK_ENABLES: 79 case CS35L45_BLOCK_ENABLES2: 80 case CS35L45_ERROR_RELEASE: 81 case CS35L45_SYNC_GPIO1: 82 case CS35L45_INTB_GPIO2_MCLK_REF: 83 case CS35L45_GPIO3: 84 case CS35L45_REFCLK_INPUT: 85 case CS35L45_GLOBAL_SAMPLE_RATE: 86 case CS35L45_ASP_ENABLES1: 87 case CS35L45_ASP_CONTROL1: 88 case CS35L45_ASP_CONTROL2: 89 case CS35L45_ASP_CONTROL3: 90 case CS35L45_ASP_FRAME_CONTROL1: 91 case CS35L45_ASP_FRAME_CONTROL2: 92 case CS35L45_ASP_FRAME_CONTROL5: 93 case CS35L45_ASP_DATA_CONTROL1: 94 case CS35L45_ASP_DATA_CONTROL5: 95 case CS35L45_DACPCM1_INPUT: 96 case CS35L45_ASPTX1_INPUT: 97 case CS35L45_ASPTX2_INPUT: 98 case CS35L45_ASPTX3_INPUT: 99 case CS35L45_ASPTX4_INPUT: 100 case CS35L45_ASPTX5_INPUT: 101 case CS35L45_AMP_PCM_CONTROL: 102 case CS35L45_AMP_PCM_HPF_TST: 103 case CS35L45_IRQ1_EINT_4: 104 case CS35L45_GPIO_STATUS1: 105 case CS35L45_GPIO1_CTRL1: 106 case CS35L45_GPIO2_CTRL1: 107 case CS35L45_GPIO3_CTRL1: 108 return true; 109 default: 110 return false; 111 } 112 } 113 114 static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg) 115 { 116 switch (reg) { 117 case CS35L45_DEVID ... CS35L45_OTPID: 118 case CS35L45_SFT_RESET: 119 case CS35L45_GLOBAL_ENABLES: 120 case CS35L45_ERROR_RELEASE: 121 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */ 122 case CS35L45_IRQ1_EINT_4: 123 case CS35L45_GPIO_STATUS1: 124 return true; 125 default: 126 return false; 127 } 128 } 129 130 const struct regmap_config cs35l45_i2c_regmap = { 131 .reg_bits = 32, 132 .val_bits = 32, 133 .reg_stride = 4, 134 .reg_format_endian = REGMAP_ENDIAN_BIG, 135 .val_format_endian = REGMAP_ENDIAN_BIG, 136 .max_register = CS35L45_LASTREG, 137 .reg_defaults = cs35l45_defaults, 138 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 139 .volatile_reg = cs35l45_volatile_reg, 140 .readable_reg = cs35l45_readable_reg, 141 .cache_type = REGCACHE_RBTREE, 142 }; 143 EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45); 144 145 const struct regmap_config cs35l45_spi_regmap = { 146 .reg_bits = 32, 147 .val_bits = 32, 148 .pad_bits = 16, 149 .reg_stride = 4, 150 .reg_format_endian = REGMAP_ENDIAN_BIG, 151 .val_format_endian = REGMAP_ENDIAN_BIG, 152 .max_register = CS35L45_LASTREG, 153 .reg_defaults = cs35l45_defaults, 154 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 155 .volatile_reg = cs35l45_volatile_reg, 156 .readable_reg = cs35l45_readable_reg, 157 .cache_type = REGCACHE_RBTREE, 158 }; 159 EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45); 160 161 static const struct { 162 u8 cfg_id; 163 u32 freq; 164 } cs35l45_pll_refclk_freq[] = { 165 { 0x0C, 128000 }, 166 { 0x0F, 256000 }, 167 { 0x11, 384000 }, 168 { 0x12, 512000 }, 169 { 0x15, 768000 }, 170 { 0x17, 1024000 }, 171 { 0x19, 1411200 }, 172 { 0x1B, 1536000 }, 173 { 0x1C, 2116800 }, 174 { 0x1D, 2048000 }, 175 { 0x1E, 2304000 }, 176 { 0x1F, 2822400 }, 177 { 0x21, 3072000 }, 178 { 0x23, 4233600 }, 179 { 0x24, 4096000 }, 180 { 0x25, 4608000 }, 181 { 0x26, 5644800 }, 182 { 0x27, 6000000 }, 183 { 0x28, 6144000 }, 184 { 0x29, 6350400 }, 185 { 0x2A, 6912000 }, 186 { 0x2D, 7526400 }, 187 { 0x2E, 8467200 }, 188 { 0x2F, 8192000 }, 189 { 0x30, 9216000 }, 190 { 0x31, 11289600 }, 191 { 0x33, 12288000 }, 192 { 0x37, 16934400 }, 193 { 0x38, 18432000 }, 194 { 0x39, 22579200 }, 195 { 0x3B, 24576000 }, 196 }; 197 198 unsigned int cs35l45_get_clk_freq_id(unsigned int freq) 199 { 200 int i; 201 202 if (freq == 0) 203 return -EINVAL; 204 205 for (i = 0; i < ARRAY_SIZE(cs35l45_pll_refclk_freq); ++i) { 206 if (cs35l45_pll_refclk_freq[i].freq == freq) 207 return cs35l45_pll_refclk_freq[i].cfg_id; 208 } 209 210 return -EINVAL; 211 } 212 EXPORT_SYMBOL_NS_GPL(cs35l45_get_clk_freq_id, SND_SOC_CS35L45); 213