1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41.c -- CS35l41 ALSA SoC audio driver 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 9 #include <linux/acpi.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/property.h> 19 #include <sound/initval.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/tlv.h> 25 26 #include "cs35l41.h" 27 28 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = { 29 "VA", 30 "VP", 31 }; 32 33 struct cs35l41_pll_sysclk_config { 34 int freq; 35 int clk_cfg; 36 }; 37 38 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = { 39 { 32768, 0x00 }, 40 { 8000, 0x01 }, 41 { 11025, 0x02 }, 42 { 12000, 0x03 }, 43 { 16000, 0x04 }, 44 { 22050, 0x05 }, 45 { 24000, 0x06 }, 46 { 32000, 0x07 }, 47 { 44100, 0x08 }, 48 { 48000, 0x09 }, 49 { 88200, 0x0A }, 50 { 96000, 0x0B }, 51 { 128000, 0x0C }, 52 { 176400, 0x0D }, 53 { 192000, 0x0E }, 54 { 256000, 0x0F }, 55 { 352800, 0x10 }, 56 { 384000, 0x11 }, 57 { 512000, 0x12 }, 58 { 705600, 0x13 }, 59 { 750000, 0x14 }, 60 { 768000, 0x15 }, 61 { 1000000, 0x16 }, 62 { 1024000, 0x17 }, 63 { 1200000, 0x18 }, 64 { 1411200, 0x19 }, 65 { 1500000, 0x1A }, 66 { 1536000, 0x1B }, 67 { 2000000, 0x1C }, 68 { 2048000, 0x1D }, 69 { 2400000, 0x1E }, 70 { 2822400, 0x1F }, 71 { 3000000, 0x20 }, 72 { 3072000, 0x21 }, 73 { 3200000, 0x22 }, 74 { 4000000, 0x23 }, 75 { 4096000, 0x24 }, 76 { 4800000, 0x25 }, 77 { 5644800, 0x26 }, 78 { 6000000, 0x27 }, 79 { 6144000, 0x28 }, 80 { 6250000, 0x29 }, 81 { 6400000, 0x2A }, 82 { 6500000, 0x2B }, 83 { 6750000, 0x2C }, 84 { 7526400, 0x2D }, 85 { 8000000, 0x2E }, 86 { 8192000, 0x2F }, 87 { 9600000, 0x30 }, 88 { 11289600, 0x31 }, 89 { 12000000, 0x32 }, 90 { 12288000, 0x33 }, 91 { 12500000, 0x34 }, 92 { 12800000, 0x35 }, 93 { 13000000, 0x36 }, 94 { 13500000, 0x37 }, 95 { 19200000, 0x38 }, 96 { 22579200, 0x39 }, 97 { 24000000, 0x3A }, 98 { 24576000, 0x3B }, 99 { 25000000, 0x3C }, 100 { 25600000, 0x3D }, 101 { 26000000, 0x3E }, 102 { 27000000, 0x3F }, 103 }; 104 105 struct cs35l41_fs_mon_config { 106 int freq; 107 unsigned int fs1; 108 unsigned int fs2; 109 }; 110 111 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = { 112 { 32768, 2254, 3754 }, 113 { 8000, 9220, 15364 }, 114 { 11025, 6148, 10244 }, 115 { 12000, 6148, 10244 }, 116 { 16000, 4612, 7684 }, 117 { 22050, 3076, 5124 }, 118 { 24000, 3076, 5124 }, 119 { 32000, 2308, 3844 }, 120 { 44100, 1540, 2564 }, 121 { 48000, 1540, 2564 }, 122 { 88200, 772, 1284 }, 123 { 96000, 772, 1284 }, 124 { 128000, 580, 964 }, 125 { 176400, 388, 644 }, 126 { 192000, 388, 644 }, 127 { 256000, 292, 484 }, 128 { 352800, 196, 324 }, 129 { 384000, 196, 324 }, 130 { 512000, 148, 244 }, 131 { 705600, 100, 164 }, 132 { 750000, 100, 164 }, 133 { 768000, 100, 164 }, 134 { 1000000, 76, 124 }, 135 { 1024000, 76, 124 }, 136 { 1200000, 64, 104 }, 137 { 1411200, 52, 84 }, 138 { 1500000, 52, 84 }, 139 { 1536000, 52, 84 }, 140 { 2000000, 40, 64 }, 141 { 2048000, 40, 64 }, 142 { 2400000, 34, 54 }, 143 { 2822400, 28, 44 }, 144 { 3000000, 28, 44 }, 145 { 3072000, 28, 44 }, 146 { 3200000, 27, 42 }, 147 { 4000000, 22, 34 }, 148 { 4096000, 22, 34 }, 149 { 4800000, 19, 29 }, 150 { 5644800, 16, 24 }, 151 { 6000000, 16, 24 }, 152 { 6144000, 16, 24 }, 153 }; 154 155 static int cs35l41_get_fs_mon_config_index(int freq) 156 { 157 int i; 158 159 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) { 160 if (cs35l41_fs_mon[i].freq == freq) 161 return i; 162 } 163 164 return -EINVAL; 165 } 166 167 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 168 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 169 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200)); 170 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1); 171 172 static const struct snd_kcontrol_new dre_ctrl = 173 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0); 174 175 static const char * const cs35l41_pcm_sftramp_text[] = { 176 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms" 177 }; 178 179 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, 180 CS35L41_AMP_DIG_VOL_CTRL, 0, 181 cs35l41_pcm_sftramp_text); 182 183 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w, 184 struct snd_kcontrol *kcontrol, int event) 185 { 186 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 187 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 188 int ret; 189 190 switch (event) { 191 case SND_SOC_DAPM_PRE_PMU: 192 if (cs35l41->dsp.cs_dsp.booted) 193 return 0; 194 195 return wm_adsp_early_event(w, kcontrol, event); 196 case SND_SOC_DAPM_PRE_PMD: 197 if (cs35l41->dsp.preloaded) 198 return 0; 199 200 if (cs35l41->dsp.cs_dsp.running) { 201 ret = wm_adsp_event(w, kcontrol, event); 202 if (ret) 203 return ret; 204 } 205 206 return wm_adsp_early_event(w, kcontrol, event); 207 default: 208 return 0; 209 } 210 } 211 212 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w, 213 struct snd_kcontrol *kcontrol, int event) 214 { 215 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 216 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 217 unsigned int fw_status; 218 int ret; 219 220 switch (event) { 221 case SND_SOC_DAPM_POST_PMU: 222 if (!cs35l41->dsp.cs_dsp.running) 223 return wm_adsp_event(w, kcontrol, event); 224 225 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status); 226 if (ret < 0) { 227 dev_err(cs35l41->dev, 228 "Failed to read firmware status: %d\n", ret); 229 return ret; 230 } 231 232 switch (fw_status) { 233 case CSPL_MBOX_STS_RUNNING: 234 case CSPL_MBOX_STS_PAUSED: 235 break; 236 default: 237 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n", 238 fw_status); 239 return -EINVAL; 240 } 241 242 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 243 CSPL_MBOX_CMD_RESUME); 244 case SND_SOC_DAPM_PRE_PMD: 245 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, 246 CSPL_MBOX_CMD_PAUSE); 247 default: 248 return 0; 249 } 250 } 251 252 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"}; 253 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32}; 254 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, 255 CS35L41_DAC_PCM1_SRC, 256 0, CS35L41_ASP_SOURCE_MASK, 257 cs35l41_pcm_source_texts, 258 cs35l41_pcm_source_values); 259 260 static const struct snd_kcontrol_new pcm_source_mux = 261 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); 262 263 static const char * const cs35l41_tx_input_texts[] = { 264 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON", 265 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2" 266 }; 267 268 static const unsigned int cs35l41_tx_input_values[] = { 269 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2, 270 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON, 271 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2 272 }; 273 274 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, 275 CS35L41_ASP_TX1_SRC, 276 0, CS35L41_ASP_SOURCE_MASK, 277 cs35l41_tx_input_texts, 278 cs35l41_tx_input_values); 279 280 static const struct snd_kcontrol_new asp_tx1_mux = 281 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum); 282 283 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum, 284 CS35L41_ASP_TX2_SRC, 285 0, CS35L41_ASP_SOURCE_MASK, 286 cs35l41_tx_input_texts, 287 cs35l41_tx_input_values); 288 289 static const struct snd_kcontrol_new asp_tx2_mux = 290 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum); 291 292 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum, 293 CS35L41_ASP_TX3_SRC, 294 0, CS35L41_ASP_SOURCE_MASK, 295 cs35l41_tx_input_texts, 296 cs35l41_tx_input_values); 297 298 static const struct snd_kcontrol_new asp_tx3_mux = 299 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum); 300 301 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum, 302 CS35L41_ASP_TX4_SRC, 303 0, CS35L41_ASP_SOURCE_MASK, 304 cs35l41_tx_input_texts, 305 cs35l41_tx_input_values); 306 307 static const struct snd_kcontrol_new asp_tx4_mux = 308 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum); 309 310 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum, 311 CS35L41_DSP1_RX1_SRC, 312 0, CS35L41_ASP_SOURCE_MASK, 313 cs35l41_tx_input_texts, 314 cs35l41_tx_input_values); 315 316 static const struct snd_kcontrol_new dsp_rx1_mux = 317 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum); 318 319 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum, 320 CS35L41_DSP1_RX2_SRC, 321 0, CS35L41_ASP_SOURCE_MASK, 322 cs35l41_tx_input_texts, 323 cs35l41_tx_input_values); 324 325 static const struct snd_kcontrol_new dsp_rx2_mux = 326 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum); 327 328 static const struct snd_kcontrol_new cs35l41_aud_controls[] = { 329 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL, 330 3, 0x4CF, 0x391, dig_vol_tlv), 331 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0, 332 amp_gain_tlv), 333 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp), 334 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0), 335 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0), 336 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0), 337 SOC_SINGLE("Aux Noise Gate CH1 Switch", 338 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0), 339 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay", 340 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0), 341 SOC_SINGLE("Aux Noise Gate CH1 Threshold", 342 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0), 343 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay", 344 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0), 345 SOC_SINGLE("Aux Noise Gate CH2 Switch", 346 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0), 347 SOC_SINGLE("Aux Noise Gate CH2 Threshold", 348 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0), 349 SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0), 350 SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0), 351 SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL, 352 CS35L41_AMP_INV_PCM_SHIFT, 1, 0), 353 SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL, 354 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0), 355 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), 356 WM_ADSP_FW_CONTROL("DSP1", 0), 357 }; 358 359 static irqreturn_t cs35l41_irq(int irq, void *data) 360 { 361 struct cs35l41_private *cs35l41 = data; 362 unsigned int status[4] = { 0, 0, 0, 0 }; 363 unsigned int masks[4] = { 0, 0, 0, 0 }; 364 int ret = IRQ_NONE; 365 unsigned int i; 366 367 pm_runtime_get_sync(cs35l41->dev); 368 369 for (i = 0; i < ARRAY_SIZE(status); i++) { 370 regmap_read(cs35l41->regmap, 371 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE), 372 &status[i]); 373 regmap_read(cs35l41->regmap, 374 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE), 375 &masks[i]); 376 } 377 378 /* Check to see if unmasked bits are active */ 379 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && 380 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) 381 goto done; 382 383 if (status[3] & CS35L41_OTP_BOOT_DONE) { 384 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4, 385 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE); 386 } 387 388 /* 389 * The following interrupts require a 390 * protection release cycle to get the 391 * speaker out of Safe-Mode. 392 */ 393 if (status[0] & CS35L41_AMP_SHORT_ERR) { 394 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n"); 395 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 396 CS35L41_AMP_SHORT_ERR); 397 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 398 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 399 CS35L41_AMP_SHORT_ERR_RLS, 400 CS35L41_AMP_SHORT_ERR_RLS); 401 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 402 CS35L41_AMP_SHORT_ERR_RLS, 0); 403 ret = IRQ_HANDLED; 404 } 405 406 if (status[0] & CS35L41_TEMP_WARN) { 407 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n"); 408 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 409 CS35L41_TEMP_WARN); 410 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 411 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 412 CS35L41_TEMP_WARN_ERR_RLS, 413 CS35L41_TEMP_WARN_ERR_RLS); 414 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 415 CS35L41_TEMP_WARN_ERR_RLS, 0); 416 ret = IRQ_HANDLED; 417 } 418 419 if (status[0] & CS35L41_TEMP_ERR) { 420 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n"); 421 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 422 CS35L41_TEMP_ERR); 423 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 424 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 425 CS35L41_TEMP_ERR_RLS, 426 CS35L41_TEMP_ERR_RLS); 427 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 428 CS35L41_TEMP_ERR_RLS, 0); 429 ret = IRQ_HANDLED; 430 } 431 432 if (status[0] & CS35L41_BST_OVP_ERR) { 433 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n"); 434 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 435 CS35L41_BST_EN_MASK, 0); 436 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 437 CS35L41_BST_OVP_ERR); 438 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 439 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 440 CS35L41_BST_OVP_ERR_RLS, 441 CS35L41_BST_OVP_ERR_RLS); 442 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 443 CS35L41_BST_OVP_ERR_RLS, 0); 444 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 445 CS35L41_BST_EN_MASK, 446 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 447 ret = IRQ_HANDLED; 448 } 449 450 if (status[0] & CS35L41_BST_DCM_UVP_ERR) { 451 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n"); 452 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 453 CS35L41_BST_EN_MASK, 0); 454 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 455 CS35L41_BST_DCM_UVP_ERR); 456 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 457 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 458 CS35L41_BST_UVP_ERR_RLS, 459 CS35L41_BST_UVP_ERR_RLS); 460 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 461 CS35L41_BST_UVP_ERR_RLS, 0); 462 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 463 CS35L41_BST_EN_MASK, 464 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 465 ret = IRQ_HANDLED; 466 } 467 468 if (status[0] & CS35L41_BST_SHORT_ERR) { 469 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n"); 470 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 471 CS35L41_BST_EN_MASK, 0); 472 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 473 CS35L41_BST_SHORT_ERR); 474 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 475 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 476 CS35L41_BST_SHORT_ERR_RLS, 477 CS35L41_BST_SHORT_ERR_RLS); 478 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 479 CS35L41_BST_SHORT_ERR_RLS, 0); 480 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 481 CS35L41_BST_EN_MASK, 482 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 483 ret = IRQ_HANDLED; 484 } 485 486 done: 487 pm_runtime_mark_last_busy(cs35l41->dev); 488 pm_runtime_put_autosuspend(cs35l41->dev); 489 490 return ret; 491 } 492 493 static const struct reg_sequence cs35l41_pup_patch[] = { 494 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 495 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 496 { 0x00002084, 0x002F1AA0 }, 497 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 498 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 499 }; 500 501 static const struct reg_sequence cs35l41_pdn_patch[] = { 502 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 503 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 504 { 0x00002084, 0x002F1AA3 }, 505 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 506 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 507 }; 508 509 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, 510 struct snd_kcontrol *kcontrol, int event) 511 { 512 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 513 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 514 unsigned int val; 515 int ret = 0; 516 517 switch (event) { 518 case SND_SOC_DAPM_PRE_PMU: 519 regmap_multi_reg_write_bypassed(cs35l41->regmap, 520 cs35l41_pup_patch, 521 ARRAY_SIZE(cs35l41_pup_patch)); 522 523 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 1); 524 break; 525 case SND_SOC_DAPM_POST_PMD: 526 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 0); 527 528 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 529 val, val & CS35L41_PDN_DONE_MASK, 530 1000, 100000); 531 if (ret) 532 dev_warn(cs35l41->dev, "PDN failed: %d\n", ret); 533 534 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 535 CS35L41_PDN_DONE_MASK); 536 537 regmap_multi_reg_write_bypassed(cs35l41->regmap, 538 cs35l41_pdn_patch, 539 ARRAY_SIZE(cs35l41_pdn_patch)); 540 break; 541 default: 542 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); 543 ret = -EINVAL; 544 } 545 546 return ret; 547 } 548 549 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { 550 SND_SOC_DAPM_SPK("DSP1 Preload", NULL), 551 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, 552 cs35l41_dsp_preload_ev, 553 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 554 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, 555 cs35l41_dsp_audio_ev, 556 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 557 558 SND_SOC_DAPM_OUTPUT("SPK"), 559 560 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0), 561 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0), 562 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0), 563 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0), 564 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0), 565 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0), 566 567 SND_SOC_DAPM_SIGGEN("VSENSE"), 568 SND_SOC_DAPM_SIGGEN("ISENSE"), 569 SND_SOC_DAPM_SIGGEN("VP"), 570 SND_SOC_DAPM_SIGGEN("VBST"), 571 SND_SOC_DAPM_SIGGEN("TEMP"), 572 573 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0), 574 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0), 575 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0), 576 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0), 577 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0), 578 579 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0), 580 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0), 581 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 582 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0), 583 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 584 585 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0), 586 587 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0, 588 cs35l41_main_amp_event, 589 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 590 591 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux), 592 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux), 593 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux), 594 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux), 595 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux), 596 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux), 597 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux), 598 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl), 599 }; 600 601 static const struct snd_soc_dapm_route cs35l41_audio_map[] = { 602 {"DSP RX1 Source", "ASPRX1", "ASPRX1"}, 603 {"DSP RX1 Source", "ASPRX2", "ASPRX2"}, 604 {"DSP RX2 Source", "ASPRX1", "ASPRX1"}, 605 {"DSP RX2 Source", "ASPRX2", "ASPRX2"}, 606 607 {"DSP1", NULL, "DSP RX1 Source"}, 608 {"DSP1", NULL, "DSP RX2 Source"}, 609 610 {"ASP TX1 Source", "VMON", "VMON ADC"}, 611 {"ASP TX1 Source", "IMON", "IMON ADC"}, 612 {"ASP TX1 Source", "VPMON", "VPMON ADC"}, 613 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"}, 614 {"ASP TX1 Source", "DSPTX1", "DSP1"}, 615 {"ASP TX1 Source", "DSPTX2", "DSP1"}, 616 {"ASP TX1 Source", "ASPRX1", "ASPRX1" }, 617 {"ASP TX1 Source", "ASPRX2", "ASPRX2" }, 618 {"ASP TX2 Source", "VMON", "VMON ADC"}, 619 {"ASP TX2 Source", "IMON", "IMON ADC"}, 620 {"ASP TX2 Source", "VPMON", "VPMON ADC"}, 621 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"}, 622 {"ASP TX2 Source", "DSPTX1", "DSP1"}, 623 {"ASP TX2 Source", "DSPTX2", "DSP1"}, 624 {"ASP TX2 Source", "ASPRX1", "ASPRX1" }, 625 {"ASP TX2 Source", "ASPRX2", "ASPRX2" }, 626 {"ASP TX3 Source", "VMON", "VMON ADC"}, 627 {"ASP TX3 Source", "IMON", "IMON ADC"}, 628 {"ASP TX3 Source", "VPMON", "VPMON ADC"}, 629 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"}, 630 {"ASP TX3 Source", "DSPTX1", "DSP1"}, 631 {"ASP TX3 Source", "DSPTX2", "DSP1"}, 632 {"ASP TX3 Source", "ASPRX1", "ASPRX1" }, 633 {"ASP TX3 Source", "ASPRX2", "ASPRX2" }, 634 {"ASP TX4 Source", "VMON", "VMON ADC"}, 635 {"ASP TX4 Source", "IMON", "IMON ADC"}, 636 {"ASP TX4 Source", "VPMON", "VPMON ADC"}, 637 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"}, 638 {"ASP TX4 Source", "DSPTX1", "DSP1"}, 639 {"ASP TX4 Source", "DSPTX2", "DSP1"}, 640 {"ASP TX4 Source", "ASPRX1", "ASPRX1" }, 641 {"ASP TX4 Source", "ASPRX2", "ASPRX2" }, 642 {"ASPTX1", NULL, "ASP TX1 Source"}, 643 {"ASPTX2", NULL, "ASP TX2 Source"}, 644 {"ASPTX3", NULL, "ASP TX3 Source"}, 645 {"ASPTX4", NULL, "ASP TX4 Source"}, 646 {"AMP Capture", NULL, "ASPTX1"}, 647 {"AMP Capture", NULL, "ASPTX2"}, 648 {"AMP Capture", NULL, "ASPTX3"}, 649 {"AMP Capture", NULL, "ASPTX4"}, 650 651 {"DSP1", NULL, "VMON"}, 652 {"DSP1", NULL, "IMON"}, 653 {"DSP1", NULL, "VPMON"}, 654 {"DSP1", NULL, "VBSTMON"}, 655 {"DSP1", NULL, "TEMPMON"}, 656 657 {"VMON ADC", NULL, "VMON"}, 658 {"IMON ADC", NULL, "IMON"}, 659 {"VPMON ADC", NULL, "VPMON"}, 660 {"VBSTMON ADC", NULL, "VBSTMON"}, 661 {"TEMPMON ADC", NULL, "TEMPMON"}, 662 663 {"VMON ADC", NULL, "VSENSE"}, 664 {"IMON ADC", NULL, "ISENSE"}, 665 {"VPMON ADC", NULL, "VP"}, 666 {"VBSTMON ADC", NULL, "VBST"}, 667 {"TEMPMON ADC", NULL, "TEMP"}, 668 669 {"DSP1 Preload", NULL, "DSP1 Preloader"}, 670 {"DSP1", NULL, "DSP1 Preloader"}, 671 672 {"ASPRX1", NULL, "AMP Playback"}, 673 {"ASPRX2", NULL, "AMP Playback"}, 674 {"DRE", "Switch", "CLASS H"}, 675 {"Main AMP", NULL, "CLASS H"}, 676 {"Main AMP", NULL, "DRE"}, 677 {"SPK", NULL, "Main AMP"}, 678 679 {"PCM Source", "ASP", "ASPRX1"}, 680 {"PCM Source", "DSP", "DSP1"}, 681 {"CLASS H", NULL, "PCM Source"}, 682 }; 683 684 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n, 685 unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot) 686 { 687 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 688 689 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot); 690 } 691 692 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 693 { 694 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 695 unsigned int daifmt = 0; 696 697 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 698 case SND_SOC_DAIFMT_CBP_CFP: 699 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK; 700 break; 701 case SND_SOC_DAIFMT_CBC_CFC: 702 break; 703 default: 704 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n"); 705 return -EINVAL; 706 } 707 708 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 709 case SND_SOC_DAIFMT_DSP_A: 710 break; 711 case SND_SOC_DAIFMT_I2S: 712 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT; 713 break; 714 default: 715 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n"); 716 return -EINVAL; 717 } 718 719 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 720 case SND_SOC_DAIFMT_NB_IF: 721 daifmt |= CS35L41_LRCLK_INV_MASK; 722 break; 723 case SND_SOC_DAIFMT_IB_NF: 724 daifmt |= CS35L41_SCLK_INV_MASK; 725 break; 726 case SND_SOC_DAIFMT_IB_IF: 727 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK; 728 break; 729 case SND_SOC_DAIFMT_NB_NF: 730 break; 731 default: 732 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n"); 733 return -EINVAL; 734 } 735 736 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 737 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK | 738 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK | 739 CS35L41_SCLK_INV_MASK, daifmt); 740 } 741 742 struct cs35l41_global_fs_config { 743 int rate; 744 int fs_cfg; 745 }; 746 747 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = { 748 { 12000, 0x01 }, 749 { 24000, 0x02 }, 750 { 48000, 0x03 }, 751 { 96000, 0x04 }, 752 { 192000, 0x05 }, 753 { 11025, 0x09 }, 754 { 22050, 0x0A }, 755 { 44100, 0x0B }, 756 { 88200, 0x0C }, 757 { 176400, 0x0D }, 758 { 8000, 0x11 }, 759 { 16000, 0x12 }, 760 { 32000, 0x13 }, 761 }; 762 763 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, 764 struct snd_pcm_hw_params *params, 765 struct snd_soc_dai *dai) 766 { 767 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 768 unsigned int rate = params_rate(params); 769 u8 asp_wl; 770 int i; 771 772 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { 773 if (rate == cs35l41_fs_rates[i].rate) 774 break; 775 } 776 777 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) { 778 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate); 779 return -EINVAL; 780 } 781 782 asp_wl = params_width(params); 783 784 if (i < ARRAY_SIZE(cs35l41_fs_rates)) 785 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, 786 CS35L41_GLOBAL_FS_MASK, 787 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT); 788 789 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 790 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 791 CS35L41_ASP_WIDTH_RX_MASK, 792 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT); 793 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, 794 CS35L41_ASP_RX_WL_MASK, 795 asp_wl << CS35L41_ASP_RX_WL_SHIFT); 796 } else { 797 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 798 CS35L41_ASP_WIDTH_TX_MASK, 799 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT); 800 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, 801 CS35L41_ASP_TX_WL_MASK, 802 asp_wl << CS35L41_ASP_TX_WL_SHIFT); 803 } 804 805 return 0; 806 } 807 808 static int cs35l41_get_clk_config(int freq) 809 { 810 int i; 811 812 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) { 813 if (cs35l41_pll_sysclk[i].freq == freq) 814 return cs35l41_pll_sysclk[i].clk_cfg; 815 } 816 817 return -EINVAL; 818 } 819 820 static const unsigned int cs35l41_src_rates[] = { 821 8000, 12000, 11025, 16000, 22050, 24000, 32000, 822 44100, 48000, 88200, 96000, 176400, 192000 823 }; 824 825 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = { 826 .count = ARRAY_SIZE(cs35l41_src_rates), 827 .list = cs35l41_src_rates, 828 }; 829 830 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream, 831 struct snd_soc_dai *dai) 832 { 833 if (substream->runtime) 834 return snd_pcm_hw_constraint_list(substream->runtime, 0, 835 SNDRV_PCM_HW_PARAM_RATE, 836 &cs35l41_constraints); 837 return 0; 838 } 839 840 static int cs35l41_component_set_sysclk(struct snd_soc_component *component, 841 int clk_id, int source, 842 unsigned int freq, int dir) 843 { 844 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 845 int extclk_cfg, clksrc; 846 847 switch (clk_id) { 848 case CS35L41_CLKID_SCLK: 849 clksrc = CS35L41_PLLSRC_SCLK; 850 break; 851 case CS35L41_CLKID_LRCLK: 852 clksrc = CS35L41_PLLSRC_LRCLK; 853 break; 854 case CS35L41_CLKID_MCLK: 855 clksrc = CS35L41_PLLSRC_MCLK; 856 break; 857 default: 858 dev_err(cs35l41->dev, "Invalid CLK Config\n"); 859 return -EINVAL; 860 } 861 862 extclk_cfg = cs35l41_get_clk_config(freq); 863 864 if (extclk_cfg < 0) { 865 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n", 866 extclk_cfg, freq); 867 return -EINVAL; 868 } 869 870 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 871 CS35L41_PLL_OPENLOOP_MASK, 872 1 << CS35L41_PLL_OPENLOOP_SHIFT); 873 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 874 CS35L41_REFCLK_FREQ_MASK, 875 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT); 876 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 877 CS35L41_PLL_CLK_EN_MASK, 878 0 << CS35L41_PLL_CLK_EN_SHIFT); 879 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 880 CS35L41_PLL_CLK_SEL_MASK, clksrc); 881 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 882 CS35L41_PLL_OPENLOOP_MASK, 883 0 << CS35L41_PLL_OPENLOOP_SHIFT); 884 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 885 CS35L41_PLL_CLK_EN_MASK, 886 1 << CS35L41_PLL_CLK_EN_SHIFT); 887 888 return 0; 889 } 890 891 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, 892 int clk_id, unsigned int freq, int dir) 893 { 894 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 895 unsigned int fs1_val; 896 unsigned int fs2_val; 897 unsigned int val; 898 int fsindex; 899 900 fsindex = cs35l41_get_fs_mon_config_index(freq); 901 if (fsindex < 0) { 902 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq); 903 return -EINVAL; 904 } 905 906 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq); 907 908 if (freq <= 6144000) { 909 /* Use the lookup table */ 910 fs1_val = cs35l41_fs_mon[fsindex].fs1; 911 fs2_val = cs35l41_fs_mon[fsindex].fs2; 912 } else { 913 /* Use hard-coded values */ 914 fs1_val = 0x10; 915 fs2_val = 0x24; 916 } 917 918 val = fs1_val; 919 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK; 920 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val); 921 922 return 0; 923 } 924 925 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) 926 { 927 struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; 928 int ret; 929 930 if (!hw_cfg->valid) 931 return -EINVAL; 932 933 if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) 934 return -EINVAL; 935 936 /* Required */ 937 ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg); 938 if (ret) 939 return ret; 940 941 /* Optional */ 942 if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0) 943 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK, 944 hw_cfg->dout_hiz); 945 946 return 0; 947 } 948 949 static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = { 950 {"Main AMP", NULL, "VSPK"}, 951 }; 952 953 static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = { 954 SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0), 955 }; 956 957 static int cs35l41_component_probe(struct snd_soc_component *component) 958 { 959 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 960 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 961 int ret; 962 963 if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) { 964 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget, 965 ARRAY_SIZE(cs35l41_ext_bst_widget)); 966 if (ret) 967 return ret; 968 969 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes, 970 ARRAY_SIZE(cs35l41_ext_bst_routes)); 971 if (ret) 972 return ret; 973 } 974 975 return wm_adsp2_component_probe(&cs35l41->dsp, component); 976 } 977 978 static void cs35l41_component_remove(struct snd_soc_component *component) 979 { 980 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 981 982 wm_adsp2_component_remove(&cs35l41->dsp, component); 983 } 984 985 static const struct snd_soc_dai_ops cs35l41_ops = { 986 .startup = cs35l41_pcm_startup, 987 .set_fmt = cs35l41_set_dai_fmt, 988 .hw_params = cs35l41_pcm_hw_params, 989 .set_sysclk = cs35l41_dai_set_sysclk, 990 .set_channel_map = cs35l41_set_channel_map, 991 }; 992 993 static struct snd_soc_dai_driver cs35l41_dai[] = { 994 { 995 .name = "cs35l41-pcm", 996 .id = 0, 997 .playback = { 998 .stream_name = "AMP Playback", 999 .channels_min = 1, 1000 .channels_max = 2, 1001 .rates = SNDRV_PCM_RATE_KNOT, 1002 .formats = CS35L41_RX_FORMATS, 1003 }, 1004 .capture = { 1005 .stream_name = "AMP Capture", 1006 .channels_min = 1, 1007 .channels_max = 4, 1008 .rates = SNDRV_PCM_RATE_KNOT, 1009 .formats = CS35L41_TX_FORMATS, 1010 }, 1011 .ops = &cs35l41_ops, 1012 .symmetric_rate = 1, 1013 }, 1014 }; 1015 1016 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = { 1017 .name = "cs35l41-codec", 1018 .probe = cs35l41_component_probe, 1019 .remove = cs35l41_component_remove, 1020 1021 .dapm_widgets = cs35l41_dapm_widgets, 1022 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets), 1023 .dapm_routes = cs35l41_audio_map, 1024 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map), 1025 1026 .controls = cs35l41_aud_controls, 1027 .num_controls = ARRAY_SIZE(cs35l41_aud_controls), 1028 .set_sysclk = cs35l41_component_set_sysclk, 1029 1030 .endianness = 1, 1031 }; 1032 1033 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg) 1034 { 1035 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; 1036 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; 1037 unsigned int val; 1038 int ret; 1039 1040 ret = device_property_read_u32(dev, "cirrus,boost-type", &val); 1041 if (ret >= 0) 1042 hw_cfg->bst_type = val; 1043 1044 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); 1045 if (ret >= 0) 1046 hw_cfg->bst_ipk = val; 1047 else 1048 hw_cfg->bst_ipk = -1; 1049 1050 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val); 1051 if (ret >= 0) 1052 hw_cfg->bst_ind = val; 1053 else 1054 hw_cfg->bst_ind = -1; 1055 1056 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val); 1057 if (ret >= 0) 1058 hw_cfg->bst_cap = val; 1059 else 1060 hw_cfg->bst_cap = -1; 1061 1062 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val); 1063 if (ret >= 0) 1064 hw_cfg->dout_hiz = val; 1065 else 1066 hw_cfg->dout_hiz = -1; 1067 1068 /* GPIO1 Pin Config */ 1069 gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert"); 1070 gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable"); 1071 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val); 1072 if (ret >= 0) { 1073 gpio1->func = val; 1074 gpio1->valid = true; 1075 } 1076 1077 /* GPIO2 Pin Config */ 1078 gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert"); 1079 gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable"); 1080 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val); 1081 if (ret >= 0) { 1082 gpio2->func = val; 1083 gpio2->valid = true; 1084 } 1085 1086 hw_cfg->valid = true; 1087 1088 return 0; 1089 } 1090 1091 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) 1092 { 1093 struct wm_adsp *dsp; 1094 int ret; 1095 1096 dsp = &cs35l41->dsp; 1097 dsp->part = "cs35l41"; 1098 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */ 1099 dsp->toggle_preload = true; 1100 1101 cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp); 1102 1103 ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap); 1104 if (ret < 0) 1105 return ret; 1106 1107 ret = wm_halo_init(dsp); 1108 if (ret) { 1109 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret); 1110 return ret; 1111 } 1112 1113 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, 1114 CS35L41_INPUT_SRC_VPMON); 1115 if (ret < 0) { 1116 dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret); 1117 goto err_dsp; 1118 } 1119 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, 1120 CS35L41_INPUT_SRC_CLASSH); 1121 if (ret < 0) { 1122 dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret); 1123 goto err_dsp; 1124 } 1125 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, 1126 CS35L41_INPUT_SRC_TEMPMON); 1127 if (ret < 0) { 1128 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret); 1129 goto err_dsp; 1130 } 1131 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, 1132 CS35L41_INPUT_SRC_RSVD); 1133 if (ret < 0) { 1134 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret); 1135 goto err_dsp; 1136 } 1137 1138 return 0; 1139 1140 err_dsp: 1141 wm_adsp2_remove(dsp); 1142 1143 return ret; 1144 } 1145 1146 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41) 1147 { 1148 acpi_handle handle = ACPI_HANDLE(cs35l41->dev); 1149 const char *sub; 1150 1151 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */ 1152 if (!handle) 1153 return 0; 1154 1155 sub = acpi_get_subsystem_id(handle); 1156 if (IS_ERR(sub)) { 1157 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */ 1158 if (PTR_ERR(sub) == -ENODATA) 1159 return 0; 1160 else 1161 return PTR_ERR(sub); 1162 } 1163 1164 cs35l41->dsp.system_name = sub; 1165 dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name); 1166 1167 return 0; 1168 } 1169 1170 int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg) 1171 { 1172 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; 1173 int irq_pol = 0; 1174 int ret; 1175 1176 if (hw_cfg) { 1177 cs35l41->hw_cfg = *hw_cfg; 1178 } else { 1179 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg); 1180 if (ret != 0) 1181 return ret; 1182 } 1183 1184 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++) 1185 cs35l41->supplies[i].supply = cs35l41_supplies[i]; 1186 1187 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES, 1188 cs35l41->supplies); 1189 if (ret != 0) { 1190 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret); 1191 return ret; 1192 } 1193 1194 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1195 if (ret != 0) { 1196 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret); 1197 return ret; 1198 } 1199 1200 /* returning NULL can be an option if in stereo mode */ 1201 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset", 1202 GPIOD_OUT_LOW); 1203 if (IS_ERR(cs35l41->reset_gpio)) { 1204 ret = PTR_ERR(cs35l41->reset_gpio); 1205 cs35l41->reset_gpio = NULL; 1206 if (ret == -EBUSY) { 1207 dev_info(cs35l41->dev, 1208 "Reset line busy, assuming shared reset\n"); 1209 } else { 1210 dev_err(cs35l41->dev, 1211 "Failed to get reset GPIO: %d\n", ret); 1212 goto err; 1213 } 1214 } 1215 if (cs35l41->reset_gpio) { 1216 /* satisfy minimum reset pulse width spec */ 1217 usleep_range(2000, 2100); 1218 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1); 1219 } 1220 1221 usleep_range(2000, 2100); 1222 1223 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4, 1224 int_status, int_status & CS35L41_OTP_BOOT_DONE, 1225 1000, 100000); 1226 if (ret) { 1227 dev_err(cs35l41->dev, 1228 "Failed waiting for OTP_BOOT_DONE: %d\n", ret); 1229 goto err; 1230 } 1231 1232 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status); 1233 if (int_status & CS35L41_OTP_BOOT_ERR) { 1234 dev_err(cs35l41->dev, "OTP Boot error\n"); 1235 ret = -EINVAL; 1236 goto err; 1237 } 1238 1239 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); 1240 if (ret < 0) { 1241 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret); 1242 goto err; 1243 } 1244 1245 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); 1246 if (ret < 0) { 1247 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret); 1248 goto err; 1249 } 1250 1251 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; 1252 1253 /* CS35L41 will have even MTLREVID 1254 * CS35L41R will have odd MTLREVID 1255 */ 1256 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; 1257 if (regid != chipid_match) { 1258 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n", 1259 regid, chipid_match); 1260 ret = -ENODEV; 1261 goto err; 1262 } 1263 1264 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1265 1266 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid); 1267 if (ret) 1268 goto err; 1269 1270 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap); 1271 if (ret < 0) { 1272 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret); 1273 goto err; 1274 } 1275 1276 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1277 1278 irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg); 1279 1280 /* Set interrupt masks for critical errors */ 1281 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 1282 CS35L41_INT1_MASK_DEFAULT); 1283 1284 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq, 1285 IRQF_ONESHOT | IRQF_SHARED | irq_pol, 1286 "cs35l41", cs35l41); 1287 if (ret != 0) { 1288 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret); 1289 goto err; 1290 } 1291 1292 ret = cs35l41_set_pdata(cs35l41); 1293 if (ret < 0) { 1294 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret); 1295 goto err; 1296 } 1297 1298 ret = cs35l41_acpi_get_name(cs35l41); 1299 if (ret < 0) 1300 goto err; 1301 1302 ret = cs35l41_dsp_init(cs35l41); 1303 if (ret < 0) 1304 goto err; 1305 1306 pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000); 1307 pm_runtime_use_autosuspend(cs35l41->dev); 1308 pm_runtime_mark_last_busy(cs35l41->dev); 1309 pm_runtime_set_active(cs35l41->dev); 1310 pm_runtime_get_noresume(cs35l41->dev); 1311 pm_runtime_enable(cs35l41->dev); 1312 1313 ret = devm_snd_soc_register_component(cs35l41->dev, 1314 &soc_component_dev_cs35l41, 1315 cs35l41_dai, ARRAY_SIZE(cs35l41_dai)); 1316 if (ret < 0) { 1317 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret); 1318 goto err_pm; 1319 } 1320 1321 pm_runtime_put_autosuspend(cs35l41->dev); 1322 1323 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", 1324 regid, reg_revid); 1325 1326 return 0; 1327 1328 err_pm: 1329 pm_runtime_disable(cs35l41->dev); 1330 pm_runtime_put_noidle(cs35l41->dev); 1331 1332 wm_adsp2_remove(&cs35l41->dsp); 1333 err: 1334 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1335 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1336 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1337 1338 return ret; 1339 } 1340 EXPORT_SYMBOL_GPL(cs35l41_probe); 1341 1342 void cs35l41_remove(struct cs35l41_private *cs35l41) 1343 { 1344 pm_runtime_get_sync(cs35l41->dev); 1345 pm_runtime_disable(cs35l41->dev); 1346 1347 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); 1348 kfree(cs35l41->dsp.system_name); 1349 wm_adsp2_remove(&cs35l41->dsp); 1350 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1351 1352 pm_runtime_put_noidle(cs35l41->dev); 1353 1354 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1355 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1356 } 1357 EXPORT_SYMBOL_GPL(cs35l41_remove); 1358 1359 static int __maybe_unused cs35l41_runtime_suspend(struct device *dev) 1360 { 1361 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1362 1363 dev_dbg(cs35l41->dev, "Runtime suspend\n"); 1364 1365 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1366 return 0; 1367 1368 cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type); 1369 1370 regcache_cache_only(cs35l41->regmap, true); 1371 regcache_mark_dirty(cs35l41->regmap); 1372 1373 return 0; 1374 } 1375 1376 static int __maybe_unused cs35l41_runtime_resume(struct device *dev) 1377 { 1378 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1379 int ret; 1380 1381 dev_dbg(cs35l41->dev, "Runtime resume\n"); 1382 1383 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running) 1384 return 0; 1385 1386 regcache_cache_only(cs35l41->regmap, false); 1387 1388 ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap); 1389 if (ret) 1390 return ret; 1391 1392 /* Test key needs to be unlocked to allow the OTP settings to re-apply */ 1393 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap); 1394 ret = regcache_sync(cs35l41->regmap); 1395 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); 1396 if (ret) { 1397 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret); 1398 return ret; 1399 } 1400 cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg); 1401 1402 return 0; 1403 } 1404 1405 static int __maybe_unused cs35l41_sys_suspend(struct device *dev) 1406 { 1407 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1408 1409 dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n"); 1410 disable_irq(cs35l41->irq); 1411 1412 return 0; 1413 } 1414 1415 static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev) 1416 { 1417 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1418 1419 dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n"); 1420 enable_irq(cs35l41->irq); 1421 1422 return 0; 1423 } 1424 1425 static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev) 1426 { 1427 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1428 1429 dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n"); 1430 disable_irq(cs35l41->irq); 1431 1432 return 0; 1433 } 1434 1435 static int __maybe_unused cs35l41_sys_resume(struct device *dev) 1436 { 1437 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev); 1438 1439 dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n"); 1440 enable_irq(cs35l41->irq); 1441 1442 return 0; 1443 } 1444 1445 const struct dev_pm_ops cs35l41_pm_ops = { 1446 SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL) 1447 1448 SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume) 1449 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq) 1450 }; 1451 EXPORT_SYMBOL_GPL(cs35l41_pm_ops); 1452 1453 MODULE_DESCRIPTION("ASoC CS35L41 driver"); 1454 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1455 MODULE_LICENSE("GPL"); 1456