1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41-lib.c -- CS35L41 Common functions for HDA and ASoC Audio drivers 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 // Author: Lucas Tanure <lucas.tanure@cirrus.com> 9 10 #include <linux/dev_printk.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/slab.h> 15 #include <linux/firmware/cirrus/wmfw.h> 16 17 #include <sound/cs35l41.h> 18 19 static const struct reg_default cs35l41_reg[] = { 20 { CS35L41_PWR_CTRL1, 0x00000000 }, 21 { CS35L41_PWR_CTRL2, 0x00000000 }, 22 { CS35L41_PWR_CTRL3, 0x01000010 }, 23 { CS35L41_GPIO_PAD_CONTROL, 0x00000000 }, 24 { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 }, 25 { CS35L41_TST_FS_MON0, 0x00020016 }, 26 { CS35L41_BSTCVRT_COEFF, 0x00002424 }, 27 { CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 }, 28 { CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A }, 29 { CS35L41_SP_ENABLES, 0x00000000 }, 30 { CS35L41_SP_RATE_CTRL, 0x00000028 }, 31 { CS35L41_SP_FORMAT, 0x18180200 }, 32 { CS35L41_SP_HIZ_CTRL, 0x00000002 }, 33 { CS35L41_SP_FRAME_TX_SLOT, 0x03020100 }, 34 { CS35L41_SP_FRAME_RX_SLOT, 0x00000100 }, 35 { CS35L41_SP_TX_WL, 0x00000018 }, 36 { CS35L41_SP_RX_WL, 0x00000018 }, 37 { CS35L41_DAC_PCM1_SRC, 0x00000008 }, 38 { CS35L41_ASP_TX1_SRC, 0x00000018 }, 39 { CS35L41_ASP_TX2_SRC, 0x00000019 }, 40 { CS35L41_ASP_TX3_SRC, 0x00000020 }, 41 { CS35L41_ASP_TX4_SRC, 0x00000021 }, 42 { CS35L41_DSP1_RX1_SRC, 0x00000008 }, 43 { CS35L41_DSP1_RX2_SRC, 0x00000009 }, 44 { CS35L41_DSP1_RX3_SRC, 0x00000018 }, 45 { CS35L41_DSP1_RX4_SRC, 0x00000019 }, 46 { CS35L41_DSP1_RX5_SRC, 0x00000020 }, 47 { CS35L41_DSP1_RX6_SRC, 0x00000021 }, 48 { CS35L41_DSP1_RX7_SRC, 0x0000003A }, 49 { CS35L41_DSP1_RX8_SRC, 0x00000001 }, 50 { CS35L41_NGATE1_SRC, 0x00000008 }, 51 { CS35L41_NGATE2_SRC, 0x00000009 }, 52 { CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 }, 53 { CS35L41_CLASSH_CFG, 0x000B0405 }, 54 { CS35L41_WKFET_CFG, 0x00000111 }, 55 { CS35L41_NG_CFG, 0x00000033 }, 56 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 57 { CS35L41_IRQ1_MASK1, 0xFFFFFFFF }, 58 { CS35L41_IRQ1_MASK2, 0xFFFFFFFF }, 59 { CS35L41_IRQ1_MASK3, 0xFFFF87FF }, 60 { CS35L41_IRQ1_MASK4, 0xFEFFFFFF }, 61 { CS35L41_GPIO1_CTRL1, 0xE1000001 }, 62 { CS35L41_GPIO2_CTRL1, 0xE1000001 }, 63 { CS35L41_MIXER_NGATE_CFG, 0x00000000 }, 64 { CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 }, 65 { CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 }, 66 { CS35L41_DSP1_CCM_CORE_CTRL, 0x00000101 }, 67 }; 68 69 static bool cs35l41_readable_reg(struct device *dev, unsigned int reg) 70 { 71 switch (reg) { 72 case CS35L41_DEVID: 73 case CS35L41_REVID: 74 case CS35L41_FABID: 75 case CS35L41_RELID: 76 case CS35L41_OTPID: 77 case CS35L41_TEST_KEY_CTL: 78 case CS35L41_USER_KEY_CTL: 79 case CS35L41_OTP_CTRL0: 80 case CS35L41_OTP_CTRL3: 81 case CS35L41_OTP_CTRL4: 82 case CS35L41_OTP_CTRL5: 83 case CS35L41_OTP_CTRL6: 84 case CS35L41_OTP_CTRL7: 85 case CS35L41_OTP_CTRL8: 86 case CS35L41_PWR_CTRL1: 87 case CS35L41_PWR_CTRL2: 88 case CS35L41_PWR_CTRL3: 89 case CS35L41_CTRL_OVRRIDE: 90 case CS35L41_AMP_OUT_MUTE: 91 case CS35L41_PROTECT_REL_ERR_IGN: 92 case CS35L41_GPIO_PAD_CONTROL: 93 case CS35L41_JTAG_CONTROL: 94 case CS35L41_PWRMGT_CTL: 95 case CS35L41_WAKESRC_CTL: 96 case CS35L41_PWRMGT_STS: 97 case CS35L41_PLL_CLK_CTRL: 98 case CS35L41_DSP_CLK_CTRL: 99 case CS35L41_GLOBAL_CLK_CTRL: 100 case CS35L41_DATA_FS_SEL: 101 case CS35L41_TST_FS_MON0: 102 case CS35L41_MDSYNC_EN: 103 case CS35L41_MDSYNC_TX_ID: 104 case CS35L41_MDSYNC_PWR_CTRL: 105 case CS35L41_MDSYNC_DATA_TX: 106 case CS35L41_MDSYNC_TX_STATUS: 107 case CS35L41_MDSYNC_DATA_RX: 108 case CS35L41_MDSYNC_RX_STATUS: 109 case CS35L41_MDSYNC_ERR_STATUS: 110 case CS35L41_MDSYNC_SYNC_PTE2: 111 case CS35L41_MDSYNC_SYNC_PTE3: 112 case CS35L41_MDSYNC_SYNC_MSM_STATUS: 113 case CS35L41_BSTCVRT_VCTRL1: 114 case CS35L41_BSTCVRT_VCTRL2: 115 case CS35L41_BSTCVRT_PEAK_CUR: 116 case CS35L41_BSTCVRT_SFT_RAMP: 117 case CS35L41_BSTCVRT_COEFF: 118 case CS35L41_BSTCVRT_SLOPE_LBST: 119 case CS35L41_BSTCVRT_SW_FREQ: 120 case CS35L41_BSTCVRT_DCM_CTRL: 121 case CS35L41_BSTCVRT_DCM_MODE_FORCE: 122 case CS35L41_BSTCVRT_OVERVOLT_CTRL: 123 case CS35L41_VI_VOL_POL: 124 case CS35L41_DTEMP_WARN_THLD: 125 case CS35L41_DTEMP_CFG: 126 case CS35L41_DTEMP_EN: 127 case CS35L41_VPVBST_FS_SEL: 128 case CS35L41_SP_ENABLES: 129 case CS35L41_SP_RATE_CTRL: 130 case CS35L41_SP_FORMAT: 131 case CS35L41_SP_HIZ_CTRL: 132 case CS35L41_SP_FRAME_TX_SLOT: 133 case CS35L41_SP_FRAME_RX_SLOT: 134 case CS35L41_SP_TX_WL: 135 case CS35L41_SP_RX_WL: 136 case CS35L41_DAC_PCM1_SRC: 137 case CS35L41_ASP_TX1_SRC: 138 case CS35L41_ASP_TX2_SRC: 139 case CS35L41_ASP_TX3_SRC: 140 case CS35L41_ASP_TX4_SRC: 141 case CS35L41_DSP1_RX1_SRC: 142 case CS35L41_DSP1_RX2_SRC: 143 case CS35L41_DSP1_RX3_SRC: 144 case CS35L41_DSP1_RX4_SRC: 145 case CS35L41_DSP1_RX5_SRC: 146 case CS35L41_DSP1_RX6_SRC: 147 case CS35L41_DSP1_RX7_SRC: 148 case CS35L41_DSP1_RX8_SRC: 149 case CS35L41_NGATE1_SRC: 150 case CS35L41_NGATE2_SRC: 151 case CS35L41_AMP_DIG_VOL_CTRL: 152 case CS35L41_VPBR_CFG: 153 case CS35L41_VBBR_CFG: 154 case CS35L41_VPBR_STATUS: 155 case CS35L41_VBBR_STATUS: 156 case CS35L41_OVERTEMP_CFG: 157 case CS35L41_AMP_ERR_VOL: 158 case CS35L41_VOL_STATUS_TO_DSP: 159 case CS35L41_CLASSH_CFG: 160 case CS35L41_WKFET_CFG: 161 case CS35L41_NG_CFG: 162 case CS35L41_AMP_GAIN_CTRL: 163 case CS35L41_DAC_MSM_CFG: 164 case CS35L41_IRQ1_CFG: 165 case CS35L41_IRQ1_STATUS: 166 case CS35L41_IRQ1_STATUS1: 167 case CS35L41_IRQ1_STATUS2: 168 case CS35L41_IRQ1_STATUS3: 169 case CS35L41_IRQ1_STATUS4: 170 case CS35L41_IRQ1_RAW_STATUS1: 171 case CS35L41_IRQ1_RAW_STATUS2: 172 case CS35L41_IRQ1_RAW_STATUS3: 173 case CS35L41_IRQ1_RAW_STATUS4: 174 case CS35L41_IRQ1_MASK1: 175 case CS35L41_IRQ1_MASK2: 176 case CS35L41_IRQ1_MASK3: 177 case CS35L41_IRQ1_MASK4: 178 case CS35L41_IRQ1_FRC1: 179 case CS35L41_IRQ1_FRC2: 180 case CS35L41_IRQ1_FRC3: 181 case CS35L41_IRQ1_FRC4: 182 case CS35L41_IRQ1_EDGE1: 183 case CS35L41_IRQ1_EDGE4: 184 case CS35L41_IRQ1_POL1: 185 case CS35L41_IRQ1_POL2: 186 case CS35L41_IRQ1_POL3: 187 case CS35L41_IRQ1_POL4: 188 case CS35L41_IRQ1_DB3: 189 case CS35L41_IRQ2_CFG: 190 case CS35L41_IRQ2_STATUS: 191 case CS35L41_IRQ2_STATUS1: 192 case CS35L41_IRQ2_STATUS2: 193 case CS35L41_IRQ2_STATUS3: 194 case CS35L41_IRQ2_STATUS4: 195 case CS35L41_IRQ2_RAW_STATUS1: 196 case CS35L41_IRQ2_RAW_STATUS2: 197 case CS35L41_IRQ2_RAW_STATUS3: 198 case CS35L41_IRQ2_RAW_STATUS4: 199 case CS35L41_IRQ2_MASK1: 200 case CS35L41_IRQ2_MASK2: 201 case CS35L41_IRQ2_MASK3: 202 case CS35L41_IRQ2_MASK4: 203 case CS35L41_IRQ2_FRC1: 204 case CS35L41_IRQ2_FRC2: 205 case CS35L41_IRQ2_FRC3: 206 case CS35L41_IRQ2_FRC4: 207 case CS35L41_IRQ2_EDGE1: 208 case CS35L41_IRQ2_EDGE4: 209 case CS35L41_IRQ2_POL1: 210 case CS35L41_IRQ2_POL2: 211 case CS35L41_IRQ2_POL3: 212 case CS35L41_IRQ2_POL4: 213 case CS35L41_IRQ2_DB3: 214 case CS35L41_GPIO_STATUS1: 215 case CS35L41_GPIO1_CTRL1: 216 case CS35L41_GPIO2_CTRL1: 217 case CS35L41_MIXER_NGATE_CFG: 218 case CS35L41_MIXER_NGATE_CH1_CFG: 219 case CS35L41_MIXER_NGATE_CH2_CFG: 220 case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: 221 case CS35L41_CLOCK_DETECT_1: 222 case CS35L41_DIE_STS1: 223 case CS35L41_DIE_STS2: 224 case CS35L41_TEMP_CAL1: 225 case CS35L41_TEMP_CAL2: 226 case CS35L41_DSP1_TIMESTAMP_COUNT: 227 case CS35L41_DSP1_SYS_ID: 228 case CS35L41_DSP1_SYS_VERSION: 229 case CS35L41_DSP1_SYS_CORE_ID: 230 case CS35L41_DSP1_SYS_AHB_ADDR: 231 case CS35L41_DSP1_SYS_XSRAM_SIZE: 232 case CS35L41_DSP1_SYS_YSRAM_SIZE: 233 case CS35L41_DSP1_SYS_PSRAM_SIZE: 234 case CS35L41_DSP1_SYS_PM_BOOT_SIZE: 235 case CS35L41_DSP1_SYS_FEATURES: 236 case CS35L41_DSP1_SYS_FIR_FILTERS: 237 case CS35L41_DSP1_SYS_LMS_FILTERS: 238 case CS35L41_DSP1_SYS_XM_BANK_SIZE: 239 case CS35L41_DSP1_SYS_YM_BANK_SIZE: 240 case CS35L41_DSP1_SYS_PM_BANK_SIZE: 241 case CS35L41_DSP1_RX1_RATE: 242 case CS35L41_DSP1_RX2_RATE: 243 case CS35L41_DSP1_RX3_RATE: 244 case CS35L41_DSP1_RX4_RATE: 245 case CS35L41_DSP1_RX5_RATE: 246 case CS35L41_DSP1_RX6_RATE: 247 case CS35L41_DSP1_RX7_RATE: 248 case CS35L41_DSP1_RX8_RATE: 249 case CS35L41_DSP1_TX1_RATE: 250 case CS35L41_DSP1_TX2_RATE: 251 case CS35L41_DSP1_TX3_RATE: 252 case CS35L41_DSP1_TX4_RATE: 253 case CS35L41_DSP1_TX5_RATE: 254 case CS35L41_DSP1_TX6_RATE: 255 case CS35L41_DSP1_TX7_RATE: 256 case CS35L41_DSP1_TX8_RATE: 257 case CS35L41_DSP1_SCRATCH1: 258 case CS35L41_DSP1_SCRATCH2: 259 case CS35L41_DSP1_SCRATCH3: 260 case CS35L41_DSP1_SCRATCH4: 261 case CS35L41_DSP1_CCM_CORE_CTRL: 262 case CS35L41_DSP1_CCM_CLK_OVERRIDE: 263 case CS35L41_DSP1_XM_MSTR_EN: 264 case CS35L41_DSP1_XM_CORE_PRI: 265 case CS35L41_DSP1_XM_AHB_PACK_PL_PRI: 266 case CS35L41_DSP1_XM_AHB_UP_PL_PRI: 267 case CS35L41_DSP1_XM_ACCEL_PL0_PRI: 268 case CS35L41_DSP1_XM_NPL0_PRI: 269 case CS35L41_DSP1_YM_MSTR_EN: 270 case CS35L41_DSP1_YM_CORE_PRI: 271 case CS35L41_DSP1_YM_AHB_PACK_PL_PRI: 272 case CS35L41_DSP1_YM_AHB_UP_PL_PRI: 273 case CS35L41_DSP1_YM_ACCEL_PL0_PRI: 274 case CS35L41_DSP1_YM_NPL0_PRI: 275 case CS35L41_DSP1_MPU_XM_ACCESS0: 276 case CS35L41_DSP1_MPU_YM_ACCESS0: 277 case CS35L41_DSP1_MPU_WNDW_ACCESS0: 278 case CS35L41_DSP1_MPU_XREG_ACCESS0: 279 case CS35L41_DSP1_MPU_YREG_ACCESS0: 280 case CS35L41_DSP1_MPU_XM_ACCESS1: 281 case CS35L41_DSP1_MPU_YM_ACCESS1: 282 case CS35L41_DSP1_MPU_WNDW_ACCESS1: 283 case CS35L41_DSP1_MPU_XREG_ACCESS1: 284 case CS35L41_DSP1_MPU_YREG_ACCESS1: 285 case CS35L41_DSP1_MPU_XM_ACCESS2: 286 case CS35L41_DSP1_MPU_YM_ACCESS2: 287 case CS35L41_DSP1_MPU_WNDW_ACCESS2: 288 case CS35L41_DSP1_MPU_XREG_ACCESS2: 289 case CS35L41_DSP1_MPU_YREG_ACCESS2: 290 case CS35L41_DSP1_MPU_XM_ACCESS3: 291 case CS35L41_DSP1_MPU_YM_ACCESS3: 292 case CS35L41_DSP1_MPU_WNDW_ACCESS3: 293 case CS35L41_DSP1_MPU_XREG_ACCESS3: 294 case CS35L41_DSP1_MPU_YREG_ACCESS3: 295 case CS35L41_DSP1_MPU_XM_VIO_ADDR: 296 case CS35L41_DSP1_MPU_XM_VIO_STATUS: 297 case CS35L41_DSP1_MPU_YM_VIO_ADDR: 298 case CS35L41_DSP1_MPU_YM_VIO_STATUS: 299 case CS35L41_DSP1_MPU_PM_VIO_ADDR: 300 case CS35L41_DSP1_MPU_PM_VIO_STATUS: 301 case CS35L41_DSP1_MPU_LOCK_CONFIG: 302 case CS35L41_DSP1_MPU_WDT_RST_CTRL: 303 case CS35L41_OTP_TRIM_1: 304 case CS35L41_OTP_TRIM_2: 305 case CS35L41_OTP_TRIM_3: 306 case CS35L41_OTP_TRIM_4: 307 case CS35L41_OTP_TRIM_5: 308 case CS35L41_OTP_TRIM_6: 309 case CS35L41_OTP_TRIM_7: 310 case CS35L41_OTP_TRIM_8: 311 case CS35L41_OTP_TRIM_9: 312 case CS35L41_OTP_TRIM_10: 313 case CS35L41_OTP_TRIM_11: 314 case CS35L41_OTP_TRIM_12: 315 case CS35L41_OTP_TRIM_13: 316 case CS35L41_OTP_TRIM_14: 317 case CS35L41_OTP_TRIM_15: 318 case CS35L41_OTP_TRIM_16: 319 case CS35L41_OTP_TRIM_17: 320 case CS35L41_OTP_TRIM_18: 321 case CS35L41_OTP_TRIM_19: 322 case CS35L41_OTP_TRIM_20: 323 case CS35L41_OTP_TRIM_21: 324 case CS35L41_OTP_TRIM_22: 325 case CS35L41_OTP_TRIM_23: 326 case CS35L41_OTP_TRIM_24: 327 case CS35L41_OTP_TRIM_25: 328 case CS35L41_OTP_TRIM_26: 329 case CS35L41_OTP_TRIM_27: 330 case CS35L41_OTP_TRIM_28: 331 case CS35L41_OTP_TRIM_29: 332 case CS35L41_OTP_TRIM_30: 333 case CS35L41_OTP_TRIM_31: 334 case CS35L41_OTP_TRIM_32: 335 case CS35L41_OTP_TRIM_33: 336 case CS35L41_OTP_TRIM_34: 337 case CS35L41_OTP_TRIM_35: 338 case CS35L41_OTP_TRIM_36: 339 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 340 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 341 case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: 342 case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: 343 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 344 case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: 345 case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: 346 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 347 /*test regs*/ 348 case CS35L41_PLL_OVR: 349 case CS35L41_BST_TEST_DUTY: 350 case CS35L41_DIGPWM_IOCTRL: 351 return true; 352 default: 353 return false; 354 } 355 } 356 357 static bool cs35l41_precious_reg(struct device *dev, unsigned int reg) 358 { 359 switch (reg) { 360 case CS35L41_TEST_KEY_CTL: 361 case CS35L41_USER_KEY_CTL: 362 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 363 case CS35L41_TST_FS_MON0: 364 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 365 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 366 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 367 return true; 368 default: 369 return false; 370 } 371 } 372 373 static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg) 374 { 375 switch (reg) { 376 case CS35L41_DEVID: 377 case CS35L41_SFT_RESET: 378 case CS35L41_FABID: 379 case CS35L41_REVID: 380 case CS35L41_OTPID: 381 case CS35L41_TEST_KEY_CTL: 382 case CS35L41_USER_KEY_CTL: 383 case CS35L41_PWRMGT_CTL: 384 case CS35L41_WAKESRC_CTL: 385 case CS35L41_PWRMGT_STS: 386 case CS35L41_DTEMP_EN: 387 case CS35L41_IRQ1_STATUS: 388 case CS35L41_IRQ1_STATUS1: 389 case CS35L41_IRQ1_STATUS2: 390 case CS35L41_IRQ1_STATUS3: 391 case CS35L41_IRQ1_STATUS4: 392 case CS35L41_IRQ1_RAW_STATUS1: 393 case CS35L41_IRQ1_RAW_STATUS2: 394 case CS35L41_IRQ1_RAW_STATUS3: 395 case CS35L41_IRQ1_RAW_STATUS4: 396 case CS35L41_IRQ2_STATUS: 397 case CS35L41_IRQ2_STATUS1: 398 case CS35L41_IRQ2_STATUS2: 399 case CS35L41_IRQ2_STATUS3: 400 case CS35L41_IRQ2_STATUS4: 401 case CS35L41_IRQ2_RAW_STATUS1: 402 case CS35L41_IRQ2_RAW_STATUS2: 403 case CS35L41_IRQ2_RAW_STATUS3: 404 case CS35L41_IRQ2_RAW_STATUS4: 405 case CS35L41_GPIO_STATUS1: 406 case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: 407 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 408 case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: 409 case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: 410 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 411 case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: 412 case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: 413 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 414 case CS35L41_DSP1_SCRATCH1: 415 case CS35L41_DSP1_SCRATCH2: 416 case CS35L41_DSP1_SCRATCH3: 417 case CS35L41_DSP1_SCRATCH4: 418 case CS35L41_DSP1_CCM_CLK_OVERRIDE ... CS35L41_DSP1_WDT_STATUS: 419 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 420 return true; 421 default: 422 return false; 423 } 424 } 425 426 static const struct cs35l41_otp_packed_element_t otp_map_1[] = { 427 /* addr shift size */ 428 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ 429 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ 430 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ 431 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ 432 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ 433 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ 434 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ 435 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ 436 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ 437 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ 438 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ 439 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ 440 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ 441 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ 442 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ 443 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ 444 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ 445 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ 446 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ 447 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ 448 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ 449 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ 450 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ 451 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ 452 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ 453 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ 454 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ 455 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ 456 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ 457 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ 458 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ 459 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ 460 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ 461 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ 462 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ 463 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ 464 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ 465 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ 466 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ 467 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ 468 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ 469 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ 470 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ 471 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ 472 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ 473 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ 474 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ 475 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ 476 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ 477 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ 478 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ 479 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ 480 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ 481 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ 482 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ 483 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ 484 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ 485 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ 486 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ 487 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ 488 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ 489 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ 490 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ 491 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ 492 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ 493 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ 494 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ 495 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ 496 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ 497 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ 498 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ 499 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ 500 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ 501 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ 502 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ 503 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ 504 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ 505 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ 506 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ 507 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ 508 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ 509 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ 510 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ 511 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ 512 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ 513 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ 514 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ 515 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ 516 { 0x00007434, 17, 1 }, /*FORCE_CAL*/ 517 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ 518 { 0x00007068, 0, 9 }, /*MODIX*/ 519 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ 520 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ 521 { 0x00000000, 0, 1 }, /*extra bit*/ 522 { 0x00017040, 0, 8 }, /*X_COORDINATE*/ 523 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ 524 { 0x00017040, 16, 8 }, /*WAFER_ID*/ 525 { 0x00017040, 24, 8 }, /*DVS*/ 526 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ 527 }; 528 529 static const struct cs35l41_otp_packed_element_t otp_map_2[] = { 530 /* addr shift size */ 531 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ 532 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ 533 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ 534 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ 535 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ 536 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ 537 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ 538 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ 539 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ 540 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ 541 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ 542 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ 543 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ 544 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ 545 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ 546 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ 547 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ 548 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ 549 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ 550 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ 551 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ 552 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ 553 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ 554 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ 555 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ 556 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ 557 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ 558 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ 559 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ 560 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ 561 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ 562 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ 563 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ 564 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ 565 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ 566 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ 567 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ 568 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ 569 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ 570 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ 571 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ 572 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ 573 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ 574 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ 575 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ 576 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ 577 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ 578 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ 579 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ 580 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ 581 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ 582 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ 583 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ 584 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ 585 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ 586 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ 587 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ 588 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ 589 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ 590 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ 591 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ 592 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ 593 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ 594 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ 595 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ 596 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ 597 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ 598 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ 599 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ 600 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ 601 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ 602 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ 603 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ 604 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ 605 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ 606 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ 607 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ 608 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ 609 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ 610 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ 611 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ 612 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ 613 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ 614 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ 615 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ 616 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ 617 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ 618 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ 619 { 0x00007434, 17, 1 }, /*FORCE_CAL*/ 620 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ 621 { 0x00007068, 0, 9 }, /*MODIX*/ 622 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ 623 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ 624 { 0x00004000, 11, 1 }, /*VMON_POL*/ 625 { 0x00017040, 0, 8 }, /*X_COORDINATE*/ 626 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ 627 { 0x00017040, 16, 8 }, /*WAFER_ID*/ 628 { 0x00017040, 24, 8 }, /*DVS*/ 629 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ 630 }; 631 632 static const struct reg_sequence cs35l41_reva0_errata_patch[] = { 633 { 0x00003854, 0x05180240 }, 634 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 635 { 0x00004310, 0x00000000 }, 636 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 637 { CS35L41_OTP_TRIM_30, 0x9091A1C8 }, 638 { 0x00003014, 0x0200EE0E }, 639 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 640 { 0x00000054, 0x00000004 }, 641 { CS35L41_IRQ1_DB3, 0x00000000 }, 642 { CS35L41_IRQ2_DB3, 0x00000000 }, 643 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 644 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 645 { CS35L41_PWR_CTRL2, 0x00000000 }, 646 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 647 }; 648 649 static const struct reg_sequence cs35l41_revb0_errata_patch[] = { 650 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 651 { 0x00004310, 0x00000000 }, 652 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 653 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 654 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 655 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 656 { CS35L41_PWR_CTRL2, 0x00000000 }, 657 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 658 }; 659 660 static const struct reg_sequence cs35l41_revb2_errata_patch[] = { 661 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 662 { 0x00004310, 0x00000000 }, 663 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 664 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 665 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 666 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 667 { CS35L41_PWR_CTRL2, 0x00000000 }, 668 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 669 }; 670 671 static const struct reg_sequence cs35l41_fs_errata_patch[] = { 672 { CS35L41_DSP1_RX1_RATE, 0x00000001 }, 673 { CS35L41_DSP1_RX2_RATE, 0x00000001 }, 674 { CS35L41_DSP1_RX3_RATE, 0x00000001 }, 675 { CS35L41_DSP1_RX4_RATE, 0x00000001 }, 676 { CS35L41_DSP1_RX5_RATE, 0x00000001 }, 677 { CS35L41_DSP1_RX6_RATE, 0x00000001 }, 678 { CS35L41_DSP1_RX7_RATE, 0x00000001 }, 679 { CS35L41_DSP1_RX8_RATE, 0x00000001 }, 680 { CS35L41_DSP1_TX1_RATE, 0x00000001 }, 681 { CS35L41_DSP1_TX2_RATE, 0x00000001 }, 682 { CS35L41_DSP1_TX3_RATE, 0x00000001 }, 683 { CS35L41_DSP1_TX4_RATE, 0x00000001 }, 684 { CS35L41_DSP1_TX5_RATE, 0x00000001 }, 685 { CS35L41_DSP1_TX6_RATE, 0x00000001 }, 686 { CS35L41_DSP1_TX7_RATE, 0x00000001 }, 687 { CS35L41_DSP1_TX8_RATE, 0x00000001 }, 688 }; 689 690 static const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[] = { 691 { 692 .id = 0x01, 693 .map = otp_map_1, 694 .num_elements = ARRAY_SIZE(otp_map_1), 695 .bit_offset = 16, 696 .word_offset = 2, 697 }, 698 { 699 .id = 0x02, 700 .map = otp_map_2, 701 .num_elements = ARRAY_SIZE(otp_map_2), 702 .bit_offset = 16, 703 .word_offset = 2, 704 }, 705 { 706 .id = 0x03, 707 .map = otp_map_2, 708 .num_elements = ARRAY_SIZE(otp_map_2), 709 .bit_offset = 16, 710 .word_offset = 2, 711 }, 712 { 713 .id = 0x06, 714 .map = otp_map_2, 715 .num_elements = ARRAY_SIZE(otp_map_2), 716 .bit_offset = 16, 717 .word_offset = 2, 718 }, 719 { 720 .id = 0x08, 721 .map = otp_map_1, 722 .num_elements = ARRAY_SIZE(otp_map_1), 723 .bit_offset = 16, 724 .word_offset = 2, 725 }, 726 }; 727 728 struct regmap_config cs35l41_regmap_i2c = { 729 .reg_bits = 32, 730 .val_bits = 32, 731 .reg_stride = CS35L41_REGSTRIDE, 732 .reg_format_endian = REGMAP_ENDIAN_BIG, 733 .val_format_endian = REGMAP_ENDIAN_BIG, 734 .max_register = CS35L41_LASTREG, 735 .reg_defaults = cs35l41_reg, 736 .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), 737 .volatile_reg = cs35l41_volatile_reg, 738 .readable_reg = cs35l41_readable_reg, 739 .precious_reg = cs35l41_precious_reg, 740 .cache_type = REGCACHE_RBTREE, 741 }; 742 EXPORT_SYMBOL_GPL(cs35l41_regmap_i2c); 743 744 struct regmap_config cs35l41_regmap_spi = { 745 .reg_bits = 32, 746 .val_bits = 32, 747 .pad_bits = 16, 748 .reg_stride = CS35L41_REGSTRIDE, 749 .reg_format_endian = REGMAP_ENDIAN_BIG, 750 .val_format_endian = REGMAP_ENDIAN_BIG, 751 .max_register = CS35L41_LASTREG, 752 .reg_defaults = cs35l41_reg, 753 .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), 754 .volatile_reg = cs35l41_volatile_reg, 755 .readable_reg = cs35l41_readable_reg, 756 .precious_reg = cs35l41_precious_reg, 757 .cache_type = REGCACHE_RBTREE, 758 }; 759 EXPORT_SYMBOL_GPL(cs35l41_regmap_spi); 760 761 static const struct cs35l41_otp_map_element_t *cs35l41_find_otp_map(u32 otp_id) 762 { 763 int i; 764 765 for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) { 766 if (cs35l41_otp_map_map[i].id == otp_id) 767 return &cs35l41_otp_map_map[i]; 768 } 769 770 return NULL; 771 } 772 773 int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap) 774 { 775 static const struct reg_sequence unlock[] = { 776 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 777 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 778 }; 779 int ret; 780 781 ret = regmap_multi_reg_write(regmap, unlock, ARRAY_SIZE(unlock)); 782 if (ret) 783 dev_err(dev, "Failed to unlock test key: %d\n", ret); 784 785 return ret; 786 } 787 EXPORT_SYMBOL_GPL(cs35l41_test_key_unlock); 788 789 int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap) 790 { 791 static const struct reg_sequence unlock[] = { 792 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 793 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 794 }; 795 int ret; 796 797 ret = regmap_multi_reg_write(regmap, unlock, ARRAY_SIZE(unlock)); 798 if (ret) 799 dev_err(dev, "Failed to lock test key: %d\n", ret); 800 801 return ret; 802 } 803 EXPORT_SYMBOL_GPL(cs35l41_test_key_lock); 804 805 /* Must be called with the TEST_KEY unlocked */ 806 int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap) 807 { 808 const struct cs35l41_otp_map_element_t *otp_map_match; 809 const struct cs35l41_otp_packed_element_t *otp_map; 810 int bit_offset, word_offset, ret, i; 811 unsigned int bit_sum = 8; 812 u32 otp_val, otp_id_reg; 813 u32 *otp_mem; 814 815 otp_mem = kmalloc_array(CS35L41_OTP_SIZE_WORDS, sizeof(*otp_mem), GFP_KERNEL); 816 if (!otp_mem) 817 return -ENOMEM; 818 819 ret = regmap_read(regmap, CS35L41_OTPID, &otp_id_reg); 820 if (ret) { 821 dev_err(dev, "Read OTP ID failed: %d\n", ret); 822 goto err_otp_unpack; 823 } 824 825 otp_map_match = cs35l41_find_otp_map(otp_id_reg); 826 827 if (!otp_map_match) { 828 dev_err(dev, "OTP Map matching ID %d not found\n", otp_id_reg); 829 ret = -EINVAL; 830 goto err_otp_unpack; 831 } 832 833 ret = regmap_bulk_read(regmap, CS35L41_OTP_MEM0, otp_mem, CS35L41_OTP_SIZE_WORDS); 834 if (ret) { 835 dev_err(dev, "Read OTP Mem failed: %d\n", ret); 836 goto err_otp_unpack; 837 } 838 839 otp_map = otp_map_match->map; 840 841 bit_offset = otp_map_match->bit_offset; 842 word_offset = otp_map_match->word_offset; 843 844 for (i = 0; i < otp_map_match->num_elements; i++) { 845 dev_dbg(dev, "bitoffset= %d, word_offset=%d, bit_sum mod 32=%d, otp_map[i].size = %u\n", 846 bit_offset, word_offset, bit_sum % 32, otp_map[i].size); 847 if (bit_offset + otp_map[i].size - 1 >= 32) { 848 otp_val = (otp_mem[word_offset] & 849 GENMASK(31, bit_offset)) >> bit_offset; 850 otp_val |= (otp_mem[++word_offset] & 851 GENMASK(bit_offset + otp_map[i].size - 33, 0)) << 852 (32 - bit_offset); 853 bit_offset += otp_map[i].size - 32; 854 } else if (bit_offset + otp_map[i].size - 1 >= 0) { 855 otp_val = (otp_mem[word_offset] & 856 GENMASK(bit_offset + otp_map[i].size - 1, bit_offset) 857 ) >> bit_offset; 858 bit_offset += otp_map[i].size; 859 } else /* both bit_offset and otp_map[i].size are 0 */ 860 otp_val = 0; 861 862 bit_sum += otp_map[i].size; 863 864 if (bit_offset == 32) { 865 bit_offset = 0; 866 word_offset++; 867 } 868 869 if (otp_map[i].reg != 0) { 870 ret = regmap_update_bits(regmap, otp_map[i].reg, 871 GENMASK(otp_map[i].shift + otp_map[i].size - 1, 872 otp_map[i].shift), 873 otp_val << otp_map[i].shift); 874 if (ret < 0) { 875 dev_err(dev, "Write OTP val failed: %d\n", ret); 876 goto err_otp_unpack; 877 } 878 } 879 } 880 881 ret = 0; 882 883 err_otp_unpack: 884 kfree(otp_mem); 885 886 return ret; 887 } 888 EXPORT_SYMBOL_GPL(cs35l41_otp_unpack); 889 890 /* Must be called with the TEST_KEY unlocked */ 891 int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid) 892 { 893 char *rev; 894 int ret; 895 896 switch (reg_revid) { 897 case CS35L41_REVID_A0: 898 ret = regmap_register_patch(reg, cs35l41_reva0_errata_patch, 899 ARRAY_SIZE(cs35l41_reva0_errata_patch)); 900 rev = "A0"; 901 break; 902 case CS35L41_REVID_B0: 903 ret = regmap_register_patch(reg, cs35l41_revb0_errata_patch, 904 ARRAY_SIZE(cs35l41_revb0_errata_patch)); 905 rev = "B0"; 906 break; 907 case CS35L41_REVID_B2: 908 ret = regmap_register_patch(reg, cs35l41_revb2_errata_patch, 909 ARRAY_SIZE(cs35l41_revb2_errata_patch)); 910 rev = "B2"; 911 break; 912 default: 913 ret = -EINVAL; 914 rev = "XX"; 915 break; 916 } 917 918 if (ret) 919 dev_err(dev, "Failed to apply %s errata patch: %d\n", rev, ret); 920 921 ret = regmap_write(reg, CS35L41_DSP1_CCM_CORE_CTRL, 0); 922 if (ret < 0) 923 dev_err(dev, "Write CCM_CORE_CTRL failed: %d\n", ret); 924 925 return ret; 926 } 927 EXPORT_SYMBOL_GPL(cs35l41_register_errata_patch); 928 929 int cs35l41_set_channels(struct device *dev, struct regmap *reg, 930 unsigned int tx_num, unsigned int *tx_slot, 931 unsigned int rx_num, unsigned int *rx_slot) 932 { 933 unsigned int val, mask; 934 int i; 935 936 if (tx_num > 4 || rx_num > 2) 937 return -EINVAL; 938 939 val = 0; 940 mask = 0; 941 for (i = 0; i < rx_num; i++) { 942 dev_dbg(dev, "rx slot %d position = %d\n", i, rx_slot[i]); 943 val |= rx_slot[i] << (i * 8); 944 mask |= 0x3F << (i * 8); 945 } 946 regmap_update_bits(reg, CS35L41_SP_FRAME_RX_SLOT, mask, val); 947 948 val = 0; 949 mask = 0; 950 for (i = 0; i < tx_num; i++) { 951 dev_dbg(dev, "tx slot %d position = %d\n", i, tx_slot[i]); 952 val |= tx_slot[i] << (i * 8); 953 mask |= 0x3F << (i * 8); 954 } 955 regmap_update_bits(reg, CS35L41_SP_FRAME_TX_SLOT, mask, val); 956 957 return 0; 958 } 959 EXPORT_SYMBOL_GPL(cs35l41_set_channels); 960 961 static const unsigned char cs35l41_bst_k1_table[4][5] = { 962 { 0x24, 0x32, 0x32, 0x4F, 0x57 }, 963 { 0x24, 0x32, 0x32, 0x4F, 0x57 }, 964 { 0x40, 0x32, 0x32, 0x4F, 0x57 }, 965 { 0x40, 0x32, 0x32, 0x4F, 0x57 } 966 }; 967 968 static const unsigned char cs35l41_bst_k2_table[4][5] = { 969 { 0x24, 0x49, 0x66, 0xA3, 0xEA }, 970 { 0x24, 0x49, 0x66, 0xA3, 0xEA }, 971 { 0x48, 0x49, 0x66, 0xA3, 0xEA }, 972 { 0x48, 0x49, 0x66, 0xA3, 0xEA } 973 }; 974 975 static const unsigned char cs35l41_bst_slope_table[4] = { 976 0x75, 0x6B, 0x3B, 0x28 977 }; 978 979 static int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, 980 int boost_cap, int boost_ipk) 981 { 982 unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled; 983 int ret; 984 985 switch (boost_ind) { 986 case 1000: /* 1.0 uH */ 987 bst_lbst_val = 0; 988 break; 989 case 1200: /* 1.2 uH */ 990 bst_lbst_val = 1; 991 break; 992 case 1500: /* 1.5 uH */ 993 bst_lbst_val = 2; 994 break; 995 case 2200: /* 2.2 uH */ 996 bst_lbst_val = 3; 997 break; 998 default: 999 dev_err(dev, "Invalid boost inductor value: %d nH\n", boost_ind); 1000 return -EINVAL; 1001 } 1002 1003 switch (boost_cap) { 1004 case 0 ... 19: 1005 bst_cbst_range = 0; 1006 break; 1007 case 20 ... 50: 1008 bst_cbst_range = 1; 1009 break; 1010 case 51 ... 100: 1011 bst_cbst_range = 2; 1012 break; 1013 case 101 ... 200: 1014 bst_cbst_range = 3; 1015 break; 1016 default: 1017 if (boost_cap < 0) { 1018 dev_err(dev, "Invalid boost capacitor value: %d nH\n", boost_cap); 1019 return -EINVAL; 1020 } 1021 /* 201 uF and greater */ 1022 bst_cbst_range = 4; 1023 } 1024 1025 if (boost_ipk < 1600 || boost_ipk > 4500) { 1026 dev_err(dev, "Invalid boost inductor peak current: %d mA\n", boost_ipk); 1027 return -EINVAL; 1028 } 1029 1030 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_COEFF, 1031 CS35L41_BST_K1_MASK | CS35L41_BST_K2_MASK, 1032 cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range] 1033 << CS35L41_BST_K1_SHIFT | 1034 cs35l41_bst_k2_table[bst_lbst_val][bst_cbst_range] 1035 << CS35L41_BST_K2_SHIFT); 1036 if (ret) { 1037 dev_err(dev, "Failed to write boost coefficients: %d\n", ret); 1038 return ret; 1039 } 1040 1041 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST, 1042 CS35L41_BST_SLOPE_MASK | CS35L41_BST_LBST_VAL_MASK, 1043 cs35l41_bst_slope_table[bst_lbst_val] 1044 << CS35L41_BST_SLOPE_SHIFT | 1045 bst_lbst_val << CS35L41_BST_LBST_VAL_SHIFT); 1046 if (ret) { 1047 dev_err(dev, "Failed to write boost slope/inductor value: %d\n", ret); 1048 return ret; 1049 } 1050 1051 bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10; 1052 1053 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR, CS35L41_BST_IPK_MASK, 1054 bst_ipk_scaled << CS35L41_BST_IPK_SHIFT); 1055 if (ret) { 1056 dev_err(dev, "Failed to write boost inductor peak current: %d\n", ret); 1057 return ret; 1058 } 1059 1060 regmap_update_bits(regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, 1061 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 1062 1063 return 0; 1064 } 1065 1066 static const struct reg_sequence cs35l41_safe_to_reset[] = { 1067 { 0x00000040, 0x00000055 }, 1068 { 0x00000040, 0x000000AA }, 1069 { 0x0000393C, 0x000000C0, 6000}, 1070 { 0x0000393C, 0x00000000 }, 1071 { 0x00007414, 0x00C82222 }, 1072 { 0x0000742C, 0x00000000 }, 1073 { 0x00000040, 0x000000CC }, 1074 { 0x00000040, 0x00000033 }, 1075 }; 1076 1077 static const struct reg_sequence cs35l41_active_to_safe[] = { 1078 { 0x00000040, 0x00000055 }, 1079 { 0x00000040, 0x000000AA }, 1080 { 0x00007438, 0x00585941 }, 1081 { CS35L41_PWR_CTRL1, 0x00000000 }, 1082 { 0x0000742C, 0x00000009, 3000 }, 1083 { 0x00007438, 0x00580941 }, 1084 { 0x00000040, 0x000000CC }, 1085 { 0x00000040, 0x00000033 }, 1086 }; 1087 1088 static const struct reg_sequence cs35l41_safe_to_active[] = { 1089 { 0x00000040, 0x00000055 }, 1090 { 0x00000040, 0x000000AA }, 1091 { 0x0000742C, 0x0000000F }, 1092 { 0x0000742C, 0x00000079 }, 1093 { 0x00007438, 0x00585941 }, 1094 { CS35L41_PWR_CTRL1, 0x00000001, 3000 }, // GLOBAL_EN = 1 1095 { 0x0000742C, 0x000000F9 }, 1096 { 0x00007438, 0x00580941 }, 1097 { 0x00000040, 0x000000CC }, 1098 { 0x00000040, 0x00000033 }, 1099 }; 1100 1101 static const struct reg_sequence cs35l41_reset_to_safe[] = { 1102 { 0x00000040, 0x00000055 }, 1103 { 0x00000040, 0x000000AA }, 1104 { 0x00007438, 0x00585941 }, 1105 { 0x00007414, 0x08C82222 }, 1106 { 0x0000742C, 0x00000009 }, 1107 { 0x00000040, 0x000000CC }, 1108 { 0x00000040, 0x00000033 }, 1109 }; 1110 1111 int cs35l41_init_boost(struct device *dev, struct regmap *regmap, 1112 struct cs35l41_hw_cfg *hw_cfg) 1113 { 1114 int ret; 1115 1116 switch (hw_cfg->bst_type) { 1117 case CS35L41_INT_BOOST: 1118 ret = cs35l41_boost_config(dev, regmap, hw_cfg->bst_ind, 1119 hw_cfg->bst_cap, hw_cfg->bst_ipk); 1120 if (ret) 1121 dev_err(dev, "Error in Boost DT config: %d\n", ret); 1122 break; 1123 case CS35L41_EXT_BOOST: 1124 case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: 1125 /* Only CLSA0100 doesn't use GPIO as VSPK switch, but even on that laptop we can 1126 * toggle GPIO1 as is not connected to anything. 1127 * There will be no other device without VSPK switch. 1128 */ 1129 regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001); 1130 regmap_multi_reg_write(regmap, cs35l41_reset_to_safe, 1131 ARRAY_SIZE(cs35l41_reset_to_safe)); 1132 ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, 1133 CS35L41_BST_DIS_FET_OFF << CS35L41_BST_EN_SHIFT); 1134 break; 1135 default: 1136 dev_err(dev, "Boost type %d not supported\n", hw_cfg->bst_type); 1137 ret = -EINVAL; 1138 break; 1139 } 1140 1141 return ret; 1142 } 1143 EXPORT_SYMBOL_GPL(cs35l41_init_boost); 1144 1145 bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type) 1146 { 1147 switch (b_type) { 1148 /* There is only one laptop that doesn't have VSPK switch. */ 1149 case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: 1150 return false; 1151 case CS35L41_EXT_BOOST: 1152 regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001); 1153 regmap_multi_reg_write(regmap, cs35l41_safe_to_reset, 1154 ARRAY_SIZE(cs35l41_safe_to_reset)); 1155 return true; 1156 default: 1157 return true; 1158 } 1159 } 1160 EXPORT_SYMBOL_GPL(cs35l41_safe_reset); 1161 1162 int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable) 1163 { 1164 int ret; 1165 1166 switch (b_type) { 1167 case CS35L41_INT_BOOST: 1168 ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL1, CS35L41_GLOBAL_EN_MASK, 1169 enable << CS35L41_GLOBAL_EN_SHIFT); 1170 usleep_range(3000, 3100); 1171 break; 1172 case CS35L41_EXT_BOOST: 1173 case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: 1174 if (enable) 1175 ret = regmap_multi_reg_write(regmap, cs35l41_safe_to_active, 1176 ARRAY_SIZE(cs35l41_safe_to_active)); 1177 else 1178 ret = regmap_multi_reg_write(regmap, cs35l41_active_to_safe, 1179 ARRAY_SIZE(cs35l41_active_to_safe)); 1180 break; 1181 default: 1182 ret = -EINVAL; 1183 break; 1184 } 1185 1186 return ret; 1187 } 1188 EXPORT_SYMBOL_GPL(cs35l41_global_enable); 1189 1190 int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg) 1191 { 1192 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; 1193 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; 1194 int irq_pol = IRQF_TRIGGER_NONE; 1195 1196 regmap_update_bits(regmap, CS35L41_GPIO1_CTRL1, 1197 CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, 1198 gpio1->pol_inv << CS35L41_GPIO_POL_SHIFT | 1199 !gpio1->out_en << CS35L41_GPIO_DIR_SHIFT); 1200 1201 regmap_update_bits(regmap, CS35L41_GPIO2_CTRL1, 1202 CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, 1203 gpio2->pol_inv << CS35L41_GPIO_POL_SHIFT | 1204 !gpio2->out_en << CS35L41_GPIO_DIR_SHIFT); 1205 1206 if (gpio1->valid) 1207 regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO1_CTRL_MASK, 1208 gpio1->func << CS35L41_GPIO1_CTRL_SHIFT); 1209 1210 if (gpio2->valid) { 1211 regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO2_CTRL_MASK, 1212 gpio2->func << CS35L41_GPIO2_CTRL_SHIFT); 1213 1214 switch (gpio2->func) { 1215 case CS35L41_GPIO2_INT_PUSH_PULL_LOW: 1216 case CS35L41_GPIO2_INT_OPEN_DRAIN: 1217 irq_pol = IRQF_TRIGGER_LOW; 1218 break; 1219 case CS35L41_GPIO2_INT_PUSH_PULL_HIGH: 1220 irq_pol = IRQF_TRIGGER_HIGH; 1221 break; 1222 default: 1223 break; 1224 } 1225 } 1226 1227 return irq_pol; 1228 } 1229 EXPORT_SYMBOL_GPL(cs35l41_gpio_config); 1230 1231 static const struct cs_dsp_region cs35l41_dsp1_regions[] = { 1232 { .type = WMFW_HALO_PM_PACKED, .base = CS35L41_DSP1_PMEM_0 }, 1233 { .type = WMFW_HALO_XM_PACKED, .base = CS35L41_DSP1_XMEM_PACK_0 }, 1234 { .type = WMFW_HALO_YM_PACKED, .base = CS35L41_DSP1_YMEM_PACK_0 }, 1235 {. type = WMFW_ADSP2_XM, .base = CS35L41_DSP1_XMEM_UNPACK24_0}, 1236 {. type = WMFW_ADSP2_YM, .base = CS35L41_DSP1_YMEM_UNPACK24_0}, 1237 }; 1238 1239 void cs35l41_configure_cs_dsp(struct device *dev, struct regmap *reg, struct cs_dsp *dsp) 1240 { 1241 dsp->num = 1; 1242 dsp->type = WMFW_HALO; 1243 dsp->rev = 0; 1244 dsp->dev = dev; 1245 dsp->regmap = reg; 1246 dsp->base = CS35L41_DSP1_CTRL_BASE; 1247 dsp->base_sysinfo = CS35L41_DSP1_SYS_ID; 1248 dsp->mem = cs35l41_dsp1_regions; 1249 dsp->num_mems = ARRAY_SIZE(cs35l41_dsp1_regions); 1250 dsp->lock_regions = 0xFFFFFFFF; 1251 } 1252 EXPORT_SYMBOL_GPL(cs35l41_configure_cs_dsp); 1253 1254 static bool cs35l41_check_cspl_mbox_sts(enum cs35l41_cspl_mbox_cmd cmd, 1255 enum cs35l41_cspl_mbox_status sts) 1256 { 1257 switch (cmd) { 1258 case CSPL_MBOX_CMD_NONE: 1259 case CSPL_MBOX_CMD_UNKNOWN_CMD: 1260 return true; 1261 case CSPL_MBOX_CMD_PAUSE: 1262 case CSPL_MBOX_CMD_OUT_OF_HIBERNATE: 1263 return (sts == CSPL_MBOX_STS_PAUSED); 1264 case CSPL_MBOX_CMD_RESUME: 1265 return (sts == CSPL_MBOX_STS_RUNNING); 1266 case CSPL_MBOX_CMD_REINIT: 1267 return (sts == CSPL_MBOX_STS_RUNNING); 1268 case CSPL_MBOX_CMD_STOP_PRE_REINIT: 1269 return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT); 1270 default: 1271 return false; 1272 } 1273 } 1274 1275 int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap, 1276 enum cs35l41_cspl_mbox_cmd cmd) 1277 { 1278 unsigned int sts = 0, i; 1279 int ret; 1280 1281 // Set mailbox cmd 1282 ret = regmap_write(regmap, CS35L41_DSP_VIRT1_MBOX_1, cmd); 1283 if (ret < 0) { 1284 if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE) 1285 dev_err(dev, "Failed to write MBOX: %d\n", ret); 1286 return ret; 1287 } 1288 1289 // Read mailbox status and verify it is appropriate for the given cmd 1290 for (i = 0; i < 5; i++) { 1291 usleep_range(1000, 1100); 1292 1293 ret = regmap_read(regmap, CS35L41_DSP_MBOX_2, &sts); 1294 if (ret < 0) { 1295 dev_err(dev, "Failed to read MBOX STS: %d\n", ret); 1296 continue; 1297 } 1298 1299 if (!cs35l41_check_cspl_mbox_sts(cmd, sts)) 1300 dev_dbg(dev, "[%u] cmd %u returned invalid sts %u", i, cmd, sts); 1301 else 1302 return 0; 1303 } 1304 1305 dev_err(dev, "Failed to set mailbox cmd %u (status %u)\n", cmd, sts); 1306 1307 return -ENOMSG; 1308 } 1309 EXPORT_SYMBOL_GPL(cs35l41_set_cspl_mbox_cmd); 1310 1311 int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap) 1312 { 1313 int ret; 1314 1315 ret = regmap_multi_reg_write(regmap, cs35l41_fs_errata_patch, 1316 ARRAY_SIZE(cs35l41_fs_errata_patch)); 1317 if (ret < 0) 1318 dev_err(dev, "Failed to write fs errata: %d\n", ret); 1319 1320 return ret; 1321 } 1322 EXPORT_SYMBOL_GPL(cs35l41_write_fs_errata); 1323 1324 MODULE_DESCRIPTION("CS35L41 library"); 1325 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1326 MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <tanureal@opensource.cirrus.com>"); 1327 MODULE_LICENSE("GPL"); 1328