1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41-lib.c -- CS35L41 Common functions for HDA and ASoC Audio drivers 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 // Author: Lucas Tanure <lucas.tanure@cirrus.com> 9 10 #include <linux/dev_printk.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/slab.h> 15 16 #include <sound/cs35l41.h> 17 18 static const struct reg_default cs35l41_reg[] = { 19 { CS35L41_PWR_CTRL1, 0x00000000 }, 20 { CS35L41_PWR_CTRL2, 0x00000000 }, 21 { CS35L41_PWR_CTRL3, 0x01000010 }, 22 { CS35L41_GPIO_PAD_CONTROL, 0x00000000 }, 23 { CS35L41_SP_ENABLES, 0x00000000 }, 24 { CS35L41_SP_RATE_CTRL, 0x00000028 }, 25 { CS35L41_SP_FORMAT, 0x18180200 }, 26 { CS35L41_SP_HIZ_CTRL, 0x00000002 }, 27 { CS35L41_SP_FRAME_TX_SLOT, 0x03020100 }, 28 { CS35L41_SP_FRAME_RX_SLOT, 0x00000100 }, 29 { CS35L41_SP_TX_WL, 0x00000018 }, 30 { CS35L41_SP_RX_WL, 0x00000018 }, 31 { CS35L41_DAC_PCM1_SRC, 0x00000008 }, 32 { CS35L41_ASP_TX1_SRC, 0x00000018 }, 33 { CS35L41_ASP_TX2_SRC, 0x00000019 }, 34 { CS35L41_ASP_TX3_SRC, 0x00000020 }, 35 { CS35L41_ASP_TX4_SRC, 0x00000021 }, 36 { CS35L41_DSP1_RX1_SRC, 0x00000008 }, 37 { CS35L41_DSP1_RX2_SRC, 0x00000009 }, 38 { CS35L41_DSP1_RX3_SRC, 0x00000018 }, 39 { CS35L41_DSP1_RX4_SRC, 0x00000019 }, 40 { CS35L41_DSP1_RX5_SRC, 0x00000020 }, 41 { CS35L41_DSP1_RX6_SRC, 0x00000021 }, 42 { CS35L41_DSP1_RX7_SRC, 0x0000003A }, 43 { CS35L41_DSP1_RX8_SRC, 0x00000001 }, 44 { CS35L41_NGATE1_SRC, 0x00000008 }, 45 { CS35L41_NGATE2_SRC, 0x00000009 }, 46 { CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 }, 47 { CS35L41_CLASSH_CFG, 0x000B0405 }, 48 { CS35L41_WKFET_CFG, 0x00000111 }, 49 { CS35L41_NG_CFG, 0x00000033 }, 50 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 51 { CS35L41_GPIO1_CTRL1, 0xE1000001 }, 52 { CS35L41_GPIO2_CTRL1, 0xE1000001 }, 53 { CS35L41_MIXER_NGATE_CFG, 0x00000000 }, 54 { CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 }, 55 { CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 }, 56 }; 57 58 static bool cs35l41_readable_reg(struct device *dev, unsigned int reg) 59 { 60 switch (reg) { 61 case CS35L41_DEVID: 62 case CS35L41_REVID: 63 case CS35L41_FABID: 64 case CS35L41_RELID: 65 case CS35L41_OTPID: 66 case CS35L41_TEST_KEY_CTL: 67 case CS35L41_USER_KEY_CTL: 68 case CS35L41_OTP_CTRL0: 69 case CS35L41_OTP_CTRL3: 70 case CS35L41_OTP_CTRL4: 71 case CS35L41_OTP_CTRL5: 72 case CS35L41_OTP_CTRL6: 73 case CS35L41_OTP_CTRL7: 74 case CS35L41_OTP_CTRL8: 75 case CS35L41_PWR_CTRL1: 76 case CS35L41_PWR_CTRL2: 77 case CS35L41_PWR_CTRL3: 78 case CS35L41_CTRL_OVRRIDE: 79 case CS35L41_AMP_OUT_MUTE: 80 case CS35L41_PROTECT_REL_ERR_IGN: 81 case CS35L41_GPIO_PAD_CONTROL: 82 case CS35L41_JTAG_CONTROL: 83 case CS35L41_PLL_CLK_CTRL: 84 case CS35L41_DSP_CLK_CTRL: 85 case CS35L41_GLOBAL_CLK_CTRL: 86 case CS35L41_DATA_FS_SEL: 87 case CS35L41_MDSYNC_EN: 88 case CS35L41_MDSYNC_TX_ID: 89 case CS35L41_MDSYNC_PWR_CTRL: 90 case CS35L41_MDSYNC_DATA_TX: 91 case CS35L41_MDSYNC_TX_STATUS: 92 case CS35L41_MDSYNC_DATA_RX: 93 case CS35L41_MDSYNC_RX_STATUS: 94 case CS35L41_MDSYNC_ERR_STATUS: 95 case CS35L41_MDSYNC_SYNC_PTE2: 96 case CS35L41_MDSYNC_SYNC_PTE3: 97 case CS35L41_MDSYNC_SYNC_MSM_STATUS: 98 case CS35L41_BSTCVRT_VCTRL1: 99 case CS35L41_BSTCVRT_VCTRL2: 100 case CS35L41_BSTCVRT_PEAK_CUR: 101 case CS35L41_BSTCVRT_SFT_RAMP: 102 case CS35L41_BSTCVRT_COEFF: 103 case CS35L41_BSTCVRT_SLOPE_LBST: 104 case CS35L41_BSTCVRT_SW_FREQ: 105 case CS35L41_BSTCVRT_DCM_CTRL: 106 case CS35L41_BSTCVRT_DCM_MODE_FORCE: 107 case CS35L41_BSTCVRT_OVERVOLT_CTRL: 108 case CS35L41_VI_VOL_POL: 109 case CS35L41_DTEMP_WARN_THLD: 110 case CS35L41_DTEMP_CFG: 111 case CS35L41_DTEMP_EN: 112 case CS35L41_VPVBST_FS_SEL: 113 case CS35L41_SP_ENABLES: 114 case CS35L41_SP_RATE_CTRL: 115 case CS35L41_SP_FORMAT: 116 case CS35L41_SP_HIZ_CTRL: 117 case CS35L41_SP_FRAME_TX_SLOT: 118 case CS35L41_SP_FRAME_RX_SLOT: 119 case CS35L41_SP_TX_WL: 120 case CS35L41_SP_RX_WL: 121 case CS35L41_DAC_PCM1_SRC: 122 case CS35L41_ASP_TX1_SRC: 123 case CS35L41_ASP_TX2_SRC: 124 case CS35L41_ASP_TX3_SRC: 125 case CS35L41_ASP_TX4_SRC: 126 case CS35L41_DSP1_RX1_SRC: 127 case CS35L41_DSP1_RX2_SRC: 128 case CS35L41_DSP1_RX3_SRC: 129 case CS35L41_DSP1_RX4_SRC: 130 case CS35L41_DSP1_RX5_SRC: 131 case CS35L41_DSP1_RX6_SRC: 132 case CS35L41_DSP1_RX7_SRC: 133 case CS35L41_DSP1_RX8_SRC: 134 case CS35L41_NGATE1_SRC: 135 case CS35L41_NGATE2_SRC: 136 case CS35L41_AMP_DIG_VOL_CTRL: 137 case CS35L41_VPBR_CFG: 138 case CS35L41_VBBR_CFG: 139 case CS35L41_VPBR_STATUS: 140 case CS35L41_VBBR_STATUS: 141 case CS35L41_OVERTEMP_CFG: 142 case CS35L41_AMP_ERR_VOL: 143 case CS35L41_VOL_STATUS_TO_DSP: 144 case CS35L41_CLASSH_CFG: 145 case CS35L41_WKFET_CFG: 146 case CS35L41_NG_CFG: 147 case CS35L41_AMP_GAIN_CTRL: 148 case CS35L41_DAC_MSM_CFG: 149 case CS35L41_IRQ1_CFG: 150 case CS35L41_IRQ1_STATUS: 151 case CS35L41_IRQ1_STATUS1: 152 case CS35L41_IRQ1_STATUS2: 153 case CS35L41_IRQ1_STATUS3: 154 case CS35L41_IRQ1_STATUS4: 155 case CS35L41_IRQ1_RAW_STATUS1: 156 case CS35L41_IRQ1_RAW_STATUS2: 157 case CS35L41_IRQ1_RAW_STATUS3: 158 case CS35L41_IRQ1_RAW_STATUS4: 159 case CS35L41_IRQ1_MASK1: 160 case CS35L41_IRQ1_MASK2: 161 case CS35L41_IRQ1_MASK3: 162 case CS35L41_IRQ1_MASK4: 163 case CS35L41_IRQ1_FRC1: 164 case CS35L41_IRQ1_FRC2: 165 case CS35L41_IRQ1_FRC3: 166 case CS35L41_IRQ1_FRC4: 167 case CS35L41_IRQ1_EDGE1: 168 case CS35L41_IRQ1_EDGE4: 169 case CS35L41_IRQ1_POL1: 170 case CS35L41_IRQ1_POL2: 171 case CS35L41_IRQ1_POL3: 172 case CS35L41_IRQ1_POL4: 173 case CS35L41_IRQ1_DB3: 174 case CS35L41_IRQ2_CFG: 175 case CS35L41_IRQ2_STATUS: 176 case CS35L41_IRQ2_STATUS1: 177 case CS35L41_IRQ2_STATUS2: 178 case CS35L41_IRQ2_STATUS3: 179 case CS35L41_IRQ2_STATUS4: 180 case CS35L41_IRQ2_RAW_STATUS1: 181 case CS35L41_IRQ2_RAW_STATUS2: 182 case CS35L41_IRQ2_RAW_STATUS3: 183 case CS35L41_IRQ2_RAW_STATUS4: 184 case CS35L41_IRQ2_MASK1: 185 case CS35L41_IRQ2_MASK2: 186 case CS35L41_IRQ2_MASK3: 187 case CS35L41_IRQ2_MASK4: 188 case CS35L41_IRQ2_FRC1: 189 case CS35L41_IRQ2_FRC2: 190 case CS35L41_IRQ2_FRC3: 191 case CS35L41_IRQ2_FRC4: 192 case CS35L41_IRQ2_EDGE1: 193 case CS35L41_IRQ2_EDGE4: 194 case CS35L41_IRQ2_POL1: 195 case CS35L41_IRQ2_POL2: 196 case CS35L41_IRQ2_POL3: 197 case CS35L41_IRQ2_POL4: 198 case CS35L41_IRQ2_DB3: 199 case CS35L41_GPIO_STATUS1: 200 case CS35L41_GPIO1_CTRL1: 201 case CS35L41_GPIO2_CTRL1: 202 case CS35L41_MIXER_NGATE_CFG: 203 case CS35L41_MIXER_NGATE_CH1_CFG: 204 case CS35L41_MIXER_NGATE_CH2_CFG: 205 case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: 206 case CS35L41_CLOCK_DETECT_1: 207 case CS35L41_DIE_STS1: 208 case CS35L41_DIE_STS2: 209 case CS35L41_TEMP_CAL1: 210 case CS35L41_TEMP_CAL2: 211 case CS35L41_DSP1_TIMESTAMP_COUNT: 212 case CS35L41_DSP1_SYS_ID: 213 case CS35L41_DSP1_SYS_VERSION: 214 case CS35L41_DSP1_SYS_CORE_ID: 215 case CS35L41_DSP1_SYS_AHB_ADDR: 216 case CS35L41_DSP1_SYS_XSRAM_SIZE: 217 case CS35L41_DSP1_SYS_YSRAM_SIZE: 218 case CS35L41_DSP1_SYS_PSRAM_SIZE: 219 case CS35L41_DSP1_SYS_PM_BOOT_SIZE: 220 case CS35L41_DSP1_SYS_FEATURES: 221 case CS35L41_DSP1_SYS_FIR_FILTERS: 222 case CS35L41_DSP1_SYS_LMS_FILTERS: 223 case CS35L41_DSP1_SYS_XM_BANK_SIZE: 224 case CS35L41_DSP1_SYS_YM_BANK_SIZE: 225 case CS35L41_DSP1_SYS_PM_BANK_SIZE: 226 case CS35L41_DSP1_RX1_RATE: 227 case CS35L41_DSP1_RX2_RATE: 228 case CS35L41_DSP1_RX3_RATE: 229 case CS35L41_DSP1_RX4_RATE: 230 case CS35L41_DSP1_RX5_RATE: 231 case CS35L41_DSP1_RX6_RATE: 232 case CS35L41_DSP1_RX7_RATE: 233 case CS35L41_DSP1_RX8_RATE: 234 case CS35L41_DSP1_TX1_RATE: 235 case CS35L41_DSP1_TX2_RATE: 236 case CS35L41_DSP1_TX3_RATE: 237 case CS35L41_DSP1_TX4_RATE: 238 case CS35L41_DSP1_TX5_RATE: 239 case CS35L41_DSP1_TX6_RATE: 240 case CS35L41_DSP1_TX7_RATE: 241 case CS35L41_DSP1_TX8_RATE: 242 case CS35L41_DSP1_SCRATCH1: 243 case CS35L41_DSP1_SCRATCH2: 244 case CS35L41_DSP1_SCRATCH3: 245 case CS35L41_DSP1_SCRATCH4: 246 case CS35L41_DSP1_CCM_CORE_CTRL: 247 case CS35L41_DSP1_CCM_CLK_OVERRIDE: 248 case CS35L41_DSP1_XM_MSTR_EN: 249 case CS35L41_DSP1_XM_CORE_PRI: 250 case CS35L41_DSP1_XM_AHB_PACK_PL_PRI: 251 case CS35L41_DSP1_XM_AHB_UP_PL_PRI: 252 case CS35L41_DSP1_XM_ACCEL_PL0_PRI: 253 case CS35L41_DSP1_XM_NPL0_PRI: 254 case CS35L41_DSP1_YM_MSTR_EN: 255 case CS35L41_DSP1_YM_CORE_PRI: 256 case CS35L41_DSP1_YM_AHB_PACK_PL_PRI: 257 case CS35L41_DSP1_YM_AHB_UP_PL_PRI: 258 case CS35L41_DSP1_YM_ACCEL_PL0_PRI: 259 case CS35L41_DSP1_YM_NPL0_PRI: 260 case CS35L41_DSP1_MPU_XM_ACCESS0: 261 case CS35L41_DSP1_MPU_YM_ACCESS0: 262 case CS35L41_DSP1_MPU_WNDW_ACCESS0: 263 case CS35L41_DSP1_MPU_XREG_ACCESS0: 264 case CS35L41_DSP1_MPU_YREG_ACCESS0: 265 case CS35L41_DSP1_MPU_XM_ACCESS1: 266 case CS35L41_DSP1_MPU_YM_ACCESS1: 267 case CS35L41_DSP1_MPU_WNDW_ACCESS1: 268 case CS35L41_DSP1_MPU_XREG_ACCESS1: 269 case CS35L41_DSP1_MPU_YREG_ACCESS1: 270 case CS35L41_DSP1_MPU_XM_ACCESS2: 271 case CS35L41_DSP1_MPU_YM_ACCESS2: 272 case CS35L41_DSP1_MPU_WNDW_ACCESS2: 273 case CS35L41_DSP1_MPU_XREG_ACCESS2: 274 case CS35L41_DSP1_MPU_YREG_ACCESS2: 275 case CS35L41_DSP1_MPU_XM_ACCESS3: 276 case CS35L41_DSP1_MPU_YM_ACCESS3: 277 case CS35L41_DSP1_MPU_WNDW_ACCESS3: 278 case CS35L41_DSP1_MPU_XREG_ACCESS3: 279 case CS35L41_DSP1_MPU_YREG_ACCESS3: 280 case CS35L41_DSP1_MPU_XM_VIO_ADDR: 281 case CS35L41_DSP1_MPU_XM_VIO_STATUS: 282 case CS35L41_DSP1_MPU_YM_VIO_ADDR: 283 case CS35L41_DSP1_MPU_YM_VIO_STATUS: 284 case CS35L41_DSP1_MPU_PM_VIO_ADDR: 285 case CS35L41_DSP1_MPU_PM_VIO_STATUS: 286 case CS35L41_DSP1_MPU_LOCK_CONFIG: 287 case CS35L41_DSP1_MPU_WDT_RST_CTRL: 288 case CS35L41_OTP_TRIM_1: 289 case CS35L41_OTP_TRIM_2: 290 case CS35L41_OTP_TRIM_3: 291 case CS35L41_OTP_TRIM_4: 292 case CS35L41_OTP_TRIM_5: 293 case CS35L41_OTP_TRIM_6: 294 case CS35L41_OTP_TRIM_7: 295 case CS35L41_OTP_TRIM_8: 296 case CS35L41_OTP_TRIM_9: 297 case CS35L41_OTP_TRIM_10: 298 case CS35L41_OTP_TRIM_11: 299 case CS35L41_OTP_TRIM_12: 300 case CS35L41_OTP_TRIM_13: 301 case CS35L41_OTP_TRIM_14: 302 case CS35L41_OTP_TRIM_15: 303 case CS35L41_OTP_TRIM_16: 304 case CS35L41_OTP_TRIM_17: 305 case CS35L41_OTP_TRIM_18: 306 case CS35L41_OTP_TRIM_19: 307 case CS35L41_OTP_TRIM_20: 308 case CS35L41_OTP_TRIM_21: 309 case CS35L41_OTP_TRIM_22: 310 case CS35L41_OTP_TRIM_23: 311 case CS35L41_OTP_TRIM_24: 312 case CS35L41_OTP_TRIM_25: 313 case CS35L41_OTP_TRIM_26: 314 case CS35L41_OTP_TRIM_27: 315 case CS35L41_OTP_TRIM_28: 316 case CS35L41_OTP_TRIM_29: 317 case CS35L41_OTP_TRIM_30: 318 case CS35L41_OTP_TRIM_31: 319 case CS35L41_OTP_TRIM_32: 320 case CS35L41_OTP_TRIM_33: 321 case CS35L41_OTP_TRIM_34: 322 case CS35L41_OTP_TRIM_35: 323 case CS35L41_OTP_TRIM_36: 324 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 325 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 326 case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: 327 case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: 328 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 329 case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: 330 case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: 331 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 332 /*test regs*/ 333 case CS35L41_PLL_OVR: 334 case CS35L41_BST_TEST_DUTY: 335 case CS35L41_DIGPWM_IOCTRL: 336 return true; 337 default: 338 return false; 339 } 340 } 341 342 static bool cs35l41_precious_reg(struct device *dev, unsigned int reg) 343 { 344 switch (reg) { 345 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 346 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 347 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 348 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 349 return true; 350 default: 351 return false; 352 } 353 } 354 355 static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg) 356 { 357 switch (reg) { 358 case CS35L41_DEVID: 359 case CS35L41_SFT_RESET: 360 case CS35L41_FABID: 361 case CS35L41_REVID: 362 case CS35L41_DTEMP_EN: 363 case CS35L41_IRQ1_STATUS: 364 case CS35L41_IRQ1_STATUS1: 365 case CS35L41_IRQ1_STATUS2: 366 case CS35L41_IRQ1_STATUS3: 367 case CS35L41_IRQ1_STATUS4: 368 case CS35L41_IRQ1_RAW_STATUS1: 369 case CS35L41_IRQ1_RAW_STATUS2: 370 case CS35L41_IRQ1_RAW_STATUS3: 371 case CS35L41_IRQ1_RAW_STATUS4: 372 case CS35L41_IRQ1_FRC1: 373 case CS35L41_IRQ1_FRC2: 374 case CS35L41_IRQ1_FRC3: 375 case CS35L41_IRQ1_FRC4: 376 case CS35L41_IRQ1_EDGE1: 377 case CS35L41_IRQ1_EDGE4: 378 case CS35L41_IRQ1_POL1: 379 case CS35L41_IRQ1_POL2: 380 case CS35L41_IRQ1_POL3: 381 case CS35L41_IRQ1_POL4: 382 case CS35L41_IRQ1_DB3: 383 case CS35L41_IRQ2_STATUS: 384 case CS35L41_IRQ2_STATUS1: 385 case CS35L41_IRQ2_STATUS2: 386 case CS35L41_IRQ2_STATUS3: 387 case CS35L41_IRQ2_STATUS4: 388 case CS35L41_IRQ2_RAW_STATUS1: 389 case CS35L41_IRQ2_RAW_STATUS2: 390 case CS35L41_IRQ2_RAW_STATUS3: 391 case CS35L41_IRQ2_RAW_STATUS4: 392 case CS35L41_IRQ2_FRC1: 393 case CS35L41_IRQ2_FRC2: 394 case CS35L41_IRQ2_FRC3: 395 case CS35L41_IRQ2_FRC4: 396 case CS35L41_IRQ2_EDGE1: 397 case CS35L41_IRQ2_EDGE4: 398 case CS35L41_IRQ2_POL1: 399 case CS35L41_IRQ2_POL2: 400 case CS35L41_IRQ2_POL3: 401 case CS35L41_IRQ2_POL4: 402 case CS35L41_IRQ2_DB3: 403 case CS35L41_GPIO_STATUS1: 404 case CS35L41_OTP_TRIM_1: 405 case CS35L41_OTP_TRIM_2: 406 case CS35L41_OTP_TRIM_3: 407 case CS35L41_OTP_TRIM_4: 408 case CS35L41_OTP_TRIM_5: 409 case CS35L41_OTP_TRIM_6: 410 case CS35L41_OTP_TRIM_7: 411 case CS35L41_OTP_TRIM_8: 412 case CS35L41_OTP_TRIM_9: 413 case CS35L41_OTP_TRIM_10: 414 case CS35L41_OTP_TRIM_11: 415 case CS35L41_OTP_TRIM_12: 416 case CS35L41_OTP_TRIM_13: 417 case CS35L41_OTP_TRIM_14: 418 case CS35L41_OTP_TRIM_15: 419 case CS35L41_OTP_TRIM_16: 420 case CS35L41_OTP_TRIM_17: 421 case CS35L41_OTP_TRIM_18: 422 case CS35L41_OTP_TRIM_19: 423 case CS35L41_OTP_TRIM_20: 424 case CS35L41_OTP_TRIM_21: 425 case CS35L41_OTP_TRIM_22: 426 case CS35L41_OTP_TRIM_23: 427 case CS35L41_OTP_TRIM_24: 428 case CS35L41_OTP_TRIM_25: 429 case CS35L41_OTP_TRIM_26: 430 case CS35L41_OTP_TRIM_27: 431 case CS35L41_OTP_TRIM_28: 432 case CS35L41_OTP_TRIM_29: 433 case CS35L41_OTP_TRIM_30: 434 case CS35L41_OTP_TRIM_31: 435 case CS35L41_OTP_TRIM_32: 436 case CS35L41_OTP_TRIM_33: 437 case CS35L41_OTP_TRIM_34: 438 case CS35L41_OTP_TRIM_35: 439 case CS35L41_OTP_TRIM_36: 440 case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: 441 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 442 case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: 443 case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: 444 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 445 case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: 446 case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: 447 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 448 case CS35L41_DSP1_CCM_CORE_CTRL ... CS35L41_DSP1_WDT_STATUS: 449 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 450 return true; 451 default: 452 return false; 453 } 454 } 455 456 static const struct cs35l41_otp_packed_element_t otp_map_1[CS35L41_NUM_OTP_ELEM] = { 457 /* addr shift size */ 458 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ 459 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ 460 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ 461 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ 462 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ 463 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ 464 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ 465 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ 466 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ 467 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ 468 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ 469 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ 470 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ 471 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ 472 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ 473 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ 474 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ 475 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ 476 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ 477 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ 478 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ 479 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ 480 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ 481 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ 482 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ 483 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ 484 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ 485 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ 486 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ 487 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ 488 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ 489 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ 490 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ 491 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ 492 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ 493 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ 494 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ 495 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ 496 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ 497 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ 498 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ 499 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ 500 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ 501 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ 502 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ 503 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ 504 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ 505 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ 506 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ 507 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ 508 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ 509 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ 510 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ 511 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ 512 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ 513 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ 514 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ 515 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ 516 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ 517 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ 518 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ 519 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ 520 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ 521 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ 522 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ 523 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ 524 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ 525 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ 526 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ 527 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ 528 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ 529 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ 530 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ 531 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ 532 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ 533 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ 534 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ 535 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ 536 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ 537 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ 538 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ 539 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ 540 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ 541 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ 542 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ 543 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ 544 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ 545 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ 546 { 0x00007434, 17, 1 }, /*FORCE_CAL*/ 547 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ 548 { 0x00007068, 0, 9 }, /*MODIX*/ 549 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ 550 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ 551 { 0x00000000, 0, 1 }, /*extra bit*/ 552 { 0x00017040, 0, 8 }, /*X_COORDINATE*/ 553 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ 554 { 0x00017040, 16, 8 }, /*WAFER_ID*/ 555 { 0x00017040, 24, 8 }, /*DVS*/ 556 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ 557 }; 558 559 static const struct cs35l41_otp_packed_element_t otp_map_2[CS35L41_NUM_OTP_ELEM] = { 560 /* addr shift size */ 561 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ 562 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ 563 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ 564 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ 565 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ 566 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ 567 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ 568 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ 569 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ 570 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ 571 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ 572 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ 573 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ 574 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ 575 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ 576 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ 577 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ 578 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ 579 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ 580 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ 581 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ 582 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ 583 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ 584 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ 585 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ 586 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ 587 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ 588 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ 589 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ 590 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ 591 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ 592 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ 593 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ 594 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ 595 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ 596 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ 597 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ 598 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ 599 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ 600 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ 601 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ 602 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ 603 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ 604 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ 605 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ 606 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ 607 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ 608 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ 609 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ 610 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ 611 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ 612 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ 613 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ 614 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ 615 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ 616 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ 617 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ 618 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ 619 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ 620 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ 621 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ 622 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ 623 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ 624 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ 625 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ 626 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ 627 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ 628 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ 629 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ 630 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ 631 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ 632 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ 633 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ 634 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ 635 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ 636 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ 637 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ 638 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ 639 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ 640 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ 641 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ 642 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ 643 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ 644 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ 645 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ 646 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ 647 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ 648 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ 649 { 0x00007434, 17, 1 }, /*FORCE_CAL*/ 650 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ 651 { 0x00007068, 0, 9 }, /*MODIX*/ 652 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ 653 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ 654 { 0x00004000, 11, 1 }, /*VMON_POL*/ 655 { 0x00017040, 0, 8 }, /*X_COORDINATE*/ 656 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ 657 { 0x00017040, 16, 8 }, /*WAFER_ID*/ 658 { 0x00017040, 24, 8 }, /*DVS*/ 659 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ 660 }; 661 662 static const struct reg_sequence cs35l41_reva0_errata_patch[] = { 663 { 0x00000040, 0x00005555 }, 664 { 0x00000040, 0x0000AAAA }, 665 { 0x00003854, 0x05180240 }, 666 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 667 { 0x00004310, 0x00000000 }, 668 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 669 { CS35L41_OTP_TRIM_30, 0x9091A1C8 }, 670 { 0x00003014, 0x0200EE0E }, 671 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 672 { 0x00000054, 0x00000004 }, 673 { CS35L41_IRQ1_DB3, 0x00000000 }, 674 { CS35L41_IRQ2_DB3, 0x00000000 }, 675 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 676 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 677 { 0x00000040, 0x0000CCCC }, 678 { 0x00000040, 0x00003333 }, 679 { CS35L41_PWR_CTRL2, 0x00000000 }, 680 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 681 }; 682 683 static const struct reg_sequence cs35l41_revb0_errata_patch[] = { 684 { 0x00000040, 0x00005555 }, 685 { 0x00000040, 0x0000AAAA }, 686 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 687 { 0x00004310, 0x00000000 }, 688 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 689 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 690 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 691 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 692 { 0x00000040, 0x0000CCCC }, 693 { 0x00000040, 0x00003333 }, 694 { CS35L41_PWR_CTRL2, 0x00000000 }, 695 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 696 }; 697 698 static const struct reg_sequence cs35l41_revb2_errata_patch[] = { 699 { 0x00000040, 0x00005555 }, 700 { 0x00000040, 0x0000AAAA }, 701 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 702 { 0x00004310, 0x00000000 }, 703 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 704 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 705 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 706 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 707 { 0x00000040, 0x0000CCCC }, 708 { 0x00000040, 0x00003333 }, 709 { CS35L41_PWR_CTRL2, 0x00000000 }, 710 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 711 }; 712 713 static const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[] = { 714 { 715 .id = 0x01, 716 .map = otp_map_1, 717 .num_elements = CS35L41_NUM_OTP_ELEM, 718 .bit_offset = 16, 719 .word_offset = 2, 720 }, 721 { 722 .id = 0x02, 723 .map = otp_map_2, 724 .num_elements = CS35L41_NUM_OTP_ELEM, 725 .bit_offset = 16, 726 .word_offset = 2, 727 }, 728 { 729 .id = 0x03, 730 .map = otp_map_2, 731 .num_elements = CS35L41_NUM_OTP_ELEM, 732 .bit_offset = 16, 733 .word_offset = 2, 734 }, 735 { 736 .id = 0x06, 737 .map = otp_map_2, 738 .num_elements = CS35L41_NUM_OTP_ELEM, 739 .bit_offset = 16, 740 .word_offset = 2, 741 }, 742 { 743 .id = 0x08, 744 .map = otp_map_1, 745 .num_elements = CS35L41_NUM_OTP_ELEM, 746 .bit_offset = 16, 747 .word_offset = 2, 748 }, 749 }; 750 751 struct regmap_config cs35l41_regmap_i2c = { 752 .reg_bits = 32, 753 .val_bits = 32, 754 .reg_stride = CS35L41_REGSTRIDE, 755 .reg_format_endian = REGMAP_ENDIAN_BIG, 756 .val_format_endian = REGMAP_ENDIAN_BIG, 757 .max_register = CS35L41_LASTREG, 758 .reg_defaults = cs35l41_reg, 759 .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), 760 .volatile_reg = cs35l41_volatile_reg, 761 .readable_reg = cs35l41_readable_reg, 762 .precious_reg = cs35l41_precious_reg, 763 .cache_type = REGCACHE_RBTREE, 764 }; 765 EXPORT_SYMBOL_GPL(cs35l41_regmap_i2c); 766 767 struct regmap_config cs35l41_regmap_spi = { 768 .reg_bits = 32, 769 .val_bits = 32, 770 .pad_bits = 16, 771 .reg_stride = CS35L41_REGSTRIDE, 772 .reg_format_endian = REGMAP_ENDIAN_BIG, 773 .val_format_endian = REGMAP_ENDIAN_BIG, 774 .max_register = CS35L41_LASTREG, 775 .reg_defaults = cs35l41_reg, 776 .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), 777 .volatile_reg = cs35l41_volatile_reg, 778 .readable_reg = cs35l41_readable_reg, 779 .precious_reg = cs35l41_precious_reg, 780 .cache_type = REGCACHE_RBTREE, 781 }; 782 EXPORT_SYMBOL_GPL(cs35l41_regmap_spi); 783 784 static const struct cs35l41_otp_map_element_t *cs35l41_find_otp_map(u32 otp_id) 785 { 786 int i; 787 788 for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) { 789 if (cs35l41_otp_map_map[i].id == otp_id) 790 return &cs35l41_otp_map_map[i]; 791 } 792 793 return NULL; 794 } 795 796 int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap) 797 { 798 const struct cs35l41_otp_map_element_t *otp_map_match; 799 const struct cs35l41_otp_packed_element_t *otp_map; 800 int bit_offset, word_offset, ret, i; 801 unsigned int bit_sum = 8; 802 u32 otp_val, otp_id_reg; 803 u32 *otp_mem; 804 805 otp_mem = kmalloc_array(CS35L41_OTP_SIZE_WORDS, sizeof(*otp_mem), GFP_KERNEL); 806 if (!otp_mem) 807 return -ENOMEM; 808 809 ret = regmap_read(regmap, CS35L41_OTPID, &otp_id_reg); 810 if (ret) { 811 dev_err(dev, "Read OTP ID failed: %d\n", ret); 812 goto err_otp_unpack; 813 } 814 815 otp_map_match = cs35l41_find_otp_map(otp_id_reg); 816 817 if (!otp_map_match) { 818 dev_err(dev, "OTP Map matching ID %d not found\n", otp_id_reg); 819 ret = -EINVAL; 820 goto err_otp_unpack; 821 } 822 823 ret = regmap_bulk_read(regmap, CS35L41_OTP_MEM0, otp_mem, CS35L41_OTP_SIZE_WORDS); 824 if (ret) { 825 dev_err(dev, "Read OTP Mem failed: %d\n", ret); 826 goto err_otp_unpack; 827 } 828 829 otp_map = otp_map_match->map; 830 831 bit_offset = otp_map_match->bit_offset; 832 word_offset = otp_map_match->word_offset; 833 834 ret = regmap_write(regmap, CS35L41_TEST_KEY_CTL, 0x00000055); 835 if (ret) { 836 dev_err(dev, "Write Unlock key failed 1/2: %d\n", ret); 837 goto err_otp_unpack; 838 } 839 ret = regmap_write(regmap, CS35L41_TEST_KEY_CTL, 0x000000AA); 840 if (ret) { 841 dev_err(dev, "Write Unlock key failed 2/2: %d\n", ret); 842 goto err_otp_unpack; 843 } 844 845 for (i = 0; i < otp_map_match->num_elements; i++) { 846 dev_dbg(dev, "bitoffset= %d, word_offset=%d, bit_sum mod 32=%d\n", 847 bit_offset, word_offset, bit_sum % 32); 848 if (bit_offset + otp_map[i].size - 1 >= 32) { 849 otp_val = (otp_mem[word_offset] & 850 GENMASK(31, bit_offset)) >> bit_offset; 851 otp_val |= (otp_mem[++word_offset] & 852 GENMASK(bit_offset + otp_map[i].size - 33, 0)) << 853 (32 - bit_offset); 854 bit_offset += otp_map[i].size - 32; 855 } else { 856 otp_val = (otp_mem[word_offset] & 857 GENMASK(bit_offset + otp_map[i].size - 1, bit_offset) 858 ) >> bit_offset; 859 bit_offset += otp_map[i].size; 860 } 861 bit_sum += otp_map[i].size; 862 863 if (bit_offset == 32) { 864 bit_offset = 0; 865 word_offset++; 866 } 867 868 if (otp_map[i].reg != 0) { 869 ret = regmap_update_bits(regmap, otp_map[i].reg, 870 GENMASK(otp_map[i].shift + otp_map[i].size - 1, 871 otp_map[i].shift), 872 otp_val << otp_map[i].shift); 873 if (ret < 0) { 874 dev_err(dev, "Write OTP val failed: %d\n", ret); 875 goto err_otp_unpack; 876 } 877 } 878 } 879 880 ret = regmap_write(regmap, CS35L41_TEST_KEY_CTL, 0x000000CC); 881 if (ret) { 882 dev_err(dev, "Write Lock key failed 1/2: %d\n", ret); 883 goto err_otp_unpack; 884 } 885 ret = regmap_write(regmap, CS35L41_TEST_KEY_CTL, 0x00000033); 886 if (ret) { 887 dev_err(dev, "Write Lock key failed 2/2: %d\n", ret); 888 goto err_otp_unpack; 889 } 890 ret = 0; 891 892 err_otp_unpack: 893 kfree(otp_mem); 894 895 return ret; 896 } 897 EXPORT_SYMBOL_GPL(cs35l41_otp_unpack); 898 899 int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid) 900 { 901 char *rev; 902 int ret; 903 904 switch (reg_revid) { 905 case CS35L41_REVID_A0: 906 ret = regmap_register_patch(reg, cs35l41_reva0_errata_patch, 907 ARRAY_SIZE(cs35l41_reva0_errata_patch)); 908 rev = "A0"; 909 break; 910 case CS35L41_REVID_B0: 911 ret = regmap_register_patch(reg, cs35l41_revb0_errata_patch, 912 ARRAY_SIZE(cs35l41_revb0_errata_patch)); 913 rev = "B0"; 914 break; 915 case CS35L41_REVID_B2: 916 ret = regmap_register_patch(reg, cs35l41_revb2_errata_patch, 917 ARRAY_SIZE(cs35l41_revb2_errata_patch)); 918 rev = "B2"; 919 break; 920 default: 921 ret = -EINVAL; 922 rev = "XX"; 923 break; 924 } 925 926 if (ret) 927 dev_err(dev, "Failed to apply %s errata patch: %d\n", rev, ret); 928 929 ret = regmap_write(reg, CS35L41_DSP1_CCM_CORE_CTRL, 0); 930 if (ret < 0) 931 dev_err(dev, "Write CCM_CORE_CTRL failed: %d\n", ret); 932 933 return ret; 934 } 935 EXPORT_SYMBOL_GPL(cs35l41_register_errata_patch); 936 937 int cs35l41_set_channels(struct device *dev, struct regmap *reg, 938 unsigned int tx_num, unsigned int *tx_slot, 939 unsigned int rx_num, unsigned int *rx_slot) 940 { 941 unsigned int val, mask; 942 int i; 943 944 if (tx_num > 4 || rx_num > 2) 945 return -EINVAL; 946 947 val = 0; 948 mask = 0; 949 for (i = 0; i < rx_num; i++) { 950 dev_dbg(dev, "rx slot %d position = %d\n", i, rx_slot[i]); 951 val |= rx_slot[i] << (i * 8); 952 mask |= 0x3F << (i * 8); 953 } 954 regmap_update_bits(reg, CS35L41_SP_FRAME_RX_SLOT, mask, val); 955 956 val = 0; 957 mask = 0; 958 for (i = 0; i < tx_num; i++) { 959 dev_dbg(dev, "tx slot %d position = %d\n", i, tx_slot[i]); 960 val |= tx_slot[i] << (i * 8); 961 mask |= 0x3F << (i * 8); 962 } 963 regmap_update_bits(reg, CS35L41_SP_FRAME_TX_SLOT, mask, val); 964 965 return 0; 966 } 967 EXPORT_SYMBOL_GPL(cs35l41_set_channels); 968 969 static const unsigned char cs35l41_bst_k1_table[4][5] = { 970 { 0x24, 0x32, 0x32, 0x4F, 0x57 }, 971 { 0x24, 0x32, 0x32, 0x4F, 0x57 }, 972 { 0x40, 0x32, 0x32, 0x4F, 0x57 }, 973 { 0x40, 0x32, 0x32, 0x4F, 0x57 } 974 }; 975 976 static const unsigned char cs35l41_bst_k2_table[4][5] = { 977 { 0x24, 0x49, 0x66, 0xA3, 0xEA }, 978 { 0x24, 0x49, 0x66, 0xA3, 0xEA }, 979 { 0x48, 0x49, 0x66, 0xA3, 0xEA }, 980 { 0x48, 0x49, 0x66, 0xA3, 0xEA } 981 }; 982 983 static const unsigned char cs35l41_bst_slope_table[4] = { 984 0x75, 0x6B, 0x3B, 0x28 985 }; 986 987 988 int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, int boost_cap, 989 int boost_ipk) 990 { 991 unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled; 992 int ret; 993 994 switch (boost_ind) { 995 case 1000: /* 1.0 uH */ 996 bst_lbst_val = 0; 997 break; 998 case 1200: /* 1.2 uH */ 999 bst_lbst_val = 1; 1000 break; 1001 case 1500: /* 1.5 uH */ 1002 bst_lbst_val = 2; 1003 break; 1004 case 2200: /* 2.2 uH */ 1005 bst_lbst_val = 3; 1006 break; 1007 default: 1008 dev_err(dev, "Invalid boost inductor value: %d nH\n", boost_ind); 1009 return -EINVAL; 1010 } 1011 1012 switch (boost_cap) { 1013 case 0 ... 19: 1014 bst_cbst_range = 0; 1015 break; 1016 case 20 ... 50: 1017 bst_cbst_range = 1; 1018 break; 1019 case 51 ... 100: 1020 bst_cbst_range = 2; 1021 break; 1022 case 101 ... 200: 1023 bst_cbst_range = 3; 1024 break; 1025 default: /* 201 uF and greater */ 1026 bst_cbst_range = 4; 1027 } 1028 1029 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_COEFF, 1030 CS35L41_BST_K1_MASK | CS35L41_BST_K2_MASK, 1031 cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range] 1032 << CS35L41_BST_K1_SHIFT | 1033 cs35l41_bst_k2_table[bst_lbst_val][bst_cbst_range] 1034 << CS35L41_BST_K2_SHIFT); 1035 if (ret) { 1036 dev_err(dev, "Failed to write boost coefficients: %d\n", ret); 1037 return ret; 1038 } 1039 1040 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST, 1041 CS35L41_BST_SLOPE_MASK | CS35L41_BST_LBST_VAL_MASK, 1042 cs35l41_bst_slope_table[bst_lbst_val] 1043 << CS35L41_BST_SLOPE_SHIFT | 1044 bst_lbst_val << CS35L41_BST_LBST_VAL_SHIFT); 1045 if (ret) { 1046 dev_err(dev, "Failed to write boost slope/inductor value: %d\n", ret); 1047 return ret; 1048 } 1049 1050 if (boost_ipk < 1600 || boost_ipk > 4500) { 1051 dev_err(dev, "Invalid boost inductor peak current: %d mA\n", boost_ipk); 1052 return -EINVAL; 1053 } 1054 bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10; 1055 1056 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR, CS35L41_BST_IPK_MASK, 1057 bst_ipk_scaled << CS35L41_BST_IPK_SHIFT); 1058 if (ret) { 1059 dev_err(dev, "Failed to write boost inductor peak current: %d\n", ret); 1060 return ret; 1061 } 1062 1063 return 0; 1064 } 1065 EXPORT_SYMBOL_GPL(cs35l41_boost_config); 1066 1067 MODULE_DESCRIPTION("CS35L41 library"); 1068 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1069 MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <tanureal@opensource.cirrus.com>"); 1070 MODULE_LICENSE("GPL"); 1071