1 /* 2 * cs35l33.h -- CS35L33 ALSA SoC audio driver 3 * 4 * Copyright 2016 Cirrus Logic, Inc. 5 * 6 * Author: Paul Handrigan <paul.handrigan@cirrus.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 */ 13 14 #ifndef __CS35L33_H__ 15 #define __CS35L33_H__ 16 17 #define CS35L33_CHIP_ID 0x00035A33 18 #define CS35L33_DEVID_AB 0x01 /* Device ID A & B [RO] */ 19 #define CS35L33_DEVID_CD 0x02 /* Device ID C & D [RO] */ 20 #define CS35L33_DEVID_E 0x03 /* Device ID E [RO] */ 21 #define CS35L33_FAB_ID 0x04 /* Fab ID [RO] */ 22 #define CS35L33_REV_ID 0x05 /* Revision ID [RO] */ 23 #define CS35L33_PWRCTL1 0x06 /* Power Ctl 1 */ 24 #define CS35L33_PWRCTL2 0x07 /* Power Ctl 2 */ 25 #define CS35L33_CLK_CTL 0x08 /* Clock Ctl */ 26 #define CS35L33_BST_PEAK_CTL 0x09 /* Max Current for Boost */ 27 #define CS35L33_PROTECT_CTL 0x0A /* Amp Protection Parameters */ 28 #define CS35L33_BST_CTL1 0x0B /* Boost Converter CTL1 */ 29 #define CS35L33_BST_CTL2 0x0C /* Boost Converter CTL2 */ 30 #define CS35L33_ADSP_CTL 0x0D /* Serial Port Control */ 31 #define CS35L33_ADC_CTL 0x0E /* ADC Control */ 32 #define CS35L33_DAC_CTL 0x0F /* DAC Control */ 33 #define CS35L33_DIG_VOL_CTL 0x10 /* Digital Volume CTL */ 34 #define CS35L33_CLASSD_CTL 0x11 /* Class D Amp CTL */ 35 #define CS35L33_AMP_CTL 0x12 /* Amp Gain/Protecton Release CTL */ 36 #define CS35L33_INT_MASK_1 0x13 /* Interrupt Mask 1 */ 37 #define CS35L33_INT_MASK_2 0x14 /* Interrupt Mask 2 */ 38 #define CS35L33_INT_STATUS_1 0x15 /* Interrupt Status 1 [RO] */ 39 #define CS35L33_INT_STATUS_2 0x16 /* Interrupt Status 2 [RO] */ 40 #define CS35L33_DIAG_LOCK 0x17 /* Diagnostic Mode Register Lock */ 41 #define CS35L33_DIAG_CTRL_1 0x18 /* Diagnostic Mode Register Control */ 42 #define CS35L33_DIAG_CTRL_2 0x19 /* Diagnostic Mode Register Control 2 */ 43 #define CS35L33_HG_MEMLDO_CTL 0x23 /* H/G Memory/LDO CTL */ 44 #define CS35L33_HG_REL_RATE 0x24 /* H/G Release Rate */ 45 #define CS35L33_LDO_DEL 0x25 /* LDO Entry Delay/VPhg Control 1 */ 46 #define CS35L33_HG_HEAD 0x29 /* H/G Headroom */ 47 #define CS35L33_HG_EN 0x2A /* H/G Enable/VPhg CNT2 */ 48 #define CS35L33_TX_VMON 0x2D /* TDM TX Control 1 (VMON) */ 49 #define CS35L33_TX_IMON 0x2E /* TDM TX Control 2 (IMON) */ 50 #define CS35L33_TX_VPMON 0x2F /* TDM TX Control 3 (VPMON) */ 51 #define CS35L33_TX_VBSTMON 0x30 /* TDM TX Control 4 (VBSTMON) */ 52 #define CS35L33_TX_FLAG 0x31 /* TDM TX Control 5 (FLAG) */ 53 #define CS35L33_TX_EN1 0x32 /* TDM TX Enable 1 */ 54 #define CS35L33_TX_EN2 0x33 /* TDM TX Enable 2 */ 55 #define CS35L33_TX_EN3 0x34 /* TDM TX Enable 3 */ 56 #define CS35L33_TX_EN4 0x35 /* TDM TX Enable 4 */ 57 #define CS35L33_RX_AUD 0x36 /* TDM RX Control 1 */ 58 #define CS35L33_RX_SPLY 0x37 /* TDM RX Control 2 */ 59 #define CS35L33_RX_ALIVE 0x38 /* TDM RX Control 3 */ 60 #define CS35L33_BST_CTL4 0x39 /* Boost Converter Control 4 */ 61 #define CS35L33_HG_STATUS 0x3F /* H/G Status */ 62 #define CS35L33_MAX_REGISTER 0x59 63 64 #define CS35L33_MCLK_5644 5644800 65 #define CS35L33_MCLK_6144 6144000 66 #define CS35L33_MCLK_6 6000000 67 #define CS35L33_MCLK_11289 11289600 68 #define CS35L33_MCLK_12 12000000 69 #define CS35L33_MCLK_12288 12288000 70 71 /* CS35L33_PWRCTL1 */ 72 #define CS35L33_PDN_AMP (1 << 7) 73 #define CS35L33_PDN_BST (1 << 2) 74 #define CS35L33_PDN_ALL 1 75 76 /* CS35L33_PWRCTL2 */ 77 #define CS35L33_PDN_VMON_SHIFT 7 78 #define CS35L33_PDN_VMON (1 << CS35L33_PDN_VMON_SHIFT) 79 #define CS35L33_PDN_IMON_SHIFT 6 80 #define CS35L33_PDN_IMON (1 << CS35L33_PDN_IMON_SHIFT) 81 #define CS35L33_PDN_VPMON_SHIFT 5 82 #define CS35L33_PDN_VPMON (1 << CS35L33_PDN_VPMON_SHIFT) 83 #define CS35L33_PDN_VBSTMON_SHIFT 4 84 #define CS35L33_PDN_VBSTMON (1 << CS35L33_PDN_VBSTMON_SHIFT) 85 #define CS35L33_SDOUT_3ST_I2S_SHIFT 3 86 #define CS35L33_SDOUT_3ST_I2S (1 << CS35L33_SDOUT_3ST_I2S_SHIFT) 87 #define CS35L33_PDN_SDIN_SHIFT 2 88 #define CS35L33_PDN_SDIN (1 << CS35L33_PDN_SDIN_SHIFT) 89 #define CS35L33_PDN_TDM_SHIFT 1 90 #define CS35L33_PDN_TDM (1 << CS35L33_PDN_TDM_SHIFT) 91 92 /* CS35L33_CLK_CTL */ 93 #define CS35L33_MCLKDIS (1 << 7) 94 #define CS35L33_MCLKDIV2 (1 << 6) 95 #define CS35L33_SDOUT_3ST_TDM (1 << 5) 96 #define CS35L33_INT_FS_RATE (1 << 4) 97 #define CS35L33_ADSP_FS 0xF 98 99 /* CS35L33_PROTECT_CTL */ 100 #define CS35L33_ALIVE_WD_DIS (3 << 2) 101 102 /* CS35L33_BST_CTL1 */ 103 #define CS35L33_BST_CTL_SRC (1 << 6) 104 #define CS35L33_BST_CTL_SHIFT (1 << 5) 105 #define CS35L33_BST_CTL_MASK 0x3F 106 107 /* CS35L33_BST_CTL2 */ 108 #define CS35L33_TDM_WD_SEL (1 << 4) 109 #define CS35L33_ALIVE_WD_DIS2 (1 << 3) 110 #define CS35L33_VBST_SR_STEP 0x3 111 112 /* CS35L33_ADSP_CTL */ 113 #define CS35L33_ADSP_DRIVE (1 << 7) 114 #define CS35L33_MS_MASK (1 << 6) 115 #define CS35L33_SDIN_LOC (3 << 4) 116 #define CS35L33_ALIVE_RATE 0x3 117 118 /* CS35L33_ADC_CTL */ 119 #define CS35L33_INV_VMON (1 << 7) 120 #define CS35L33_INV_IMON (1 << 6) 121 #define CS35L33_ADC_NOTCH_DIS (1 << 5) 122 #define CS35L33_IMON_SCALE 0xF 123 124 /* CS35L33_DAC_CTL */ 125 #define CS35L33_INV_DAC (1 << 7) 126 #define CS35L33_DAC_NOTCH_DIS (1 << 5) 127 #define CS35L33_DIGSFT (1 << 4) 128 #define CS35L33_DSR_RATE 0xF 129 130 /* CS35L33_CLASSD_CTL */ 131 #define CS35L33_AMP_SD (1 << 6) 132 #define CS35L33_AMP_DRV_SEL_SRC (1 << 5) 133 #define CS35L33_AMP_DRV_SEL_MASK 0x10 134 #define CS35L33_AMP_DRV_SEL_SHIFT 4 135 #define CS35L33_AMP_CAL (1 << 3) 136 #define CS35L33_GAIN_CHG_ZC_MASK 0x04 137 #define CS35L33_GAIN_CHG_ZC_SHIFT 2 138 #define CS35L33_CLASS_D_CTL_MASK 0x3F 139 140 /* CS35L33_AMP_CTL */ 141 #define CS35L33_AMP_GAIN 0xF0 142 #define CS35L33_CAL_ERR_RLS (1 << 3) 143 #define CS35L33_AMP_SHORT_RLS (1 << 2) 144 #define CS35L33_OTW_RLS (1 << 1) 145 #define CS35L33_OTE_RLS 1 146 147 /* CS35L33_INT_MASK_1 */ 148 #define CS35L33_M_CAL_ERR_SHIFT 6 149 #define CS35L33_M_CAL_ERR (1 << CS35L33_M_CAL_ERR_SHIFT) 150 #define CS35L33_M_ALIVE_ERR_SHIFT 5 151 #define CS35L33_M_ALIVE_ERR (1 << CS35L33_M_ALIVE_ERR_SHIFT) 152 #define CS35L33_M_AMP_SHORT_SHIFT 2 153 #define CS35L33_M_AMP_SHORT (1 << CS35L33_M_AMP_SHORT_SHIFT) 154 #define CS35L33_M_OTW_SHIFT 1 155 #define CS35L33_M_OTW (1 << CS35L33_M_OTW_SHIFT) 156 #define CS35L33_M_OTE_SHIFT 0 157 #define CS35L33_M_OTE (1 << CS35L33_M_OTE_SHIFT) 158 159 /* CS35L33_INT_STATUS_1 */ 160 #define CS35L33_CAL_ERR (1 << 6) 161 #define CS35L33_ALIVE_ERR (1 << 5) 162 #define CS35L33_ADSPCLK_ERR (1 << 4) 163 #define CS35L33_MCLK_ERR (1 << 3) 164 #define CS35L33_AMP_SHORT (1 << 2) 165 #define CS35L33_OTW (1 << 1) 166 #define CS35L33_OTE (1 << 0) 167 168 /* CS35L33_INT_STATUS_2 */ 169 #define CS35L33_VMON_OVFL (1 << 7) 170 #define CS35L33_IMON_OVFL (1 << 6) 171 #define CS35L33_VPMON_OVFL (1 << 5) 172 #define CS35L33_VBSTMON_OVFL (1 << 4) 173 #define CS35L33_PDN_DONE 1 174 175 /* CS35L33_BST_CTL4 */ 176 #define CS35L33_BST_RGS 0x70 177 #define CS35L33_BST_COEFF3 0xF 178 179 /* CS35L33_HG_MEMLDO_CTL */ 180 #define CS35L33_MEM_DEPTH_SHIFT 5 181 #define CS35L33_MEM_DEPTH_MASK (0x3 << CS35L33_MEM_DEPTH_SHIFT) 182 #define CS35L33_LDO_THLD_SHIFT 1 183 #define CS35L33_LDO_THLD_MASK (0xF << CS35L33_LDO_THLD_SHIFT) 184 #define CS35L33_LDO_DISABLE_SHIFT 0 185 #define CS35L33_LDO_DISABLE_MASK (0x1 << CS35L33_LDO_DISABLE_SHIFT) 186 187 /* CS35L33_LDO_DEL */ 188 #define CS35L33_VP_HG_VA_SHIFT 5 189 #define CS35L33_VP_HG_VA_MASK (0x7 << CS35L33_VP_HG_VA_SHIFT) 190 #define CS35L33_LDO_ENTRY_DELAY_SHIFT 2 191 #define CS35L33_LDO_ENTRY_DELAY_MASK (0x7 << CS35L33_LDO_ENTRY_DELAY_SHIFT) 192 #define CS35L33_VP_HG_RATE_SHIFT 0 193 #define CS35L33_VP_HG_RATE_MASK (0x3 << CS35L33_VP_HG_RATE_SHIFT) 194 195 /* CS35L33_HG_HEAD */ 196 #define CS35L33_HD_RM_SHIFT 0 197 #define CS35L33_HD_RM_MASK (0x7F << CS35L33_HD_RM_SHIFT) 198 199 /* CS35L33_HG_EN */ 200 #define CS35L33_CLASS_HG_ENA_SHIFT 7 201 #define CS35L33_CLASS_HG_EN_MASK (0x1 << CS35L33_CLASS_HG_ENA_SHIFT) 202 #define CS35L33_VP_HG_AUTO_SHIFT 6 203 #define CS35L33_VP_HG_AUTO_MASK (0x1 << 6) 204 #define CS35L33_VP_HG_SHIFT 0 205 #define CS35L33_VP_HG_MASK (0x1F << CS35L33_VP_HG_SHIFT) 206 207 #define CS35L33_RATES (SNDRV_PCM_RATE_8000_48000) 208 #define CS35L33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 209 SNDRV_PCM_FMTBIT_S24_LE) 210 211 /* CS35L33_{RX,TX}_X */ 212 #define CS35L33_X_STATE_SHIFT 7 213 #define CS35L33_X_STATE (1 << CS35L33_X_STATE_SHIFT) 214 #define CS35L33_X_LOC_SHIFT 0 215 #define CS35L33_X_LOC (0x1F << CS35L33_X_LOC_SHIFT) 216 217 /* CS35L33_RX_AUD */ 218 #define CS35L33_AUDIN_RX_DEPTH_SHIFT 5 219 #define CS35L33_AUDIN_RX_DEPTH (0x7 << CS35L33_AUDIN_RX_DEPTH_SHIFT) 220 221 #endif 222