1*028a2ae2SWeidong Wang // SPDX-License-Identifier: GPL-2.0-only 2*028a2ae2SWeidong Wang // 3*028a2ae2SWeidong Wang // aw88261.h -- AW88261 ALSA SoC Audio driver 4*028a2ae2SWeidong Wang // 5*028a2ae2SWeidong Wang // Copyright (c) 2023 awinic Technology CO., LTD 6*028a2ae2SWeidong Wang // 7*028a2ae2SWeidong Wang // Author: Jimmy Zhang <zhangjianming@awinic.com> 8*028a2ae2SWeidong Wang // Author: Weidong Wang <wangweidong.a@awinic.com> 9*028a2ae2SWeidong Wang // 10*028a2ae2SWeidong Wang 11*028a2ae2SWeidong Wang #ifndef __AW88261_H__ 12*028a2ae2SWeidong Wang #define __AW88261_H__ 13*028a2ae2SWeidong Wang 14*028a2ae2SWeidong Wang #define AW88261_ID_REG (0x00) 15*028a2ae2SWeidong Wang #define AW88261_SYSST_REG (0x01) 16*028a2ae2SWeidong Wang #define AW88261_SYSINT_REG (0x02) 17*028a2ae2SWeidong Wang #define AW88261_SYSINTM_REG (0x03) 18*028a2ae2SWeidong Wang #define AW88261_SYSCTRL_REG (0x04) 19*028a2ae2SWeidong Wang #define AW88261_SYSCTRL2_REG (0x05) 20*028a2ae2SWeidong Wang #define AW88261_I2SCTRL1_REG (0x06) 21*028a2ae2SWeidong Wang #define AW88261_I2SCTRL2_REG (0x07) 22*028a2ae2SWeidong Wang #define AW88261_I2SCTRL3_REG (0x08) 23*028a2ae2SWeidong Wang #define AW88261_DACCFG1_REG (0x09) 24*028a2ae2SWeidong Wang #define AW88261_DACCFG2_REG (0x0A) 25*028a2ae2SWeidong Wang #define AW88261_DACCFG3_REG (0x0B) 26*028a2ae2SWeidong Wang #define AW88261_DACCFG4_REG (0x0C) 27*028a2ae2SWeidong Wang #define AW88261_DACCFG5_REG (0x0D) 28*028a2ae2SWeidong Wang #define AW88261_DACCFG6_REG (0x0E) 29*028a2ae2SWeidong Wang #define AW88261_DACCFG7_REG (0x0F) 30*028a2ae2SWeidong Wang #define AW88261_DACCFG8_REG (0x10) 31*028a2ae2SWeidong Wang #define AW88261_PWMCTRL1_REG (0x11) 32*028a2ae2SWeidong Wang #define AW88261_PWMCTRL2_REG (0x12) 33*028a2ae2SWeidong Wang #define AW88261_I2SCFG1_REG (0x13) 34*028a2ae2SWeidong Wang #define AW88261_DBGCTRL_REG (0x14) 35*028a2ae2SWeidong Wang #define AW88261_DACCFG9_REG (0x15) 36*028a2ae2SWeidong Wang #define AW88261_DACCFG10_REG (0x16) 37*028a2ae2SWeidong Wang #define AW88261_DACST_REG (0x20) 38*028a2ae2SWeidong Wang #define AW88261_VBAT_REG (0x21) 39*028a2ae2SWeidong Wang #define AW88261_TEMP_REG (0x22) 40*028a2ae2SWeidong Wang #define AW88261_PVDD_REG (0x23) 41*028a2ae2SWeidong Wang #define AW88261_ISNDAT_REG (0x24) 42*028a2ae2SWeidong Wang #define AW88261_VSNDAT_REG (0x25) 43*028a2ae2SWeidong Wang #define AW88261_I2SINT_REG (0x26) 44*028a2ae2SWeidong Wang #define AW88261_I2SCAPCNT_REG (0x27) 45*028a2ae2SWeidong Wang #define AW88261_ANASTA1_REG (0x28) 46*028a2ae2SWeidong Wang #define AW88261_ANASTA2_REG (0x29) 47*028a2ae2SWeidong Wang #define AW88261_ANASTA3_REG (0x2A) 48*028a2ae2SWeidong Wang #define AW88261_TESTDET_REG (0x2B) 49*028a2ae2SWeidong Wang #define AW88261_DSMCFG1_REG (0x30) 50*028a2ae2SWeidong Wang #define AW88261_DSMCFG2_REG (0x31) 51*028a2ae2SWeidong Wang #define AW88261_DSMCFG3_REG (0x32) 52*028a2ae2SWeidong Wang #define AW88261_DSMCFG4_REG (0x33) 53*028a2ae2SWeidong Wang #define AW88261_DSMCFG5_REG (0x34) 54*028a2ae2SWeidong Wang #define AW88261_DSMCFG6_REG (0x35) 55*028a2ae2SWeidong Wang #define AW88261_DSMCFG7_REG (0x36) 56*028a2ae2SWeidong Wang #define AW88261_DSMCFG8_REG (0x37) 57*028a2ae2SWeidong Wang #define AW88261_TESTIN_REG (0x38) 58*028a2ae2SWeidong Wang #define AW88261_TESTOUT_REG (0x39) 59*028a2ae2SWeidong Wang #define AW88261_SADCCTRL1_REG (0x3A) 60*028a2ae2SWeidong Wang #define AW88261_SADCCTRL2_REG (0x3B) 61*028a2ae2SWeidong Wang #define AW88261_SADCCTRL3_REG (0x3C) 62*028a2ae2SWeidong Wang #define AW88261_SADCCTRL4_REG (0x3D) 63*028a2ae2SWeidong Wang #define AW88261_SADCCTRL5_REG (0x3E) 64*028a2ae2SWeidong Wang #define AW88261_SADCCTRL6_REG (0x3F) 65*028a2ae2SWeidong Wang #define AW88261_SADCCTRL7_REG (0x40) 66*028a2ae2SWeidong Wang #define AW88261_VSNTM1_REG (0x50) 67*028a2ae2SWeidong Wang #define AW88261_VSNTM2_REG (0x51) 68*028a2ae2SWeidong Wang #define AW88261_ISNCTRL1_REG (0x52) 69*028a2ae2SWeidong Wang #define AW88261_ISNCTRL2_REG (0x53) 70*028a2ae2SWeidong Wang #define AW88261_PLLCTRL1_REG (0x54) 71*028a2ae2SWeidong Wang #define AW88261_PLLCTRL2_REG (0x55) 72*028a2ae2SWeidong Wang #define AW88261_PLLCTRL3_REG (0x56) 73*028a2ae2SWeidong Wang #define AW88261_CDACTRL1_REG (0x57) 74*028a2ae2SWeidong Wang #define AW88261_CDACTRL2_REG (0x58) 75*028a2ae2SWeidong Wang #define AW88261_DITHERCFG1_REG (0x59) 76*028a2ae2SWeidong Wang #define AW88261_DITHERCFG2_REG (0x5A) 77*028a2ae2SWeidong Wang #define AW88261_DITHERCFG3_REG (0x5B) 78*028a2ae2SWeidong Wang #define AW88261_CPCTRL_REG (0x5C) 79*028a2ae2SWeidong Wang #define AW88261_BSTCTRL1_REG (0x60) 80*028a2ae2SWeidong Wang #define AW88261_BSTCTRL2_REG (0x61) 81*028a2ae2SWeidong Wang #define AW88261_BSTCTRL3_REG (0x62) 82*028a2ae2SWeidong Wang #define AW88261_BSTCTRL4_REG (0x63) 83*028a2ae2SWeidong Wang #define AW88261_BSTCTRL5_REG (0x64) 84*028a2ae2SWeidong Wang #define AW88261_BSTCTRL6_REG (0x65) 85*028a2ae2SWeidong Wang #define AW88261_BSTCTRL7_REG (0x66) 86*028a2ae2SWeidong Wang #define AW88261_BSTCTRL8_REG (0x67) 87*028a2ae2SWeidong Wang #define AW88261_BSTCTRL9_REG (0x68) 88*028a2ae2SWeidong Wang #define AW88261_TM_REG (0x6F) 89*028a2ae2SWeidong Wang #define AW88261_TESTCTRL1_REG (0x70) 90*028a2ae2SWeidong Wang #define AW88261_TESTCTRL2_REG (0x71) 91*028a2ae2SWeidong Wang #define AW88261_EFCTRL1_REG (0x72) 92*028a2ae2SWeidong Wang #define AW88261_EFCTRL2_REG (0x73) 93*028a2ae2SWeidong Wang #define AW88261_EFWH_REG (0x74) 94*028a2ae2SWeidong Wang #define AW88261_EFWM2_REG (0x75) 95*028a2ae2SWeidong Wang #define AW88261_EFWM1_REG (0x76) 96*028a2ae2SWeidong Wang #define AW88261_EFWL_REG (0x77) 97*028a2ae2SWeidong Wang #define AW88261_EFRH4_REG (0x78) 98*028a2ae2SWeidong Wang #define AW88261_EFRH3_REG (0x79) 99*028a2ae2SWeidong Wang #define AW88261_EFRH2_REG (0x7A) 100*028a2ae2SWeidong Wang #define AW88261_EFRH1_REG (0x7B) 101*028a2ae2SWeidong Wang #define AW88261_EFRL4_REG (0x7C) 102*028a2ae2SWeidong Wang #define AW88261_EFRL3_REG (0x7D) 103*028a2ae2SWeidong Wang #define AW88261_EFRL2_REG (0x7E) 104*028a2ae2SWeidong Wang #define AW88261_EFRL1_REG (0x7F) 105*028a2ae2SWeidong Wang 106*028a2ae2SWeidong Wang #define AW88261_REG_MAX (0x80) 107*028a2ae2SWeidong Wang #define AW88261_EF_DBMD_MASK (0xfff7) 108*028a2ae2SWeidong Wang #define AW88261_OR_VALUE (0x0008) 109*028a2ae2SWeidong Wang 110*028a2ae2SWeidong Wang #define AW88261_TEMH_MASK (0x83ff) 111*028a2ae2SWeidong Wang #define AW88261_TEML_MASK (0x83ff) 112*028a2ae2SWeidong Wang #define AW88261_DEFAULT_CFG (0x0000) 113*028a2ae2SWeidong Wang 114*028a2ae2SWeidong Wang #define AW88261_ICALK_SHIFT (0) 115*028a2ae2SWeidong Wang #define AW88261_ICALKL_SHIFT (0) 116*028a2ae2SWeidong Wang #define AW88261_VCALK_SHIFT (0) 117*028a2ae2SWeidong Wang #define AW88261_VCALKL_SHIFT (0) 118*028a2ae2SWeidong Wang 119*028a2ae2SWeidong Wang #define AW88261_AMPPD_START_BIT (1) 120*028a2ae2SWeidong Wang #define AW88261_AMPPD_BITS_LEN (1) 121*028a2ae2SWeidong Wang #define AW88261_AMPPD_MASK \ 122*028a2ae2SWeidong Wang (~(((1<<AW88261_AMPPD_BITS_LEN)-1) << AW88261_AMPPD_START_BIT)) 123*028a2ae2SWeidong Wang 124*028a2ae2SWeidong Wang #define AW88261_UVLS_START_BIT (14) 125*028a2ae2SWeidong Wang #define AW88261_UVLS_NORMAL (0) 126*028a2ae2SWeidong Wang #define AW88261_UVLS_NORMAL_VALUE \ 127*028a2ae2SWeidong Wang (AW88261_UVLS_NORMAL << AW88261_UVLS_START_BIT) 128*028a2ae2SWeidong Wang 129*028a2ae2SWeidong Wang #define AW88261_BSTOCS_START_BIT (11) 130*028a2ae2SWeidong Wang #define AW88261_BSTOCS_OVER_CURRENT (1) 131*028a2ae2SWeidong Wang #define AW88261_BSTOCS_OVER_CURRENT_VALUE \ 132*028a2ae2SWeidong Wang (AW88261_BSTOCS_OVER_CURRENT << AW88261_BSTOCS_START_BIT) 133*028a2ae2SWeidong Wang 134*028a2ae2SWeidong Wang #define AW88261_BSTS_START_BIT (9) 135*028a2ae2SWeidong Wang #define AW88261_BSTS_FINISHED (1) 136*028a2ae2SWeidong Wang #define AW88261_BSTS_FINISHED_VALUE \ 137*028a2ae2SWeidong Wang (AW88261_BSTS_FINISHED << AW88261_BSTS_START_BIT) 138*028a2ae2SWeidong Wang 139*028a2ae2SWeidong Wang #define AW88261_SWS_START_BIT (8) 140*028a2ae2SWeidong Wang #define AW88261_SWS_SWITCHING (1) 141*028a2ae2SWeidong Wang #define AW88261_SWS_SWITCHING_VALUE \ 142*028a2ae2SWeidong Wang (AW88261_SWS_SWITCHING << AW88261_SWS_START_BIT) 143*028a2ae2SWeidong Wang 144*028a2ae2SWeidong Wang #define AW88261_NOCLKS_START_BIT (5) 145*028a2ae2SWeidong Wang #define AW88261_NOCLKS_NO_CLOCK (1) 146*028a2ae2SWeidong Wang #define AW88261_NOCLKS_NO_CLOCK_VALUE \ 147*028a2ae2SWeidong Wang (AW88261_NOCLKS_NO_CLOCK << AW88261_NOCLKS_START_BIT) 148*028a2ae2SWeidong Wang 149*028a2ae2SWeidong Wang #define AW88261_CLKS_START_BIT (4) 150*028a2ae2SWeidong Wang #define AW88261_CLKS_STABLE (1) 151*028a2ae2SWeidong Wang #define AW88261_CLKS_STABLE_VALUE \ 152*028a2ae2SWeidong Wang (AW88261_CLKS_STABLE << AW88261_CLKS_START_BIT) 153*028a2ae2SWeidong Wang 154*028a2ae2SWeidong Wang #define AW88261_OCDS_START_BIT (3) 155*028a2ae2SWeidong Wang #define AW88261_OCDS_OC (1) 156*028a2ae2SWeidong Wang #define AW88261_OCDS_OC_VALUE \ 157*028a2ae2SWeidong Wang (AW88261_OCDS_OC << AW88261_OCDS_START_BIT) 158*028a2ae2SWeidong Wang 159*028a2ae2SWeidong Wang #define AW88261_OTHS_START_BIT (1) 160*028a2ae2SWeidong Wang #define AW88261_OTHS_OT (1) 161*028a2ae2SWeidong Wang #define AW88261_OTHS_OT_VALUE \ 162*028a2ae2SWeidong Wang (AW88261_OTHS_OT << AW88261_OTHS_START_BIT) 163*028a2ae2SWeidong Wang 164*028a2ae2SWeidong Wang #define AW88261_PLLS_START_BIT (0) 165*028a2ae2SWeidong Wang #define AW88261_PLLS_LOCKED (1) 166*028a2ae2SWeidong Wang #define AW88261_PLLS_LOCKED_VALUE \ 167*028a2ae2SWeidong Wang (AW88261_PLLS_LOCKED << AW88261_PLLS_START_BIT) 168*028a2ae2SWeidong Wang 169*028a2ae2SWeidong Wang #define AW88261_BIT_PLL_CHECK \ 170*028a2ae2SWeidong Wang (AW88261_CLKS_STABLE_VALUE | \ 171*028a2ae2SWeidong Wang AW88261_PLLS_LOCKED_VALUE) 172*028a2ae2SWeidong Wang 173*028a2ae2SWeidong Wang #define AW88261_BIT_SYSST_CHECK_MASK \ 174*028a2ae2SWeidong Wang (~(AW88261_UVLS_NORMAL_VALUE | \ 175*028a2ae2SWeidong Wang AW88261_BSTOCS_OVER_CURRENT_VALUE | \ 176*028a2ae2SWeidong Wang AW88261_BSTS_FINISHED_VALUE | \ 177*028a2ae2SWeidong Wang AW88261_SWS_SWITCHING_VALUE | \ 178*028a2ae2SWeidong Wang AW88261_NOCLKS_NO_CLOCK_VALUE | \ 179*028a2ae2SWeidong Wang AW88261_CLKS_STABLE_VALUE | \ 180*028a2ae2SWeidong Wang AW88261_OCDS_OC_VALUE | \ 181*028a2ae2SWeidong Wang AW88261_OTHS_OT_VALUE | \ 182*028a2ae2SWeidong Wang AW88261_PLLS_LOCKED_VALUE)) 183*028a2ae2SWeidong Wang 184*028a2ae2SWeidong Wang #define AW88261_BIT_SYSST_CHECK \ 185*028a2ae2SWeidong Wang (AW88261_BSTS_FINISHED_VALUE | \ 186*028a2ae2SWeidong Wang AW88261_SWS_SWITCHING_VALUE | \ 187*028a2ae2SWeidong Wang AW88261_CLKS_STABLE_VALUE | \ 188*028a2ae2SWeidong Wang AW88261_PLLS_LOCKED_VALUE) 189*028a2ae2SWeidong Wang 190*028a2ae2SWeidong Wang #define AW88261_ULS_HMUTE_START_BIT (14) 191*028a2ae2SWeidong Wang #define AW88261_ULS_HMUTE_BITS_LEN (1) 192*028a2ae2SWeidong Wang #define AW88261_ULS_HMUTE_MASK \ 193*028a2ae2SWeidong Wang (~(((1<<AW88261_ULS_HMUTE_BITS_LEN)-1) << AW88261_ULS_HMUTE_START_BIT)) 194*028a2ae2SWeidong Wang 195*028a2ae2SWeidong Wang #define AW88261_ULS_HMUTE_DISABLE (0) 196*028a2ae2SWeidong Wang #define AW88261_ULS_HMUTE_DISABLE_VALUE \ 197*028a2ae2SWeidong Wang (AW88261_ULS_HMUTE_DISABLE << AW88261_ULS_HMUTE_START_BIT) 198*028a2ae2SWeidong Wang 199*028a2ae2SWeidong Wang #define AW88261_ULS_HMUTE_ENABLE (1) 200*028a2ae2SWeidong Wang #define AW88261_ULS_HMUTE_ENABLE_VALUE \ 201*028a2ae2SWeidong Wang (AW88261_ULS_HMUTE_ENABLE << AW88261_ULS_HMUTE_START_BIT) 202*028a2ae2SWeidong Wang 203*028a2ae2SWeidong Wang #define AW88261_HMUTE_START_BIT (8) 204*028a2ae2SWeidong Wang #define AW88261_HMUTE_BITS_LEN (1) 205*028a2ae2SWeidong Wang #define AW88261_HMUTE_MASK \ 206*028a2ae2SWeidong Wang (~(((1<<AW88261_HMUTE_BITS_LEN)-1) << AW88261_HMUTE_START_BIT)) 207*028a2ae2SWeidong Wang 208*028a2ae2SWeidong Wang #define AW88261_HMUTE_DISABLE (0) 209*028a2ae2SWeidong Wang #define AW88261_HMUTE_DISABLE_VALUE \ 210*028a2ae2SWeidong Wang (AW88261_HMUTE_DISABLE << AW88261_HMUTE_START_BIT) 211*028a2ae2SWeidong Wang 212*028a2ae2SWeidong Wang #define AW88261_HMUTE_ENABLE (1) 213*028a2ae2SWeidong Wang #define AW88261_HMUTE_ENABLE_VALUE \ 214*028a2ae2SWeidong Wang (AW88261_HMUTE_ENABLE << AW88261_HMUTE_START_BIT) 215*028a2ae2SWeidong Wang 216*028a2ae2SWeidong Wang #define AW88261_AMPPD_START_BIT (1) 217*028a2ae2SWeidong Wang #define AW88261_AMPPD_BITS_LEN (1) 218*028a2ae2SWeidong Wang #define AW88261_AMPPD_MASK \ 219*028a2ae2SWeidong Wang (~(((1<<AW88261_AMPPD_BITS_LEN)-1) << AW88261_AMPPD_START_BIT)) 220*028a2ae2SWeidong Wang 221*028a2ae2SWeidong Wang #define AW88261_AMPPD_WORKING (0) 222*028a2ae2SWeidong Wang #define AW88261_AMPPD_WORKING_VALUE \ 223*028a2ae2SWeidong Wang (AW88261_AMPPD_WORKING << AW88261_AMPPD_START_BIT) 224*028a2ae2SWeidong Wang 225*028a2ae2SWeidong Wang #define AW88261_AMPPD_POWER_DOWN (1) 226*028a2ae2SWeidong Wang #define AW88261_AMPPD_POWER_DOWN_VALUE \ 227*028a2ae2SWeidong Wang (AW88261_AMPPD_POWER_DOWN << AW88261_AMPPD_START_BIT) 228*028a2ae2SWeidong Wang 229*028a2ae2SWeidong Wang #define AW88261_PWDN_START_BIT (0) 230*028a2ae2SWeidong Wang #define AW88261_PWDN_BITS_LEN (1) 231*028a2ae2SWeidong Wang #define AW88261_PWDN_MASK \ 232*028a2ae2SWeidong Wang (~(((1<<AW88261_PWDN_BITS_LEN)-1) << AW88261_PWDN_START_BIT)) 233*028a2ae2SWeidong Wang 234*028a2ae2SWeidong Wang #define AW88261_PWDN_WORKING (0) 235*028a2ae2SWeidong Wang #define AW88261_PWDN_WORKING_VALUE \ 236*028a2ae2SWeidong Wang (AW88261_PWDN_WORKING << AW88261_PWDN_START_BIT) 237*028a2ae2SWeidong Wang 238*028a2ae2SWeidong Wang #define AW88261_PWDN_POWER_DOWN (1) 239*028a2ae2SWeidong Wang #define AW88261_PWDN_POWER_DOWN_VALUE \ 240*028a2ae2SWeidong Wang (AW88261_PWDN_POWER_DOWN << AW88261_PWDN_START_BIT) 241*028a2ae2SWeidong Wang 242*028a2ae2SWeidong Wang #define AW88261_MUTE_VOL (90 * 8) 243*028a2ae2SWeidong Wang #define AW88261_VOLUME_STEP_DB (6 * 8) 244*028a2ae2SWeidong Wang 245*028a2ae2SWeidong Wang #define AW88261_VOL_6DB_START (6) 246*028a2ae2SWeidong Wang 247*028a2ae2SWeidong Wang #define AW88261_VOL_START_BIT (0) 248*028a2ae2SWeidong Wang #define AW88261_VOL_BITS_LEN (10) 249*028a2ae2SWeidong Wang #define AW88261_VOL_MASK \ 250*028a2ae2SWeidong Wang (~(((1<<AW88261_VOL_BITS_LEN)-1) << AW88261_VOL_START_BIT)) 251*028a2ae2SWeidong Wang 252*028a2ae2SWeidong Wang #define AW88261_VOL_DEFAULT_VALUE (0) 253*028a2ae2SWeidong Wang 254*028a2ae2SWeidong Wang #define AW88261_I2STXEN_START_BIT (6) 255*028a2ae2SWeidong Wang #define AW88261_I2STXEN_BITS_LEN (1) 256*028a2ae2SWeidong Wang #define AW88261_I2STXEN_MASK \ 257*028a2ae2SWeidong Wang (~(((1<<AW88261_I2STXEN_BITS_LEN)-1) << AW88261_I2STXEN_START_BIT)) 258*028a2ae2SWeidong Wang 259*028a2ae2SWeidong Wang #define AW88261_I2STXEN_DISABLE (0) 260*028a2ae2SWeidong Wang #define AW88261_I2STXEN_DISABLE_VALUE \ 261*028a2ae2SWeidong Wang (AW88261_I2STXEN_DISABLE << AW88261_I2STXEN_START_BIT) 262*028a2ae2SWeidong Wang 263*028a2ae2SWeidong Wang #define AW88261_I2STXEN_ENABLE (1) 264*028a2ae2SWeidong Wang #define AW88261_I2STXEN_ENABLE_VALUE \ 265*028a2ae2SWeidong Wang (AW88261_I2STXEN_ENABLE << AW88261_I2STXEN_START_BIT) 266*028a2ae2SWeidong Wang 267*028a2ae2SWeidong Wang #define AW88261_CCO_MUX_START_BIT (14) 268*028a2ae2SWeidong Wang #define AW88261_CCO_MUX_BITS_LEN (1) 269*028a2ae2SWeidong Wang #define AW88261_CCO_MUX_MASK \ 270*028a2ae2SWeidong Wang (~(((1<<AW88261_CCO_MUX_BITS_LEN)-1) << AW88261_CCO_MUX_START_BIT)) 271*028a2ae2SWeidong Wang 272*028a2ae2SWeidong Wang #define AW88261_CCO_MUX_DIVIDED (0) 273*028a2ae2SWeidong Wang #define AW88261_CCO_MUX_DIVIDED_VALUE \ 274*028a2ae2SWeidong Wang (AW88261_CCO_MUX_DIVIDED << AW88261_CCO_MUX_START_BIT) 275*028a2ae2SWeidong Wang 276*028a2ae2SWeidong Wang #define AW88261_CCO_MUX_BYPASS (1) 277*028a2ae2SWeidong Wang #define AW88261_CCO_MUX_BYPASS_VALUE \ 278*028a2ae2SWeidong Wang (AW88261_CCO_MUX_BYPASS << AW88261_CCO_MUX_START_BIT) 279*028a2ae2SWeidong Wang 280*028a2ae2SWeidong Wang #define AW88261_EF_VSN_GESLP_H_START_BIT (0) 281*028a2ae2SWeidong Wang #define AW88261_EF_VSN_GESLP_H_BITS_LEN (10) 282*028a2ae2SWeidong Wang #define AW88261_EF_VSN_GESLP_H_MASK \ 283*028a2ae2SWeidong Wang (~(((1<<AW88261_EF_VSN_GESLP_H_BITS_LEN)-1) << AW88261_EF_VSN_GESLP_H_START_BIT)) 284*028a2ae2SWeidong Wang 285*028a2ae2SWeidong Wang #define AW88261_EF_VSN_GESLP_L_START_BIT (0) 286*028a2ae2SWeidong Wang #define AW88261_EF_VSN_GESLP_L_BITS_LEN (10) 287*028a2ae2SWeidong Wang #define AW88261_EF_VSN_GESLP_L_MASK \ 288*028a2ae2SWeidong Wang (~(((1<<AW88261_EF_VSN_GESLP_L_BITS_LEN)-1) << AW88261_EF_VSN_GESLP_L_START_BIT)) 289*028a2ae2SWeidong Wang 290*028a2ae2SWeidong Wang #define AW88261_FORCE_PWM_START_BIT (12) 291*028a2ae2SWeidong Wang #define AW88261_FORCE_PWM_BITS_LEN (1) 292*028a2ae2SWeidong Wang #define AW88261_FORCE_PWM_MASK \ 293*028a2ae2SWeidong Wang (~(((1<<AW88261_FORCE_PWM_BITS_LEN)-1) << AW88261_FORCE_PWM_START_BIT)) 294*028a2ae2SWeidong Wang 295*028a2ae2SWeidong Wang #define AW88261_FORCE_PWM_FORCEMINUS_PWM (1) 296*028a2ae2SWeidong Wang #define AW88261_FORCE_PWM_FORCEMINUS_PWM_VALUE \ 297*028a2ae2SWeidong Wang (AW88261_FORCE_PWM_FORCEMINUS_PWM << AW88261_FORCE_PWM_START_BIT) 298*028a2ae2SWeidong Wang 299*028a2ae2SWeidong Wang #define AW88261_BST_OS_WIDTH_START_BIT (0) 300*028a2ae2SWeidong Wang #define AW88261_BST_OS_WIDTH_BITS_LEN (3) 301*028a2ae2SWeidong Wang #define AW88261_BST_OS_WIDTH_MASK \ 302*028a2ae2SWeidong Wang (~(((1<<AW88261_BST_OS_WIDTH_BITS_LEN)-1) << AW88261_BST_OS_WIDTH_START_BIT)) 303*028a2ae2SWeidong Wang 304*028a2ae2SWeidong Wang #define AW88261_BST_OS_WIDTH_50NS (4) 305*028a2ae2SWeidong Wang #define AW88261_BST_OS_WIDTH_50NS_VALUE \ 306*028a2ae2SWeidong Wang (AW88261_BST_OS_WIDTH_50NS << AW88261_BST_OS_WIDTH_START_BIT) 307*028a2ae2SWeidong Wang 308*028a2ae2SWeidong Wang /* BST_LOOPR bit 1:0 (BSTCTRL6 0x65) */ 309*028a2ae2SWeidong Wang #define AW88261_BST_LOOPR_START_BIT (0) 310*028a2ae2SWeidong Wang #define AW88261_BST_LOOPR_BITS_LEN (2) 311*028a2ae2SWeidong Wang #define AW88261_BST_LOOPR_MASK \ 312*028a2ae2SWeidong Wang (~(((1<<AW88261_BST_LOOPR_BITS_LEN)-1) << AW88261_BST_LOOPR_START_BIT)) 313*028a2ae2SWeidong Wang 314*028a2ae2SWeidong Wang #define AW88261_BST_LOOPR_340K (2) 315*028a2ae2SWeidong Wang #define AW88261_BST_LOOPR_340K_VALUE \ 316*028a2ae2SWeidong Wang (AW88261_BST_LOOPR_340K << AW88261_BST_LOOPR_START_BIT) 317*028a2ae2SWeidong Wang 318*028a2ae2SWeidong Wang /* RSQN_DLY bit 15:14 (BSTCTRL7 0x66) */ 319*028a2ae2SWeidong Wang #define AW88261_RSQN_DLY_START_BIT (14) 320*028a2ae2SWeidong Wang #define AW88261_RSQN_DLY_BITS_LEN (2) 321*028a2ae2SWeidong Wang #define AW88261_RSQN_DLY_MASK \ 322*028a2ae2SWeidong Wang (~(((1<<AW88261_RSQN_DLY_BITS_LEN)-1) << AW88261_RSQN_DLY_START_BIT)) 323*028a2ae2SWeidong Wang 324*028a2ae2SWeidong Wang #define AW88261_RSQN_DLY_35NS (2) 325*028a2ae2SWeidong Wang #define AW88261_RSQN_DLY_35NS_VALUE \ 326*028a2ae2SWeidong Wang (AW88261_RSQN_DLY_35NS << AW88261_RSQN_DLY_START_BIT) 327*028a2ae2SWeidong Wang 328*028a2ae2SWeidong Wang /* BURST_SSMODE bit 3 (BSTCTRL8 0x67) */ 329*028a2ae2SWeidong Wang #define AW88261_BURST_SSMODE_START_BIT (3) 330*028a2ae2SWeidong Wang #define AW88261_BURST_SSMODE_BITS_LEN (1) 331*028a2ae2SWeidong Wang #define AW88261_BURST_SSMODE_MASK \ 332*028a2ae2SWeidong Wang (~(((1<<AW88261_BURST_SSMODE_BITS_LEN)-1) << AW88261_BURST_SSMODE_START_BIT)) 333*028a2ae2SWeidong Wang 334*028a2ae2SWeidong Wang #define AW88261_BURST_SSMODE_FAST (0) 335*028a2ae2SWeidong Wang #define AW88261_BURST_SSMODE_FAST_VALUE \ 336*028a2ae2SWeidong Wang (AW88261_BURST_SSMODE_FAST << AW88261_BURST_SSMODE_START_BIT) 337*028a2ae2SWeidong Wang 338*028a2ae2SWeidong Wang /* BST_BURST bit 9:7 (BSTCTRL9 0x68) */ 339*028a2ae2SWeidong Wang #define AW88261_BST_BURST_START_BIT (7) 340*028a2ae2SWeidong Wang #define AW88261_BST_BURST_BITS_LEN (3) 341*028a2ae2SWeidong Wang #define AW88261_BST_BURST_MASK \ 342*028a2ae2SWeidong Wang (~(((1<<AW88261_BST_BURST_BITS_LEN)-1) << AW88261_BST_BURST_START_BIT)) 343*028a2ae2SWeidong Wang 344*028a2ae2SWeidong Wang #define AW88261_BST_BURST_30MA (2) 345*028a2ae2SWeidong Wang #define AW88261_BST_BURST_30MA_VALUE \ 346*028a2ae2SWeidong Wang (AW88261_BST_BURST_30MA << AW88261_BST_BURST_START_BIT) 347*028a2ae2SWeidong Wang 348*028a2ae2SWeidong Wang #define AW88261_EF_VSN_GESLP_SIGN_MASK (~0x0200) 349*028a2ae2SWeidong Wang #define AW88261_EF_VSN_GESLP_NEG (~0xfc00) 350*028a2ae2SWeidong Wang 351*028a2ae2SWeidong Wang #define AW88261_EF_ISN_GESLP_SIGN_MASK (~0x0200) 352*028a2ae2SWeidong Wang #define AW88261_EF_ISN_GESLP_NEG (~0xfc00) 353*028a2ae2SWeidong Wang 354*028a2ae2SWeidong Wang #define AW88261_EF_ISN_GESLP_H_START_BIT (0) 355*028a2ae2SWeidong Wang #define AW88261_EF_ISN_GESLP_H_BITS_LEN (10) 356*028a2ae2SWeidong Wang #define AW88261_EF_ISN_GESLP_H_MASK \ 357*028a2ae2SWeidong Wang (~(((1<<AW88261_EF_ISN_GESLP_H_BITS_LEN)-1) << AW88261_EF_ISN_GESLP_H_START_BIT)) 358*028a2ae2SWeidong Wang 359*028a2ae2SWeidong Wang #define AW88261_EF_ISN_GESLP_L_START_BIT (0) 360*028a2ae2SWeidong Wang #define AW88261_EF_ISN_GESLP_L_BITS_LEN (10) 361*028a2ae2SWeidong Wang #define AW88261_EF_ISN_GESLP_L_MASK \ 362*028a2ae2SWeidong Wang (~(((1<<AW88261_EF_ISN_GESLP_L_BITS_LEN)-1) << AW88261_EF_ISN_GESLP_L_START_BIT)) 363*028a2ae2SWeidong Wang 364*028a2ae2SWeidong Wang #define AW88261_CABL_BASE_VALUE (1000) 365*028a2ae2SWeidong Wang #define AW88261_ICABLK_FACTOR (1) 366*028a2ae2SWeidong Wang #define AW88261_VCABLK_FACTOR (1) 367*028a2ae2SWeidong Wang 368*028a2ae2SWeidong Wang #define AW88261_VCAL_FACTOR (1<<13) 369*028a2ae2SWeidong Wang 370*028a2ae2SWeidong Wang #define AW88261_START_RETRIES (5) 371*028a2ae2SWeidong Wang #define AW88261_START_WORK_DELAY_MS (0) 372*028a2ae2SWeidong Wang 373*028a2ae2SWeidong Wang #define AW88261_I2C_NAME "aw88261_smartpa" 374*028a2ae2SWeidong Wang 375*028a2ae2SWeidong Wang #define AW88261_RATES (SNDRV_PCM_RATE_8000_48000 | \ 376*028a2ae2SWeidong Wang SNDRV_PCM_RATE_96000) 377*028a2ae2SWeidong Wang #define AW88261_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 378*028a2ae2SWeidong Wang SNDRV_PCM_FMTBIT_S24_LE | \ 379*028a2ae2SWeidong Wang SNDRV_PCM_FMTBIT_S32_LE) 380*028a2ae2SWeidong Wang 381*028a2ae2SWeidong Wang #define FADE_TIME_MAX 100000 382*028a2ae2SWeidong Wang #define FADE_TIME_MIN 0 383*028a2ae2SWeidong Wang 384*028a2ae2SWeidong Wang #define AW88261_DEV_DEFAULT_CH (0) 385*028a2ae2SWeidong Wang #define AW88261_ACF_FILE "aw88261_acf.bin" 386*028a2ae2SWeidong Wang #define AW88261_DEV_SYSST_CHECK_MAX (10) 387*028a2ae2SWeidong Wang #define AW88261_SOFT_RESET_VALUE (0x55aa) 388*028a2ae2SWeidong Wang #define AW88261_REG_TO_DB (0x3f) 389*028a2ae2SWeidong Wang #define AW88261_VOL_START_MASK (0xfc00) 390*028a2ae2SWeidong Wang #define AW88261_INIT_PROFILE (0) 391*028a2ae2SWeidong Wang 392*028a2ae2SWeidong Wang #define REG_VAL_TO_DB(value) ((((value) >> AW88261_VOL_6DB_START) * \ 393*028a2ae2SWeidong Wang AW88261_VOLUME_STEP_DB) + \ 394*028a2ae2SWeidong Wang ((value) & AW88261_REG_TO_DB)) 395*028a2ae2SWeidong Wang #define DB_TO_REG_VAL(value) ((((value) / AW88261_VOLUME_STEP_DB) << \ 396*028a2ae2SWeidong Wang AW88261_VOL_6DB_START) + \ 397*028a2ae2SWeidong Wang ((value) % AW88261_VOLUME_STEP_DB)) 398*028a2ae2SWeidong Wang 399*028a2ae2SWeidong Wang #define AW88261_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \ 400*028a2ae2SWeidong Wang { \ 401*028a2ae2SWeidong Wang .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 402*028a2ae2SWeidong Wang .name = xname, \ 403*028a2ae2SWeidong Wang .info = profile_info, \ 404*028a2ae2SWeidong Wang .get = profile_get, \ 405*028a2ae2SWeidong Wang .put = profile_set, \ 406*028a2ae2SWeidong Wang } 407*028a2ae2SWeidong Wang 408*028a2ae2SWeidong Wang enum { 409*028a2ae2SWeidong Wang AW88261_SYNC_START = 0, 410*028a2ae2SWeidong Wang AW88261_ASYNC_START, 411*028a2ae2SWeidong Wang }; 412*028a2ae2SWeidong Wang 413*028a2ae2SWeidong Wang enum aw88261_id { 414*028a2ae2SWeidong Wang AW88261_CHIP_ID = 0x2113, 415*028a2ae2SWeidong Wang }; 416*028a2ae2SWeidong Wang 417*028a2ae2SWeidong Wang enum { 418*028a2ae2SWeidong Wang AW88261_500_US = 500, 419*028a2ae2SWeidong Wang AW88261_1000_US = 1000, 420*028a2ae2SWeidong Wang AW88261_2000_US = 2000, 421*028a2ae2SWeidong Wang }; 422*028a2ae2SWeidong Wang 423*028a2ae2SWeidong Wang enum { 424*028a2ae2SWeidong Wang AW88261_DEV_PW_OFF = 0, 425*028a2ae2SWeidong Wang AW88261_DEV_PW_ON, 426*028a2ae2SWeidong Wang }; 427*028a2ae2SWeidong Wang 428*028a2ae2SWeidong Wang enum { 429*028a2ae2SWeidong Wang AW88261_DEV_FW_FAILED = 0, 430*028a2ae2SWeidong Wang AW88261_DEV_FW_OK, 431*028a2ae2SWeidong Wang }; 432*028a2ae2SWeidong Wang 433*028a2ae2SWeidong Wang enum { 434*028a2ae2SWeidong Wang AW88261_EF_AND_CHECK = 0, 435*028a2ae2SWeidong Wang AW88261_EF_OR_CHECK, 436*028a2ae2SWeidong Wang }; 437*028a2ae2SWeidong Wang 438*028a2ae2SWeidong Wang enum { 439*028a2ae2SWeidong Wang AW88261_FRCSET_DISABLE = 0, 440*028a2ae2SWeidong Wang AW88261_FRCSET_ENABLE, 441*028a2ae2SWeidong Wang }; 442*028a2ae2SWeidong Wang 443*028a2ae2SWeidong Wang struct aw88261 { 444*028a2ae2SWeidong Wang struct aw_device *aw_pa; 445*028a2ae2SWeidong Wang struct mutex lock; 446*028a2ae2SWeidong Wang struct gpio_desc *reset_gpio; 447*028a2ae2SWeidong Wang struct delayed_work start_work; 448*028a2ae2SWeidong Wang struct regmap *regmap; 449*028a2ae2SWeidong Wang struct aw_container *aw_cfg; 450*028a2ae2SWeidong Wang 451*028a2ae2SWeidong Wang int efuse_check; 452*028a2ae2SWeidong Wang int frcset_en; 453*028a2ae2SWeidong Wang unsigned int mute_st; 454*028a2ae2SWeidong Wang unsigned int amppd_st; 455*028a2ae2SWeidong Wang 456*028a2ae2SWeidong Wang unsigned char phase_sync; 457*028a2ae2SWeidong Wang }; 458*028a2ae2SWeidong Wang 459*028a2ae2SWeidong Wang #endif 460