1 /* 2 * ADAV80X Audio Codec driver supporting ADAV801, ADAV803 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * Author: Yi Li <yi.li@analog.com> 6 * Author: Lars-Peter Clausen <lars@metafoo.de> 7 * 8 * Licensed under the GPL-2 or later. 9 */ 10 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/i2c.h> 15 #include <linux/spi/spi.h> 16 #include <linux/slab.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/tlv.h> 21 #include <sound/soc.h> 22 23 #include "adav80x.h" 24 25 #define ADAV80X_PLAYBACK_CTRL 0x04 26 #define ADAV80X_AUX_IN_CTRL 0x05 27 #define ADAV80X_REC_CTRL 0x06 28 #define ADAV80X_AUX_OUT_CTRL 0x07 29 #define ADAV80X_DPATH_CTRL1 0x62 30 #define ADAV80X_DPATH_CTRL2 0x63 31 #define ADAV80X_DAC_CTRL1 0x64 32 #define ADAV80X_DAC_CTRL2 0x65 33 #define ADAV80X_DAC_CTRL3 0x66 34 #define ADAV80X_DAC_L_VOL 0x68 35 #define ADAV80X_DAC_R_VOL 0x69 36 #define ADAV80X_PGA_L_VOL 0x6c 37 #define ADAV80X_PGA_R_VOL 0x6d 38 #define ADAV80X_ADC_CTRL1 0x6e 39 #define ADAV80X_ADC_CTRL2 0x6f 40 #define ADAV80X_ADC_L_VOL 0x70 41 #define ADAV80X_ADC_R_VOL 0x71 42 #define ADAV80X_PLL_CTRL1 0x74 43 #define ADAV80X_PLL_CTRL2 0x75 44 #define ADAV80X_ICLK_CTRL1 0x76 45 #define ADAV80X_ICLK_CTRL2 0x77 46 #define ADAV80X_PLL_CLK_SRC 0x78 47 #define ADAV80X_PLL_OUTE 0x7a 48 49 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 50 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) 51 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) 52 53 #define ADAV80X_ICLK_CTRL1_DAC_SRC(src) ((src) << 5) 54 #define ADAV80X_ICLK_CTRL1_ADC_SRC(src) ((src) << 2) 55 #define ADAV80X_ICLK_CTRL1_ICLK2_SRC(src) (src) 56 #define ADAV80X_ICLK_CTRL2_ICLK1_SRC(src) ((src) << 3) 57 58 #define ADAV80X_PLL_CTRL1_PLLDIV 0x10 59 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) 60 #define ADAV80X_PLL_CTRL1_XTLPD 0x02 61 62 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) 63 64 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) 65 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) 66 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) 67 68 #define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02) 69 #define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01) 70 #define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0f) 71 72 #define ADAV80X_ADC_CTRL1_MODULATOR_MASK 0x80 73 #define ADAV80X_ADC_CTRL1_MODULATOR_128FS 0x00 74 #define ADAV80X_ADC_CTRL1_MODULATOR_64FS 0x80 75 76 #define ADAV80X_DAC_CTRL1_PD 0x80 77 78 #define ADAV80X_DAC_CTRL2_DIV1 0x00 79 #define ADAV80X_DAC_CTRL2_DIV1_5 0x10 80 #define ADAV80X_DAC_CTRL2_DIV2 0x20 81 #define ADAV80X_DAC_CTRL2_DIV3 0x30 82 #define ADAV80X_DAC_CTRL2_DIV_MASK 0x30 83 84 #define ADAV80X_DAC_CTRL2_INTERPOL_256FS 0x00 85 #define ADAV80X_DAC_CTRL2_INTERPOL_128FS 0x40 86 #define ADAV80X_DAC_CTRL2_INTERPOL_64FS 0x80 87 #define ADAV80X_DAC_CTRL2_INTERPOL_MASK 0xc0 88 89 #define ADAV80X_DAC_CTRL2_DEEMPH_NONE 0x00 90 #define ADAV80X_DAC_CTRL2_DEEMPH_44 0x01 91 #define ADAV80X_DAC_CTRL2_DEEMPH_32 0x02 92 #define ADAV80X_DAC_CTRL2_DEEMPH_48 0x03 93 #define ADAV80X_DAC_CTRL2_DEEMPH_MASK 0x01 94 95 #define ADAV80X_CAPTURE_MODE_MASTER 0x20 96 #define ADAV80X_CAPTURE_WORD_LEN24 0x00 97 #define ADAV80X_CAPTURE_WORD_LEN20 0x04 98 #define ADAV80X_CAPTRUE_WORD_LEN18 0x08 99 #define ADAV80X_CAPTURE_WORD_LEN16 0x0c 100 #define ADAV80X_CAPTURE_WORD_LEN_MASK 0x0c 101 102 #define ADAV80X_CAPTURE_MODE_LEFT_J 0x00 103 #define ADAV80X_CAPTURE_MODE_I2S 0x01 104 #define ADAV80X_CAPTURE_MODE_RIGHT_J 0x03 105 #define ADAV80X_CAPTURE_MODE_MASK 0x03 106 107 #define ADAV80X_PLAYBACK_MODE_MASTER 0x10 108 #define ADAV80X_PLAYBACK_MODE_LEFT_J 0x00 109 #define ADAV80X_PLAYBACK_MODE_I2S 0x01 110 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_24 0x04 111 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_20 0x05 112 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_18 0x06 113 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_16 0x07 114 #define ADAV80X_PLAYBACK_MODE_MASK 0x07 115 116 #define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x)) 117 118 static struct reg_default adav80x_reg_defaults[] = { 119 { ADAV80X_PLAYBACK_CTRL, 0x01 }, 120 { ADAV80X_AUX_IN_CTRL, 0x01 }, 121 { ADAV80X_REC_CTRL, 0x02 }, 122 { ADAV80X_AUX_OUT_CTRL, 0x01 }, 123 { ADAV80X_DPATH_CTRL1, 0xc0 }, 124 { ADAV80X_DPATH_CTRL2, 0x11 }, 125 { ADAV80X_DAC_CTRL1, 0x00 }, 126 { ADAV80X_DAC_CTRL2, 0x00 }, 127 { ADAV80X_DAC_CTRL3, 0x00 }, 128 { ADAV80X_DAC_L_VOL, 0xff }, 129 { ADAV80X_DAC_R_VOL, 0xff }, 130 { ADAV80X_PGA_L_VOL, 0x00 }, 131 { ADAV80X_PGA_R_VOL, 0x00 }, 132 { ADAV80X_ADC_CTRL1, 0x00 }, 133 { ADAV80X_ADC_CTRL2, 0x00 }, 134 { ADAV80X_ADC_L_VOL, 0xff }, 135 { ADAV80X_ADC_R_VOL, 0xff }, 136 { ADAV80X_PLL_CTRL1, 0x00 }, 137 { ADAV80X_PLL_CTRL2, 0x00 }, 138 { ADAV80X_ICLK_CTRL1, 0x00 }, 139 { ADAV80X_ICLK_CTRL2, 0x00 }, 140 { ADAV80X_PLL_CLK_SRC, 0x00 }, 141 { ADAV80X_PLL_OUTE, 0x00 }, 142 }; 143 144 struct adav80x { 145 struct regmap *regmap; 146 147 enum adav80x_clk_src clk_src; 148 unsigned int sysclk; 149 enum adav80x_pll_src pll_src; 150 151 unsigned int dai_fmt[2]; 152 unsigned int rate; 153 bool deemph; 154 bool sysclk_pd[3]; 155 }; 156 157 static const char *adav80x_mux_text[] = { 158 "ADC", 159 "Playback", 160 "Aux Playback", 161 }; 162 163 static const unsigned int adav80x_mux_values[] = { 164 0, 2, 3, 165 }; 166 167 #define ADAV80X_MUX_ENUM_DECL(name, reg, shift) \ 168 SOC_VALUE_ENUM_DOUBLE_DECL(name, reg, shift, 7, \ 169 ARRAY_SIZE(adav80x_mux_text), adav80x_mux_text, \ 170 adav80x_mux_values) 171 172 static ADAV80X_MUX_ENUM_DECL(adav80x_aux_capture_enum, ADAV80X_DPATH_CTRL1, 0); 173 static ADAV80X_MUX_ENUM_DECL(adav80x_capture_enum, ADAV80X_DPATH_CTRL1, 3); 174 static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, ADAV80X_DPATH_CTRL2, 3); 175 176 static const struct snd_kcontrol_new adav80x_aux_capture_mux_ctrl = 177 SOC_DAPM_VALUE_ENUM("Route", adav80x_aux_capture_enum); 178 static const struct snd_kcontrol_new adav80x_capture_mux_ctrl = 179 SOC_DAPM_VALUE_ENUM("Route", adav80x_capture_enum); 180 static const struct snd_kcontrol_new adav80x_dac_mux_ctrl = 181 SOC_DAPM_VALUE_ENUM("Route", adav80x_dac_enum); 182 183 #define ADAV80X_MUX(name, ctrl) \ 184 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) 185 186 static const struct snd_soc_dapm_widget adav80x_dapm_widgets[] = { 187 SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_DAC_CTRL1, 7, 1), 188 SND_SOC_DAPM_ADC("ADC", NULL, ADAV80X_ADC_CTRL1, 5, 1), 189 190 SND_SOC_DAPM_PGA("Right PGA", ADAV80X_ADC_CTRL1, 0, 1, NULL, 0), 191 SND_SOC_DAPM_PGA("Left PGA", ADAV80X_ADC_CTRL1, 1, 1, NULL, 0), 192 193 SND_SOC_DAPM_AIF_OUT("AIFOUT", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 194 SND_SOC_DAPM_AIF_IN("AIFIN", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 195 196 SND_SOC_DAPM_AIF_OUT("AIFAUXOUT", "Aux Capture", 0, SND_SOC_NOPM, 0, 0), 197 SND_SOC_DAPM_AIF_IN("AIFAUXIN", "Aux Playback", 0, SND_SOC_NOPM, 0, 0), 198 199 ADAV80X_MUX("Aux Capture Select", &adav80x_aux_capture_mux_ctrl), 200 ADAV80X_MUX("Capture Select", &adav80x_capture_mux_ctrl), 201 ADAV80X_MUX("DAC Select", &adav80x_dac_mux_ctrl), 202 203 SND_SOC_DAPM_INPUT("VINR"), 204 SND_SOC_DAPM_INPUT("VINL"), 205 SND_SOC_DAPM_OUTPUT("VOUTR"), 206 SND_SOC_DAPM_OUTPUT("VOUTL"), 207 208 SND_SOC_DAPM_SUPPLY("SYSCLK", SND_SOC_NOPM, 0, 0, NULL, 0), 209 SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0), 210 SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0), 211 SND_SOC_DAPM_SUPPLY("OSC", ADAV80X_PLL_CTRL1, 1, 1, NULL, 0), 212 }; 213 214 static int adav80x_dapm_sysclk_check(struct snd_soc_dapm_widget *source, 215 struct snd_soc_dapm_widget *sink) 216 { 217 struct snd_soc_codec *codec = source->codec; 218 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 219 const char *clk; 220 221 switch (adav80x->clk_src) { 222 case ADAV80X_CLK_PLL1: 223 clk = "PLL1"; 224 break; 225 case ADAV80X_CLK_PLL2: 226 clk = "PLL2"; 227 break; 228 case ADAV80X_CLK_XTAL: 229 clk = "OSC"; 230 break; 231 default: 232 return 0; 233 } 234 235 return strcmp(source->name, clk) == 0; 236 } 237 238 static int adav80x_dapm_pll_check(struct snd_soc_dapm_widget *source, 239 struct snd_soc_dapm_widget *sink) 240 { 241 struct snd_soc_codec *codec = source->codec; 242 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 243 244 return adav80x->pll_src == ADAV80X_PLL_SRC_XTAL; 245 } 246 247 248 static const struct snd_soc_dapm_route adav80x_dapm_routes[] = { 249 { "DAC Select", "ADC", "ADC" }, 250 { "DAC Select", "Playback", "AIFIN" }, 251 { "DAC Select", "Aux Playback", "AIFAUXIN" }, 252 { "DAC", NULL, "DAC Select" }, 253 254 { "Capture Select", "ADC", "ADC" }, 255 { "Capture Select", "Playback", "AIFIN" }, 256 { "Capture Select", "Aux Playback", "AIFAUXIN" }, 257 { "AIFOUT", NULL, "Capture Select" }, 258 259 { "Aux Capture Select", "ADC", "ADC" }, 260 { "Aux Capture Select", "Playback", "AIFIN" }, 261 { "Aux Capture Select", "Aux Playback", "AIFAUXIN" }, 262 { "AIFAUXOUT", NULL, "Aux Capture Select" }, 263 264 { "VOUTR", NULL, "DAC" }, 265 { "VOUTL", NULL, "DAC" }, 266 267 { "Left PGA", NULL, "VINL" }, 268 { "Right PGA", NULL, "VINR" }, 269 { "ADC", NULL, "Left PGA" }, 270 { "ADC", NULL, "Right PGA" }, 271 272 { "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check }, 273 { "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check }, 274 { "SYSCLK", NULL, "OSC", adav80x_dapm_sysclk_check }, 275 { "PLL1", NULL, "OSC", adav80x_dapm_pll_check }, 276 { "PLL2", NULL, "OSC", adav80x_dapm_pll_check }, 277 278 { "ADC", NULL, "SYSCLK" }, 279 { "DAC", NULL, "SYSCLK" }, 280 { "AIFOUT", NULL, "SYSCLK" }, 281 { "AIFAUXOUT", NULL, "SYSCLK" }, 282 { "AIFIN", NULL, "SYSCLK" }, 283 { "AIFAUXIN", NULL, "SYSCLK" }, 284 }; 285 286 static int adav80x_set_deemph(struct snd_soc_codec *codec) 287 { 288 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 289 unsigned int val; 290 291 if (adav80x->deemph) { 292 switch (adav80x->rate) { 293 case 32000: 294 val = ADAV80X_DAC_CTRL2_DEEMPH_32; 295 break; 296 case 44100: 297 val = ADAV80X_DAC_CTRL2_DEEMPH_44; 298 break; 299 case 48000: 300 case 64000: 301 case 88200: 302 case 96000: 303 val = ADAV80X_DAC_CTRL2_DEEMPH_48; 304 break; 305 default: 306 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE; 307 break; 308 } 309 } else { 310 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE; 311 } 312 313 return regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2, 314 ADAV80X_DAC_CTRL2_DEEMPH_MASK, val); 315 } 316 317 static int adav80x_put_deemph(struct snd_kcontrol *kcontrol, 318 struct snd_ctl_elem_value *ucontrol) 319 { 320 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 321 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 322 unsigned int deemph = ucontrol->value.enumerated.item[0]; 323 324 if (deemph > 1) 325 return -EINVAL; 326 327 adav80x->deemph = deemph; 328 329 return adav80x_set_deemph(codec); 330 } 331 332 static int adav80x_get_deemph(struct snd_kcontrol *kcontrol, 333 struct snd_ctl_elem_value *ucontrol) 334 { 335 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 336 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 337 338 ucontrol->value.enumerated.item[0] = adav80x->deemph; 339 return 0; 340 }; 341 342 static const DECLARE_TLV_DB_SCALE(adav80x_inpga_tlv, 0, 50, 0); 343 static const DECLARE_TLV_DB_MINMAX(adav80x_digital_tlv, -9563, 0); 344 345 static const struct snd_kcontrol_new adav80x_controls[] = { 346 SOC_DOUBLE_R_TLV("Master Playback Volume", ADAV80X_DAC_L_VOL, 347 ADAV80X_DAC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv), 348 SOC_DOUBLE_R_TLV("Master Capture Volume", ADAV80X_ADC_L_VOL, 349 ADAV80X_ADC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv), 350 351 SOC_DOUBLE_R_TLV("PGA Capture Volume", ADAV80X_PGA_L_VOL, 352 ADAV80X_PGA_R_VOL, 0, 0x30, 0, adav80x_inpga_tlv), 353 354 SOC_DOUBLE("Master Playback Switch", ADAV80X_DAC_CTRL1, 0, 1, 1, 0), 355 SOC_DOUBLE("Master Capture Switch", ADAV80X_ADC_CTRL1, 2, 3, 1, 1), 356 357 SOC_SINGLE("ADC High Pass Filter Switch", ADAV80X_ADC_CTRL1, 6, 1, 0), 358 359 SOC_SINGLE_BOOL_EXT("Playback De-emphasis Switch", 0, 360 adav80x_get_deemph, adav80x_put_deemph), 361 }; 362 363 static unsigned int adav80x_port_ctrl_regs[2][2] = { 364 { ADAV80X_REC_CTRL, ADAV80X_PLAYBACK_CTRL, }, 365 { ADAV80X_AUX_OUT_CTRL, ADAV80X_AUX_IN_CTRL }, 366 }; 367 368 static int adav80x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 369 { 370 struct snd_soc_codec *codec = dai->codec; 371 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 372 unsigned int capture = 0x00; 373 unsigned int playback = 0x00; 374 375 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 376 case SND_SOC_DAIFMT_CBM_CFM: 377 capture |= ADAV80X_CAPTURE_MODE_MASTER; 378 playback |= ADAV80X_PLAYBACK_MODE_MASTER; 379 case SND_SOC_DAIFMT_CBS_CFS: 380 break; 381 default: 382 return -EINVAL; 383 } 384 385 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 386 case SND_SOC_DAIFMT_I2S: 387 capture |= ADAV80X_CAPTURE_MODE_I2S; 388 playback |= ADAV80X_PLAYBACK_MODE_I2S; 389 break; 390 case SND_SOC_DAIFMT_LEFT_J: 391 capture |= ADAV80X_CAPTURE_MODE_LEFT_J; 392 playback |= ADAV80X_PLAYBACK_MODE_LEFT_J; 393 break; 394 case SND_SOC_DAIFMT_RIGHT_J: 395 capture |= ADAV80X_CAPTURE_MODE_RIGHT_J; 396 playback |= ADAV80X_PLAYBACK_MODE_RIGHT_J_24; 397 break; 398 default: 399 return -EINVAL; 400 } 401 402 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 403 case SND_SOC_DAIFMT_NB_NF: 404 break; 405 default: 406 return -EINVAL; 407 } 408 409 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0], 410 ADAV80X_CAPTURE_MODE_MASK | ADAV80X_CAPTURE_MODE_MASTER, 411 capture); 412 regmap_write(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1], 413 playback); 414 415 adav80x->dai_fmt[dai->id] = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 416 417 return 0; 418 } 419 420 static int adav80x_set_adc_clock(struct snd_soc_codec *codec, 421 unsigned int sample_rate) 422 { 423 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 424 unsigned int val; 425 426 if (sample_rate <= 48000) 427 val = ADAV80X_ADC_CTRL1_MODULATOR_128FS; 428 else 429 val = ADAV80X_ADC_CTRL1_MODULATOR_64FS; 430 431 regmap_update_bits(adav80x->regmap, ADAV80X_ADC_CTRL1, 432 ADAV80X_ADC_CTRL1_MODULATOR_MASK, val); 433 434 return 0; 435 } 436 437 static int adav80x_set_dac_clock(struct snd_soc_codec *codec, 438 unsigned int sample_rate) 439 { 440 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 441 unsigned int val; 442 443 if (sample_rate <= 48000) 444 val = ADAV80X_DAC_CTRL2_DIV1 | ADAV80X_DAC_CTRL2_INTERPOL_256FS; 445 else 446 val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS; 447 448 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2, 449 ADAV80X_DAC_CTRL2_DIV_MASK | ADAV80X_DAC_CTRL2_INTERPOL_MASK, 450 val); 451 452 return 0; 453 } 454 455 static int adav80x_set_capture_pcm_format(struct snd_soc_codec *codec, 456 struct snd_soc_dai *dai, struct snd_pcm_hw_params *params) 457 { 458 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 459 unsigned int val; 460 461 switch (params_width(params)) { 462 case 16: 463 val = ADAV80X_CAPTURE_WORD_LEN16; 464 break; 465 case 18: 466 val = ADAV80X_CAPTRUE_WORD_LEN18; 467 break; 468 case 20: 469 val = ADAV80X_CAPTURE_WORD_LEN20; 470 break; 471 case 24: 472 val = ADAV80X_CAPTURE_WORD_LEN24; 473 break; 474 default: 475 return -EINVAL; 476 } 477 478 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0], 479 ADAV80X_CAPTURE_WORD_LEN_MASK, val); 480 481 return 0; 482 } 483 484 static int adav80x_set_playback_pcm_format(struct snd_soc_codec *codec, 485 struct snd_soc_dai *dai, struct snd_pcm_hw_params *params) 486 { 487 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 488 unsigned int val; 489 490 if (adav80x->dai_fmt[dai->id] != SND_SOC_DAIFMT_RIGHT_J) 491 return 0; 492 493 switch (params_width(params)) { 494 case 16: 495 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_16; 496 break; 497 case 18: 498 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_18; 499 break; 500 case 20: 501 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_20; 502 break; 503 case 24: 504 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_24; 505 break; 506 default: 507 return -EINVAL; 508 } 509 510 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1], 511 ADAV80X_PLAYBACK_MODE_MASK, val); 512 513 return 0; 514 } 515 516 static int adav80x_hw_params(struct snd_pcm_substream *substream, 517 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 518 { 519 struct snd_soc_codec *codec = dai->codec; 520 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 521 unsigned int rate = params_rate(params); 522 523 if (rate * 256 != adav80x->sysclk) 524 return -EINVAL; 525 526 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 527 adav80x_set_playback_pcm_format(codec, dai, params); 528 adav80x_set_dac_clock(codec, rate); 529 } else { 530 adav80x_set_capture_pcm_format(codec, dai, params); 531 adav80x_set_adc_clock(codec, rate); 532 } 533 adav80x->rate = rate; 534 adav80x_set_deemph(codec); 535 536 return 0; 537 } 538 539 static int adav80x_set_sysclk(struct snd_soc_codec *codec, 540 int clk_id, int source, 541 unsigned int freq, int dir) 542 { 543 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 544 545 if (dir == SND_SOC_CLOCK_IN) { 546 switch (clk_id) { 547 case ADAV80X_CLK_XIN: 548 case ADAV80X_CLK_XTAL: 549 case ADAV80X_CLK_MCLKI: 550 case ADAV80X_CLK_PLL1: 551 case ADAV80X_CLK_PLL2: 552 break; 553 default: 554 return -EINVAL; 555 } 556 557 adav80x->sysclk = freq; 558 559 if (adav80x->clk_src != clk_id) { 560 unsigned int iclk_ctrl1, iclk_ctrl2; 561 562 adav80x->clk_src = clk_id; 563 if (clk_id == ADAV80X_CLK_XTAL) 564 clk_id = ADAV80X_CLK_XIN; 565 566 iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) | 567 ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) | 568 ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id); 569 iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id); 570 571 regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL1, 572 iclk_ctrl1); 573 regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL2, 574 iclk_ctrl2); 575 576 snd_soc_dapm_sync(&codec->dapm); 577 } 578 } else { 579 unsigned int mask; 580 581 switch (clk_id) { 582 case ADAV80X_CLK_SYSCLK1: 583 case ADAV80X_CLK_SYSCLK2: 584 case ADAV80X_CLK_SYSCLK3: 585 break; 586 default: 587 return -EINVAL; 588 } 589 590 clk_id -= ADAV80X_CLK_SYSCLK1; 591 mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id); 592 593 if (freq == 0) { 594 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE, 595 mask, mask); 596 adav80x->sysclk_pd[clk_id] = true; 597 } else { 598 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE, 599 mask, 0); 600 adav80x->sysclk_pd[clk_id] = false; 601 } 602 603 if (adav80x->sysclk_pd[0]) 604 snd_soc_dapm_disable_pin(&codec->dapm, "PLL1"); 605 else 606 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL1"); 607 608 if (adav80x->sysclk_pd[1] || adav80x->sysclk_pd[2]) 609 snd_soc_dapm_disable_pin(&codec->dapm, "PLL2"); 610 else 611 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL2"); 612 613 snd_soc_dapm_sync(&codec->dapm); 614 } 615 616 return 0; 617 } 618 619 static int adav80x_set_pll(struct snd_soc_codec *codec, int pll_id, 620 int source, unsigned int freq_in, unsigned int freq_out) 621 { 622 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 623 unsigned int pll_ctrl1 = 0; 624 unsigned int pll_ctrl2 = 0; 625 unsigned int pll_src; 626 627 switch (source) { 628 case ADAV80X_PLL_SRC_XTAL: 629 case ADAV80X_PLL_SRC_XIN: 630 case ADAV80X_PLL_SRC_MCLKI: 631 break; 632 default: 633 return -EINVAL; 634 } 635 636 if (!freq_out) 637 return 0; 638 639 switch (freq_in) { 640 case 27000000: 641 break; 642 case 54000000: 643 if (source == ADAV80X_PLL_SRC_XIN) { 644 pll_ctrl1 |= ADAV80X_PLL_CTRL1_PLLDIV; 645 break; 646 } 647 default: 648 return -EINVAL; 649 } 650 651 if (freq_out > 12288000) { 652 pll_ctrl2 |= ADAV80X_PLL_CTRL2_DOUB(pll_id); 653 freq_out /= 2; 654 } 655 656 /* freq_out = sample_rate * 256 */ 657 switch (freq_out) { 658 case 8192000: 659 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_32(pll_id); 660 break; 661 case 11289600: 662 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_44(pll_id); 663 break; 664 case 12288000: 665 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_48(pll_id); 666 break; 667 default: 668 return -EINVAL; 669 } 670 671 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL1, 672 ADAV80X_PLL_CTRL1_PLLDIV, pll_ctrl1); 673 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL2, 674 ADAV80X_PLL_CTRL2_PLL_MASK(pll_id), pll_ctrl2); 675 676 if (source != adav80x->pll_src) { 677 if (source == ADAV80X_PLL_SRC_MCLKI) 678 pll_src = ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll_id); 679 else 680 pll_src = ADAV80X_PLL_CLK_SRC_PLL_XIN(pll_id); 681 682 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CLK_SRC, 683 ADAV80X_PLL_CLK_SRC_PLL_MASK(pll_id), pll_src); 684 685 adav80x->pll_src = source; 686 687 snd_soc_dapm_sync(&codec->dapm); 688 } 689 690 return 0; 691 } 692 693 static int adav80x_set_bias_level(struct snd_soc_codec *codec, 694 enum snd_soc_bias_level level) 695 { 696 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 697 unsigned int mask = ADAV80X_DAC_CTRL1_PD; 698 699 switch (level) { 700 case SND_SOC_BIAS_ON: 701 break; 702 case SND_SOC_BIAS_PREPARE: 703 break; 704 case SND_SOC_BIAS_STANDBY: 705 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask, 706 0x00); 707 break; 708 case SND_SOC_BIAS_OFF: 709 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask, 710 mask); 711 break; 712 } 713 714 codec->dapm.bias_level = level; 715 return 0; 716 } 717 718 /* Enforce the same sample rate on all audio interfaces */ 719 static int adav80x_dai_startup(struct snd_pcm_substream *substream, 720 struct snd_soc_dai *dai) 721 { 722 struct snd_soc_codec *codec = dai->codec; 723 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 724 725 if (!codec->active || !adav80x->rate) 726 return 0; 727 728 return snd_pcm_hw_constraint_minmax(substream->runtime, 729 SNDRV_PCM_HW_PARAM_RATE, adav80x->rate, adav80x->rate); 730 } 731 732 static void adav80x_dai_shutdown(struct snd_pcm_substream *substream, 733 struct snd_soc_dai *dai) 734 { 735 struct snd_soc_codec *codec = dai->codec; 736 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 737 738 if (!codec->active) 739 adav80x->rate = 0; 740 } 741 742 static const struct snd_soc_dai_ops adav80x_dai_ops = { 743 .set_fmt = adav80x_set_dai_fmt, 744 .hw_params = adav80x_hw_params, 745 .startup = adav80x_dai_startup, 746 .shutdown = adav80x_dai_shutdown, 747 }; 748 749 #define ADAV80X_PLAYBACK_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 750 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | \ 751 SNDRV_PCM_RATE_96000) 752 753 #define ADAV80X_CAPTURE_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000) 754 755 #define ADAV80X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \ 756 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE) 757 758 static struct snd_soc_dai_driver adav80x_dais[] = { 759 { 760 .name = "adav80x-hifi", 761 .id = 0, 762 .playback = { 763 .stream_name = "HiFi Playback", 764 .channels_min = 2, 765 .channels_max = 2, 766 .rates = ADAV80X_PLAYBACK_RATES, 767 .formats = ADAV80X_FORMATS, 768 }, 769 .capture = { 770 .stream_name = "HiFi Capture", 771 .channels_min = 2, 772 .channels_max = 2, 773 .rates = ADAV80X_CAPTURE_RATES, 774 .formats = ADAV80X_FORMATS, 775 }, 776 .ops = &adav80x_dai_ops, 777 }, 778 { 779 .name = "adav80x-aux", 780 .id = 1, 781 .playback = { 782 .stream_name = "Aux Playback", 783 .channels_min = 2, 784 .channels_max = 2, 785 .rates = ADAV80X_PLAYBACK_RATES, 786 .formats = ADAV80X_FORMATS, 787 }, 788 .capture = { 789 .stream_name = "Aux Capture", 790 .channels_min = 2, 791 .channels_max = 2, 792 .rates = ADAV80X_CAPTURE_RATES, 793 .formats = ADAV80X_FORMATS, 794 }, 795 .ops = &adav80x_dai_ops, 796 }, 797 }; 798 799 static int adav80x_probe(struct snd_soc_codec *codec) 800 { 801 int ret; 802 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 803 804 ret = snd_soc_codec_set_cache_io(codec, 0, 0, SND_SOC_REGMAP); 805 if (ret) { 806 dev_err(codec->dev, "failed to set cache I/O: %d\n", ret); 807 return ret; 808 } 809 810 /* Force PLLs on for SYSCLK output */ 811 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL1"); 812 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL2"); 813 814 /* Power down S/PDIF receiver, since it is currently not supported */ 815 regmap_write(adav80x->regmap, ADAV80X_PLL_OUTE, 0x20); 816 /* Disable DAC zero flag */ 817 regmap_write(adav80x->regmap, ADAV80X_DAC_CTRL3, 0x6); 818 819 return adav80x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 820 } 821 822 static int adav80x_suspend(struct snd_soc_codec *codec) 823 { 824 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 825 int ret; 826 827 ret = adav80x_set_bias_level(codec, SND_SOC_BIAS_OFF); 828 regcache_cache_only(adav80x->regmap, true); 829 830 return ret; 831 } 832 833 static int adav80x_resume(struct snd_soc_codec *codec) 834 { 835 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 836 837 regcache_cache_only(adav80x->regmap, false); 838 adav80x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 839 regcache_sync(adav80x->regmap); 840 841 return 0; 842 } 843 844 static int adav80x_remove(struct snd_soc_codec *codec) 845 { 846 return adav80x_set_bias_level(codec, SND_SOC_BIAS_OFF); 847 } 848 849 static struct snd_soc_codec_driver adav80x_codec_driver = { 850 .probe = adav80x_probe, 851 .remove = adav80x_remove, 852 .suspend = adav80x_suspend, 853 .resume = adav80x_resume, 854 .set_bias_level = adav80x_set_bias_level, 855 856 .set_pll = adav80x_set_pll, 857 .set_sysclk = adav80x_set_sysclk, 858 859 .controls = adav80x_controls, 860 .num_controls = ARRAY_SIZE(adav80x_controls), 861 .dapm_widgets = adav80x_dapm_widgets, 862 .num_dapm_widgets = ARRAY_SIZE(adav80x_dapm_widgets), 863 .dapm_routes = adav80x_dapm_routes, 864 .num_dapm_routes = ARRAY_SIZE(adav80x_dapm_routes), 865 }; 866 867 static int adav80x_bus_probe(struct device *dev, struct regmap *regmap) 868 { 869 struct adav80x *adav80x; 870 int ret; 871 872 if (IS_ERR(regmap)) 873 return PTR_ERR(regmap); 874 875 adav80x = kzalloc(sizeof(*adav80x), GFP_KERNEL); 876 if (!adav80x) 877 return -ENOMEM; 878 879 880 dev_set_drvdata(dev, adav80x); 881 adav80x->regmap = regmap; 882 883 ret = snd_soc_register_codec(dev, &adav80x_codec_driver, 884 adav80x_dais, ARRAY_SIZE(adav80x_dais)); 885 if (ret) 886 kfree(adav80x); 887 888 return ret; 889 } 890 891 static int adav80x_bus_remove(struct device *dev) 892 { 893 snd_soc_unregister_codec(dev); 894 kfree(dev_get_drvdata(dev)); 895 return 0; 896 } 897 898 #if defined(CONFIG_SPI_MASTER) 899 static const struct regmap_config adav80x_spi_regmap_config = { 900 .val_bits = 8, 901 .pad_bits = 1, 902 .reg_bits = 7, 903 .read_flag_mask = 0x01, 904 905 .max_register = ADAV80X_PLL_OUTE, 906 907 .cache_type = REGCACHE_RBTREE, 908 .reg_defaults = adav80x_reg_defaults, 909 .num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults), 910 }; 911 912 static const struct spi_device_id adav80x_spi_id[] = { 913 { "adav801", 0 }, 914 { } 915 }; 916 MODULE_DEVICE_TABLE(spi, adav80x_spi_id); 917 918 static int adav80x_spi_probe(struct spi_device *spi) 919 { 920 return adav80x_bus_probe(&spi->dev, 921 devm_regmap_init_spi(spi, &adav80x_spi_regmap_config)); 922 } 923 924 static int adav80x_spi_remove(struct spi_device *spi) 925 { 926 return adav80x_bus_remove(&spi->dev); 927 } 928 929 static struct spi_driver adav80x_spi_driver = { 930 .driver = { 931 .name = "adav801", 932 .owner = THIS_MODULE, 933 }, 934 .probe = adav80x_spi_probe, 935 .remove = adav80x_spi_remove, 936 .id_table = adav80x_spi_id, 937 }; 938 #endif 939 940 #if IS_ENABLED(CONFIG_I2C) 941 static const struct regmap_config adav80x_i2c_regmap_config = { 942 .val_bits = 8, 943 .pad_bits = 1, 944 .reg_bits = 7, 945 946 .max_register = ADAV80X_PLL_OUTE, 947 948 .cache_type = REGCACHE_RBTREE, 949 .reg_defaults = adav80x_reg_defaults, 950 .num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults), 951 }; 952 953 static const struct i2c_device_id adav80x_i2c_id[] = { 954 { "adav803", 0 }, 955 { } 956 }; 957 MODULE_DEVICE_TABLE(i2c, adav80x_i2c_id); 958 959 static int adav80x_i2c_probe(struct i2c_client *client, 960 const struct i2c_device_id *id) 961 { 962 return adav80x_bus_probe(&client->dev, 963 devm_regmap_init_i2c(client, &adav80x_i2c_regmap_config)); 964 } 965 966 static int adav80x_i2c_remove(struct i2c_client *client) 967 { 968 return adav80x_bus_remove(&client->dev); 969 } 970 971 static struct i2c_driver adav80x_i2c_driver = { 972 .driver = { 973 .name = "adav803", 974 .owner = THIS_MODULE, 975 }, 976 .probe = adav80x_i2c_probe, 977 .remove = adav80x_i2c_remove, 978 .id_table = adav80x_i2c_id, 979 }; 980 #endif 981 982 static int __init adav80x_init(void) 983 { 984 int ret = 0; 985 986 #if IS_ENABLED(CONFIG_I2C) 987 ret = i2c_add_driver(&adav80x_i2c_driver); 988 if (ret) 989 return ret; 990 #endif 991 992 #if defined(CONFIG_SPI_MASTER) 993 ret = spi_register_driver(&adav80x_spi_driver); 994 #endif 995 996 return ret; 997 } 998 module_init(adav80x_init); 999 1000 static void __exit adav80x_exit(void) 1001 { 1002 #if IS_ENABLED(CONFIG_I2C) 1003 i2c_del_driver(&adav80x_i2c_driver); 1004 #endif 1005 #if defined(CONFIG_SPI_MASTER) 1006 spi_unregister_driver(&adav80x_spi_driver); 1007 #endif 1008 } 1009 module_exit(adav80x_exit); 1010 1011 MODULE_DESCRIPTION("ASoC ADAV80x driver"); 1012 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1013 MODULE_AUTHOR("Yi Li <yi.li@analog.com>>"); 1014 MODULE_LICENSE("GPL"); 1015