1 #ifndef __ADAU17X1_H__ 2 #define __ADAU17X1_H__ 3 4 #include <linux/regmap.h> 5 #include <linux/platform_data/adau17x1.h> 6 7 enum adau17x1_type { 8 ADAU1361, 9 ADAU1761, 10 ADAU1381, 11 ADAU1781, 12 }; 13 14 enum adau17x1_pll { 15 ADAU17X1_PLL, 16 }; 17 18 enum adau17x1_pll_src { 19 ADAU17X1_PLL_SRC_MCLK, 20 }; 21 22 enum adau17x1_clk_src { 23 ADAU17X1_CLK_SRC_MCLK, 24 ADAU17X1_CLK_SRC_PLL, 25 }; 26 27 struct adau { 28 unsigned int sysclk; 29 unsigned int pll_freq; 30 31 enum adau17x1_clk_src clk_src; 32 enum adau17x1_type type; 33 void (*switch_mode)(struct device *dev); 34 35 unsigned int dai_fmt; 36 37 uint8_t pll_regs[6]; 38 39 bool master; 40 41 unsigned int tdm_slot[2]; 42 bool dsp_bypass[2]; 43 44 struct regmap *regmap; 45 }; 46 47 int adau17x1_add_widgets(struct snd_soc_codec *codec); 48 int adau17x1_add_routes(struct snd_soc_codec *codec); 49 int adau17x1_probe(struct device *dev, struct regmap *regmap, 50 enum adau17x1_type type, void (*switch_mode)(struct device *dev)); 51 int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec, 52 enum adau17x1_micbias_voltage micbias); 53 bool adau17x1_readable_register(struct device *dev, unsigned int reg); 54 bool adau17x1_volatile_register(struct device *dev, unsigned int reg); 55 int adau17x1_suspend(struct snd_soc_codec *codec); 56 int adau17x1_resume(struct snd_soc_codec *codec); 57 58 extern const struct snd_soc_dai_ops adau17x1_dai_ops; 59 60 int adau17x1_load_firmware(struct adau *adau, struct device *dev, 61 const char *firmware); 62 bool adau17x1_has_dsp(struct adau *adau); 63 64 #define ADAU17X1_CLOCK_CONTROL 0x4000 65 #define ADAU17X1_PLL_CONTROL 0x4002 66 #define ADAU17X1_REC_POWER_MGMT 0x4009 67 #define ADAU17X1_MICBIAS 0x4010 68 #define ADAU17X1_SERIAL_PORT0 0x4015 69 #define ADAU17X1_SERIAL_PORT1 0x4016 70 #define ADAU17X1_CONVERTER0 0x4017 71 #define ADAU17X1_CONVERTER1 0x4018 72 #define ADAU17X1_LEFT_INPUT_DIGITAL_VOL 0x401a 73 #define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL 0x401b 74 #define ADAU17X1_ADC_CONTROL 0x4019 75 #define ADAU17X1_PLAY_POWER_MGMT 0x4029 76 #define ADAU17X1_DAC_CONTROL0 0x402a 77 #define ADAU17X1_DAC_CONTROL1 0x402b 78 #define ADAU17X1_DAC_CONTROL2 0x402c 79 #define ADAU17X1_SERIAL_PORT_PAD 0x402d 80 #define ADAU17X1_CONTROL_PORT_PAD0 0x402f 81 #define ADAU17X1_CONTROL_PORT_PAD1 0x4030 82 #define ADAU17X1_DSP_SAMPLING_RATE 0x40eb 83 #define ADAU17X1_SERIAL_INPUT_ROUTE 0x40f2 84 #define ADAU17X1_SERIAL_OUTPUT_ROUTE 0x40f3 85 #define ADAU17X1_DSP_ENABLE 0x40f5 86 #define ADAU17X1_DSP_RUN 0x40f6 87 #define ADAU17X1_SERIAL_SAMPLING_RATE 0x40f8 88 89 #define ADAU17X1_SERIAL_PORT0_BCLK_POL BIT(4) 90 #define ADAU17X1_SERIAL_PORT0_LRCLK_POL BIT(3) 91 #define ADAU17X1_SERIAL_PORT0_MASTER BIT(0) 92 93 #define ADAU17X1_SERIAL_PORT1_DELAY1 0x00 94 #define ADAU17X1_SERIAL_PORT1_DELAY0 0x01 95 #define ADAU17X1_SERIAL_PORT1_DELAY8 0x02 96 #define ADAU17X1_SERIAL_PORT1_DELAY16 0x03 97 #define ADAU17X1_SERIAL_PORT1_DELAY_MASK 0x03 98 99 #define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK 0x6 100 #define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL BIT(3) 101 #define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN BIT(0) 102 103 #define ADAU17X1_SERIAL_PORT1_BCLK32 (0x0 << 5) 104 #define ADAU17X1_SERIAL_PORT1_BCLK48 (0x1 << 5) 105 #define ADAU17X1_SERIAL_PORT1_BCLK64 (0x2 << 5) 106 #define ADAU17X1_SERIAL_PORT1_BCLK128 (0x3 << 5) 107 #define ADAU17X1_SERIAL_PORT1_BCLK256 (0x4 << 5) 108 #define ADAU17X1_SERIAL_PORT1_BCLK_MASK (0x7 << 5) 109 110 #define ADAU17X1_SERIAL_PORT0_STEREO (0x0 << 1) 111 #define ADAU17X1_SERIAL_PORT0_TDM4 (0x1 << 1) 112 #define ADAU17X1_SERIAL_PORT0_TDM8 (0x2 << 1) 113 #define ADAU17X1_SERIAL_PORT0_TDM_MASK (0x3 << 1) 114 #define ADAU17X1_SERIAL_PORT0_PULSE_MODE BIT(5) 115 116 #define ADAU17X1_CONVERTER0_DAC_PAIR(x) (((x) - 1) << 5) 117 #define ADAU17X1_CONVERTER0_DAC_PAIR_MASK (0x3 << 5) 118 #define ADAU17X1_CONVERTER1_ADC_PAIR(x) ((x) - 1) 119 #define ADAU17X1_CONVERTER1_ADC_PAIR_MASK 0x3 120 121 #define ADAU17X1_CONVERTER0_CONVSR_MASK 0x7 122 123 124 #endif 125