14101866cSLars-Peter Clausen #ifndef __ADAU17X1_H__ 24101866cSLars-Peter Clausen #define __ADAU17X1_H__ 34101866cSLars-Peter Clausen 44101866cSLars-Peter Clausen #include <linux/regmap.h> 54101866cSLars-Peter Clausen #include <linux/platform_data/adau17x1.h> 64101866cSLars-Peter Clausen 7d48b088eSLars-Peter Clausen #include "sigmadsp.h" 8d48b088eSLars-Peter Clausen 94101866cSLars-Peter Clausen enum adau17x1_type { 104101866cSLars-Peter Clausen ADAU1361, 114101866cSLars-Peter Clausen ADAU1761, 124101866cSLars-Peter Clausen ADAU1381, 134101866cSLars-Peter Clausen ADAU1781, 144101866cSLars-Peter Clausen }; 154101866cSLars-Peter Clausen 164101866cSLars-Peter Clausen enum adau17x1_pll { 174101866cSLars-Peter Clausen ADAU17X1_PLL, 184101866cSLars-Peter Clausen }; 194101866cSLars-Peter Clausen 204101866cSLars-Peter Clausen enum adau17x1_pll_src { 214101866cSLars-Peter Clausen ADAU17X1_PLL_SRC_MCLK, 224101866cSLars-Peter Clausen }; 234101866cSLars-Peter Clausen 244101866cSLars-Peter Clausen enum adau17x1_clk_src { 254101866cSLars-Peter Clausen ADAU17X1_CLK_SRC_MCLK, 264101866cSLars-Peter Clausen ADAU17X1_CLK_SRC_PLL, 274101866cSLars-Peter Clausen }; 284101866cSLars-Peter Clausen 294101866cSLars-Peter Clausen struct adau { 304101866cSLars-Peter Clausen unsigned int sysclk; 314101866cSLars-Peter Clausen unsigned int pll_freq; 324101866cSLars-Peter Clausen 334101866cSLars-Peter Clausen enum adau17x1_clk_src clk_src; 344101866cSLars-Peter Clausen enum adau17x1_type type; 354101866cSLars-Peter Clausen void (*switch_mode)(struct device *dev); 364101866cSLars-Peter Clausen 374101866cSLars-Peter Clausen unsigned int dai_fmt; 384101866cSLars-Peter Clausen 394101866cSLars-Peter Clausen uint8_t pll_regs[6]; 404101866cSLars-Peter Clausen 414101866cSLars-Peter Clausen bool master; 424101866cSLars-Peter Clausen 434101866cSLars-Peter Clausen unsigned int tdm_slot[2]; 444101866cSLars-Peter Clausen bool dsp_bypass[2]; 454101866cSLars-Peter Clausen 464101866cSLars-Peter Clausen struct regmap *regmap; 47d48b088eSLars-Peter Clausen struct sigmadsp *sigmadsp; 484101866cSLars-Peter Clausen }; 494101866cSLars-Peter Clausen 504101866cSLars-Peter Clausen int adau17x1_add_widgets(struct snd_soc_codec *codec); 514101866cSLars-Peter Clausen int adau17x1_add_routes(struct snd_soc_codec *codec); 524101866cSLars-Peter Clausen int adau17x1_probe(struct device *dev, struct regmap *regmap, 53d48b088eSLars-Peter Clausen enum adau17x1_type type, void (*switch_mode)(struct device *dev), 54d48b088eSLars-Peter Clausen const char *firmware_name); 554101866cSLars-Peter Clausen int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec, 564101866cSLars-Peter Clausen enum adau17x1_micbias_voltage micbias); 574101866cSLars-Peter Clausen bool adau17x1_readable_register(struct device *dev, unsigned int reg); 584101866cSLars-Peter Clausen bool adau17x1_volatile_register(struct device *dev, unsigned int reg); 59dee9cec4SLars-Peter Clausen bool adau17x1_precious_register(struct device *dev, unsigned int reg); 604101866cSLars-Peter Clausen int adau17x1_resume(struct snd_soc_codec *codec); 614101866cSLars-Peter Clausen 624101866cSLars-Peter Clausen extern const struct snd_soc_dai_ops adau17x1_dai_ops; 634101866cSLars-Peter Clausen 64d48b088eSLars-Peter Clausen int adau17x1_setup_firmware(struct adau *adau, unsigned int rate); 654101866cSLars-Peter Clausen bool adau17x1_has_dsp(struct adau *adau); 664101866cSLars-Peter Clausen 674101866cSLars-Peter Clausen #define ADAU17X1_CLOCK_CONTROL 0x4000 684101866cSLars-Peter Clausen #define ADAU17X1_PLL_CONTROL 0x4002 694101866cSLars-Peter Clausen #define ADAU17X1_REC_POWER_MGMT 0x4009 704101866cSLars-Peter Clausen #define ADAU17X1_MICBIAS 0x4010 714101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0 0x4015 724101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1 0x4016 734101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER0 0x4017 744101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER1 0x4018 754101866cSLars-Peter Clausen #define ADAU17X1_LEFT_INPUT_DIGITAL_VOL 0x401a 764101866cSLars-Peter Clausen #define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL 0x401b 774101866cSLars-Peter Clausen #define ADAU17X1_ADC_CONTROL 0x4019 784101866cSLars-Peter Clausen #define ADAU17X1_PLAY_POWER_MGMT 0x4029 794101866cSLars-Peter Clausen #define ADAU17X1_DAC_CONTROL0 0x402a 804101866cSLars-Peter Clausen #define ADAU17X1_DAC_CONTROL1 0x402b 814101866cSLars-Peter Clausen #define ADAU17X1_DAC_CONTROL2 0x402c 824101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT_PAD 0x402d 834101866cSLars-Peter Clausen #define ADAU17X1_CONTROL_PORT_PAD0 0x402f 844101866cSLars-Peter Clausen #define ADAU17X1_CONTROL_PORT_PAD1 0x4030 854101866cSLars-Peter Clausen #define ADAU17X1_DSP_SAMPLING_RATE 0x40eb 864101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_INPUT_ROUTE 0x40f2 874101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_OUTPUT_ROUTE 0x40f3 884101866cSLars-Peter Clausen #define ADAU17X1_DSP_ENABLE 0x40f5 894101866cSLars-Peter Clausen #define ADAU17X1_DSP_RUN 0x40f6 904101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_SAMPLING_RATE 0x40f8 914101866cSLars-Peter Clausen 924101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_BCLK_POL BIT(4) 934101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_LRCLK_POL BIT(3) 944101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_MASTER BIT(0) 954101866cSLars-Peter Clausen 964101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_DELAY1 0x00 974101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_DELAY0 0x01 984101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_DELAY8 0x02 994101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_DELAY16 0x03 1004101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_DELAY_MASK 0x03 1014101866cSLars-Peter Clausen 1024101866cSLars-Peter Clausen #define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK 0x6 1034101866cSLars-Peter Clausen #define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL BIT(3) 1044101866cSLars-Peter Clausen #define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN BIT(0) 1054101866cSLars-Peter Clausen 1067c139db2SAndreas Irestål #define ADAU17X1_SERIAL_PORT1_BCLK64 (0x0 << 5) 1077c139db2SAndreas Irestål #define ADAU17X1_SERIAL_PORT1_BCLK32 (0x1 << 5) 1087c139db2SAndreas Irestål #define ADAU17X1_SERIAL_PORT1_BCLK48 (0x2 << 5) 1094101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_BCLK128 (0x3 << 5) 1104101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_BCLK256 (0x4 << 5) 1114101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_BCLK_MASK (0x7 << 5) 1124101866cSLars-Peter Clausen 1134101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_STEREO (0x0 << 1) 1144101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_TDM4 (0x1 << 1) 1154101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_TDM8 (0x2 << 1) 1164101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_TDM_MASK (0x3 << 1) 1174101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_PULSE_MODE BIT(5) 1184101866cSLars-Peter Clausen 1194101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER0_DAC_PAIR(x) (((x) - 1) << 5) 1204101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER0_DAC_PAIR_MASK (0x3 << 5) 1214101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER1_ADC_PAIR(x) ((x) - 1) 1224101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER1_ADC_PAIR_MASK 0x3 1234101866cSLars-Peter Clausen 1244101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER0_CONVSR_MASK 0x7 1254101866cSLars-Peter Clausen 1264101866cSLars-Peter Clausen 1274101866cSLars-Peter Clausen #endif 128