1 /* 2 * Common code for ADAU1X61 and ADAU1X81 codecs 3 * 4 * Copyright 2011-2014 Analog Devices Inc. 5 * Author: Lars-Peter Clausen <lars@metafoo.de> 6 * 7 * Licensed under the GPL-2 or later. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/init.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/slab.h> 15 #include <sound/core.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc.h> 19 #include <sound/tlv.h> 20 #include <linux/gcd.h> 21 #include <linux/i2c.h> 22 #include <linux/spi/spi.h> 23 #include <linux/regmap.h> 24 #include <asm/unaligned.h> 25 26 #include "sigmadsp.h" 27 #include "adau17x1.h" 28 #include "adau-utils.h" 29 30 #define ADAU17X1_SAFELOAD_TARGET_ADDRESS 0x0006 31 #define ADAU17X1_SAFELOAD_TRIGGER 0x0007 32 #define ADAU17X1_SAFELOAD_DATA 0x0001 33 #define ADAU17X1_SAFELOAD_DATA_SIZE 20 34 #define ADAU17X1_WORD_SIZE 4 35 36 static const char * const adau17x1_capture_mixer_boost_text[] = { 37 "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3", 38 }; 39 40 static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum, 41 ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text); 42 43 static const char * const adau17x1_mic_bias_mode_text[] = { 44 "Normal operation", "High performance", 45 }; 46 47 static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum, 48 ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text); 49 50 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0); 51 52 static const struct snd_kcontrol_new adau17x1_controls[] = { 53 SOC_DOUBLE_R_TLV("Digital Capture Volume", 54 ADAU17X1_LEFT_INPUT_DIGITAL_VOL, 55 ADAU17X1_RIGHT_INPUT_DIGITAL_VOL, 56 0, 0xff, 1, adau17x1_digital_tlv), 57 SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1, 58 ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv), 59 60 SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL, 61 5, 1, 0), 62 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0, 63 2, 1, 0), 64 65 SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum), 66 67 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum), 68 }; 69 70 static int adau17x1_setup_firmware(struct snd_soc_component *component, 71 unsigned int rate); 72 73 static int adau17x1_pll_event(struct snd_soc_dapm_widget *w, 74 struct snd_kcontrol *kcontrol, int event) 75 { 76 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 77 struct adau *adau = snd_soc_component_get_drvdata(component); 78 79 if (SND_SOC_DAPM_EVENT_ON(event)) { 80 adau->pll_regs[5] = 1; 81 } else { 82 adau->pll_regs[5] = 0; 83 /* Bypass the PLL when disabled, otherwise registers will become 84 * inaccessible. */ 85 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, 86 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0); 87 } 88 89 /* The PLL register is 6 bytes long and can only be written at once. */ 90 regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL, 91 adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); 92 93 if (SND_SOC_DAPM_EVENT_ON(event)) { 94 mdelay(5); 95 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, 96 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 97 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL); 98 } 99 100 return 0; 101 } 102 103 static int adau17x1_adc_fixup(struct snd_soc_dapm_widget *w, 104 struct snd_kcontrol *kcontrol, int event) 105 { 106 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 107 struct adau *adau = snd_soc_component_get_drvdata(component); 108 109 /* 110 * If we are capturing, toggle the ADOSR bit in Converter Control 0 to 111 * avoid losing SNR (workaround from ADI). This must be done after 112 * the ADC(s) have been enabled. According to the data sheet, it is 113 * normally illegal to set this bit when the sampling rate is 96 kHz, 114 * but according to ADI it is acceptable for this workaround. 115 */ 116 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, 117 ADAU17X1_CONVERTER0_ADOSR, ADAU17X1_CONVERTER0_ADOSR); 118 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, 119 ADAU17X1_CONVERTER0_ADOSR, 0); 120 121 return 0; 122 } 123 124 static const char * const adau17x1_mono_stereo_text[] = { 125 "Stereo", 126 "Mono Left Channel (L+R)", 127 "Mono Right Channel (L+R)", 128 "Mono (L+R)", 129 }; 130 131 static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum, 132 ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text); 133 134 static const struct snd_kcontrol_new adau17x1_dac_mode_mux = 135 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum); 136 137 static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = { 138 SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event, 139 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 140 141 SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0), 142 143 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0), 144 145 SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT, 146 0, 0, NULL, 0), 147 SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT, 148 1, 0, NULL, 0), 149 150 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0, 151 &adau17x1_dac_mode_mux), 152 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0, 153 &adau17x1_dac_mode_mux), 154 155 SND_SOC_DAPM_ADC_E("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0, 156 adau17x1_adc_fixup, SND_SOC_DAPM_POST_PMU), 157 SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0), 158 SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0), 159 SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0), 160 }; 161 162 static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = { 163 { "Left Decimator", NULL, "SYSCLK" }, 164 { "Right Decimator", NULL, "SYSCLK" }, 165 { "Left DAC", NULL, "SYSCLK" }, 166 { "Right DAC", NULL, "SYSCLK" }, 167 { "Capture", NULL, "SYSCLK" }, 168 { "Playback", NULL, "SYSCLK" }, 169 170 { "Left DAC", NULL, "Left DAC Mode Mux" }, 171 { "Right DAC", NULL, "Right DAC Mode Mux" }, 172 173 { "Capture", NULL, "AIFCLK" }, 174 { "Playback", NULL, "AIFCLK" }, 175 }; 176 177 static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = { 178 "SYSCLK", NULL, "PLL", 179 }; 180 181 /* 182 * The MUX register for the Capture and Playback MUXs selects either DSP as 183 * source/destination or one of the TDM slots. The TDM slot is selected via 184 * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or 185 * directly to the DAI interface with this control. 186 */ 187 static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol, 188 struct snd_ctl_elem_value *ucontrol) 189 { 190 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); 191 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 192 struct adau *adau = snd_soc_component_get_drvdata(component); 193 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 194 struct snd_soc_dapm_update update = {}; 195 unsigned int stream = e->shift_l; 196 unsigned int val, change; 197 int reg; 198 199 if (ucontrol->value.enumerated.item[0] >= e->items) 200 return -EINVAL; 201 202 switch (ucontrol->value.enumerated.item[0]) { 203 case 0: 204 val = 0; 205 adau->dsp_bypass[stream] = false; 206 break; 207 default: 208 val = (adau->tdm_slot[stream] * 2) + 1; 209 adau->dsp_bypass[stream] = true; 210 break; 211 } 212 213 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 214 reg = ADAU17X1_SERIAL_INPUT_ROUTE; 215 else 216 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE; 217 218 change = snd_soc_component_test_bits(component, reg, 0xff, val); 219 if (change) { 220 update.kcontrol = kcontrol; 221 update.mask = 0xff; 222 update.reg = reg; 223 update.val = val; 224 225 snd_soc_dapm_mux_update_power(dapm, kcontrol, 226 ucontrol->value.enumerated.item[0], e, &update); 227 } 228 229 return change; 230 } 231 232 static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol, 233 struct snd_ctl_elem_value *ucontrol) 234 { 235 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); 236 struct adau *adau = snd_soc_component_get_drvdata(component); 237 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 238 unsigned int stream = e->shift_l; 239 unsigned int reg, val; 240 int ret; 241 242 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 243 reg = ADAU17X1_SERIAL_INPUT_ROUTE; 244 else 245 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE; 246 247 ret = regmap_read(adau->regmap, reg, &val); 248 if (ret) 249 return ret; 250 251 if (val != 0) 252 val = 1; 253 ucontrol->value.enumerated.item[0] = val; 254 255 return 0; 256 } 257 258 #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \ 259 const struct snd_kcontrol_new _name = \ 260 SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\ 261 SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \ 262 ARRAY_SIZE(_text), _text), \ 263 adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put) 264 265 static const char * const adau17x1_dac_mux_text[] = { 266 "DSP", 267 "AIFIN", 268 }; 269 270 static const char * const adau17x1_capture_mux_text[] = { 271 "DSP", 272 "Decimator", 273 }; 274 275 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux", 276 SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text); 277 278 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux", 279 SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text); 280 281 static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = { 282 SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0), 283 SND_SOC_DAPM_SIGGEN("DSP Siggen"), 284 285 SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0, 286 &adau17x1_dac_mux), 287 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, 288 &adau17x1_capture_mux), 289 }; 290 291 static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = { 292 { "DAC Playback Mux", "DSP", "DSP" }, 293 { "DAC Playback Mux", "AIFIN", "Playback" }, 294 295 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" }, 296 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" }, 297 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" }, 298 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" }, 299 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" }, 300 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" }, 301 302 { "Capture Mux", "DSP", "DSP" }, 303 { "Capture Mux", "Decimator", "Left Decimator" }, 304 { "Capture Mux", "Decimator", "Right Decimator" }, 305 306 { "Capture", NULL, "Capture Mux" }, 307 308 { "DSP", NULL, "DSP Siggen" }, 309 310 { "DSP", NULL, "Left Decimator" }, 311 { "DSP", NULL, "Right Decimator" }, 312 { "DSP", NULL, "Playback" }, 313 }; 314 315 static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = { 316 { "Left DAC Mode Mux", "Stereo", "Playback" }, 317 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" }, 318 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" }, 319 { "Right DAC Mode Mux", "Stereo", "Playback" }, 320 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" }, 321 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" }, 322 { "Capture", NULL, "Left Decimator" }, 323 { "Capture", NULL, "Right Decimator" }, 324 }; 325 326 static bool adau17x1_has_dsp(struct adau *adau) 327 { 328 switch (adau->type) { 329 case ADAU1761: 330 case ADAU1381: 331 case ADAU1781: 332 return true; 333 default: 334 return false; 335 } 336 } 337 338 static bool adau17x1_has_safeload(struct adau *adau) 339 { 340 switch (adau->type) { 341 case ADAU1761: 342 case ADAU1781: 343 return true; 344 default: 345 return false; 346 } 347 } 348 349 static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id, 350 int source, unsigned int freq_in, unsigned int freq_out) 351 { 352 struct snd_soc_component *component = dai->component; 353 struct adau *adau = snd_soc_component_get_drvdata(component); 354 int ret; 355 356 if (freq_in < 8000000 || freq_in > 27000000) 357 return -EINVAL; 358 359 ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs); 360 if (ret < 0) 361 return ret; 362 363 /* The PLL register is 6 bytes long and can only be written at once. */ 364 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL, 365 adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); 366 if (ret) 367 return ret; 368 369 adau->pll_freq = freq_out; 370 371 return 0; 372 } 373 374 static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai, 375 int clk_id, unsigned int freq, int dir) 376 { 377 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component); 378 struct adau *adau = snd_soc_component_get_drvdata(dai->component); 379 bool is_pll; 380 bool was_pll; 381 382 switch (clk_id) { 383 case ADAU17X1_CLK_SRC_MCLK: 384 is_pll = false; 385 break; 386 case ADAU17X1_CLK_SRC_PLL_AUTO: 387 if (!adau->mclk) 388 return -EINVAL; 389 /* Fall-through */ 390 case ADAU17X1_CLK_SRC_PLL: 391 is_pll = true; 392 break; 393 default: 394 return -EINVAL; 395 } 396 397 switch (adau->clk_src) { 398 case ADAU17X1_CLK_SRC_MCLK: 399 was_pll = false; 400 break; 401 case ADAU17X1_CLK_SRC_PLL: 402 case ADAU17X1_CLK_SRC_PLL_AUTO: 403 was_pll = true; 404 break; 405 default: 406 return -EINVAL; 407 } 408 409 adau->sysclk = freq; 410 411 if (is_pll != was_pll) { 412 if (is_pll) { 413 snd_soc_dapm_add_routes(dapm, 414 &adau17x1_dapm_pll_route, 1); 415 } else { 416 snd_soc_dapm_del_routes(dapm, 417 &adau17x1_dapm_pll_route, 1); 418 } 419 } 420 421 adau->clk_src = clk_id; 422 423 return 0; 424 } 425 426 static int adau17x1_auto_pll(struct snd_soc_dai *dai, 427 struct snd_pcm_hw_params *params) 428 { 429 struct adau *adau = snd_soc_dai_get_drvdata(dai); 430 unsigned int pll_rate; 431 432 switch (params_rate(params)) { 433 case 48000: 434 case 8000: 435 case 12000: 436 case 16000: 437 case 24000: 438 case 32000: 439 case 96000: 440 pll_rate = 48000 * 1024; 441 break; 442 case 44100: 443 case 7350: 444 case 11025: 445 case 14700: 446 case 22050: 447 case 29400: 448 case 88200: 449 pll_rate = 44100 * 1024; 450 break; 451 default: 452 return -EINVAL; 453 } 454 455 return adau17x1_set_dai_pll(dai, ADAU17X1_PLL, ADAU17X1_PLL_SRC_MCLK, 456 clk_get_rate(adau->mclk), pll_rate); 457 } 458 459 static int adau17x1_hw_params(struct snd_pcm_substream *substream, 460 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 461 { 462 struct snd_soc_component *component = dai->component; 463 struct adau *adau = snd_soc_component_get_drvdata(component); 464 unsigned int val, div, dsp_div; 465 unsigned int freq; 466 int ret; 467 468 switch (adau->clk_src) { 469 case ADAU17X1_CLK_SRC_PLL_AUTO: 470 ret = adau17x1_auto_pll(dai, params); 471 if (ret) 472 return ret; 473 /* Fall-through */ 474 case ADAU17X1_CLK_SRC_PLL: 475 freq = adau->pll_freq; 476 break; 477 default: 478 freq = adau->sysclk; 479 break; 480 } 481 482 if (freq % params_rate(params) != 0) 483 return -EINVAL; 484 485 switch (freq / params_rate(params)) { 486 case 1024: /* fs */ 487 div = 0; 488 dsp_div = 1; 489 break; 490 case 6144: /* fs / 6 */ 491 div = 1; 492 dsp_div = 6; 493 break; 494 case 4096: /* fs / 4 */ 495 div = 2; 496 dsp_div = 5; 497 break; 498 case 3072: /* fs / 3 */ 499 div = 3; 500 dsp_div = 4; 501 break; 502 case 2048: /* fs / 2 */ 503 div = 4; 504 dsp_div = 3; 505 break; 506 case 1536: /* fs / 1.5 */ 507 div = 5; 508 dsp_div = 2; 509 break; 510 case 512: /* fs / 0.5 */ 511 div = 6; 512 dsp_div = 0; 513 break; 514 default: 515 return -EINVAL; 516 } 517 518 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, 519 ADAU17X1_CONVERTER0_CONVSR_MASK, div); 520 if (adau17x1_has_dsp(adau)) { 521 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div); 522 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div); 523 } 524 525 if (adau->sigmadsp) { 526 ret = adau17x1_setup_firmware(component, params_rate(params)); 527 if (ret < 0) 528 return ret; 529 } 530 531 if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J) 532 return 0; 533 534 switch (params_width(params)) { 535 case 16: 536 val = ADAU17X1_SERIAL_PORT1_DELAY16; 537 break; 538 case 24: 539 val = ADAU17X1_SERIAL_PORT1_DELAY8; 540 break; 541 case 32: 542 val = ADAU17X1_SERIAL_PORT1_DELAY0; 543 break; 544 default: 545 return -EINVAL; 546 } 547 548 return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1, 549 ADAU17X1_SERIAL_PORT1_DELAY_MASK, val); 550 } 551 552 static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai, 553 unsigned int fmt) 554 { 555 struct adau *adau = snd_soc_component_get_drvdata(dai->component); 556 unsigned int ctrl0, ctrl1; 557 int lrclk_pol; 558 559 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 560 case SND_SOC_DAIFMT_CBM_CFM: 561 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER; 562 adau->master = true; 563 break; 564 case SND_SOC_DAIFMT_CBS_CFS: 565 ctrl0 = 0; 566 adau->master = false; 567 break; 568 default: 569 return -EINVAL; 570 } 571 572 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 573 case SND_SOC_DAIFMT_I2S: 574 lrclk_pol = 0; 575 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1; 576 break; 577 case SND_SOC_DAIFMT_LEFT_J: 578 case SND_SOC_DAIFMT_RIGHT_J: 579 lrclk_pol = 1; 580 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0; 581 break; 582 case SND_SOC_DAIFMT_DSP_A: 583 lrclk_pol = 1; 584 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; 585 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1; 586 break; 587 case SND_SOC_DAIFMT_DSP_B: 588 lrclk_pol = 1; 589 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; 590 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0; 591 break; 592 default: 593 return -EINVAL; 594 } 595 596 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 597 case SND_SOC_DAIFMT_NB_NF: 598 break; 599 case SND_SOC_DAIFMT_IB_NF: 600 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; 601 break; 602 case SND_SOC_DAIFMT_NB_IF: 603 lrclk_pol = !lrclk_pol; 604 break; 605 case SND_SOC_DAIFMT_IB_IF: 606 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; 607 lrclk_pol = !lrclk_pol; 608 break; 609 default: 610 return -EINVAL; 611 } 612 613 if (lrclk_pol) 614 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL; 615 616 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0); 617 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1); 618 619 adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 620 621 return 0; 622 } 623 624 static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai, 625 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 626 { 627 struct adau *adau = snd_soc_component_get_drvdata(dai->component); 628 unsigned int ser_ctrl0, ser_ctrl1; 629 unsigned int conv_ctrl0, conv_ctrl1; 630 631 /* I2S mode */ 632 if (slots == 0) { 633 slots = 2; 634 rx_mask = 3; 635 tx_mask = 3; 636 slot_width = 32; 637 } 638 639 switch (slots) { 640 case 2: 641 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO; 642 break; 643 case 4: 644 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4; 645 break; 646 case 8: 647 if (adau->type == ADAU1361) 648 return -EINVAL; 649 650 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8; 651 break; 652 default: 653 return -EINVAL; 654 } 655 656 switch (slot_width * slots) { 657 case 32: 658 if (adau->type == ADAU1761) 659 return -EINVAL; 660 661 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32; 662 break; 663 case 64: 664 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64; 665 break; 666 case 48: 667 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48; 668 break; 669 case 128: 670 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128; 671 break; 672 case 256: 673 if (adau->type == ADAU1361) 674 return -EINVAL; 675 676 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256; 677 break; 678 default: 679 return -EINVAL; 680 } 681 682 switch (rx_mask) { 683 case 0x03: 684 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1); 685 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0; 686 break; 687 case 0x0c: 688 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2); 689 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1; 690 break; 691 case 0x30: 692 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3); 693 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2; 694 break; 695 case 0xc0: 696 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4); 697 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3; 698 break; 699 default: 700 return -EINVAL; 701 } 702 703 switch (tx_mask) { 704 case 0x03: 705 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1); 706 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0; 707 break; 708 case 0x0c: 709 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2); 710 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1; 711 break; 712 case 0x30: 713 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3); 714 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2; 715 break; 716 case 0xc0: 717 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4); 718 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3; 719 break; 720 default: 721 return -EINVAL; 722 } 723 724 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, 725 ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0); 726 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1, 727 ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1); 728 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0, 729 ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0); 730 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1, 731 ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1); 732 733 if (!adau17x1_has_dsp(adau)) 734 return 0; 735 736 if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) { 737 regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE, 738 (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1); 739 } 740 741 if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) { 742 regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE, 743 (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1); 744 } 745 746 return 0; 747 } 748 749 static int adau17x1_startup(struct snd_pcm_substream *substream, 750 struct snd_soc_dai *dai) 751 { 752 struct adau *adau = snd_soc_component_get_drvdata(dai->component); 753 754 if (adau->sigmadsp) 755 return sigmadsp_restrict_params(adau->sigmadsp, substream); 756 757 return 0; 758 } 759 760 const struct snd_soc_dai_ops adau17x1_dai_ops = { 761 .hw_params = adau17x1_hw_params, 762 .set_sysclk = adau17x1_set_dai_sysclk, 763 .set_fmt = adau17x1_set_dai_fmt, 764 .set_pll = adau17x1_set_dai_pll, 765 .set_tdm_slot = adau17x1_set_dai_tdm_slot, 766 .startup = adau17x1_startup, 767 }; 768 EXPORT_SYMBOL_GPL(adau17x1_dai_ops); 769 770 int adau17x1_set_micbias_voltage(struct snd_soc_component *component, 771 enum adau17x1_micbias_voltage micbias) 772 { 773 struct adau *adau = snd_soc_component_get_drvdata(component); 774 775 switch (micbias) { 776 case ADAU17X1_MICBIAS_0_90_AVDD: 777 case ADAU17X1_MICBIAS_0_65_AVDD: 778 break; 779 default: 780 return -EINVAL; 781 } 782 783 return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2); 784 } 785 EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage); 786 787 bool adau17x1_precious_register(struct device *dev, unsigned int reg) 788 { 789 /* SigmaDSP parameter memory */ 790 if (reg < 0x400) 791 return true; 792 793 return false; 794 } 795 EXPORT_SYMBOL_GPL(adau17x1_precious_register); 796 797 bool adau17x1_readable_register(struct device *dev, unsigned int reg) 798 { 799 /* SigmaDSP parameter memory */ 800 if (reg < 0x400) 801 return true; 802 803 switch (reg) { 804 case ADAU17X1_CLOCK_CONTROL: 805 case ADAU17X1_PLL_CONTROL: 806 case ADAU17X1_REC_POWER_MGMT: 807 case ADAU17X1_MICBIAS: 808 case ADAU17X1_SERIAL_PORT0: 809 case ADAU17X1_SERIAL_PORT1: 810 case ADAU17X1_CONVERTER0: 811 case ADAU17X1_CONVERTER1: 812 case ADAU17X1_LEFT_INPUT_DIGITAL_VOL: 813 case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL: 814 case ADAU17X1_ADC_CONTROL: 815 case ADAU17X1_PLAY_POWER_MGMT: 816 case ADAU17X1_DAC_CONTROL0: 817 case ADAU17X1_DAC_CONTROL1: 818 case ADAU17X1_DAC_CONTROL2: 819 case ADAU17X1_SERIAL_PORT_PAD: 820 case ADAU17X1_CONTROL_PORT_PAD0: 821 case ADAU17X1_CONTROL_PORT_PAD1: 822 case ADAU17X1_DSP_SAMPLING_RATE: 823 case ADAU17X1_SERIAL_INPUT_ROUTE: 824 case ADAU17X1_SERIAL_OUTPUT_ROUTE: 825 case ADAU17X1_DSP_ENABLE: 826 case ADAU17X1_DSP_RUN: 827 case ADAU17X1_SERIAL_SAMPLING_RATE: 828 return true; 829 default: 830 break; 831 } 832 return false; 833 } 834 EXPORT_SYMBOL_GPL(adau17x1_readable_register); 835 836 bool adau17x1_volatile_register(struct device *dev, unsigned int reg) 837 { 838 /* SigmaDSP parameter and program memory */ 839 if (reg < 0x4000) 840 return true; 841 842 switch (reg) { 843 /* The PLL register is 6 bytes long */ 844 case ADAU17X1_PLL_CONTROL: 845 case ADAU17X1_PLL_CONTROL + 1: 846 case ADAU17X1_PLL_CONTROL + 2: 847 case ADAU17X1_PLL_CONTROL + 3: 848 case ADAU17X1_PLL_CONTROL + 4: 849 case ADAU17X1_PLL_CONTROL + 5: 850 return true; 851 default: 852 break; 853 } 854 855 return false; 856 } 857 EXPORT_SYMBOL_GPL(adau17x1_volatile_register); 858 859 static int adau17x1_setup_firmware(struct snd_soc_component *component, 860 unsigned int rate) 861 { 862 int ret; 863 int dspsr, dsp_run; 864 struct adau *adau = snd_soc_component_get_drvdata(component); 865 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 866 867 /* Check if sample rate is the same as before. If it is there is no 868 * point in performing the below steps as the call to 869 * sigmadsp_setup(...) will return directly when it finds the sample 870 * rate to be the same as before. By checking this we can prevent an 871 * audiable popping noise which occours when toggling DSP_RUN. 872 */ 873 if (adau->sigmadsp->current_samplerate == rate) 874 return 0; 875 876 snd_soc_dapm_mutex_lock(dapm); 877 878 ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr); 879 if (ret) 880 goto err; 881 882 ret = regmap_read(adau->regmap, ADAU17X1_DSP_RUN, &dsp_run); 883 if (ret) 884 goto err; 885 886 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1); 887 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf); 888 regmap_write(adau->regmap, ADAU17X1_DSP_RUN, 0); 889 890 ret = sigmadsp_setup(adau->sigmadsp, rate); 891 if (ret) { 892 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0); 893 goto err; 894 } 895 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr); 896 regmap_write(adau->regmap, ADAU17X1_DSP_RUN, dsp_run); 897 898 err: 899 snd_soc_dapm_mutex_unlock(dapm); 900 901 return ret; 902 } 903 904 int adau17x1_add_widgets(struct snd_soc_component *component) 905 { 906 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 907 struct adau *adau = snd_soc_component_get_drvdata(component); 908 int ret; 909 910 ret = snd_soc_add_component_controls(component, adau17x1_controls, 911 ARRAY_SIZE(adau17x1_controls)); 912 if (ret) 913 return ret; 914 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets, 915 ARRAY_SIZE(adau17x1_dapm_widgets)); 916 if (ret) 917 return ret; 918 919 if (adau17x1_has_dsp(adau)) { 920 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets, 921 ARRAY_SIZE(adau17x1_dsp_dapm_widgets)); 922 if (ret) 923 return ret; 924 925 if (!adau->sigmadsp) 926 return 0; 927 928 ret = sigmadsp_attach(adau->sigmadsp, component); 929 if (ret) { 930 dev_err(component->dev, "Failed to attach firmware: %d\n", 931 ret); 932 return ret; 933 } 934 } 935 936 return 0; 937 } 938 EXPORT_SYMBOL_GPL(adau17x1_add_widgets); 939 940 int adau17x1_add_routes(struct snd_soc_component *component) 941 { 942 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 943 struct adau *adau = snd_soc_component_get_drvdata(component); 944 int ret; 945 946 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes, 947 ARRAY_SIZE(adau17x1_dapm_routes)); 948 if (ret) 949 return ret; 950 951 if (adau17x1_has_dsp(adau)) { 952 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes, 953 ARRAY_SIZE(adau17x1_dsp_dapm_routes)); 954 } else { 955 ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes, 956 ARRAY_SIZE(adau17x1_no_dsp_dapm_routes)); 957 } 958 959 if (adau->clk_src != ADAU17X1_CLK_SRC_MCLK) 960 snd_soc_dapm_add_routes(dapm, &adau17x1_dapm_pll_route, 1); 961 962 return ret; 963 } 964 EXPORT_SYMBOL_GPL(adau17x1_add_routes); 965 966 int adau17x1_resume(struct snd_soc_component *component) 967 { 968 struct adau *adau = snd_soc_component_get_drvdata(component); 969 970 if (adau->switch_mode) 971 adau->switch_mode(component->dev); 972 973 regcache_sync(adau->regmap); 974 975 return 0; 976 } 977 EXPORT_SYMBOL_GPL(adau17x1_resume); 978 979 static int adau17x1_safeload(struct sigmadsp *sigmadsp, unsigned int addr, 980 const uint8_t bytes[], size_t len) 981 { 982 uint8_t buf[ADAU17X1_WORD_SIZE]; 983 uint8_t data[ADAU17X1_SAFELOAD_DATA_SIZE]; 984 unsigned int addr_offset; 985 unsigned int nbr_words; 986 int ret; 987 988 /* write data to safeload addresses. Check if len is not a multiple of 989 * 4 bytes, if so we need to zero pad. 990 */ 991 nbr_words = len / ADAU17X1_WORD_SIZE; 992 if ((len - nbr_words * ADAU17X1_WORD_SIZE) == 0) { 993 ret = regmap_raw_write(sigmadsp->control_data, 994 ADAU17X1_SAFELOAD_DATA, bytes, len); 995 } else { 996 nbr_words++; 997 memset(data, 0, ADAU17X1_SAFELOAD_DATA_SIZE); 998 memcpy(data, bytes, len); 999 ret = regmap_raw_write(sigmadsp->control_data, 1000 ADAU17X1_SAFELOAD_DATA, data, 1001 nbr_words * ADAU17X1_WORD_SIZE); 1002 } 1003 1004 if (ret < 0) 1005 return ret; 1006 1007 /* Write target address, target address is offset by 1 */ 1008 addr_offset = addr - 1; 1009 put_unaligned_be32(addr_offset, buf); 1010 ret = regmap_raw_write(sigmadsp->control_data, 1011 ADAU17X1_SAFELOAD_TARGET_ADDRESS, buf, ADAU17X1_WORD_SIZE); 1012 if (ret < 0) 1013 return ret; 1014 1015 /* write nbr of words to trigger address */ 1016 put_unaligned_be32(nbr_words, buf); 1017 ret = regmap_raw_write(sigmadsp->control_data, 1018 ADAU17X1_SAFELOAD_TRIGGER, buf, ADAU17X1_WORD_SIZE); 1019 if (ret < 0) 1020 return ret; 1021 1022 return 0; 1023 } 1024 1025 static const struct sigmadsp_ops adau17x1_sigmadsp_ops = { 1026 .safeload = adau17x1_safeload, 1027 }; 1028 1029 int adau17x1_probe(struct device *dev, struct regmap *regmap, 1030 enum adau17x1_type type, void (*switch_mode)(struct device *dev), 1031 const char *firmware_name) 1032 { 1033 struct adau *adau; 1034 int ret; 1035 1036 if (IS_ERR(regmap)) 1037 return PTR_ERR(regmap); 1038 1039 adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL); 1040 if (!adau) 1041 return -ENOMEM; 1042 1043 adau->mclk = devm_clk_get(dev, "mclk"); 1044 if (IS_ERR(adau->mclk)) { 1045 if (PTR_ERR(adau->mclk) != -ENOENT) 1046 return PTR_ERR(adau->mclk); 1047 /* Clock is optional (for the driver) */ 1048 adau->mclk = NULL; 1049 } else if (adau->mclk) { 1050 adau->clk_src = ADAU17X1_CLK_SRC_PLL_AUTO; 1051 1052 /* 1053 * Any valid PLL output rate will work at this point, use one 1054 * that is likely to be chosen later as well. The register will 1055 * be written when the PLL is powered up for the first time. 1056 */ 1057 ret = adau_calc_pll_cfg(clk_get_rate(adau->mclk), 48000 * 1024, 1058 adau->pll_regs); 1059 if (ret < 0) 1060 return ret; 1061 1062 ret = clk_prepare_enable(adau->mclk); 1063 if (ret) 1064 return ret; 1065 } 1066 1067 adau->regmap = regmap; 1068 adau->switch_mode = switch_mode; 1069 adau->type = type; 1070 1071 dev_set_drvdata(dev, adau); 1072 1073 if (firmware_name) { 1074 if (adau17x1_has_safeload(adau)) { 1075 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, 1076 &adau17x1_sigmadsp_ops, firmware_name); 1077 } else { 1078 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, 1079 NULL, firmware_name); 1080 } 1081 if (IS_ERR(adau->sigmadsp)) { 1082 dev_warn(dev, "Could not find firmware file: %ld\n", 1083 PTR_ERR(adau->sigmadsp)); 1084 adau->sigmadsp = NULL; 1085 } 1086 } 1087 1088 if (switch_mode) 1089 switch_mode(dev); 1090 1091 return 0; 1092 } 1093 EXPORT_SYMBOL_GPL(adau17x1_probe); 1094 1095 void adau17x1_remove(struct device *dev) 1096 { 1097 struct adau *adau = dev_get_drvdata(dev); 1098 1099 if (adau->mclk) 1100 clk_disable_unprepare(adau->mclk); 1101 } 1102 EXPORT_SYMBOL_GPL(adau17x1_remove); 1103 1104 MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code"); 1105 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1106 MODULE_LICENSE("GPL"); 1107