1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Common code for ADAU1X61 and ADAU1X81 codecs 4 * 5 * Copyright 2011-2014 Analog Devices Inc. 6 * Author: Lars-Peter Clausen <lars@metafoo.de> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <sound/core.h> 15 #include <sound/pcm.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include <sound/tlv.h> 19 #include <linux/gcd.h> 20 #include <linux/i2c.h> 21 #include <linux/spi/spi.h> 22 #include <linux/regmap.h> 23 #include <asm/unaligned.h> 24 25 #include "sigmadsp.h" 26 #include "adau17x1.h" 27 #include "adau-utils.h" 28 29 #define ADAU17X1_SAFELOAD_TARGET_ADDRESS 0x0006 30 #define ADAU17X1_SAFELOAD_TRIGGER 0x0007 31 #define ADAU17X1_SAFELOAD_DATA 0x0001 32 #define ADAU17X1_SAFELOAD_DATA_SIZE 20 33 #define ADAU17X1_WORD_SIZE 4 34 35 static const char * const adau17x1_capture_mixer_boost_text[] = { 36 "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3", 37 }; 38 39 static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum, 40 ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text); 41 42 static const char * const adau17x1_mic_bias_mode_text[] = { 43 "Normal operation", "High performance", 44 }; 45 46 static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum, 47 ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text); 48 49 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0); 50 51 static const struct snd_kcontrol_new adau17x1_controls[] = { 52 SOC_DOUBLE_R_TLV("Digital Capture Volume", 53 ADAU17X1_LEFT_INPUT_DIGITAL_VOL, 54 ADAU17X1_RIGHT_INPUT_DIGITAL_VOL, 55 0, 0xff, 1, adau17x1_digital_tlv), 56 SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1, 57 ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv), 58 59 SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL, 60 5, 1, 0), 61 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0, 62 2, 1, 0), 63 64 SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum), 65 66 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum), 67 }; 68 69 static int adau17x1_setup_firmware(struct snd_soc_component *component, 70 unsigned int rate); 71 72 static int adau17x1_pll_event(struct snd_soc_dapm_widget *w, 73 struct snd_kcontrol *kcontrol, int event) 74 { 75 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 76 struct adau *adau = snd_soc_component_get_drvdata(component); 77 78 if (SND_SOC_DAPM_EVENT_ON(event)) { 79 adau->pll_regs[5] = 1; 80 } else { 81 adau->pll_regs[5] = 0; 82 /* Bypass the PLL when disabled, otherwise registers will become 83 * inaccessible. */ 84 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, 85 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0); 86 } 87 88 /* The PLL register is 6 bytes long and can only be written at once. */ 89 regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL, 90 adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); 91 92 if (SND_SOC_DAPM_EVENT_ON(event)) { 93 mdelay(5); 94 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, 95 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 96 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL); 97 } 98 99 return 0; 100 } 101 102 static int adau17x1_adc_fixup(struct snd_soc_dapm_widget *w, 103 struct snd_kcontrol *kcontrol, int event) 104 { 105 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 106 struct adau *adau = snd_soc_component_get_drvdata(component); 107 108 /* 109 * If we are capturing, toggle the ADOSR bit in Converter Control 0 to 110 * avoid losing SNR (workaround from ADI). This must be done after 111 * the ADC(s) have been enabled. According to the data sheet, it is 112 * normally illegal to set this bit when the sampling rate is 96 kHz, 113 * but according to ADI it is acceptable for this workaround. 114 */ 115 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, 116 ADAU17X1_CONVERTER0_ADOSR, ADAU17X1_CONVERTER0_ADOSR); 117 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, 118 ADAU17X1_CONVERTER0_ADOSR, 0); 119 120 return 0; 121 } 122 123 static const char * const adau17x1_mono_stereo_text[] = { 124 "Stereo", 125 "Mono Left Channel (L+R)", 126 "Mono Right Channel (L+R)", 127 "Mono (L+R)", 128 }; 129 130 static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum, 131 ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text); 132 133 static const struct snd_kcontrol_new adau17x1_dac_mode_mux = 134 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum); 135 136 static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = { 137 SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event, 138 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 139 140 SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0), 141 142 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0), 143 144 SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT, 145 0, 0, NULL, 0), 146 SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT, 147 1, 0, NULL, 0), 148 149 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0, 150 &adau17x1_dac_mode_mux), 151 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0, 152 &adau17x1_dac_mode_mux), 153 154 SND_SOC_DAPM_ADC_E("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0, 155 adau17x1_adc_fixup, SND_SOC_DAPM_POST_PMU), 156 SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0), 157 SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0), 158 SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0), 159 }; 160 161 static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = { 162 { "Left Decimator", NULL, "SYSCLK" }, 163 { "Right Decimator", NULL, "SYSCLK" }, 164 { "Left DAC", NULL, "SYSCLK" }, 165 { "Right DAC", NULL, "SYSCLK" }, 166 { "Capture", NULL, "SYSCLK" }, 167 { "Playback", NULL, "SYSCLK" }, 168 169 { "Left DAC", NULL, "Left DAC Mode Mux" }, 170 { "Right DAC", NULL, "Right DAC Mode Mux" }, 171 172 { "Capture", NULL, "AIFCLK" }, 173 { "Playback", NULL, "AIFCLK" }, 174 }; 175 176 static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = { 177 "SYSCLK", NULL, "PLL", 178 }; 179 180 /* 181 * The MUX register for the Capture and Playback MUXs selects either DSP as 182 * source/destination or one of the TDM slots. The TDM slot is selected via 183 * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or 184 * directly to the DAI interface with this control. 185 */ 186 static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol, 187 struct snd_ctl_elem_value *ucontrol) 188 { 189 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); 190 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 191 struct adau *adau = snd_soc_component_get_drvdata(component); 192 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 193 struct snd_soc_dapm_update update = {}; 194 unsigned int stream = e->shift_l; 195 unsigned int val, change; 196 int reg; 197 198 if (ucontrol->value.enumerated.item[0] >= e->items) 199 return -EINVAL; 200 201 switch (ucontrol->value.enumerated.item[0]) { 202 case 0: 203 val = 0; 204 adau->dsp_bypass[stream] = false; 205 break; 206 default: 207 val = (adau->tdm_slot[stream] * 2) + 1; 208 adau->dsp_bypass[stream] = true; 209 break; 210 } 211 212 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 213 reg = ADAU17X1_SERIAL_INPUT_ROUTE; 214 else 215 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE; 216 217 change = snd_soc_component_test_bits(component, reg, 0xff, val); 218 if (change) { 219 update.kcontrol = kcontrol; 220 update.mask = 0xff; 221 update.reg = reg; 222 update.val = val; 223 224 snd_soc_dapm_mux_update_power(dapm, kcontrol, 225 ucontrol->value.enumerated.item[0], e, &update); 226 } 227 228 return change; 229 } 230 231 static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol, 232 struct snd_ctl_elem_value *ucontrol) 233 { 234 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); 235 struct adau *adau = snd_soc_component_get_drvdata(component); 236 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 237 unsigned int stream = e->shift_l; 238 unsigned int reg, val; 239 int ret; 240 241 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 242 reg = ADAU17X1_SERIAL_INPUT_ROUTE; 243 else 244 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE; 245 246 ret = regmap_read(adau->regmap, reg, &val); 247 if (ret) 248 return ret; 249 250 if (val != 0) 251 val = 1; 252 ucontrol->value.enumerated.item[0] = val; 253 254 return 0; 255 } 256 257 #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \ 258 const struct snd_kcontrol_new _name = \ 259 SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\ 260 SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \ 261 ARRAY_SIZE(_text), _text), \ 262 adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put) 263 264 static const char * const adau17x1_dac_mux_text[] = { 265 "DSP", 266 "AIFIN", 267 }; 268 269 static const char * const adau17x1_capture_mux_text[] = { 270 "DSP", 271 "Decimator", 272 }; 273 274 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux", 275 SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text); 276 277 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux", 278 SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text); 279 280 static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = { 281 SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0), 282 SND_SOC_DAPM_SIGGEN("DSP Siggen"), 283 284 SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0, 285 &adau17x1_dac_mux), 286 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, 287 &adau17x1_capture_mux), 288 }; 289 290 static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = { 291 { "DAC Playback Mux", "DSP", "DSP" }, 292 { "DAC Playback Mux", "AIFIN", "Playback" }, 293 294 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" }, 295 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" }, 296 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" }, 297 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" }, 298 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" }, 299 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" }, 300 301 { "Capture Mux", "DSP", "DSP" }, 302 { "Capture Mux", "Decimator", "Left Decimator" }, 303 { "Capture Mux", "Decimator", "Right Decimator" }, 304 305 { "Capture", NULL, "Capture Mux" }, 306 307 { "DSP", NULL, "DSP Siggen" }, 308 309 { "DSP", NULL, "Left Decimator" }, 310 { "DSP", NULL, "Right Decimator" }, 311 { "DSP", NULL, "Playback" }, 312 }; 313 314 static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = { 315 { "Left DAC Mode Mux", "Stereo", "Playback" }, 316 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" }, 317 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" }, 318 { "Right DAC Mode Mux", "Stereo", "Playback" }, 319 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" }, 320 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" }, 321 { "Capture", NULL, "Left Decimator" }, 322 { "Capture", NULL, "Right Decimator" }, 323 }; 324 325 static bool adau17x1_has_dsp(struct adau *adau) 326 { 327 switch (adau->type) { 328 case ADAU1761: 329 case ADAU1381: 330 case ADAU1781: 331 return true; 332 default: 333 return false; 334 } 335 } 336 337 /* Chip has a DSP but we're pretending it doesn't. */ 338 static bool adau17x1_has_disused_dsp(struct adau *adau) 339 { 340 switch (adau->type) { 341 case ADAU1761_AS_1361: 342 return true; 343 default: 344 return false; 345 } 346 } 347 348 static bool adau17x1_has_safeload(struct adau *adau) 349 { 350 switch (adau->type) { 351 case ADAU1761: 352 case ADAU1781: 353 return true; 354 default: 355 return false; 356 } 357 } 358 359 static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id, 360 int source, unsigned int freq_in, unsigned int freq_out) 361 { 362 struct snd_soc_component *component = dai->component; 363 struct adau *adau = snd_soc_component_get_drvdata(component); 364 int ret; 365 366 if (freq_in < 8000000 || freq_in > 27000000) 367 return -EINVAL; 368 369 ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs); 370 if (ret < 0) 371 return ret; 372 373 /* The PLL register is 6 bytes long and can only be written at once. */ 374 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL, 375 adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); 376 if (ret) 377 return ret; 378 379 adau->pll_freq = freq_out; 380 381 return 0; 382 } 383 384 static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai, 385 int clk_id, unsigned int freq, int dir) 386 { 387 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component); 388 struct adau *adau = snd_soc_component_get_drvdata(dai->component); 389 bool is_pll; 390 bool was_pll; 391 392 switch (clk_id) { 393 case ADAU17X1_CLK_SRC_MCLK: 394 is_pll = false; 395 break; 396 case ADAU17X1_CLK_SRC_PLL_AUTO: 397 if (!adau->mclk) 398 return -EINVAL; 399 fallthrough; 400 case ADAU17X1_CLK_SRC_PLL: 401 is_pll = true; 402 break; 403 default: 404 return -EINVAL; 405 } 406 407 switch (adau->clk_src) { 408 case ADAU17X1_CLK_SRC_MCLK: 409 was_pll = false; 410 break; 411 case ADAU17X1_CLK_SRC_PLL: 412 case ADAU17X1_CLK_SRC_PLL_AUTO: 413 was_pll = true; 414 break; 415 default: 416 return -EINVAL; 417 } 418 419 adau->sysclk = freq; 420 421 if (is_pll != was_pll) { 422 if (is_pll) { 423 snd_soc_dapm_add_routes(dapm, 424 &adau17x1_dapm_pll_route, 1); 425 } else { 426 snd_soc_dapm_del_routes(dapm, 427 &adau17x1_dapm_pll_route, 1); 428 } 429 } 430 431 adau->clk_src = clk_id; 432 433 return 0; 434 } 435 436 static int adau17x1_auto_pll(struct snd_soc_dai *dai, 437 struct snd_pcm_hw_params *params) 438 { 439 struct adau *adau = snd_soc_dai_get_drvdata(dai); 440 unsigned int pll_rate; 441 442 switch (params_rate(params)) { 443 case 48000: 444 case 8000: 445 case 12000: 446 case 16000: 447 case 24000: 448 case 32000: 449 case 96000: 450 pll_rate = 48000 * 1024; 451 break; 452 case 44100: 453 case 7350: 454 case 11025: 455 case 14700: 456 case 22050: 457 case 29400: 458 case 88200: 459 pll_rate = 44100 * 1024; 460 break; 461 default: 462 return -EINVAL; 463 } 464 465 return adau17x1_set_dai_pll(dai, ADAU17X1_PLL, ADAU17X1_PLL_SRC_MCLK, 466 clk_get_rate(adau->mclk), pll_rate); 467 } 468 469 static int adau17x1_hw_params(struct snd_pcm_substream *substream, 470 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 471 { 472 struct snd_soc_component *component = dai->component; 473 struct adau *adau = snd_soc_component_get_drvdata(component); 474 unsigned int val, div, dsp_div; 475 unsigned int freq; 476 int ret; 477 478 switch (adau->clk_src) { 479 case ADAU17X1_CLK_SRC_PLL_AUTO: 480 ret = adau17x1_auto_pll(dai, params); 481 if (ret) 482 return ret; 483 fallthrough; 484 case ADAU17X1_CLK_SRC_PLL: 485 freq = adau->pll_freq; 486 break; 487 default: 488 freq = adau->sysclk; 489 break; 490 } 491 492 if (freq % params_rate(params) != 0) 493 return -EINVAL; 494 495 switch (freq / params_rate(params)) { 496 case 1024: /* fs */ 497 div = 0; 498 dsp_div = 1; 499 break; 500 case 6144: /* fs / 6 */ 501 div = 1; 502 dsp_div = 6; 503 break; 504 case 4096: /* fs / 4 */ 505 div = 2; 506 dsp_div = 5; 507 break; 508 case 3072: /* fs / 3 */ 509 div = 3; 510 dsp_div = 4; 511 break; 512 case 2048: /* fs / 2 */ 513 div = 4; 514 dsp_div = 3; 515 break; 516 case 1536: /* fs / 1.5 */ 517 div = 5; 518 dsp_div = 2; 519 break; 520 case 512: /* fs / 0.5 */ 521 div = 6; 522 dsp_div = 0; 523 break; 524 default: 525 return -EINVAL; 526 } 527 528 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, 529 ADAU17X1_CONVERTER0_CONVSR_MASK, div); 530 531 if (adau17x1_has_dsp(adau) || adau17x1_has_disused_dsp(adau)) 532 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div); 533 if (adau17x1_has_dsp(adau)) 534 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div); 535 536 if (adau->sigmadsp) { 537 ret = adau17x1_setup_firmware(component, params_rate(params)); 538 if (ret < 0) 539 return ret; 540 } 541 542 if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J) 543 return 0; 544 545 switch (params_width(params)) { 546 case 16: 547 val = ADAU17X1_SERIAL_PORT1_DELAY16; 548 break; 549 case 24: 550 val = ADAU17X1_SERIAL_PORT1_DELAY8; 551 break; 552 case 32: 553 val = ADAU17X1_SERIAL_PORT1_DELAY0; 554 break; 555 default: 556 return -EINVAL; 557 } 558 559 return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1, 560 ADAU17X1_SERIAL_PORT1_DELAY_MASK, val); 561 } 562 563 static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai, 564 unsigned int fmt) 565 { 566 struct adau *adau = snd_soc_component_get_drvdata(dai->component); 567 unsigned int ctrl0, ctrl1; 568 unsigned int ctrl0_mask; 569 int lrclk_pol; 570 571 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 572 case SND_SOC_DAIFMT_CBP_CFP: 573 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER; 574 adau->master = true; 575 break; 576 case SND_SOC_DAIFMT_CBC_CFC: 577 ctrl0 = 0; 578 adau->master = false; 579 break; 580 default: 581 return -EINVAL; 582 } 583 584 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 585 case SND_SOC_DAIFMT_I2S: 586 lrclk_pol = 0; 587 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1; 588 break; 589 case SND_SOC_DAIFMT_LEFT_J: 590 case SND_SOC_DAIFMT_RIGHT_J: 591 lrclk_pol = 1; 592 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0; 593 break; 594 case SND_SOC_DAIFMT_DSP_A: 595 lrclk_pol = 1; 596 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; 597 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1; 598 break; 599 case SND_SOC_DAIFMT_DSP_B: 600 lrclk_pol = 1; 601 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; 602 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0; 603 break; 604 default: 605 return -EINVAL; 606 } 607 608 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 609 case SND_SOC_DAIFMT_NB_NF: 610 break; 611 case SND_SOC_DAIFMT_IB_NF: 612 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; 613 break; 614 case SND_SOC_DAIFMT_NB_IF: 615 lrclk_pol = !lrclk_pol; 616 break; 617 case SND_SOC_DAIFMT_IB_IF: 618 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; 619 lrclk_pol = !lrclk_pol; 620 break; 621 default: 622 return -EINVAL; 623 } 624 625 if (lrclk_pol) 626 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL; 627 628 /* Set the mask to update all relevant bits in ADAU17X1_SERIAL_PORT0 */ 629 ctrl0_mask = ADAU17X1_SERIAL_PORT0_MASTER | 630 ADAU17X1_SERIAL_PORT0_LRCLK_POL | 631 ADAU17X1_SERIAL_PORT0_BCLK_POL | 632 ADAU17X1_SERIAL_PORT0_PULSE_MODE; 633 634 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0_mask, 635 ctrl0); 636 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1, 637 ADAU17X1_SERIAL_PORT1_DELAY_MASK, ctrl1); 638 639 adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 640 641 return 0; 642 } 643 644 static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai, 645 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 646 { 647 struct adau *adau = snd_soc_component_get_drvdata(dai->component); 648 unsigned int ser_ctrl0, ser_ctrl1; 649 unsigned int conv_ctrl0, conv_ctrl1; 650 651 /* I2S mode */ 652 if (slots == 0) { 653 slots = 2; 654 rx_mask = 3; 655 tx_mask = 3; 656 slot_width = 32; 657 } 658 659 switch (slots) { 660 case 2: 661 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO; 662 break; 663 case 4: 664 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4; 665 break; 666 case 8: 667 if (adau->type == ADAU1361) 668 return -EINVAL; 669 670 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8; 671 break; 672 default: 673 return -EINVAL; 674 } 675 676 switch (slot_width * slots) { 677 case 32: 678 if (adau->type == ADAU1761 || adau->type == ADAU1761_AS_1361) 679 return -EINVAL; 680 681 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32; 682 break; 683 case 64: 684 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64; 685 break; 686 case 48: 687 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48; 688 break; 689 case 128: 690 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128; 691 break; 692 case 256: 693 if (adau->type == ADAU1361) 694 return -EINVAL; 695 696 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256; 697 break; 698 default: 699 return -EINVAL; 700 } 701 702 switch (rx_mask) { 703 case 0x03: 704 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1); 705 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0; 706 break; 707 case 0x0c: 708 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2); 709 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1; 710 break; 711 case 0x30: 712 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3); 713 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2; 714 break; 715 case 0xc0: 716 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4); 717 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3; 718 break; 719 default: 720 return -EINVAL; 721 } 722 723 switch (tx_mask) { 724 case 0x03: 725 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1); 726 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0; 727 break; 728 case 0x0c: 729 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2); 730 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1; 731 break; 732 case 0x30: 733 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3); 734 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2; 735 break; 736 case 0xc0: 737 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4); 738 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3; 739 break; 740 default: 741 return -EINVAL; 742 } 743 744 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, 745 ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0); 746 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1, 747 ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1); 748 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0, 749 ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0); 750 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1, 751 ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1); 752 753 if (!adau17x1_has_dsp(adau) && !adau17x1_has_disused_dsp(adau)) 754 return 0; 755 756 if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) { 757 regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE, 758 (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1); 759 } 760 761 if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) { 762 regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE, 763 (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1); 764 } 765 766 return 0; 767 } 768 769 static int adau17x1_startup(struct snd_pcm_substream *substream, 770 struct snd_soc_dai *dai) 771 { 772 struct adau *adau = snd_soc_component_get_drvdata(dai->component); 773 774 if (adau->sigmadsp) 775 return sigmadsp_restrict_params(adau->sigmadsp, substream); 776 777 return 0; 778 } 779 780 const struct snd_soc_dai_ops adau17x1_dai_ops = { 781 .hw_params = adau17x1_hw_params, 782 .set_sysclk = adau17x1_set_dai_sysclk, 783 .set_fmt = adau17x1_set_dai_fmt, 784 .set_pll = adau17x1_set_dai_pll, 785 .set_tdm_slot = adau17x1_set_dai_tdm_slot, 786 .startup = adau17x1_startup, 787 }; 788 EXPORT_SYMBOL_GPL(adau17x1_dai_ops); 789 790 int adau17x1_set_micbias_voltage(struct snd_soc_component *component, 791 enum adau17x1_micbias_voltage micbias) 792 { 793 struct adau *adau = snd_soc_component_get_drvdata(component); 794 795 switch (micbias) { 796 case ADAU17X1_MICBIAS_0_90_AVDD: 797 case ADAU17X1_MICBIAS_0_65_AVDD: 798 break; 799 default: 800 return -EINVAL; 801 } 802 803 return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2); 804 } 805 EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage); 806 807 bool adau17x1_precious_register(struct device *dev, unsigned int reg) 808 { 809 /* SigmaDSP parameter memory */ 810 if (reg < 0x400) 811 return true; 812 813 return false; 814 } 815 EXPORT_SYMBOL_GPL(adau17x1_precious_register); 816 817 bool adau17x1_readable_register(struct device *dev, unsigned int reg) 818 { 819 /* SigmaDSP parameter memory */ 820 if (reg < 0x400) 821 return true; 822 823 switch (reg) { 824 case ADAU17X1_CLOCK_CONTROL: 825 case ADAU17X1_PLL_CONTROL: 826 case ADAU17X1_REC_POWER_MGMT: 827 case ADAU17X1_MICBIAS: 828 case ADAU17X1_SERIAL_PORT0: 829 case ADAU17X1_SERIAL_PORT1: 830 case ADAU17X1_CONVERTER0: 831 case ADAU17X1_CONVERTER1: 832 case ADAU17X1_LEFT_INPUT_DIGITAL_VOL: 833 case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL: 834 case ADAU17X1_ADC_CONTROL: 835 case ADAU17X1_PLAY_POWER_MGMT: 836 case ADAU17X1_DAC_CONTROL0: 837 case ADAU17X1_DAC_CONTROL1: 838 case ADAU17X1_DAC_CONTROL2: 839 case ADAU17X1_SERIAL_PORT_PAD: 840 case ADAU17X1_CONTROL_PORT_PAD0: 841 case ADAU17X1_CONTROL_PORT_PAD1: 842 case ADAU17X1_DSP_SAMPLING_RATE: 843 case ADAU17X1_SERIAL_INPUT_ROUTE: 844 case ADAU17X1_SERIAL_OUTPUT_ROUTE: 845 case ADAU17X1_DSP_ENABLE: 846 case ADAU17X1_DSP_RUN: 847 case ADAU17X1_SERIAL_SAMPLING_RATE: 848 return true; 849 default: 850 break; 851 } 852 return false; 853 } 854 EXPORT_SYMBOL_GPL(adau17x1_readable_register); 855 856 bool adau17x1_volatile_register(struct device *dev, unsigned int reg) 857 { 858 /* SigmaDSP parameter and program memory */ 859 if (reg < 0x4000) 860 return true; 861 862 switch (reg) { 863 /* The PLL register is 6 bytes long */ 864 case ADAU17X1_PLL_CONTROL: 865 case ADAU17X1_PLL_CONTROL + 1: 866 case ADAU17X1_PLL_CONTROL + 2: 867 case ADAU17X1_PLL_CONTROL + 3: 868 case ADAU17X1_PLL_CONTROL + 4: 869 case ADAU17X1_PLL_CONTROL + 5: 870 return true; 871 default: 872 break; 873 } 874 875 return false; 876 } 877 EXPORT_SYMBOL_GPL(adau17x1_volatile_register); 878 879 static int adau17x1_setup_firmware(struct snd_soc_component *component, 880 unsigned int rate) 881 { 882 int ret; 883 int dspsr, dsp_run; 884 struct adau *adau = snd_soc_component_get_drvdata(component); 885 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 886 887 /* Check if sample rate is the same as before. If it is there is no 888 * point in performing the below steps as the call to 889 * sigmadsp_setup(...) will return directly when it finds the sample 890 * rate to be the same as before. By checking this we can prevent an 891 * audiable popping noise which occours when toggling DSP_RUN. 892 */ 893 if (adau->sigmadsp->current_samplerate == rate) 894 return 0; 895 896 snd_soc_dapm_mutex_lock(dapm); 897 898 ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr); 899 if (ret) 900 goto err; 901 902 ret = regmap_read(adau->regmap, ADAU17X1_DSP_RUN, &dsp_run); 903 if (ret) 904 goto err; 905 906 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1); 907 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf); 908 regmap_write(adau->regmap, ADAU17X1_DSP_RUN, 0); 909 910 ret = sigmadsp_setup(adau->sigmadsp, rate); 911 if (ret) { 912 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0); 913 goto err; 914 } 915 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr); 916 regmap_write(adau->regmap, ADAU17X1_DSP_RUN, dsp_run); 917 918 err: 919 snd_soc_dapm_mutex_unlock(dapm); 920 921 return ret; 922 } 923 924 int adau17x1_add_widgets(struct snd_soc_component *component) 925 { 926 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 927 struct adau *adau = snd_soc_component_get_drvdata(component); 928 int ret; 929 930 ret = snd_soc_add_component_controls(component, adau17x1_controls, 931 ARRAY_SIZE(adau17x1_controls)); 932 if (ret) 933 return ret; 934 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets, 935 ARRAY_SIZE(adau17x1_dapm_widgets)); 936 if (ret) 937 return ret; 938 939 if (adau17x1_has_dsp(adau)) { 940 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets, 941 ARRAY_SIZE(adau17x1_dsp_dapm_widgets)); 942 if (ret) 943 return ret; 944 945 if (!adau->sigmadsp) 946 return 0; 947 948 ret = sigmadsp_attach(adau->sigmadsp, component); 949 if (ret) { 950 dev_err(component->dev, "Failed to attach firmware: %d\n", 951 ret); 952 return ret; 953 } 954 } 955 956 return 0; 957 } 958 EXPORT_SYMBOL_GPL(adau17x1_add_widgets); 959 960 int adau17x1_add_routes(struct snd_soc_component *component) 961 { 962 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 963 struct adau *adau = snd_soc_component_get_drvdata(component); 964 int ret; 965 966 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes, 967 ARRAY_SIZE(adau17x1_dapm_routes)); 968 if (ret) 969 return ret; 970 971 if (adau17x1_has_dsp(adau)) { 972 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes, 973 ARRAY_SIZE(adau17x1_dsp_dapm_routes)); 974 } else { 975 ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes, 976 ARRAY_SIZE(adau17x1_no_dsp_dapm_routes)); 977 } 978 979 if (adau->clk_src != ADAU17X1_CLK_SRC_MCLK) 980 snd_soc_dapm_add_routes(dapm, &adau17x1_dapm_pll_route, 1); 981 982 return ret; 983 } 984 EXPORT_SYMBOL_GPL(adau17x1_add_routes); 985 986 int adau17x1_resume(struct snd_soc_component *component) 987 { 988 struct adau *adau = snd_soc_component_get_drvdata(component); 989 990 if (adau->switch_mode) 991 adau->switch_mode(component->dev); 992 993 regcache_sync(adau->regmap); 994 995 return 0; 996 } 997 EXPORT_SYMBOL_GPL(adau17x1_resume); 998 999 static int adau17x1_safeload(struct sigmadsp *sigmadsp, unsigned int addr, 1000 const uint8_t bytes[], size_t len) 1001 { 1002 uint8_t buf[ADAU17X1_WORD_SIZE]; 1003 uint8_t data[ADAU17X1_SAFELOAD_DATA_SIZE]; 1004 unsigned int addr_offset; 1005 unsigned int nbr_words; 1006 int ret; 1007 1008 /* write data to safeload addresses. Check if len is not a multiple of 1009 * 4 bytes, if so we need to zero pad. 1010 */ 1011 nbr_words = len / ADAU17X1_WORD_SIZE; 1012 if ((len - nbr_words * ADAU17X1_WORD_SIZE) == 0) { 1013 ret = regmap_raw_write(sigmadsp->control_data, 1014 ADAU17X1_SAFELOAD_DATA, bytes, len); 1015 } else { 1016 nbr_words++; 1017 memset(data, 0, ADAU17X1_SAFELOAD_DATA_SIZE); 1018 memcpy(data, bytes, len); 1019 ret = regmap_raw_write(sigmadsp->control_data, 1020 ADAU17X1_SAFELOAD_DATA, data, 1021 nbr_words * ADAU17X1_WORD_SIZE); 1022 } 1023 1024 if (ret < 0) 1025 return ret; 1026 1027 /* Write target address, target address is offset by 1 */ 1028 addr_offset = addr - 1; 1029 put_unaligned_be32(addr_offset, buf); 1030 ret = regmap_raw_write(sigmadsp->control_data, 1031 ADAU17X1_SAFELOAD_TARGET_ADDRESS, buf, ADAU17X1_WORD_SIZE); 1032 if (ret < 0) 1033 return ret; 1034 1035 /* write nbr of words to trigger address */ 1036 put_unaligned_be32(nbr_words, buf); 1037 ret = regmap_raw_write(sigmadsp->control_data, 1038 ADAU17X1_SAFELOAD_TRIGGER, buf, ADAU17X1_WORD_SIZE); 1039 if (ret < 0) 1040 return ret; 1041 1042 return 0; 1043 } 1044 1045 static const struct sigmadsp_ops adau17x1_sigmadsp_ops = { 1046 .safeload = adau17x1_safeload, 1047 }; 1048 1049 int adau17x1_probe(struct device *dev, struct regmap *regmap, 1050 enum adau17x1_type type, void (*switch_mode)(struct device *dev), 1051 const char *firmware_name) 1052 { 1053 struct adau *adau; 1054 int ret; 1055 1056 if (IS_ERR(regmap)) 1057 return PTR_ERR(regmap); 1058 1059 adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL); 1060 if (!adau) 1061 return -ENOMEM; 1062 1063 adau->mclk = devm_clk_get(dev, "mclk"); 1064 if (IS_ERR(adau->mclk)) { 1065 if (PTR_ERR(adau->mclk) != -ENOENT) 1066 return PTR_ERR(adau->mclk); 1067 /* Clock is optional (for the driver) */ 1068 adau->mclk = NULL; 1069 } else if (adau->mclk) { 1070 adau->clk_src = ADAU17X1_CLK_SRC_PLL_AUTO; 1071 1072 /* 1073 * Any valid PLL output rate will work at this point, use one 1074 * that is likely to be chosen later as well. The register will 1075 * be written when the PLL is powered up for the first time. 1076 */ 1077 ret = adau_calc_pll_cfg(clk_get_rate(adau->mclk), 48000 * 1024, 1078 adau->pll_regs); 1079 if (ret < 0) 1080 return ret; 1081 1082 ret = clk_prepare_enable(adau->mclk); 1083 if (ret) 1084 return ret; 1085 } 1086 1087 adau->regmap = regmap; 1088 adau->switch_mode = switch_mode; 1089 adau->type = type; 1090 1091 dev_set_drvdata(dev, adau); 1092 1093 if (firmware_name) { 1094 if (adau17x1_has_safeload(adau)) { 1095 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, 1096 &adau17x1_sigmadsp_ops, firmware_name); 1097 } else { 1098 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, 1099 NULL, firmware_name); 1100 } 1101 if (IS_ERR(adau->sigmadsp)) { 1102 dev_warn(dev, "Could not find firmware file: %ld\n", 1103 PTR_ERR(adau->sigmadsp)); 1104 adau->sigmadsp = NULL; 1105 } 1106 } 1107 1108 if (switch_mode) 1109 switch_mode(dev); 1110 1111 return 0; 1112 } 1113 EXPORT_SYMBOL_GPL(adau17x1_probe); 1114 1115 void adau17x1_remove(struct device *dev) 1116 { 1117 struct adau *adau = dev_get_drvdata(dev); 1118 1119 clk_disable_unprepare(adau->mclk); 1120 } 1121 EXPORT_SYMBOL_GPL(adau17x1_remove); 1122 1123 MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code"); 1124 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1125 MODULE_LICENSE("GPL"); 1126