1 /* 2 * Analog Devices ADAU1373 Audio Codec drive 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * Author: Lars-Peter Clausen <lars@metafoo.de> 6 * 7 * Licensed under the GPL-2 or later. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/slab.h> 16 #include <linux/gcd.h> 17 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/tlv.h> 22 #include <sound/soc.h> 23 #include <sound/adau1373.h> 24 25 #include "adau1373.h" 26 27 struct adau1373_dai { 28 unsigned int clk_src; 29 unsigned int sysclk; 30 bool enable_src; 31 bool master; 32 }; 33 34 struct adau1373 { 35 struct adau1373_dai dais[3]; 36 }; 37 38 #define ADAU1373_INPUT_MODE 0x00 39 #define ADAU1373_AINL_CTRL(x) (0x01 + (x) * 2) 40 #define ADAU1373_AINR_CTRL(x) (0x02 + (x) * 2) 41 #define ADAU1373_LLINE_OUT(x) (0x9 + (x) * 2) 42 #define ADAU1373_RLINE_OUT(x) (0xa + (x) * 2) 43 #define ADAU1373_LSPK_OUT 0x0d 44 #define ADAU1373_RSPK_OUT 0x0e 45 #define ADAU1373_LHP_OUT 0x0f 46 #define ADAU1373_RHP_OUT 0x10 47 #define ADAU1373_ADC_GAIN 0x11 48 #define ADAU1373_LADC_MIXER 0x12 49 #define ADAU1373_RADC_MIXER 0x13 50 #define ADAU1373_LLINE1_MIX 0x14 51 #define ADAU1373_RLINE1_MIX 0x15 52 #define ADAU1373_LLINE2_MIX 0x16 53 #define ADAU1373_RLINE2_MIX 0x17 54 #define ADAU1373_LSPK_MIX 0x18 55 #define ADAU1373_RSPK_MIX 0x19 56 #define ADAU1373_LHP_MIX 0x1a 57 #define ADAU1373_RHP_MIX 0x1b 58 #define ADAU1373_EP_MIX 0x1c 59 #define ADAU1373_HP_CTRL 0x1d 60 #define ADAU1373_HP_CTRL2 0x1e 61 #define ADAU1373_LS_CTRL 0x1f 62 #define ADAU1373_EP_CTRL 0x21 63 #define ADAU1373_MICBIAS_CTRL1 0x22 64 #define ADAU1373_MICBIAS_CTRL2 0x23 65 #define ADAU1373_OUTPUT_CTRL 0x24 66 #define ADAU1373_PWDN_CTRL1 0x25 67 #define ADAU1373_PWDN_CTRL2 0x26 68 #define ADAU1373_PWDN_CTRL3 0x27 69 #define ADAU1373_DPLL_CTRL(x) (0x28 + (x) * 7) 70 #define ADAU1373_PLL_CTRL1(x) (0x29 + (x) * 7) 71 #define ADAU1373_PLL_CTRL2(x) (0x2a + (x) * 7) 72 #define ADAU1373_PLL_CTRL3(x) (0x2b + (x) * 7) 73 #define ADAU1373_PLL_CTRL4(x) (0x2c + (x) * 7) 74 #define ADAU1373_PLL_CTRL5(x) (0x2d + (x) * 7) 75 #define ADAU1373_PLL_CTRL6(x) (0x2e + (x) * 7) 76 #define ADAU1373_PLL_CTRL7(x) (0x2f + (x) * 7) 77 #define ADAU1373_HEADDECT 0x36 78 #define ADAU1373_ADC_DAC_STATUS 0x37 79 #define ADAU1373_ADC_CTRL 0x3c 80 #define ADAU1373_DAI(x) (0x44 + (x)) 81 #define ADAU1373_CLK_SRC_DIV(x) (0x40 + (x) * 2) 82 #define ADAU1373_BCLKDIV(x) (0x47 + (x)) 83 #define ADAU1373_SRC_RATIOA(x) (0x4a + (x) * 2) 84 #define ADAU1373_SRC_RATIOB(x) (0x4b + (x) * 2) 85 #define ADAU1373_DEEMP_CTRL 0x50 86 #define ADAU1373_SRC_DAI_CTRL(x) (0x51 + (x)) 87 #define ADAU1373_DIN_MIX_CTRL(x) (0x56 + (x)) 88 #define ADAU1373_DOUT_MIX_CTRL(x) (0x5b + (x)) 89 #define ADAU1373_DAI_PBL_VOL(x) (0x62 + (x) * 2) 90 #define ADAU1373_DAI_PBR_VOL(x) (0x63 + (x) * 2) 91 #define ADAU1373_DAI_RECL_VOL(x) (0x68 + (x) * 2) 92 #define ADAU1373_DAI_RECR_VOL(x) (0x69 + (x) * 2) 93 #define ADAU1373_DAC1_PBL_VOL 0x6e 94 #define ADAU1373_DAC1_PBR_VOL 0x6f 95 #define ADAU1373_DAC2_PBL_VOL 0x70 96 #define ADAU1373_DAC2_PBR_VOL 0x71 97 #define ADAU1373_ADC_RECL_VOL 0x72 98 #define ADAU1373_ADC_RECR_VOL 0x73 99 #define ADAU1373_DMIC_RECL_VOL 0x74 100 #define ADAU1373_DMIC_RECR_VOL 0x75 101 #define ADAU1373_VOL_GAIN1 0x76 102 #define ADAU1373_VOL_GAIN2 0x77 103 #define ADAU1373_VOL_GAIN3 0x78 104 #define ADAU1373_HPF_CTRL 0x7d 105 #define ADAU1373_BASS1 0x7e 106 #define ADAU1373_BASS2 0x7f 107 #define ADAU1373_DRC(x) (0x80 + (x) * 0x10) 108 #define ADAU1373_3D_CTRL1 0xc0 109 #define ADAU1373_3D_CTRL2 0xc1 110 #define ADAU1373_FDSP_SEL1 0xdc 111 #define ADAU1373_FDSP_SEL2 0xdd 112 #define ADAU1373_FDSP_SEL3 0xde 113 #define ADAU1373_FDSP_SEL4 0xdf 114 #define ADAU1373_DIGMICCTRL 0xe2 115 #define ADAU1373_DIGEN 0xeb 116 #define ADAU1373_SOFT_RESET 0xff 117 118 119 #define ADAU1373_PLL_CTRL6_DPLL_BYPASS BIT(1) 120 #define ADAU1373_PLL_CTRL6_PLL_EN BIT(0) 121 122 #define ADAU1373_DAI_INVERT_BCLK BIT(7) 123 #define ADAU1373_DAI_MASTER BIT(6) 124 #define ADAU1373_DAI_INVERT_LRCLK BIT(4) 125 #define ADAU1373_DAI_WLEN_16 0x0 126 #define ADAU1373_DAI_WLEN_20 0x4 127 #define ADAU1373_DAI_WLEN_24 0x8 128 #define ADAU1373_DAI_WLEN_32 0xc 129 #define ADAU1373_DAI_WLEN_MASK 0xc 130 #define ADAU1373_DAI_FORMAT_RIGHT_J 0x0 131 #define ADAU1373_DAI_FORMAT_LEFT_J 0x1 132 #define ADAU1373_DAI_FORMAT_I2S 0x2 133 #define ADAU1373_DAI_FORMAT_DSP 0x3 134 135 #define ADAU1373_BCLKDIV_SOURCE BIT(5) 136 #define ADAU1373_BCLKDIV_SR_MASK (0x07 << 2) 137 #define ADAU1373_BCLKDIV_BCLK_MASK 0x03 138 #define ADAU1373_BCLKDIV_32 0x03 139 #define ADAU1373_BCLKDIV_64 0x02 140 #define ADAU1373_BCLKDIV_128 0x01 141 #define ADAU1373_BCLKDIV_256 0x00 142 143 #define ADAU1373_ADC_CTRL_PEAK_DETECT BIT(0) 144 #define ADAU1373_ADC_CTRL_RESET BIT(1) 145 #define ADAU1373_ADC_CTRL_RESET_FORCE BIT(2) 146 147 #define ADAU1373_OUTPUT_CTRL_LDIFF BIT(3) 148 #define ADAU1373_OUTPUT_CTRL_LNFBEN BIT(2) 149 150 #define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0) 151 152 #define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4 153 #define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2 154 155 static const uint8_t adau1373_default_regs[] = { 156 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x00 */ 157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 158 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x10 */ 159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 160 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ 161 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 162 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, /* 0x30 */ 163 0x00, 0x00, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 164 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x00, /* 0x40 */ 165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 166 0x00, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, /* 0x50 */ 167 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 168 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x60 */ 169 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x70 */ 171 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 172 0x78, 0x18, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, /* 0x80 */ 173 0x00, 0xc0, 0x88, 0x7a, 0xdf, 0x20, 0x00, 0x00, 174 0x78, 0x18, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, /* 0x90 */ 175 0x00, 0xc0, 0x88, 0x7a, 0xdf, 0x20, 0x00, 0x00, 176 0x78, 0x18, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, /* 0xa0 */ 177 0x00, 0xc0, 0x88, 0x7a, 0xdf, 0x20, 0x00, 0x00, 178 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xb0 */ 179 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xc0 */ 181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xd0 */ 183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, /* 0xe0 */ 185 0x00, 0x1f, 0x0f, 0x00, 0x00, 186 }; 187 188 static const unsigned int adau1373_out_tlv[] = { 189 TLV_DB_RANGE_HEAD(4), 190 0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1), 191 8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0), 192 16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0), 193 24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0), 194 }; 195 196 static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv, -9563, 0); 197 static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv, -1300, 100, 1); 198 static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv, -600, 600, 1); 199 200 static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv, 0, 2000, 0); 201 static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv, 0, 600, 0); 202 static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv, 1200, 600, 0); 203 204 static const char *adau1373_fdsp_sel_text[] = { 205 "None", 206 "Channel 1", 207 "Channel 2", 208 "Channel 3", 209 "Channel 4", 210 "Channel 5", 211 }; 212 213 static const SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum, 214 ADAU1373_FDSP_SEL1, 4, adau1373_fdsp_sel_text); 215 static const SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum, 216 ADAU1373_FDSP_SEL1, 0, adau1373_fdsp_sel_text); 217 static const SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum, 218 ADAU1373_FDSP_SEL2, 0, adau1373_fdsp_sel_text); 219 static const SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum, 220 ADAU1373_FDSP_SEL3, 0, adau1373_fdsp_sel_text); 221 static const SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum, 222 ADAU1373_FDSP_SEL4, 4, adau1373_fdsp_sel_text); 223 224 static const char *adau1373_hpf_cutoff_text[] = { 225 "3.7Hz", "50Hz", "100Hz", "150Hz", "200Hz", "250Hz", "300Hz", "350Hz", 226 "400Hz", "450Hz", "500Hz", "550Hz", "600Hz", "650Hz", "700Hz", "750Hz", 227 "800Hz", 228 }; 229 230 static const SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum, 231 ADAU1373_HPF_CTRL, 3, adau1373_hpf_cutoff_text); 232 233 static const char *adau1373_bass_lpf_cutoff_text[] = { 234 "801Hz", "1001Hz", 235 }; 236 237 static const char *adau1373_bass_clip_level_text[] = { 238 "0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875", 239 }; 240 241 static const unsigned int adau1373_bass_clip_level_values[] = { 242 1, 2, 3, 4, 5, 6, 7, 243 }; 244 245 static const char *adau1373_bass_hpf_cutoff_text[] = { 246 "158Hz", "232Hz", "347Hz", "520Hz", 247 }; 248 249 static const unsigned int adau1373_bass_tlv[] = { 250 TLV_DB_RANGE_HEAD(3), 251 0, 2, TLV_DB_SCALE_ITEM(-600, 600, 1), 252 3, 4, TLV_DB_SCALE_ITEM(950, 250, 0), 253 5, 7, TLV_DB_SCALE_ITEM(1400, 150, 0), 254 }; 255 256 static const SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum, 257 ADAU1373_BASS1, 5, adau1373_bass_lpf_cutoff_text); 258 259 static const SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum, 260 ADAU1373_BASS1, 2, 7, adau1373_bass_clip_level_text, 261 adau1373_bass_clip_level_values); 262 263 static const SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum, 264 ADAU1373_BASS1, 0, adau1373_bass_hpf_cutoff_text); 265 266 static const char *adau1373_3d_level_text[] = { 267 "0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%", 268 "40%", "46.67%", "53.33%", "60%", "66.67%", "73.33%", 269 "80%", "86.67", "99.33%", "100%" 270 }; 271 272 static const char *adau1373_3d_cutoff_text[] = { 273 "No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs", 274 "0.16875 fs", "0.27083 fs" 275 }; 276 277 static const SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum, 278 ADAU1373_3D_CTRL1, 4, adau1373_3d_level_text); 279 static const SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum, 280 ADAU1373_3D_CTRL1, 0, adau1373_3d_cutoff_text); 281 282 static const unsigned int adau1373_3d_tlv[] = { 283 TLV_DB_RANGE_HEAD(2), 284 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 285 1, 7, TLV_DB_LINEAR_ITEM(-1800, -120), 286 }; 287 288 static const char *adau1373_lr_mux_text[] = { 289 "Mute", 290 "Right Channel (L+R)", 291 "Left Channel (L+R)", 292 "Stereo", 293 }; 294 295 static const SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum, 296 ADAU1373_OUTPUT_CTRL, 4, adau1373_lr_mux_text); 297 static const SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum, 298 ADAU1373_OUTPUT_CTRL, 6, adau1373_lr_mux_text); 299 static const SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum, 300 ADAU1373_LS_CTRL, 4, adau1373_lr_mux_text); 301 302 static const struct snd_kcontrol_new adau1373_controls[] = { 303 SOC_DOUBLE_R_TLV("AIF1 Capture Volume", ADAU1373_DAI_RECL_VOL(0), 304 ADAU1373_DAI_RECR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv), 305 SOC_DOUBLE_R_TLV("AIF2 Capture Volume", ADAU1373_DAI_RECL_VOL(1), 306 ADAU1373_DAI_RECR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv), 307 SOC_DOUBLE_R_TLV("AIF3 Capture Volume", ADAU1373_DAI_RECL_VOL(2), 308 ADAU1373_DAI_RECR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv), 309 310 SOC_DOUBLE_R_TLV("ADC Capture Volume", ADAU1373_ADC_RECL_VOL, 311 ADAU1373_ADC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv), 312 SOC_DOUBLE_R_TLV("DMIC Capture Volume", ADAU1373_DMIC_RECL_VOL, 313 ADAU1373_DMIC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv), 314 315 SOC_DOUBLE_R_TLV("AIF1 Playback Volume", ADAU1373_DAI_PBL_VOL(0), 316 ADAU1373_DAI_PBR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv), 317 SOC_DOUBLE_R_TLV("AIF2 Playback Volume", ADAU1373_DAI_PBL_VOL(1), 318 ADAU1373_DAI_PBR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv), 319 SOC_DOUBLE_R_TLV("AIF3 Playback Volume", ADAU1373_DAI_PBL_VOL(2), 320 ADAU1373_DAI_PBR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv), 321 322 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ADAU1373_DAC1_PBL_VOL, 323 ADAU1373_DAC1_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv), 324 SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ADAU1373_DAC2_PBL_VOL, 325 ADAU1373_DAC2_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv), 326 327 SOC_DOUBLE_R_TLV("Lineout1 Playback Volume", ADAU1373_LLINE_OUT(0), 328 ADAU1373_RLINE_OUT(0), 0, 0x1f, 0, adau1373_out_tlv), 329 SOC_DOUBLE_R_TLV("Speaker Playback Volume", ADAU1373_LSPK_OUT, 330 ADAU1373_RSPK_OUT, 0, 0x1f, 0, adau1373_out_tlv), 331 SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1373_LHP_OUT, 332 ADAU1373_RHP_OUT, 0, 0x1f, 0, adau1373_out_tlv), 333 334 SOC_DOUBLE_R_TLV("Input 1 Capture Volume", ADAU1373_AINL_CTRL(0), 335 ADAU1373_AINR_CTRL(0), 0, 0x1f, 0, adau1373_in_pga_tlv), 336 SOC_DOUBLE_R_TLV("Input 2 Capture Volume", ADAU1373_AINL_CTRL(1), 337 ADAU1373_AINR_CTRL(1), 0, 0x1f, 0, adau1373_in_pga_tlv), 338 SOC_DOUBLE_R_TLV("Input 3 Capture Volume", ADAU1373_AINL_CTRL(2), 339 ADAU1373_AINR_CTRL(2), 0, 0x1f, 0, adau1373_in_pga_tlv), 340 SOC_DOUBLE_R_TLV("Input 4 Capture Volume", ADAU1373_AINL_CTRL(3), 341 ADAU1373_AINR_CTRL(3), 0, 0x1f, 0, adau1373_in_pga_tlv), 342 343 SOC_SINGLE_TLV("Earpiece Playback Volume", ADAU1373_EP_CTRL, 0, 3, 0, 344 adau1373_ep_tlv), 345 346 SOC_DOUBLE_TLV("AIF3 Boost Playback Volume", ADAU1373_VOL_GAIN1, 4, 5, 347 1, 0, adau1373_gain_boost_tlv), 348 SOC_DOUBLE_TLV("AIF2 Boost Playback Volume", ADAU1373_VOL_GAIN1, 2, 3, 349 1, 0, adau1373_gain_boost_tlv), 350 SOC_DOUBLE_TLV("AIF1 Boost Playback Volume", ADAU1373_VOL_GAIN1, 0, 1, 351 1, 0, adau1373_gain_boost_tlv), 352 SOC_DOUBLE_TLV("AIF3 Boost Capture Volume", ADAU1373_VOL_GAIN2, 4, 5, 353 1, 0, adau1373_gain_boost_tlv), 354 SOC_DOUBLE_TLV("AIF2 Boost Capture Volume", ADAU1373_VOL_GAIN2, 2, 3, 355 1, 0, adau1373_gain_boost_tlv), 356 SOC_DOUBLE_TLV("AIF1 Boost Capture Volume", ADAU1373_VOL_GAIN2, 0, 1, 357 1, 0, adau1373_gain_boost_tlv), 358 SOC_DOUBLE_TLV("DMIC Boost Capture Volume", ADAU1373_VOL_GAIN3, 6, 7, 359 1, 0, adau1373_gain_boost_tlv), 360 SOC_DOUBLE_TLV("ADC Boost Capture Volume", ADAU1373_VOL_GAIN3, 4, 5, 361 1, 0, adau1373_gain_boost_tlv), 362 SOC_DOUBLE_TLV("DAC2 Boost Playback Volume", ADAU1373_VOL_GAIN3, 2, 3, 363 1, 0, adau1373_gain_boost_tlv), 364 SOC_DOUBLE_TLV("DAC1 Boost Playback Volume", ADAU1373_VOL_GAIN3, 0, 1, 365 1, 0, adau1373_gain_boost_tlv), 366 367 SOC_DOUBLE_TLV("Input 1 Boost Capture Volume", ADAU1373_ADC_GAIN, 0, 4, 368 1, 0, adau1373_input_boost_tlv), 369 SOC_DOUBLE_TLV("Input 2 Boost Capture Volume", ADAU1373_ADC_GAIN, 1, 5, 370 1, 0, adau1373_input_boost_tlv), 371 SOC_DOUBLE_TLV("Input 3 Boost Capture Volume", ADAU1373_ADC_GAIN, 2, 6, 372 1, 0, adau1373_input_boost_tlv), 373 SOC_DOUBLE_TLV("Input 4 Boost Capture Volume", ADAU1373_ADC_GAIN, 3, 7, 374 1, 0, adau1373_input_boost_tlv), 375 376 SOC_DOUBLE_TLV("Speaker Boost Playback Volume", ADAU1373_LS_CTRL, 2, 3, 377 1, 0, adau1373_speaker_boost_tlv), 378 379 SOC_ENUM("Lineout1 LR Mux", adau1373_lineout1_lr_mux_enum), 380 SOC_ENUM("Speaker LR Mux", adau1373_speaker_lr_mux_enum), 381 382 SOC_ENUM("HPF Cutoff", adau1373_hpf_cutoff_enum), 383 SOC_DOUBLE("HPF Switch", ADAU1373_HPF_CTRL, 1, 0, 1, 0), 384 SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum), 385 386 SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum), 387 SOC_VALUE_ENUM("Bass Clip Level Threshold", 388 adau1373_bass_clip_level_enum), 389 SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum), 390 SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0), 391 SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0, 392 adau1373_bass_tlv), 393 SOC_ENUM("Bass Channel", adau1373_bass_channel_enum), 394 395 SOC_ENUM("3D Freq", adau1373_3d_cutoff_enum), 396 SOC_ENUM("3D Level", adau1373_3d_level_enum), 397 SOC_SINGLE("3D Playback Switch", ADAU1373_3D_CTRL2, 0, 1, 0), 398 SOC_SINGLE_TLV("3D Playback Volume", ADAU1373_3D_CTRL2, 2, 7, 0, 399 adau1373_3d_tlv), 400 SOC_ENUM("3D Channel", adau1373_bass_channel_enum), 401 402 SOC_SINGLE("Zero Cross Switch", ADAU1373_PWDN_CTRL3, 7, 1, 0), 403 }; 404 405 static const struct snd_kcontrol_new adau1373_lineout2_controls[] = { 406 SOC_DOUBLE_R_TLV("Lineout2 Playback Volume", ADAU1373_LLINE_OUT(1), 407 ADAU1373_RLINE_OUT(1), 0, 0x1f, 0, adau1373_out_tlv), 408 SOC_ENUM("Lineout2 LR Mux", adau1373_lineout2_lr_mux_enum), 409 }; 410 411 static const struct snd_kcontrol_new adau1373_drc_controls[] = { 412 SOC_ENUM("DRC1 Channel", adau1373_drc1_channel_enum), 413 SOC_ENUM("DRC2 Channel", adau1373_drc2_channel_enum), 414 SOC_ENUM("DRC3 Channel", adau1373_drc3_channel_enum), 415 }; 416 417 static int adau1373_pll_event(struct snd_soc_dapm_widget *w, 418 struct snd_kcontrol *kcontrol, int event) 419 { 420 struct snd_soc_codec *codec = w->codec; 421 unsigned int pll_id = w->name[3] - '1'; 422 unsigned int val; 423 424 if (SND_SOC_DAPM_EVENT_ON(event)) 425 val = ADAU1373_PLL_CTRL6_PLL_EN; 426 else 427 val = 0; 428 429 snd_soc_update_bits(codec, ADAU1373_PLL_CTRL6(pll_id), 430 ADAU1373_PLL_CTRL6_PLL_EN, val); 431 432 if (SND_SOC_DAPM_EVENT_ON(event)) 433 mdelay(5); 434 435 return 0; 436 } 437 438 static const char *adau1373_decimator_text[] = { 439 "ADC", 440 "DMIC1", 441 }; 442 443 static const struct soc_enum adau1373_decimator_enum = 444 SOC_ENUM_SINGLE(0, 0, 2, adau1373_decimator_text); 445 446 static const struct snd_kcontrol_new adau1373_decimator_mux = 447 SOC_DAPM_ENUM_VIRT("Decimator Mux", adau1373_decimator_enum); 448 449 static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = { 450 SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0), 451 SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_LADC_MIXER, 3, 1, 0), 452 SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_LADC_MIXER, 2, 1, 0), 453 SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_LADC_MIXER, 1, 1, 0), 454 SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_LADC_MIXER, 0, 1, 0), 455 }; 456 457 static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls[] = { 458 SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_RADC_MIXER, 4, 1, 0), 459 SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_RADC_MIXER, 3, 1, 0), 460 SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_RADC_MIXER, 2, 1, 0), 461 SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_RADC_MIXER, 1, 1, 0), 462 SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_RADC_MIXER, 0, 1, 0), 463 }; 464 465 #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \ 466 const struct snd_kcontrol_new _name[] = { \ 467 SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \ 468 SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \ 469 SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \ 470 SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \ 471 SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \ 472 SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \ 473 SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \ 474 SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \ 475 } 476 477 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls, 478 ADAU1373_LLINE1_MIX); 479 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls, 480 ADAU1373_RLINE1_MIX); 481 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls, 482 ADAU1373_LLINE2_MIX); 483 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls, 484 ADAU1373_RLINE2_MIX); 485 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls, 486 ADAU1373_LSPK_MIX); 487 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls, 488 ADAU1373_RSPK_MIX); 489 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls, 490 ADAU1373_EP_MIX); 491 492 static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls[] = { 493 SOC_DAPM_SINGLE("Left DAC1 Switch", ADAU1373_LHP_MIX, 5, 1, 0), 494 SOC_DAPM_SINGLE("Left DAC2 Switch", ADAU1373_LHP_MIX, 4, 1, 0), 495 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0), 496 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0), 497 SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0), 498 SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0), 499 }; 500 501 static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls[] = { 502 SOC_DAPM_SINGLE("Right DAC1 Switch", ADAU1373_RHP_MIX, 5, 1, 0), 503 SOC_DAPM_SINGLE("Right DAC2 Switch", ADAU1373_RHP_MIX, 4, 1, 0), 504 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0), 505 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0), 506 SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_RHP_MIX, 1, 1, 0), 507 SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_RHP_MIX, 0, 1, 0), 508 }; 509 510 #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \ 511 const struct snd_kcontrol_new _name[] = { \ 512 SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \ 513 SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \ 514 SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \ 515 SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \ 516 SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \ 517 SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \ 518 SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \ 519 } 520 521 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls, 522 ADAU1373_DIN_MIX_CTRL(0)); 523 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls, 524 ADAU1373_DIN_MIX_CTRL(1)); 525 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls, 526 ADAU1373_DIN_MIX_CTRL(2)); 527 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls, 528 ADAU1373_DIN_MIX_CTRL(3)); 529 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls, 530 ADAU1373_DIN_MIX_CTRL(4)); 531 532 #define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \ 533 const struct snd_kcontrol_new _name[] = { \ 534 SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \ 535 SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \ 536 SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \ 537 SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \ 538 SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \ 539 } 540 541 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls, 542 ADAU1373_DOUT_MIX_CTRL(0)); 543 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls, 544 ADAU1373_DOUT_MIX_CTRL(1)); 545 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls, 546 ADAU1373_DOUT_MIX_CTRL(2)); 547 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls, 548 ADAU1373_DOUT_MIX_CTRL(3)); 549 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls, 550 ADAU1373_DOUT_MIX_CTRL(4)); 551 552 static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = { 553 /* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that 554 * doesn't seem to be the case. */ 555 SND_SOC_DAPM_ADC("Left ADC", NULL, ADAU1373_PWDN_CTRL1, 7, 0), 556 SND_SOC_DAPM_ADC("Right ADC", NULL, ADAU1373_PWDN_CTRL1, 6, 0), 557 558 SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0), 559 SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0), 560 561 SND_SOC_DAPM_VIRT_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0, 562 &adau1373_decimator_mux), 563 564 SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0), 565 SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1373_PWDN_CTRL1, 4, 0, NULL, 0), 566 567 SND_SOC_DAPM_PGA("IN4PGA", ADAU1373_PWDN_CTRL1, 3, 0, NULL, 0), 568 SND_SOC_DAPM_PGA("IN3PGA", ADAU1373_PWDN_CTRL1, 2, 0, NULL, 0), 569 SND_SOC_DAPM_PGA("IN2PGA", ADAU1373_PWDN_CTRL1, 1, 0, NULL, 0), 570 SND_SOC_DAPM_PGA("IN1PGA", ADAU1373_PWDN_CTRL1, 0, 0, NULL, 0), 571 572 SND_SOC_DAPM_DAC("Left DAC2", NULL, ADAU1373_PWDN_CTRL2, 7, 0), 573 SND_SOC_DAPM_DAC("Right DAC2", NULL, ADAU1373_PWDN_CTRL2, 6, 0), 574 SND_SOC_DAPM_DAC("Left DAC1", NULL, ADAU1373_PWDN_CTRL2, 5, 0), 575 SND_SOC_DAPM_DAC("Right DAC1", NULL, ADAU1373_PWDN_CTRL2, 4, 0), 576 577 SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 578 adau1373_left_adc_mixer_controls), 579 SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 580 adau1373_right_adc_mixer_controls), 581 582 SOC_MIXER_ARRAY("Left Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 3, 0, 583 adau1373_left_line2_mixer_controls), 584 SOC_MIXER_ARRAY("Right Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 2, 0, 585 adau1373_right_line2_mixer_controls), 586 SOC_MIXER_ARRAY("Left Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 1, 0, 587 adau1373_left_line1_mixer_controls), 588 SOC_MIXER_ARRAY("Right Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 0, 0, 589 adau1373_right_line1_mixer_controls), 590 591 SOC_MIXER_ARRAY("Earpiece Mixer", ADAU1373_PWDN_CTRL3, 4, 0, 592 adau1373_ep_mixer_controls), 593 SOC_MIXER_ARRAY("Left Speaker Mixer", ADAU1373_PWDN_CTRL3, 3, 0, 594 adau1373_left_spk_mixer_controls), 595 SOC_MIXER_ARRAY("Right Speaker Mixer", ADAU1373_PWDN_CTRL3, 2, 0, 596 adau1373_right_spk_mixer_controls), 597 SOC_MIXER_ARRAY("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 598 adau1373_left_hp_mixer_controls), 599 SOC_MIXER_ARRAY("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 600 adau1373_right_hp_mixer_controls), 601 SND_SOC_DAPM_SUPPLY("Headphone Enable", ADAU1373_PWDN_CTRL3, 1, 0, 602 NULL, 0), 603 604 SND_SOC_DAPM_SUPPLY("AIF1 CLK", ADAU1373_SRC_DAI_CTRL(0), 0, 0, 605 NULL, 0), 606 SND_SOC_DAPM_SUPPLY("AIF2 CLK", ADAU1373_SRC_DAI_CTRL(1), 0, 0, 607 NULL, 0), 608 SND_SOC_DAPM_SUPPLY("AIF3 CLK", ADAU1373_SRC_DAI_CTRL(2), 0, 0, 609 NULL, 0), 610 SND_SOC_DAPM_SUPPLY("AIF1 IN SRC", ADAU1373_SRC_DAI_CTRL(0), 2, 0, 611 NULL, 0), 612 SND_SOC_DAPM_SUPPLY("AIF1 OUT SRC", ADAU1373_SRC_DAI_CTRL(0), 1, 0, 613 NULL, 0), 614 SND_SOC_DAPM_SUPPLY("AIF2 IN SRC", ADAU1373_SRC_DAI_CTRL(1), 2, 0, 615 NULL, 0), 616 SND_SOC_DAPM_SUPPLY("AIF2 OUT SRC", ADAU1373_SRC_DAI_CTRL(1), 1, 0, 617 NULL, 0), 618 SND_SOC_DAPM_SUPPLY("AIF3 IN SRC", ADAU1373_SRC_DAI_CTRL(2), 2, 0, 619 NULL, 0), 620 SND_SOC_DAPM_SUPPLY("AIF3 OUT SRC", ADAU1373_SRC_DAI_CTRL(2), 1, 0, 621 NULL, 0), 622 623 SND_SOC_DAPM_AIF_IN("AIF1 IN", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 624 SND_SOC_DAPM_AIF_OUT("AIF1 OUT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 625 SND_SOC_DAPM_AIF_IN("AIF2 IN", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 626 SND_SOC_DAPM_AIF_OUT("AIF2 OUT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 627 SND_SOC_DAPM_AIF_IN("AIF3 IN", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 628 SND_SOC_DAPM_AIF_OUT("AIF3 OUT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 629 630 SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM, 0, 0, 631 adau1373_dsp_channel1_mixer_controls), 632 SOC_MIXER_ARRAY("DSP Channel2 Mixer", SND_SOC_NOPM, 0, 0, 633 adau1373_dsp_channel2_mixer_controls), 634 SOC_MIXER_ARRAY("DSP Channel3 Mixer", SND_SOC_NOPM, 0, 0, 635 adau1373_dsp_channel3_mixer_controls), 636 SOC_MIXER_ARRAY("DSP Channel4 Mixer", SND_SOC_NOPM, 0, 0, 637 adau1373_dsp_channel4_mixer_controls), 638 SOC_MIXER_ARRAY("DSP Channel5 Mixer", SND_SOC_NOPM, 0, 0, 639 adau1373_dsp_channel5_mixer_controls), 640 641 SOC_MIXER_ARRAY("AIF1 Mixer", SND_SOC_NOPM, 0, 0, 642 adau1373_aif1_mixer_controls), 643 SOC_MIXER_ARRAY("AIF2 Mixer", SND_SOC_NOPM, 0, 0, 644 adau1373_aif2_mixer_controls), 645 SOC_MIXER_ARRAY("AIF3 Mixer", SND_SOC_NOPM, 0, 0, 646 adau1373_aif3_mixer_controls), 647 SOC_MIXER_ARRAY("DAC1 Mixer", SND_SOC_NOPM, 0, 0, 648 adau1373_dac1_mixer_controls), 649 SOC_MIXER_ARRAY("DAC2 Mixer", SND_SOC_NOPM, 0, 0, 650 adau1373_dac2_mixer_controls), 651 652 SND_SOC_DAPM_SUPPLY("DSP", ADAU1373_DIGEN, 4, 0, NULL, 0), 653 SND_SOC_DAPM_SUPPLY("Recording Engine B", ADAU1373_DIGEN, 3, 0, NULL, 0), 654 SND_SOC_DAPM_SUPPLY("Recording Engine A", ADAU1373_DIGEN, 2, 0, NULL, 0), 655 SND_SOC_DAPM_SUPPLY("Playback Engine B", ADAU1373_DIGEN, 1, 0, NULL, 0), 656 SND_SOC_DAPM_SUPPLY("Playback Engine A", ADAU1373_DIGEN, 0, 0, NULL, 0), 657 658 SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM, 0, 0, adau1373_pll_event, 659 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 660 SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM, 0, 0, adau1373_pll_event, 661 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 662 SND_SOC_DAPM_SUPPLY("SYSCLK1", ADAU1373_CLK_SRC_DIV(0), 7, 0, NULL, 0), 663 SND_SOC_DAPM_SUPPLY("SYSCLK2", ADAU1373_CLK_SRC_DIV(1), 7, 0, NULL, 0), 664 665 SND_SOC_DAPM_INPUT("AIN1L"), 666 SND_SOC_DAPM_INPUT("AIN1R"), 667 SND_SOC_DAPM_INPUT("AIN2L"), 668 SND_SOC_DAPM_INPUT("AIN2R"), 669 SND_SOC_DAPM_INPUT("AIN3L"), 670 SND_SOC_DAPM_INPUT("AIN3R"), 671 SND_SOC_DAPM_INPUT("AIN4L"), 672 SND_SOC_DAPM_INPUT("AIN4R"), 673 674 SND_SOC_DAPM_INPUT("DMIC1DAT"), 675 SND_SOC_DAPM_INPUT("DMIC2DAT"), 676 677 SND_SOC_DAPM_OUTPUT("LOUT1L"), 678 SND_SOC_DAPM_OUTPUT("LOUT1R"), 679 SND_SOC_DAPM_OUTPUT("LOUT2L"), 680 SND_SOC_DAPM_OUTPUT("LOUT2R"), 681 SND_SOC_DAPM_OUTPUT("HPL"), 682 SND_SOC_DAPM_OUTPUT("HPR"), 683 SND_SOC_DAPM_OUTPUT("SPKL"), 684 SND_SOC_DAPM_OUTPUT("SPKR"), 685 SND_SOC_DAPM_OUTPUT("EP"), 686 }; 687 688 static int adau1373_check_aif_clk(struct snd_soc_dapm_widget *source, 689 struct snd_soc_dapm_widget *sink) 690 { 691 struct snd_soc_codec *codec = source->codec; 692 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 693 unsigned int dai; 694 const char *clk; 695 696 dai = sink->name[3] - '1'; 697 698 if (!adau1373->dais[dai].master) 699 return 0; 700 701 if (adau1373->dais[dai].clk_src == ADAU1373_CLK_SRC_PLL1) 702 clk = "SYSCLK1"; 703 else 704 clk = "SYSCLK2"; 705 706 return strcmp(source->name, clk) == 0; 707 } 708 709 static int adau1373_check_src(struct snd_soc_dapm_widget *source, 710 struct snd_soc_dapm_widget *sink) 711 { 712 struct snd_soc_codec *codec = source->codec; 713 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 714 unsigned int dai; 715 716 dai = sink->name[3] - '1'; 717 718 return adau1373->dais[dai].enable_src; 719 } 720 721 #define DSP_CHANNEL_MIXER_ROUTES(_sink) \ 722 { _sink, "DMIC2 Swapped Switch", "DMIC2" }, \ 723 { _sink, "DMIC2 Switch", "DMIC2" }, \ 724 { _sink, "ADC/DMIC1 Swapped Switch", "Decimator Mux" }, \ 725 { _sink, "ADC/DMIC1 Switch", "Decimator Mux" }, \ 726 { _sink, "AIF1 Switch", "AIF1 IN" }, \ 727 { _sink, "AIF2 Switch", "AIF2 IN" }, \ 728 { _sink, "AIF3 Switch", "AIF3 IN" } 729 730 #define DSP_OUTPUT_MIXER_ROUTES(_sink) \ 731 { _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \ 732 { _sink, "DSP Channel2 Switch", "DSP Channel2 Mixer" }, \ 733 { _sink, "DSP Channel3 Switch", "DSP Channel3 Mixer" }, \ 734 { _sink, "DSP Channel4 Switch", "DSP Channel4 Mixer" }, \ 735 { _sink, "DSP Channel5 Switch", "DSP Channel5 Mixer" } 736 737 #define LEFT_OUTPUT_MIXER_ROUTES(_sink) \ 738 { _sink, "Right DAC2 Switch", "Right DAC2" }, \ 739 { _sink, "Left DAC2 Switch", "Left DAC2" }, \ 740 { _sink, "Right DAC1 Switch", "Right DAC1" }, \ 741 { _sink, "Left DAC1 Switch", "Left DAC1" }, \ 742 { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \ 743 { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \ 744 { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \ 745 { _sink, "Input 4 Bypass Switch", "IN4PGA" } 746 747 #define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \ 748 { _sink, "Right DAC2 Switch", "Right DAC2" }, \ 749 { _sink, "Left DAC2 Switch", "Left DAC2" }, \ 750 { _sink, "Right DAC1 Switch", "Right DAC1" }, \ 751 { _sink, "Left DAC1 Switch", "Left DAC1" }, \ 752 { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \ 753 { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \ 754 { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \ 755 { _sink, "Input 4 Bypass Switch", "IN4PGA" } 756 757 static const struct snd_soc_dapm_route adau1373_dapm_routes[] = { 758 { "Left ADC Mixer", "DAC1 Switch", "Left DAC1" }, 759 { "Left ADC Mixer", "Input 1 Switch", "IN1PGA" }, 760 { "Left ADC Mixer", "Input 2 Switch", "IN2PGA" }, 761 { "Left ADC Mixer", "Input 3 Switch", "IN3PGA" }, 762 { "Left ADC Mixer", "Input 4 Switch", "IN4PGA" }, 763 764 { "Right ADC Mixer", "DAC1 Switch", "Right DAC1" }, 765 { "Right ADC Mixer", "Input 1 Switch", "IN1PGA" }, 766 { "Right ADC Mixer", "Input 2 Switch", "IN2PGA" }, 767 { "Right ADC Mixer", "Input 3 Switch", "IN3PGA" }, 768 { "Right ADC Mixer", "Input 4 Switch", "IN4PGA" }, 769 770 { "Left ADC", NULL, "Left ADC Mixer" }, 771 { "Right ADC", NULL, "Right ADC Mixer" }, 772 773 { "Decimator Mux", "ADC", "Left ADC" }, 774 { "Decimator Mux", "ADC", "Right ADC" }, 775 { "Decimator Mux", "DMIC1", "DMIC1" }, 776 777 DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"), 778 DSP_CHANNEL_MIXER_ROUTES("DSP Channel2 Mixer"), 779 DSP_CHANNEL_MIXER_ROUTES("DSP Channel3 Mixer"), 780 DSP_CHANNEL_MIXER_ROUTES("DSP Channel4 Mixer"), 781 DSP_CHANNEL_MIXER_ROUTES("DSP Channel5 Mixer"), 782 783 DSP_OUTPUT_MIXER_ROUTES("AIF1 Mixer"), 784 DSP_OUTPUT_MIXER_ROUTES("AIF2 Mixer"), 785 DSP_OUTPUT_MIXER_ROUTES("AIF3 Mixer"), 786 DSP_OUTPUT_MIXER_ROUTES("DAC1 Mixer"), 787 DSP_OUTPUT_MIXER_ROUTES("DAC2 Mixer"), 788 789 { "AIF1 OUT", NULL, "AIF1 Mixer" }, 790 { "AIF2 OUT", NULL, "AIF2 Mixer" }, 791 { "AIF3 OUT", NULL, "AIF3 Mixer" }, 792 { "Left DAC1", NULL, "DAC1 Mixer" }, 793 { "Right DAC1", NULL, "DAC1 Mixer" }, 794 { "Left DAC2", NULL, "DAC2 Mixer" }, 795 { "Right DAC2", NULL, "DAC2 Mixer" }, 796 797 LEFT_OUTPUT_MIXER_ROUTES("Left Lineout1 Mixer"), 798 RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout1 Mixer"), 799 LEFT_OUTPUT_MIXER_ROUTES("Left Lineout2 Mixer"), 800 RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout2 Mixer"), 801 LEFT_OUTPUT_MIXER_ROUTES("Left Speaker Mixer"), 802 RIGHT_OUTPUT_MIXER_ROUTES("Right Speaker Mixer"), 803 804 { "Left Headphone Mixer", "Left DAC2 Switch", "Left DAC2" }, 805 { "Left Headphone Mixer", "Left DAC1 Switch", "Left DAC1" }, 806 { "Left Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" }, 807 { "Left Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" }, 808 { "Left Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" }, 809 { "Left Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" }, 810 { "Right Headphone Mixer", "Right DAC2 Switch", "Right DAC2" }, 811 { "Right Headphone Mixer", "Right DAC1 Switch", "Right DAC1" }, 812 { "Right Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" }, 813 { "Right Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" }, 814 { "Right Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" }, 815 { "Right Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" }, 816 817 { "Left Headphone Mixer", NULL, "Headphone Enable" }, 818 { "Right Headphone Mixer", NULL, "Headphone Enable" }, 819 820 { "Earpiece Mixer", "Right DAC2 Switch", "Right DAC2" }, 821 { "Earpiece Mixer", "Left DAC2 Switch", "Left DAC2" }, 822 { "Earpiece Mixer", "Right DAC1 Switch", "Right DAC1" }, 823 { "Earpiece Mixer", "Left DAC1 Switch", "Left DAC1" }, 824 { "Earpiece Mixer", "Input 1 Bypass Switch", "IN1PGA" }, 825 { "Earpiece Mixer", "Input 2 Bypass Switch", "IN2PGA" }, 826 { "Earpiece Mixer", "Input 3 Bypass Switch", "IN3PGA" }, 827 { "Earpiece Mixer", "Input 4 Bypass Switch", "IN4PGA" }, 828 829 { "LOUT1L", NULL, "Left Lineout1 Mixer" }, 830 { "LOUT1R", NULL, "Right Lineout1 Mixer" }, 831 { "LOUT2L", NULL, "Left Lineout2 Mixer" }, 832 { "LOUT2R", NULL, "Right Lineout2 Mixer" }, 833 { "SPKL", NULL, "Left Speaker Mixer" }, 834 { "SPKR", NULL, "Right Speaker Mixer" }, 835 { "HPL", NULL, "Left Headphone Mixer" }, 836 { "HPR", NULL, "Right Headphone Mixer" }, 837 { "EP", NULL, "Earpiece Mixer" }, 838 839 { "IN1PGA", NULL, "AIN1L" }, 840 { "IN2PGA", NULL, "AIN2L" }, 841 { "IN3PGA", NULL, "AIN3L" }, 842 { "IN4PGA", NULL, "AIN4L" }, 843 { "IN1PGA", NULL, "AIN1R" }, 844 { "IN2PGA", NULL, "AIN2R" }, 845 { "IN3PGA", NULL, "AIN3R" }, 846 { "IN4PGA", NULL, "AIN4R" }, 847 848 { "SYSCLK1", NULL, "PLL1" }, 849 { "SYSCLK2", NULL, "PLL2" }, 850 851 { "Left DAC1", NULL, "SYSCLK1" }, 852 { "Right DAC1", NULL, "SYSCLK1" }, 853 { "Left DAC2", NULL, "SYSCLK1" }, 854 { "Right DAC2", NULL, "SYSCLK1" }, 855 { "Left ADC", NULL, "SYSCLK1" }, 856 { "Right ADC", NULL, "SYSCLK1" }, 857 858 { "DSP", NULL, "SYSCLK1" }, 859 860 { "AIF1 Mixer", NULL, "DSP" }, 861 { "AIF2 Mixer", NULL, "DSP" }, 862 { "AIF3 Mixer", NULL, "DSP" }, 863 { "DAC1 Mixer", NULL, "DSP" }, 864 { "DAC2 Mixer", NULL, "DSP" }, 865 { "DAC1 Mixer", NULL, "Playback Engine A" }, 866 { "DAC2 Mixer", NULL, "Playback Engine B" }, 867 { "Left ADC Mixer", NULL, "Recording Engine A" }, 868 { "Right ADC Mixer", NULL, "Recording Engine A" }, 869 870 { "AIF1 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk }, 871 { "AIF2 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk }, 872 { "AIF3 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk }, 873 { "AIF1 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk }, 874 { "AIF2 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk }, 875 { "AIF3 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk }, 876 877 { "AIF1 IN", NULL, "AIF1 CLK" }, 878 { "AIF1 OUT", NULL, "AIF1 CLK" }, 879 { "AIF2 IN", NULL, "AIF2 CLK" }, 880 { "AIF2 OUT", NULL, "AIF2 CLK" }, 881 { "AIF3 IN", NULL, "AIF3 CLK" }, 882 { "AIF3 OUT", NULL, "AIF3 CLK" }, 883 { "AIF1 IN", NULL, "AIF1 IN SRC", adau1373_check_src }, 884 { "AIF1 OUT", NULL, "AIF1 OUT SRC", adau1373_check_src }, 885 { "AIF2 IN", NULL, "AIF2 IN SRC", adau1373_check_src }, 886 { "AIF2 OUT", NULL, "AIF2 OUT SRC", adau1373_check_src }, 887 { "AIF3 IN", NULL, "AIF3 IN SRC", adau1373_check_src }, 888 { "AIF3 OUT", NULL, "AIF3 OUT SRC", adau1373_check_src }, 889 890 { "DMIC1", NULL, "DMIC1DAT" }, 891 { "DMIC1", NULL, "SYSCLK1" }, 892 { "DMIC1", NULL, "Recording Engine A" }, 893 { "DMIC2", NULL, "DMIC2DAT" }, 894 { "DMIC2", NULL, "SYSCLK1" }, 895 { "DMIC2", NULL, "Recording Engine B" }, 896 }; 897 898 static int adau1373_hw_params(struct snd_pcm_substream *substream, 899 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 900 { 901 struct snd_soc_codec *codec = dai->codec; 902 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 903 struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id]; 904 unsigned int div; 905 unsigned int freq; 906 unsigned int ctrl; 907 908 freq = adau1373_dai->sysclk; 909 910 if (freq % params_rate(params) != 0) 911 return -EINVAL; 912 913 switch (freq / params_rate(params)) { 914 case 1024: /* sysclk / 256 */ 915 div = 0; 916 break; 917 case 1536: /* 2/3 sysclk / 256 */ 918 div = 1; 919 break; 920 case 2048: /* 1/2 sysclk / 256 */ 921 div = 2; 922 break; 923 case 3072: /* 1/3 sysclk / 256 */ 924 div = 3; 925 break; 926 case 4096: /* 1/4 sysclk / 256 */ 927 div = 4; 928 break; 929 case 6144: /* 1/6 sysclk / 256 */ 930 div = 5; 931 break; 932 case 5632: /* 2/11 sysclk / 256 */ 933 div = 6; 934 break; 935 default: 936 return -EINVAL; 937 } 938 939 adau1373_dai->enable_src = (div != 0); 940 941 snd_soc_update_bits(codec, ADAU1373_BCLKDIV(dai->id), 942 ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK, 943 (div << 2) | ADAU1373_BCLKDIV_64); 944 945 switch (params_format(params)) { 946 case SNDRV_PCM_FORMAT_S16_LE: 947 ctrl = ADAU1373_DAI_WLEN_16; 948 break; 949 case SNDRV_PCM_FORMAT_S20_3LE: 950 ctrl = ADAU1373_DAI_WLEN_20; 951 break; 952 case SNDRV_PCM_FORMAT_S24_LE: 953 ctrl = ADAU1373_DAI_WLEN_24; 954 break; 955 case SNDRV_PCM_FORMAT_S32_LE: 956 ctrl = ADAU1373_DAI_WLEN_32; 957 break; 958 default: 959 return -EINVAL; 960 } 961 962 return snd_soc_update_bits(codec, ADAU1373_DAI(dai->id), 963 ADAU1373_DAI_WLEN_MASK, ctrl); 964 } 965 966 static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 967 { 968 struct snd_soc_codec *codec = dai->codec; 969 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 970 struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id]; 971 unsigned int ctrl; 972 973 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 974 case SND_SOC_DAIFMT_CBM_CFM: 975 ctrl = ADAU1373_DAI_MASTER; 976 adau1373_dai->master = true; 977 break; 978 case SND_SOC_DAIFMT_CBS_CFS: 979 ctrl = 0; 980 adau1373_dai->master = false; 981 break; 982 default: 983 return -EINVAL; 984 } 985 986 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 987 case SND_SOC_DAIFMT_I2S: 988 ctrl |= ADAU1373_DAI_FORMAT_I2S; 989 break; 990 case SND_SOC_DAIFMT_LEFT_J: 991 ctrl |= ADAU1373_DAI_FORMAT_LEFT_J; 992 break; 993 case SND_SOC_DAIFMT_RIGHT_J: 994 ctrl |= ADAU1373_DAI_FORMAT_RIGHT_J; 995 break; 996 case SND_SOC_DAIFMT_DSP_B: 997 ctrl |= ADAU1373_DAI_FORMAT_DSP; 998 break; 999 default: 1000 return -EINVAL; 1001 } 1002 1003 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1004 case SND_SOC_DAIFMT_NB_NF: 1005 break; 1006 case SND_SOC_DAIFMT_IB_NF: 1007 ctrl |= ADAU1373_DAI_INVERT_BCLK; 1008 break; 1009 case SND_SOC_DAIFMT_NB_IF: 1010 ctrl |= ADAU1373_DAI_INVERT_LRCLK; 1011 break; 1012 case SND_SOC_DAIFMT_IB_IF: 1013 ctrl |= ADAU1373_DAI_INVERT_LRCLK | ADAU1373_DAI_INVERT_BCLK; 1014 break; 1015 default: 1016 return -EINVAL; 1017 } 1018 1019 snd_soc_update_bits(codec, ADAU1373_DAI(dai->id), 1020 ~ADAU1373_DAI_WLEN_MASK, ctrl); 1021 1022 return 0; 1023 } 1024 1025 static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai, 1026 int clk_id, unsigned int freq, int dir) 1027 { 1028 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(dai->codec); 1029 struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id]; 1030 1031 switch (clk_id) { 1032 case ADAU1373_CLK_SRC_PLL1: 1033 case ADAU1373_CLK_SRC_PLL2: 1034 break; 1035 default: 1036 return -EINVAL; 1037 } 1038 1039 adau1373_dai->sysclk = freq; 1040 adau1373_dai->clk_src = clk_id; 1041 1042 snd_soc_update_bits(dai->codec, ADAU1373_BCLKDIV(dai->id), 1043 ADAU1373_BCLKDIV_SOURCE, clk_id << 5); 1044 1045 return 0; 1046 } 1047 1048 static const struct snd_soc_dai_ops adau1373_dai_ops = { 1049 .hw_params = adau1373_hw_params, 1050 .set_sysclk = adau1373_set_dai_sysclk, 1051 .set_fmt = adau1373_set_dai_fmt, 1052 }; 1053 1054 #define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1055 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1056 1057 static struct snd_soc_dai_driver adau1373_dai_driver[] = { 1058 { 1059 .id = 0, 1060 .name = "adau1373-aif1", 1061 .playback = { 1062 .stream_name = "AIF1 Playback", 1063 .channels_min = 2, 1064 .channels_max = 2, 1065 .rates = SNDRV_PCM_RATE_8000_48000, 1066 .formats = ADAU1373_FORMATS, 1067 }, 1068 .capture = { 1069 .stream_name = "AIF1 Capture", 1070 .channels_min = 2, 1071 .channels_max = 2, 1072 .rates = SNDRV_PCM_RATE_8000_48000, 1073 .formats = ADAU1373_FORMATS, 1074 }, 1075 .ops = &adau1373_dai_ops, 1076 .symmetric_rates = 1, 1077 }, 1078 { 1079 .id = 1, 1080 .name = "adau1373-aif2", 1081 .playback = { 1082 .stream_name = "AIF2 Playback", 1083 .channels_min = 2, 1084 .channels_max = 2, 1085 .rates = SNDRV_PCM_RATE_8000_48000, 1086 .formats = ADAU1373_FORMATS, 1087 }, 1088 .capture = { 1089 .stream_name = "AIF2 Capture", 1090 .channels_min = 2, 1091 .channels_max = 2, 1092 .rates = SNDRV_PCM_RATE_8000_48000, 1093 .formats = ADAU1373_FORMATS, 1094 }, 1095 .ops = &adau1373_dai_ops, 1096 .symmetric_rates = 1, 1097 }, 1098 { 1099 .id = 2, 1100 .name = "adau1373-aif3", 1101 .playback = { 1102 .stream_name = "AIF3 Playback", 1103 .channels_min = 2, 1104 .channels_max = 2, 1105 .rates = SNDRV_PCM_RATE_8000_48000, 1106 .formats = ADAU1373_FORMATS, 1107 }, 1108 .capture = { 1109 .stream_name = "AIF3 Capture", 1110 .channels_min = 2, 1111 .channels_max = 2, 1112 .rates = SNDRV_PCM_RATE_8000_48000, 1113 .formats = ADAU1373_FORMATS, 1114 }, 1115 .ops = &adau1373_dai_ops, 1116 .symmetric_rates = 1, 1117 }, 1118 }; 1119 1120 static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id, 1121 int source, unsigned int freq_in, unsigned int freq_out) 1122 { 1123 unsigned int dpll_div = 0; 1124 unsigned int x, r, n, m, i, j, mode; 1125 1126 switch (pll_id) { 1127 case ADAU1373_PLL1: 1128 case ADAU1373_PLL2: 1129 break; 1130 default: 1131 return -EINVAL; 1132 } 1133 1134 switch (source) { 1135 case ADAU1373_PLL_SRC_BCLK1: 1136 case ADAU1373_PLL_SRC_BCLK2: 1137 case ADAU1373_PLL_SRC_BCLK3: 1138 case ADAU1373_PLL_SRC_LRCLK1: 1139 case ADAU1373_PLL_SRC_LRCLK2: 1140 case ADAU1373_PLL_SRC_LRCLK3: 1141 case ADAU1373_PLL_SRC_MCLK1: 1142 case ADAU1373_PLL_SRC_MCLK2: 1143 case ADAU1373_PLL_SRC_GPIO1: 1144 case ADAU1373_PLL_SRC_GPIO2: 1145 case ADAU1373_PLL_SRC_GPIO3: 1146 case ADAU1373_PLL_SRC_GPIO4: 1147 break; 1148 default: 1149 return -EINVAL; 1150 } 1151 1152 if (freq_in < 7813 || freq_in > 27000000) 1153 return -EINVAL; 1154 1155 if (freq_out < 45158000 || freq_out > 49152000) 1156 return -EINVAL; 1157 1158 /* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the 1159 * DPLL to get it there. DPLL_out = (DPLL_in / div) * 1024 */ 1160 while (freq_in < 8000000) { 1161 freq_in *= 2; 1162 dpll_div++; 1163 } 1164 1165 if (freq_out % freq_in != 0) { 1166 /* fout = fin * (r + (n/m)) / x */ 1167 x = DIV_ROUND_UP(freq_in, 13500000); 1168 freq_in /= x; 1169 r = freq_out / freq_in; 1170 i = freq_out % freq_in; 1171 j = gcd(i, freq_in); 1172 n = i / j; 1173 m = freq_in / j; 1174 x--; 1175 mode = 1; 1176 } else { 1177 /* fout = fin / r */ 1178 r = freq_out / freq_in; 1179 n = 0; 1180 m = 0; 1181 x = 0; 1182 mode = 0; 1183 } 1184 1185 if (r < 2 || r > 8 || x > 3 || m > 0xffff || n > 0xffff) 1186 return -EINVAL; 1187 1188 if (dpll_div) { 1189 dpll_div = 11 - dpll_div; 1190 snd_soc_update_bits(codec, ADAU1373_PLL_CTRL6(pll_id), 1191 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0); 1192 } else { 1193 snd_soc_update_bits(codec, ADAU1373_PLL_CTRL6(pll_id), 1194 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 1195 ADAU1373_PLL_CTRL6_DPLL_BYPASS); 1196 } 1197 1198 snd_soc_write(codec, ADAU1373_DPLL_CTRL(pll_id), 1199 (source << 4) | dpll_div); 1200 snd_soc_write(codec, ADAU1373_PLL_CTRL1(pll_id), (m >> 8) & 0xff); 1201 snd_soc_write(codec, ADAU1373_PLL_CTRL2(pll_id), m & 0xff); 1202 snd_soc_write(codec, ADAU1373_PLL_CTRL3(pll_id), (n >> 8) & 0xff); 1203 snd_soc_write(codec, ADAU1373_PLL_CTRL4(pll_id), n & 0xff); 1204 snd_soc_write(codec, ADAU1373_PLL_CTRL5(pll_id), 1205 (r << 3) | (x << 1) | mode); 1206 1207 /* Set sysclk to pll_rate / 4 */ 1208 snd_soc_update_bits(codec, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09); 1209 1210 return 0; 1211 } 1212 1213 static void adau1373_load_drc_settings(struct snd_soc_codec *codec, 1214 unsigned int nr, uint8_t *drc) 1215 { 1216 unsigned int i; 1217 1218 for (i = 0; i < ADAU1373_DRC_SIZE; ++i) 1219 snd_soc_write(codec, ADAU1373_DRC(nr) + i, drc[i]); 1220 } 1221 1222 static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias) 1223 { 1224 switch (micbias) { 1225 case ADAU1373_MICBIAS_2_9V: 1226 case ADAU1373_MICBIAS_2_2V: 1227 case ADAU1373_MICBIAS_2_6V: 1228 case ADAU1373_MICBIAS_1_8V: 1229 return true; 1230 default: 1231 break; 1232 } 1233 return false; 1234 } 1235 1236 static int adau1373_probe(struct snd_soc_codec *codec) 1237 { 1238 struct adau1373_platform_data *pdata = codec->dev->platform_data; 1239 bool lineout_differential = false; 1240 unsigned int val; 1241 int ret; 1242 int i; 1243 1244 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 1245 if (ret) { 1246 dev_err(codec->dev, "failed to set cache I/O: %d\n", ret); 1247 return ret; 1248 } 1249 1250 if (pdata) { 1251 if (pdata->num_drc > ARRAY_SIZE(pdata->drc_setting)) 1252 return -EINVAL; 1253 1254 if (!adau1373_valid_micbias(pdata->micbias1) || 1255 !adau1373_valid_micbias(pdata->micbias2)) 1256 return -EINVAL; 1257 1258 for (i = 0; i < pdata->num_drc; ++i) { 1259 adau1373_load_drc_settings(codec, i, 1260 pdata->drc_setting[i]); 1261 } 1262 1263 snd_soc_add_codec_controls(codec, adau1373_drc_controls, 1264 pdata->num_drc); 1265 1266 val = 0; 1267 for (i = 0; i < 4; ++i) { 1268 if (pdata->input_differential[i]) 1269 val |= BIT(i); 1270 } 1271 snd_soc_write(codec, ADAU1373_INPUT_MODE, val); 1272 1273 val = 0; 1274 if (pdata->lineout_differential) 1275 val |= ADAU1373_OUTPUT_CTRL_LDIFF; 1276 if (pdata->lineout_ground_sense) 1277 val |= ADAU1373_OUTPUT_CTRL_LNFBEN; 1278 snd_soc_write(codec, ADAU1373_OUTPUT_CTRL, val); 1279 1280 lineout_differential = pdata->lineout_differential; 1281 1282 snd_soc_write(codec, ADAU1373_EP_CTRL, 1283 (pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) | 1284 (pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET)); 1285 } 1286 1287 if (!lineout_differential) { 1288 snd_soc_add_codec_controls(codec, adau1373_lineout2_controls, 1289 ARRAY_SIZE(adau1373_lineout2_controls)); 1290 } 1291 1292 snd_soc_write(codec, ADAU1373_ADC_CTRL, 1293 ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT); 1294 1295 return 0; 1296 } 1297 1298 static int adau1373_set_bias_level(struct snd_soc_codec *codec, 1299 enum snd_soc_bias_level level) 1300 { 1301 switch (level) { 1302 case SND_SOC_BIAS_ON: 1303 break; 1304 case SND_SOC_BIAS_PREPARE: 1305 break; 1306 case SND_SOC_BIAS_STANDBY: 1307 snd_soc_update_bits(codec, ADAU1373_PWDN_CTRL3, 1308 ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN); 1309 break; 1310 case SND_SOC_BIAS_OFF: 1311 snd_soc_update_bits(codec, ADAU1373_PWDN_CTRL3, 1312 ADAU1373_PWDN_CTRL3_PWR_EN, 0); 1313 break; 1314 } 1315 codec->dapm.bias_level = level; 1316 return 0; 1317 } 1318 1319 static int adau1373_remove(struct snd_soc_codec *codec) 1320 { 1321 adau1373_set_bias_level(codec, SND_SOC_BIAS_OFF); 1322 return 0; 1323 } 1324 1325 static int adau1373_suspend(struct snd_soc_codec *codec) 1326 { 1327 return adau1373_set_bias_level(codec, SND_SOC_BIAS_OFF); 1328 } 1329 1330 static int adau1373_resume(struct snd_soc_codec *codec) 1331 { 1332 adau1373_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1333 snd_soc_cache_sync(codec); 1334 1335 return 0; 1336 } 1337 1338 static struct snd_soc_codec_driver adau1373_codec_driver = { 1339 .probe = adau1373_probe, 1340 .remove = adau1373_remove, 1341 .suspend = adau1373_suspend, 1342 .resume = adau1373_resume, 1343 .set_bias_level = adau1373_set_bias_level, 1344 .idle_bias_off = true, 1345 .reg_cache_size = ARRAY_SIZE(adau1373_default_regs), 1346 .reg_cache_default = adau1373_default_regs, 1347 .reg_word_size = sizeof(uint8_t), 1348 1349 .set_pll = adau1373_set_pll, 1350 1351 .controls = adau1373_controls, 1352 .num_controls = ARRAY_SIZE(adau1373_controls), 1353 .dapm_widgets = adau1373_dapm_widgets, 1354 .num_dapm_widgets = ARRAY_SIZE(adau1373_dapm_widgets), 1355 .dapm_routes = adau1373_dapm_routes, 1356 .num_dapm_routes = ARRAY_SIZE(adau1373_dapm_routes), 1357 }; 1358 1359 static int adau1373_i2c_probe(struct i2c_client *client, 1360 const struct i2c_device_id *id) 1361 { 1362 struct adau1373 *adau1373; 1363 int ret; 1364 1365 adau1373 = devm_kzalloc(&client->dev, sizeof(*adau1373), GFP_KERNEL); 1366 if (!adau1373) 1367 return -ENOMEM; 1368 1369 dev_set_drvdata(&client->dev, adau1373); 1370 1371 ret = snd_soc_register_codec(&client->dev, &adau1373_codec_driver, 1372 adau1373_dai_driver, ARRAY_SIZE(adau1373_dai_driver)); 1373 return ret; 1374 } 1375 1376 static int adau1373_i2c_remove(struct i2c_client *client) 1377 { 1378 snd_soc_unregister_codec(&client->dev); 1379 return 0; 1380 } 1381 1382 static const struct i2c_device_id adau1373_i2c_id[] = { 1383 { "adau1373", 0 }, 1384 { } 1385 }; 1386 MODULE_DEVICE_TABLE(i2c, adau1373_i2c_id); 1387 1388 static struct i2c_driver adau1373_i2c_driver = { 1389 .driver = { 1390 .name = "adau1373", 1391 .owner = THIS_MODULE, 1392 }, 1393 .probe = adau1373_i2c_probe, 1394 .remove = adau1373_i2c_remove, 1395 .id_table = adau1373_i2c_id, 1396 }; 1397 1398 module_i2c_driver(adau1373_i2c_driver); 1399 1400 MODULE_DESCRIPTION("ASoC ADAU1373 driver"); 1401 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1402 MODULE_LICENSE("GPL"); 1403