1 /* 2 * Analog Devices ADAU1373 Audio Codec drive 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * Author: Lars-Peter Clausen <lars@metafoo.de> 6 * 7 * Licensed under the GPL-2 or later. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/slab.h> 16 #include <linux/gcd.h> 17 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/tlv.h> 22 #include <sound/soc.h> 23 #include <sound/adau1373.h> 24 25 #include "adau1373.h" 26 27 struct adau1373_dai { 28 unsigned int clk_src; 29 unsigned int sysclk; 30 bool enable_src; 31 bool master; 32 }; 33 34 struct adau1373 { 35 struct regmap *regmap; 36 struct adau1373_dai dais[3]; 37 }; 38 39 #define ADAU1373_INPUT_MODE 0x00 40 #define ADAU1373_AINL_CTRL(x) (0x01 + (x) * 2) 41 #define ADAU1373_AINR_CTRL(x) (0x02 + (x) * 2) 42 #define ADAU1373_LLINE_OUT(x) (0x9 + (x) * 2) 43 #define ADAU1373_RLINE_OUT(x) (0xa + (x) * 2) 44 #define ADAU1373_LSPK_OUT 0x0d 45 #define ADAU1373_RSPK_OUT 0x0e 46 #define ADAU1373_LHP_OUT 0x0f 47 #define ADAU1373_RHP_OUT 0x10 48 #define ADAU1373_ADC_GAIN 0x11 49 #define ADAU1373_LADC_MIXER 0x12 50 #define ADAU1373_RADC_MIXER 0x13 51 #define ADAU1373_LLINE1_MIX 0x14 52 #define ADAU1373_RLINE1_MIX 0x15 53 #define ADAU1373_LLINE2_MIX 0x16 54 #define ADAU1373_RLINE2_MIX 0x17 55 #define ADAU1373_LSPK_MIX 0x18 56 #define ADAU1373_RSPK_MIX 0x19 57 #define ADAU1373_LHP_MIX 0x1a 58 #define ADAU1373_RHP_MIX 0x1b 59 #define ADAU1373_EP_MIX 0x1c 60 #define ADAU1373_HP_CTRL 0x1d 61 #define ADAU1373_HP_CTRL2 0x1e 62 #define ADAU1373_LS_CTRL 0x1f 63 #define ADAU1373_EP_CTRL 0x21 64 #define ADAU1373_MICBIAS_CTRL1 0x22 65 #define ADAU1373_MICBIAS_CTRL2 0x23 66 #define ADAU1373_OUTPUT_CTRL 0x24 67 #define ADAU1373_PWDN_CTRL1 0x25 68 #define ADAU1373_PWDN_CTRL2 0x26 69 #define ADAU1373_PWDN_CTRL3 0x27 70 #define ADAU1373_DPLL_CTRL(x) (0x28 + (x) * 7) 71 #define ADAU1373_PLL_CTRL1(x) (0x29 + (x) * 7) 72 #define ADAU1373_PLL_CTRL2(x) (0x2a + (x) * 7) 73 #define ADAU1373_PLL_CTRL3(x) (0x2b + (x) * 7) 74 #define ADAU1373_PLL_CTRL4(x) (0x2c + (x) * 7) 75 #define ADAU1373_PLL_CTRL5(x) (0x2d + (x) * 7) 76 #define ADAU1373_PLL_CTRL6(x) (0x2e + (x) * 7) 77 #define ADAU1373_HEADDECT 0x36 78 #define ADAU1373_ADC_DAC_STATUS 0x37 79 #define ADAU1373_ADC_CTRL 0x3c 80 #define ADAU1373_DAI(x) (0x44 + (x)) 81 #define ADAU1373_CLK_SRC_DIV(x) (0x40 + (x) * 2) 82 #define ADAU1373_BCLKDIV(x) (0x47 + (x)) 83 #define ADAU1373_SRC_RATIOA(x) (0x4a + (x) * 2) 84 #define ADAU1373_SRC_RATIOB(x) (0x4b + (x) * 2) 85 #define ADAU1373_DEEMP_CTRL 0x50 86 #define ADAU1373_SRC_DAI_CTRL(x) (0x51 + (x)) 87 #define ADAU1373_DIN_MIX_CTRL(x) (0x56 + (x)) 88 #define ADAU1373_DOUT_MIX_CTRL(x) (0x5b + (x)) 89 #define ADAU1373_DAI_PBL_VOL(x) (0x62 + (x) * 2) 90 #define ADAU1373_DAI_PBR_VOL(x) (0x63 + (x) * 2) 91 #define ADAU1373_DAI_RECL_VOL(x) (0x68 + (x) * 2) 92 #define ADAU1373_DAI_RECR_VOL(x) (0x69 + (x) * 2) 93 #define ADAU1373_DAC1_PBL_VOL 0x6e 94 #define ADAU1373_DAC1_PBR_VOL 0x6f 95 #define ADAU1373_DAC2_PBL_VOL 0x70 96 #define ADAU1373_DAC2_PBR_VOL 0x71 97 #define ADAU1373_ADC_RECL_VOL 0x72 98 #define ADAU1373_ADC_RECR_VOL 0x73 99 #define ADAU1373_DMIC_RECL_VOL 0x74 100 #define ADAU1373_DMIC_RECR_VOL 0x75 101 #define ADAU1373_VOL_GAIN1 0x76 102 #define ADAU1373_VOL_GAIN2 0x77 103 #define ADAU1373_VOL_GAIN3 0x78 104 #define ADAU1373_HPF_CTRL 0x7d 105 #define ADAU1373_BASS1 0x7e 106 #define ADAU1373_BASS2 0x7f 107 #define ADAU1373_DRC(x) (0x80 + (x) * 0x10) 108 #define ADAU1373_3D_CTRL1 0xc0 109 #define ADAU1373_3D_CTRL2 0xc1 110 #define ADAU1373_FDSP_SEL1 0xdc 111 #define ADAU1373_FDSP_SEL2 0xdd 112 #define ADAU1373_FDSP_SEL3 0xde 113 #define ADAU1373_FDSP_SEL4 0xdf 114 #define ADAU1373_DIGMICCTRL 0xe2 115 #define ADAU1373_DIGEN 0xeb 116 #define ADAU1373_SOFT_RESET 0xff 117 118 119 #define ADAU1373_PLL_CTRL6_DPLL_BYPASS BIT(1) 120 #define ADAU1373_PLL_CTRL6_PLL_EN BIT(0) 121 122 #define ADAU1373_DAI_INVERT_BCLK BIT(7) 123 #define ADAU1373_DAI_MASTER BIT(6) 124 #define ADAU1373_DAI_INVERT_LRCLK BIT(4) 125 #define ADAU1373_DAI_WLEN_16 0x0 126 #define ADAU1373_DAI_WLEN_20 0x4 127 #define ADAU1373_DAI_WLEN_24 0x8 128 #define ADAU1373_DAI_WLEN_32 0xc 129 #define ADAU1373_DAI_WLEN_MASK 0xc 130 #define ADAU1373_DAI_FORMAT_RIGHT_J 0x0 131 #define ADAU1373_DAI_FORMAT_LEFT_J 0x1 132 #define ADAU1373_DAI_FORMAT_I2S 0x2 133 #define ADAU1373_DAI_FORMAT_DSP 0x3 134 135 #define ADAU1373_BCLKDIV_SOURCE BIT(5) 136 #define ADAU1373_BCLKDIV_SR_MASK (0x07 << 2) 137 #define ADAU1373_BCLKDIV_BCLK_MASK 0x03 138 #define ADAU1373_BCLKDIV_32 0x03 139 #define ADAU1373_BCLKDIV_64 0x02 140 #define ADAU1373_BCLKDIV_128 0x01 141 #define ADAU1373_BCLKDIV_256 0x00 142 143 #define ADAU1373_ADC_CTRL_PEAK_DETECT BIT(0) 144 #define ADAU1373_ADC_CTRL_RESET BIT(1) 145 #define ADAU1373_ADC_CTRL_RESET_FORCE BIT(2) 146 147 #define ADAU1373_OUTPUT_CTRL_LDIFF BIT(3) 148 #define ADAU1373_OUTPUT_CTRL_LNFBEN BIT(2) 149 150 #define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0) 151 152 #define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4 153 #define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2 154 155 static const struct reg_default adau1373_reg_defaults[] = { 156 { ADAU1373_INPUT_MODE, 0x00 }, 157 { ADAU1373_AINL_CTRL(0), 0x00 }, 158 { ADAU1373_AINR_CTRL(0), 0x00 }, 159 { ADAU1373_AINL_CTRL(1), 0x00 }, 160 { ADAU1373_AINR_CTRL(1), 0x00 }, 161 { ADAU1373_AINL_CTRL(2), 0x00 }, 162 { ADAU1373_AINR_CTRL(2), 0x00 }, 163 { ADAU1373_AINL_CTRL(3), 0x00 }, 164 { ADAU1373_AINR_CTRL(3), 0x00 }, 165 { ADAU1373_LLINE_OUT(0), 0x00 }, 166 { ADAU1373_RLINE_OUT(0), 0x00 }, 167 { ADAU1373_LLINE_OUT(1), 0x00 }, 168 { ADAU1373_RLINE_OUT(1), 0x00 }, 169 { ADAU1373_LSPK_OUT, 0x00 }, 170 { ADAU1373_RSPK_OUT, 0x00 }, 171 { ADAU1373_LHP_OUT, 0x00 }, 172 { ADAU1373_RHP_OUT, 0x00 }, 173 { ADAU1373_ADC_GAIN, 0x00 }, 174 { ADAU1373_LADC_MIXER, 0x00 }, 175 { ADAU1373_RADC_MIXER, 0x00 }, 176 { ADAU1373_LLINE1_MIX, 0x00 }, 177 { ADAU1373_RLINE1_MIX, 0x00 }, 178 { ADAU1373_LLINE2_MIX, 0x00 }, 179 { ADAU1373_RLINE2_MIX, 0x00 }, 180 { ADAU1373_LSPK_MIX, 0x00 }, 181 { ADAU1373_RSPK_MIX, 0x00 }, 182 { ADAU1373_LHP_MIX, 0x00 }, 183 { ADAU1373_RHP_MIX, 0x00 }, 184 { ADAU1373_EP_MIX, 0x00 }, 185 { ADAU1373_HP_CTRL, 0x00 }, 186 { ADAU1373_HP_CTRL2, 0x00 }, 187 { ADAU1373_LS_CTRL, 0x00 }, 188 { ADAU1373_EP_CTRL, 0x00 }, 189 { ADAU1373_MICBIAS_CTRL1, 0x00 }, 190 { ADAU1373_MICBIAS_CTRL2, 0x00 }, 191 { ADAU1373_OUTPUT_CTRL, 0x00 }, 192 { ADAU1373_PWDN_CTRL1, 0x00 }, 193 { ADAU1373_PWDN_CTRL2, 0x00 }, 194 { ADAU1373_PWDN_CTRL3, 0x00 }, 195 { ADAU1373_DPLL_CTRL(0), 0x00 }, 196 { ADAU1373_PLL_CTRL1(0), 0x00 }, 197 { ADAU1373_PLL_CTRL2(0), 0x00 }, 198 { ADAU1373_PLL_CTRL3(0), 0x00 }, 199 { ADAU1373_PLL_CTRL4(0), 0x00 }, 200 { ADAU1373_PLL_CTRL5(0), 0x00 }, 201 { ADAU1373_PLL_CTRL6(0), 0x02 }, 202 { ADAU1373_DPLL_CTRL(1), 0x00 }, 203 { ADAU1373_PLL_CTRL1(1), 0x00 }, 204 { ADAU1373_PLL_CTRL2(1), 0x00 }, 205 { ADAU1373_PLL_CTRL3(1), 0x00 }, 206 { ADAU1373_PLL_CTRL4(1), 0x00 }, 207 { ADAU1373_PLL_CTRL5(1), 0x00 }, 208 { ADAU1373_PLL_CTRL6(1), 0x02 }, 209 { ADAU1373_HEADDECT, 0x00 }, 210 { ADAU1373_ADC_CTRL, 0x00 }, 211 { ADAU1373_CLK_SRC_DIV(0), 0x00 }, 212 { ADAU1373_CLK_SRC_DIV(1), 0x00 }, 213 { ADAU1373_DAI(0), 0x0a }, 214 { ADAU1373_DAI(1), 0x0a }, 215 { ADAU1373_DAI(2), 0x0a }, 216 { ADAU1373_BCLKDIV(0), 0x00 }, 217 { ADAU1373_BCLKDIV(1), 0x00 }, 218 { ADAU1373_BCLKDIV(2), 0x00 }, 219 { ADAU1373_SRC_RATIOA(0), 0x00 }, 220 { ADAU1373_SRC_RATIOB(0), 0x00 }, 221 { ADAU1373_SRC_RATIOA(1), 0x00 }, 222 { ADAU1373_SRC_RATIOB(1), 0x00 }, 223 { ADAU1373_SRC_RATIOA(2), 0x00 }, 224 { ADAU1373_SRC_RATIOB(2), 0x00 }, 225 { ADAU1373_DEEMP_CTRL, 0x00 }, 226 { ADAU1373_SRC_DAI_CTRL(0), 0x08 }, 227 { ADAU1373_SRC_DAI_CTRL(1), 0x08 }, 228 { ADAU1373_SRC_DAI_CTRL(2), 0x08 }, 229 { ADAU1373_DIN_MIX_CTRL(0), 0x00 }, 230 { ADAU1373_DIN_MIX_CTRL(1), 0x00 }, 231 { ADAU1373_DIN_MIX_CTRL(2), 0x00 }, 232 { ADAU1373_DIN_MIX_CTRL(3), 0x00 }, 233 { ADAU1373_DIN_MIX_CTRL(4), 0x00 }, 234 { ADAU1373_DOUT_MIX_CTRL(0), 0x00 }, 235 { ADAU1373_DOUT_MIX_CTRL(1), 0x00 }, 236 { ADAU1373_DOUT_MIX_CTRL(2), 0x00 }, 237 { ADAU1373_DOUT_MIX_CTRL(3), 0x00 }, 238 { ADAU1373_DOUT_MIX_CTRL(4), 0x00 }, 239 { ADAU1373_DAI_PBL_VOL(0), 0x00 }, 240 { ADAU1373_DAI_PBR_VOL(0), 0x00 }, 241 { ADAU1373_DAI_PBL_VOL(1), 0x00 }, 242 { ADAU1373_DAI_PBR_VOL(1), 0x00 }, 243 { ADAU1373_DAI_PBL_VOL(2), 0x00 }, 244 { ADAU1373_DAI_PBR_VOL(2), 0x00 }, 245 { ADAU1373_DAI_RECL_VOL(0), 0x00 }, 246 { ADAU1373_DAI_RECR_VOL(0), 0x00 }, 247 { ADAU1373_DAI_RECL_VOL(1), 0x00 }, 248 { ADAU1373_DAI_RECR_VOL(1), 0x00 }, 249 { ADAU1373_DAI_RECL_VOL(2), 0x00 }, 250 { ADAU1373_DAI_RECR_VOL(2), 0x00 }, 251 { ADAU1373_DAC1_PBL_VOL, 0x00 }, 252 { ADAU1373_DAC1_PBR_VOL, 0x00 }, 253 { ADAU1373_DAC2_PBL_VOL, 0x00 }, 254 { ADAU1373_DAC2_PBR_VOL, 0x00 }, 255 { ADAU1373_ADC_RECL_VOL, 0x00 }, 256 { ADAU1373_ADC_RECR_VOL, 0x00 }, 257 { ADAU1373_DMIC_RECL_VOL, 0x00 }, 258 { ADAU1373_DMIC_RECR_VOL, 0x00 }, 259 { ADAU1373_VOL_GAIN1, 0x00 }, 260 { ADAU1373_VOL_GAIN2, 0x00 }, 261 { ADAU1373_VOL_GAIN3, 0x00 }, 262 { ADAU1373_HPF_CTRL, 0x00 }, 263 { ADAU1373_BASS1, 0x00 }, 264 { ADAU1373_BASS2, 0x00 }, 265 { ADAU1373_DRC(0) + 0x0, 0x78 }, 266 { ADAU1373_DRC(0) + 0x1, 0x18 }, 267 { ADAU1373_DRC(0) + 0x2, 0x00 }, 268 { ADAU1373_DRC(0) + 0x3, 0x00 }, 269 { ADAU1373_DRC(0) + 0x4, 0x00 }, 270 { ADAU1373_DRC(0) + 0x5, 0xc0 }, 271 { ADAU1373_DRC(0) + 0x6, 0x00 }, 272 { ADAU1373_DRC(0) + 0x7, 0x00 }, 273 { ADAU1373_DRC(0) + 0x8, 0x00 }, 274 { ADAU1373_DRC(0) + 0x9, 0xc0 }, 275 { ADAU1373_DRC(0) + 0xa, 0x88 }, 276 { ADAU1373_DRC(0) + 0xb, 0x7a }, 277 { ADAU1373_DRC(0) + 0xc, 0xdf }, 278 { ADAU1373_DRC(0) + 0xd, 0x20 }, 279 { ADAU1373_DRC(0) + 0xe, 0x00 }, 280 { ADAU1373_DRC(0) + 0xf, 0x00 }, 281 { ADAU1373_DRC(1) + 0x0, 0x78 }, 282 { ADAU1373_DRC(1) + 0x1, 0x18 }, 283 { ADAU1373_DRC(1) + 0x2, 0x00 }, 284 { ADAU1373_DRC(1) + 0x3, 0x00 }, 285 { ADAU1373_DRC(1) + 0x4, 0x00 }, 286 { ADAU1373_DRC(1) + 0x5, 0xc0 }, 287 { ADAU1373_DRC(1) + 0x6, 0x00 }, 288 { ADAU1373_DRC(1) + 0x7, 0x00 }, 289 { ADAU1373_DRC(1) + 0x8, 0x00 }, 290 { ADAU1373_DRC(1) + 0x9, 0xc0 }, 291 { ADAU1373_DRC(1) + 0xa, 0x88 }, 292 { ADAU1373_DRC(1) + 0xb, 0x7a }, 293 { ADAU1373_DRC(1) + 0xc, 0xdf }, 294 { ADAU1373_DRC(1) + 0xd, 0x20 }, 295 { ADAU1373_DRC(1) + 0xe, 0x00 }, 296 { ADAU1373_DRC(1) + 0xf, 0x00 }, 297 { ADAU1373_DRC(2) + 0x0, 0x78 }, 298 { ADAU1373_DRC(2) + 0x1, 0x18 }, 299 { ADAU1373_DRC(2) + 0x2, 0x00 }, 300 { ADAU1373_DRC(2) + 0x3, 0x00 }, 301 { ADAU1373_DRC(2) + 0x4, 0x00 }, 302 { ADAU1373_DRC(2) + 0x5, 0xc0 }, 303 { ADAU1373_DRC(2) + 0x6, 0x00 }, 304 { ADAU1373_DRC(2) + 0x7, 0x00 }, 305 { ADAU1373_DRC(2) + 0x8, 0x00 }, 306 { ADAU1373_DRC(2) + 0x9, 0xc0 }, 307 { ADAU1373_DRC(2) + 0xa, 0x88 }, 308 { ADAU1373_DRC(2) + 0xb, 0x7a }, 309 { ADAU1373_DRC(2) + 0xc, 0xdf }, 310 { ADAU1373_DRC(2) + 0xd, 0x20 }, 311 { ADAU1373_DRC(2) + 0xe, 0x00 }, 312 { ADAU1373_DRC(2) + 0xf, 0x00 }, 313 { ADAU1373_3D_CTRL1, 0x00 }, 314 { ADAU1373_3D_CTRL2, 0x00 }, 315 { ADAU1373_FDSP_SEL1, 0x00 }, 316 { ADAU1373_FDSP_SEL2, 0x00 }, 317 { ADAU1373_FDSP_SEL2, 0x00 }, 318 { ADAU1373_FDSP_SEL4, 0x00 }, 319 { ADAU1373_DIGMICCTRL, 0x00 }, 320 { ADAU1373_DIGEN, 0x00 }, 321 }; 322 323 static const unsigned int adau1373_out_tlv[] = { 324 TLV_DB_RANGE_HEAD(4), 325 0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1), 326 8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0), 327 16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0), 328 24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0), 329 }; 330 331 static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv, -9563, 0); 332 static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv, -1300, 100, 1); 333 static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv, -600, 600, 1); 334 335 static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv, 0, 2000, 0); 336 static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv, 0, 600, 0); 337 static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv, 1200, 600, 0); 338 339 static const char *adau1373_fdsp_sel_text[] = { 340 "None", 341 "Channel 1", 342 "Channel 2", 343 "Channel 3", 344 "Channel 4", 345 "Channel 5", 346 }; 347 348 static SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum, 349 ADAU1373_FDSP_SEL1, 4, adau1373_fdsp_sel_text); 350 static SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum, 351 ADAU1373_FDSP_SEL1, 0, adau1373_fdsp_sel_text); 352 static SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum, 353 ADAU1373_FDSP_SEL2, 0, adau1373_fdsp_sel_text); 354 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum, 355 ADAU1373_FDSP_SEL3, 0, adau1373_fdsp_sel_text); 356 static SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum, 357 ADAU1373_FDSP_SEL4, 4, adau1373_fdsp_sel_text); 358 359 static const char *adau1373_hpf_cutoff_text[] = { 360 "3.7Hz", "50Hz", "100Hz", "150Hz", "200Hz", "250Hz", "300Hz", "350Hz", 361 "400Hz", "450Hz", "500Hz", "550Hz", "600Hz", "650Hz", "700Hz", "750Hz", 362 "800Hz", 363 }; 364 365 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum, 366 ADAU1373_HPF_CTRL, 3, adau1373_hpf_cutoff_text); 367 368 static const char *adau1373_bass_lpf_cutoff_text[] = { 369 "801Hz", "1001Hz", 370 }; 371 372 static const char *adau1373_bass_clip_level_text[] = { 373 "0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875", 374 }; 375 376 static const unsigned int adau1373_bass_clip_level_values[] = { 377 1, 2, 3, 4, 5, 6, 7, 378 }; 379 380 static const char *adau1373_bass_hpf_cutoff_text[] = { 381 "158Hz", "232Hz", "347Hz", "520Hz", 382 }; 383 384 static const unsigned int adau1373_bass_tlv[] = { 385 TLV_DB_RANGE_HEAD(3), 386 0, 2, TLV_DB_SCALE_ITEM(-600, 600, 1), 387 3, 4, TLV_DB_SCALE_ITEM(950, 250, 0), 388 5, 7, TLV_DB_SCALE_ITEM(1400, 150, 0), 389 }; 390 391 static SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum, 392 ADAU1373_BASS1, 5, adau1373_bass_lpf_cutoff_text); 393 394 static SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum, 395 ADAU1373_BASS1, 2, 7, adau1373_bass_clip_level_text, 396 adau1373_bass_clip_level_values); 397 398 static SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum, 399 ADAU1373_BASS1, 0, adau1373_bass_hpf_cutoff_text); 400 401 static const char *adau1373_3d_level_text[] = { 402 "0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%", 403 "40%", "46.67%", "53.33%", "60%", "66.67%", "73.33%", 404 "80%", "86.67", "99.33%", "100%" 405 }; 406 407 static const char *adau1373_3d_cutoff_text[] = { 408 "No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs", 409 "0.16875 fs", "0.27083 fs" 410 }; 411 412 static SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum, 413 ADAU1373_3D_CTRL1, 4, adau1373_3d_level_text); 414 static SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum, 415 ADAU1373_3D_CTRL1, 0, adau1373_3d_cutoff_text); 416 417 static const unsigned int adau1373_3d_tlv[] = { 418 TLV_DB_RANGE_HEAD(2), 419 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 420 1, 7, TLV_DB_LINEAR_ITEM(-1800, -120), 421 }; 422 423 static const char *adau1373_lr_mux_text[] = { 424 "Mute", 425 "Right Channel (L+R)", 426 "Left Channel (L+R)", 427 "Stereo", 428 }; 429 430 static SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum, 431 ADAU1373_OUTPUT_CTRL, 4, adau1373_lr_mux_text); 432 static SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum, 433 ADAU1373_OUTPUT_CTRL, 6, adau1373_lr_mux_text); 434 static SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum, 435 ADAU1373_LS_CTRL, 4, adau1373_lr_mux_text); 436 437 static const struct snd_kcontrol_new adau1373_controls[] = { 438 SOC_DOUBLE_R_TLV("AIF1 Capture Volume", ADAU1373_DAI_RECL_VOL(0), 439 ADAU1373_DAI_RECR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv), 440 SOC_DOUBLE_R_TLV("AIF2 Capture Volume", ADAU1373_DAI_RECL_VOL(1), 441 ADAU1373_DAI_RECR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv), 442 SOC_DOUBLE_R_TLV("AIF3 Capture Volume", ADAU1373_DAI_RECL_VOL(2), 443 ADAU1373_DAI_RECR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv), 444 445 SOC_DOUBLE_R_TLV("ADC Capture Volume", ADAU1373_ADC_RECL_VOL, 446 ADAU1373_ADC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv), 447 SOC_DOUBLE_R_TLV("DMIC Capture Volume", ADAU1373_DMIC_RECL_VOL, 448 ADAU1373_DMIC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv), 449 450 SOC_DOUBLE_R_TLV("AIF1 Playback Volume", ADAU1373_DAI_PBL_VOL(0), 451 ADAU1373_DAI_PBR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv), 452 SOC_DOUBLE_R_TLV("AIF2 Playback Volume", ADAU1373_DAI_PBL_VOL(1), 453 ADAU1373_DAI_PBR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv), 454 SOC_DOUBLE_R_TLV("AIF3 Playback Volume", ADAU1373_DAI_PBL_VOL(2), 455 ADAU1373_DAI_PBR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv), 456 457 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ADAU1373_DAC1_PBL_VOL, 458 ADAU1373_DAC1_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv), 459 SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ADAU1373_DAC2_PBL_VOL, 460 ADAU1373_DAC2_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv), 461 462 SOC_DOUBLE_R_TLV("Lineout1 Playback Volume", ADAU1373_LLINE_OUT(0), 463 ADAU1373_RLINE_OUT(0), 0, 0x1f, 0, adau1373_out_tlv), 464 SOC_DOUBLE_R_TLV("Speaker Playback Volume", ADAU1373_LSPK_OUT, 465 ADAU1373_RSPK_OUT, 0, 0x1f, 0, adau1373_out_tlv), 466 SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1373_LHP_OUT, 467 ADAU1373_RHP_OUT, 0, 0x1f, 0, adau1373_out_tlv), 468 469 SOC_DOUBLE_R_TLV("Input 1 Capture Volume", ADAU1373_AINL_CTRL(0), 470 ADAU1373_AINR_CTRL(0), 0, 0x1f, 0, adau1373_in_pga_tlv), 471 SOC_DOUBLE_R_TLV("Input 2 Capture Volume", ADAU1373_AINL_CTRL(1), 472 ADAU1373_AINR_CTRL(1), 0, 0x1f, 0, adau1373_in_pga_tlv), 473 SOC_DOUBLE_R_TLV("Input 3 Capture Volume", ADAU1373_AINL_CTRL(2), 474 ADAU1373_AINR_CTRL(2), 0, 0x1f, 0, adau1373_in_pga_tlv), 475 SOC_DOUBLE_R_TLV("Input 4 Capture Volume", ADAU1373_AINL_CTRL(3), 476 ADAU1373_AINR_CTRL(3), 0, 0x1f, 0, adau1373_in_pga_tlv), 477 478 SOC_SINGLE_TLV("Earpiece Playback Volume", ADAU1373_EP_CTRL, 0, 3, 0, 479 adau1373_ep_tlv), 480 481 SOC_DOUBLE_TLV("AIF3 Boost Playback Volume", ADAU1373_VOL_GAIN1, 4, 5, 482 1, 0, adau1373_gain_boost_tlv), 483 SOC_DOUBLE_TLV("AIF2 Boost Playback Volume", ADAU1373_VOL_GAIN1, 2, 3, 484 1, 0, adau1373_gain_boost_tlv), 485 SOC_DOUBLE_TLV("AIF1 Boost Playback Volume", ADAU1373_VOL_GAIN1, 0, 1, 486 1, 0, adau1373_gain_boost_tlv), 487 SOC_DOUBLE_TLV("AIF3 Boost Capture Volume", ADAU1373_VOL_GAIN2, 4, 5, 488 1, 0, adau1373_gain_boost_tlv), 489 SOC_DOUBLE_TLV("AIF2 Boost Capture Volume", ADAU1373_VOL_GAIN2, 2, 3, 490 1, 0, adau1373_gain_boost_tlv), 491 SOC_DOUBLE_TLV("AIF1 Boost Capture Volume", ADAU1373_VOL_GAIN2, 0, 1, 492 1, 0, adau1373_gain_boost_tlv), 493 SOC_DOUBLE_TLV("DMIC Boost Capture Volume", ADAU1373_VOL_GAIN3, 6, 7, 494 1, 0, adau1373_gain_boost_tlv), 495 SOC_DOUBLE_TLV("ADC Boost Capture Volume", ADAU1373_VOL_GAIN3, 4, 5, 496 1, 0, adau1373_gain_boost_tlv), 497 SOC_DOUBLE_TLV("DAC2 Boost Playback Volume", ADAU1373_VOL_GAIN3, 2, 3, 498 1, 0, adau1373_gain_boost_tlv), 499 SOC_DOUBLE_TLV("DAC1 Boost Playback Volume", ADAU1373_VOL_GAIN3, 0, 1, 500 1, 0, adau1373_gain_boost_tlv), 501 502 SOC_DOUBLE_TLV("Input 1 Boost Capture Volume", ADAU1373_ADC_GAIN, 0, 4, 503 1, 0, adau1373_input_boost_tlv), 504 SOC_DOUBLE_TLV("Input 2 Boost Capture Volume", ADAU1373_ADC_GAIN, 1, 5, 505 1, 0, adau1373_input_boost_tlv), 506 SOC_DOUBLE_TLV("Input 3 Boost Capture Volume", ADAU1373_ADC_GAIN, 2, 6, 507 1, 0, adau1373_input_boost_tlv), 508 SOC_DOUBLE_TLV("Input 4 Boost Capture Volume", ADAU1373_ADC_GAIN, 3, 7, 509 1, 0, adau1373_input_boost_tlv), 510 511 SOC_DOUBLE_TLV("Speaker Boost Playback Volume", ADAU1373_LS_CTRL, 2, 3, 512 1, 0, adau1373_speaker_boost_tlv), 513 514 SOC_ENUM("Lineout1 LR Mux", adau1373_lineout1_lr_mux_enum), 515 SOC_ENUM("Speaker LR Mux", adau1373_speaker_lr_mux_enum), 516 517 SOC_ENUM("HPF Cutoff", adau1373_hpf_cutoff_enum), 518 SOC_DOUBLE("HPF Switch", ADAU1373_HPF_CTRL, 1, 0, 1, 0), 519 SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum), 520 521 SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum), 522 SOC_ENUM("Bass Clip Level Threshold", adau1373_bass_clip_level_enum), 523 SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum), 524 SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0), 525 SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0, 526 adau1373_bass_tlv), 527 SOC_ENUM("Bass Channel", adau1373_bass_channel_enum), 528 529 SOC_ENUM("3D Freq", adau1373_3d_cutoff_enum), 530 SOC_ENUM("3D Level", adau1373_3d_level_enum), 531 SOC_SINGLE("3D Playback Switch", ADAU1373_3D_CTRL2, 0, 1, 0), 532 SOC_SINGLE_TLV("3D Playback Volume", ADAU1373_3D_CTRL2, 2, 7, 0, 533 adau1373_3d_tlv), 534 SOC_ENUM("3D Channel", adau1373_bass_channel_enum), 535 536 SOC_SINGLE("Zero Cross Switch", ADAU1373_PWDN_CTRL3, 7, 1, 0), 537 }; 538 539 static const struct snd_kcontrol_new adau1373_lineout2_controls[] = { 540 SOC_DOUBLE_R_TLV("Lineout2 Playback Volume", ADAU1373_LLINE_OUT(1), 541 ADAU1373_RLINE_OUT(1), 0, 0x1f, 0, adau1373_out_tlv), 542 SOC_ENUM("Lineout2 LR Mux", adau1373_lineout2_lr_mux_enum), 543 }; 544 545 static const struct snd_kcontrol_new adau1373_drc_controls[] = { 546 SOC_ENUM("DRC1 Channel", adau1373_drc1_channel_enum), 547 SOC_ENUM("DRC2 Channel", adau1373_drc2_channel_enum), 548 SOC_ENUM("DRC3 Channel", adau1373_drc3_channel_enum), 549 }; 550 551 static int adau1373_pll_event(struct snd_soc_dapm_widget *w, 552 struct snd_kcontrol *kcontrol, int event) 553 { 554 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 555 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 556 unsigned int pll_id = w->name[3] - '1'; 557 unsigned int val; 558 559 if (SND_SOC_DAPM_EVENT_ON(event)) 560 val = ADAU1373_PLL_CTRL6_PLL_EN; 561 else 562 val = 0; 563 564 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id), 565 ADAU1373_PLL_CTRL6_PLL_EN, val); 566 567 if (SND_SOC_DAPM_EVENT_ON(event)) 568 mdelay(5); 569 570 return 0; 571 } 572 573 static const char *adau1373_decimator_text[] = { 574 "ADC", 575 "DMIC1", 576 }; 577 578 static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum, 579 adau1373_decimator_text); 580 581 static const struct snd_kcontrol_new adau1373_decimator_mux = 582 SOC_DAPM_ENUM("Decimator Mux", adau1373_decimator_enum); 583 584 static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = { 585 SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0), 586 SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_LADC_MIXER, 3, 1, 0), 587 SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_LADC_MIXER, 2, 1, 0), 588 SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_LADC_MIXER, 1, 1, 0), 589 SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_LADC_MIXER, 0, 1, 0), 590 }; 591 592 static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls[] = { 593 SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_RADC_MIXER, 4, 1, 0), 594 SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_RADC_MIXER, 3, 1, 0), 595 SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_RADC_MIXER, 2, 1, 0), 596 SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_RADC_MIXER, 1, 1, 0), 597 SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_RADC_MIXER, 0, 1, 0), 598 }; 599 600 #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \ 601 const struct snd_kcontrol_new _name[] = { \ 602 SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \ 603 SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \ 604 SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \ 605 SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \ 606 SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \ 607 SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \ 608 SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \ 609 SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \ 610 } 611 612 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls, 613 ADAU1373_LLINE1_MIX); 614 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls, 615 ADAU1373_RLINE1_MIX); 616 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls, 617 ADAU1373_LLINE2_MIX); 618 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls, 619 ADAU1373_RLINE2_MIX); 620 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls, 621 ADAU1373_LSPK_MIX); 622 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls, 623 ADAU1373_RSPK_MIX); 624 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls, 625 ADAU1373_EP_MIX); 626 627 static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls[] = { 628 SOC_DAPM_SINGLE("Left DAC1 Switch", ADAU1373_LHP_MIX, 5, 1, 0), 629 SOC_DAPM_SINGLE("Left DAC2 Switch", ADAU1373_LHP_MIX, 4, 1, 0), 630 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0), 631 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0), 632 SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0), 633 SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0), 634 }; 635 636 static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls[] = { 637 SOC_DAPM_SINGLE("Right DAC1 Switch", ADAU1373_RHP_MIX, 5, 1, 0), 638 SOC_DAPM_SINGLE("Right DAC2 Switch", ADAU1373_RHP_MIX, 4, 1, 0), 639 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0), 640 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0), 641 SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_RHP_MIX, 1, 1, 0), 642 SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_RHP_MIX, 0, 1, 0), 643 }; 644 645 #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \ 646 const struct snd_kcontrol_new _name[] = { \ 647 SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \ 648 SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \ 649 SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \ 650 SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \ 651 SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \ 652 SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \ 653 SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \ 654 } 655 656 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls, 657 ADAU1373_DIN_MIX_CTRL(0)); 658 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls, 659 ADAU1373_DIN_MIX_CTRL(1)); 660 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls, 661 ADAU1373_DIN_MIX_CTRL(2)); 662 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls, 663 ADAU1373_DIN_MIX_CTRL(3)); 664 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls, 665 ADAU1373_DIN_MIX_CTRL(4)); 666 667 #define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \ 668 const struct snd_kcontrol_new _name[] = { \ 669 SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \ 670 SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \ 671 SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \ 672 SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \ 673 SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \ 674 } 675 676 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls, 677 ADAU1373_DOUT_MIX_CTRL(0)); 678 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls, 679 ADAU1373_DOUT_MIX_CTRL(1)); 680 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls, 681 ADAU1373_DOUT_MIX_CTRL(2)); 682 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls, 683 ADAU1373_DOUT_MIX_CTRL(3)); 684 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls, 685 ADAU1373_DOUT_MIX_CTRL(4)); 686 687 static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = { 688 /* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that 689 * doesn't seem to be the case. */ 690 SND_SOC_DAPM_ADC("Left ADC", NULL, ADAU1373_PWDN_CTRL1, 7, 0), 691 SND_SOC_DAPM_ADC("Right ADC", NULL, ADAU1373_PWDN_CTRL1, 6, 0), 692 693 SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0), 694 SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0), 695 696 SND_SOC_DAPM_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0, 697 &adau1373_decimator_mux), 698 699 SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0), 700 SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1373_PWDN_CTRL1, 4, 0, NULL, 0), 701 702 SND_SOC_DAPM_PGA("IN4PGA", ADAU1373_PWDN_CTRL1, 3, 0, NULL, 0), 703 SND_SOC_DAPM_PGA("IN3PGA", ADAU1373_PWDN_CTRL1, 2, 0, NULL, 0), 704 SND_SOC_DAPM_PGA("IN2PGA", ADAU1373_PWDN_CTRL1, 1, 0, NULL, 0), 705 SND_SOC_DAPM_PGA("IN1PGA", ADAU1373_PWDN_CTRL1, 0, 0, NULL, 0), 706 707 SND_SOC_DAPM_DAC("Left DAC2", NULL, ADAU1373_PWDN_CTRL2, 7, 0), 708 SND_SOC_DAPM_DAC("Right DAC2", NULL, ADAU1373_PWDN_CTRL2, 6, 0), 709 SND_SOC_DAPM_DAC("Left DAC1", NULL, ADAU1373_PWDN_CTRL2, 5, 0), 710 SND_SOC_DAPM_DAC("Right DAC1", NULL, ADAU1373_PWDN_CTRL2, 4, 0), 711 712 SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 713 adau1373_left_adc_mixer_controls), 714 SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 715 adau1373_right_adc_mixer_controls), 716 717 SOC_MIXER_ARRAY("Left Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 3, 0, 718 adau1373_left_line2_mixer_controls), 719 SOC_MIXER_ARRAY("Right Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 2, 0, 720 adau1373_right_line2_mixer_controls), 721 SOC_MIXER_ARRAY("Left Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 1, 0, 722 adau1373_left_line1_mixer_controls), 723 SOC_MIXER_ARRAY("Right Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 0, 0, 724 adau1373_right_line1_mixer_controls), 725 726 SOC_MIXER_ARRAY("Earpiece Mixer", ADAU1373_PWDN_CTRL3, 4, 0, 727 adau1373_ep_mixer_controls), 728 SOC_MIXER_ARRAY("Left Speaker Mixer", ADAU1373_PWDN_CTRL3, 3, 0, 729 adau1373_left_spk_mixer_controls), 730 SOC_MIXER_ARRAY("Right Speaker Mixer", ADAU1373_PWDN_CTRL3, 2, 0, 731 adau1373_right_spk_mixer_controls), 732 SOC_MIXER_ARRAY("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 733 adau1373_left_hp_mixer_controls), 734 SOC_MIXER_ARRAY("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 735 adau1373_right_hp_mixer_controls), 736 SND_SOC_DAPM_SUPPLY("Headphone Enable", ADAU1373_PWDN_CTRL3, 1, 0, 737 NULL, 0), 738 739 SND_SOC_DAPM_SUPPLY("AIF1 CLK", ADAU1373_SRC_DAI_CTRL(0), 0, 0, 740 NULL, 0), 741 SND_SOC_DAPM_SUPPLY("AIF2 CLK", ADAU1373_SRC_DAI_CTRL(1), 0, 0, 742 NULL, 0), 743 SND_SOC_DAPM_SUPPLY("AIF3 CLK", ADAU1373_SRC_DAI_CTRL(2), 0, 0, 744 NULL, 0), 745 SND_SOC_DAPM_SUPPLY("AIF1 IN SRC", ADAU1373_SRC_DAI_CTRL(0), 2, 0, 746 NULL, 0), 747 SND_SOC_DAPM_SUPPLY("AIF1 OUT SRC", ADAU1373_SRC_DAI_CTRL(0), 1, 0, 748 NULL, 0), 749 SND_SOC_DAPM_SUPPLY("AIF2 IN SRC", ADAU1373_SRC_DAI_CTRL(1), 2, 0, 750 NULL, 0), 751 SND_SOC_DAPM_SUPPLY("AIF2 OUT SRC", ADAU1373_SRC_DAI_CTRL(1), 1, 0, 752 NULL, 0), 753 SND_SOC_DAPM_SUPPLY("AIF3 IN SRC", ADAU1373_SRC_DAI_CTRL(2), 2, 0, 754 NULL, 0), 755 SND_SOC_DAPM_SUPPLY("AIF3 OUT SRC", ADAU1373_SRC_DAI_CTRL(2), 1, 0, 756 NULL, 0), 757 758 SND_SOC_DAPM_AIF_IN("AIF1 IN", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 759 SND_SOC_DAPM_AIF_OUT("AIF1 OUT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 760 SND_SOC_DAPM_AIF_IN("AIF2 IN", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 761 SND_SOC_DAPM_AIF_OUT("AIF2 OUT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 762 SND_SOC_DAPM_AIF_IN("AIF3 IN", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 763 SND_SOC_DAPM_AIF_OUT("AIF3 OUT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 764 765 SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM, 0, 0, 766 adau1373_dsp_channel1_mixer_controls), 767 SOC_MIXER_ARRAY("DSP Channel2 Mixer", SND_SOC_NOPM, 0, 0, 768 adau1373_dsp_channel2_mixer_controls), 769 SOC_MIXER_ARRAY("DSP Channel3 Mixer", SND_SOC_NOPM, 0, 0, 770 adau1373_dsp_channel3_mixer_controls), 771 SOC_MIXER_ARRAY("DSP Channel4 Mixer", SND_SOC_NOPM, 0, 0, 772 adau1373_dsp_channel4_mixer_controls), 773 SOC_MIXER_ARRAY("DSP Channel5 Mixer", SND_SOC_NOPM, 0, 0, 774 adau1373_dsp_channel5_mixer_controls), 775 776 SOC_MIXER_ARRAY("AIF1 Mixer", SND_SOC_NOPM, 0, 0, 777 adau1373_aif1_mixer_controls), 778 SOC_MIXER_ARRAY("AIF2 Mixer", SND_SOC_NOPM, 0, 0, 779 adau1373_aif2_mixer_controls), 780 SOC_MIXER_ARRAY("AIF3 Mixer", SND_SOC_NOPM, 0, 0, 781 adau1373_aif3_mixer_controls), 782 SOC_MIXER_ARRAY("DAC1 Mixer", SND_SOC_NOPM, 0, 0, 783 adau1373_dac1_mixer_controls), 784 SOC_MIXER_ARRAY("DAC2 Mixer", SND_SOC_NOPM, 0, 0, 785 adau1373_dac2_mixer_controls), 786 787 SND_SOC_DAPM_SUPPLY("DSP", ADAU1373_DIGEN, 4, 0, NULL, 0), 788 SND_SOC_DAPM_SUPPLY("Recording Engine B", ADAU1373_DIGEN, 3, 0, NULL, 0), 789 SND_SOC_DAPM_SUPPLY("Recording Engine A", ADAU1373_DIGEN, 2, 0, NULL, 0), 790 SND_SOC_DAPM_SUPPLY("Playback Engine B", ADAU1373_DIGEN, 1, 0, NULL, 0), 791 SND_SOC_DAPM_SUPPLY("Playback Engine A", ADAU1373_DIGEN, 0, 0, NULL, 0), 792 793 SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM, 0, 0, adau1373_pll_event, 794 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 795 SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM, 0, 0, adau1373_pll_event, 796 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 797 SND_SOC_DAPM_SUPPLY("SYSCLK1", ADAU1373_CLK_SRC_DIV(0), 7, 0, NULL, 0), 798 SND_SOC_DAPM_SUPPLY("SYSCLK2", ADAU1373_CLK_SRC_DIV(1), 7, 0, NULL, 0), 799 800 SND_SOC_DAPM_INPUT("AIN1L"), 801 SND_SOC_DAPM_INPUT("AIN1R"), 802 SND_SOC_DAPM_INPUT("AIN2L"), 803 SND_SOC_DAPM_INPUT("AIN2R"), 804 SND_SOC_DAPM_INPUT("AIN3L"), 805 SND_SOC_DAPM_INPUT("AIN3R"), 806 SND_SOC_DAPM_INPUT("AIN4L"), 807 SND_SOC_DAPM_INPUT("AIN4R"), 808 809 SND_SOC_DAPM_INPUT("DMIC1DAT"), 810 SND_SOC_DAPM_INPUT("DMIC2DAT"), 811 812 SND_SOC_DAPM_OUTPUT("LOUT1L"), 813 SND_SOC_DAPM_OUTPUT("LOUT1R"), 814 SND_SOC_DAPM_OUTPUT("LOUT2L"), 815 SND_SOC_DAPM_OUTPUT("LOUT2R"), 816 SND_SOC_DAPM_OUTPUT("HPL"), 817 SND_SOC_DAPM_OUTPUT("HPR"), 818 SND_SOC_DAPM_OUTPUT("SPKL"), 819 SND_SOC_DAPM_OUTPUT("SPKR"), 820 SND_SOC_DAPM_OUTPUT("EP"), 821 }; 822 823 static int adau1373_check_aif_clk(struct snd_soc_dapm_widget *source, 824 struct snd_soc_dapm_widget *sink) 825 { 826 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 827 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 828 unsigned int dai; 829 const char *clk; 830 831 dai = sink->name[3] - '1'; 832 833 if (!adau1373->dais[dai].master) 834 return 0; 835 836 if (adau1373->dais[dai].clk_src == ADAU1373_CLK_SRC_PLL1) 837 clk = "SYSCLK1"; 838 else 839 clk = "SYSCLK2"; 840 841 return strcmp(source->name, clk) == 0; 842 } 843 844 static int adau1373_check_src(struct snd_soc_dapm_widget *source, 845 struct snd_soc_dapm_widget *sink) 846 { 847 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 848 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 849 unsigned int dai; 850 851 dai = sink->name[3] - '1'; 852 853 return adau1373->dais[dai].enable_src; 854 } 855 856 #define DSP_CHANNEL_MIXER_ROUTES(_sink) \ 857 { _sink, "DMIC2 Swapped Switch", "DMIC2" }, \ 858 { _sink, "DMIC2 Switch", "DMIC2" }, \ 859 { _sink, "ADC/DMIC1 Swapped Switch", "Decimator Mux" }, \ 860 { _sink, "ADC/DMIC1 Switch", "Decimator Mux" }, \ 861 { _sink, "AIF1 Switch", "AIF1 IN" }, \ 862 { _sink, "AIF2 Switch", "AIF2 IN" }, \ 863 { _sink, "AIF3 Switch", "AIF3 IN" } 864 865 #define DSP_OUTPUT_MIXER_ROUTES(_sink) \ 866 { _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \ 867 { _sink, "DSP Channel2 Switch", "DSP Channel2 Mixer" }, \ 868 { _sink, "DSP Channel3 Switch", "DSP Channel3 Mixer" }, \ 869 { _sink, "DSP Channel4 Switch", "DSP Channel4 Mixer" }, \ 870 { _sink, "DSP Channel5 Switch", "DSP Channel5 Mixer" } 871 872 #define LEFT_OUTPUT_MIXER_ROUTES(_sink) \ 873 { _sink, "Right DAC2 Switch", "Right DAC2" }, \ 874 { _sink, "Left DAC2 Switch", "Left DAC2" }, \ 875 { _sink, "Right DAC1 Switch", "Right DAC1" }, \ 876 { _sink, "Left DAC1 Switch", "Left DAC1" }, \ 877 { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \ 878 { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \ 879 { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \ 880 { _sink, "Input 4 Bypass Switch", "IN4PGA" } 881 882 #define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \ 883 { _sink, "Right DAC2 Switch", "Right DAC2" }, \ 884 { _sink, "Left DAC2 Switch", "Left DAC2" }, \ 885 { _sink, "Right DAC1 Switch", "Right DAC1" }, \ 886 { _sink, "Left DAC1 Switch", "Left DAC1" }, \ 887 { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \ 888 { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \ 889 { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \ 890 { _sink, "Input 4 Bypass Switch", "IN4PGA" } 891 892 static const struct snd_soc_dapm_route adau1373_dapm_routes[] = { 893 { "Left ADC Mixer", "DAC1 Switch", "Left DAC1" }, 894 { "Left ADC Mixer", "Input 1 Switch", "IN1PGA" }, 895 { "Left ADC Mixer", "Input 2 Switch", "IN2PGA" }, 896 { "Left ADC Mixer", "Input 3 Switch", "IN3PGA" }, 897 { "Left ADC Mixer", "Input 4 Switch", "IN4PGA" }, 898 899 { "Right ADC Mixer", "DAC1 Switch", "Right DAC1" }, 900 { "Right ADC Mixer", "Input 1 Switch", "IN1PGA" }, 901 { "Right ADC Mixer", "Input 2 Switch", "IN2PGA" }, 902 { "Right ADC Mixer", "Input 3 Switch", "IN3PGA" }, 903 { "Right ADC Mixer", "Input 4 Switch", "IN4PGA" }, 904 905 { "Left ADC", NULL, "Left ADC Mixer" }, 906 { "Right ADC", NULL, "Right ADC Mixer" }, 907 908 { "Decimator Mux", "ADC", "Left ADC" }, 909 { "Decimator Mux", "ADC", "Right ADC" }, 910 { "Decimator Mux", "DMIC1", "DMIC1" }, 911 912 DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"), 913 DSP_CHANNEL_MIXER_ROUTES("DSP Channel2 Mixer"), 914 DSP_CHANNEL_MIXER_ROUTES("DSP Channel3 Mixer"), 915 DSP_CHANNEL_MIXER_ROUTES("DSP Channel4 Mixer"), 916 DSP_CHANNEL_MIXER_ROUTES("DSP Channel5 Mixer"), 917 918 DSP_OUTPUT_MIXER_ROUTES("AIF1 Mixer"), 919 DSP_OUTPUT_MIXER_ROUTES("AIF2 Mixer"), 920 DSP_OUTPUT_MIXER_ROUTES("AIF3 Mixer"), 921 DSP_OUTPUT_MIXER_ROUTES("DAC1 Mixer"), 922 DSP_OUTPUT_MIXER_ROUTES("DAC2 Mixer"), 923 924 { "AIF1 OUT", NULL, "AIF1 Mixer" }, 925 { "AIF2 OUT", NULL, "AIF2 Mixer" }, 926 { "AIF3 OUT", NULL, "AIF3 Mixer" }, 927 { "Left DAC1", NULL, "DAC1 Mixer" }, 928 { "Right DAC1", NULL, "DAC1 Mixer" }, 929 { "Left DAC2", NULL, "DAC2 Mixer" }, 930 { "Right DAC2", NULL, "DAC2 Mixer" }, 931 932 LEFT_OUTPUT_MIXER_ROUTES("Left Lineout1 Mixer"), 933 RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout1 Mixer"), 934 LEFT_OUTPUT_MIXER_ROUTES("Left Lineout2 Mixer"), 935 RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout2 Mixer"), 936 LEFT_OUTPUT_MIXER_ROUTES("Left Speaker Mixer"), 937 RIGHT_OUTPUT_MIXER_ROUTES("Right Speaker Mixer"), 938 939 { "Left Headphone Mixer", "Left DAC2 Switch", "Left DAC2" }, 940 { "Left Headphone Mixer", "Left DAC1 Switch", "Left DAC1" }, 941 { "Left Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" }, 942 { "Left Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" }, 943 { "Left Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" }, 944 { "Left Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" }, 945 { "Right Headphone Mixer", "Right DAC2 Switch", "Right DAC2" }, 946 { "Right Headphone Mixer", "Right DAC1 Switch", "Right DAC1" }, 947 { "Right Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" }, 948 { "Right Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" }, 949 { "Right Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" }, 950 { "Right Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" }, 951 952 { "Left Headphone Mixer", NULL, "Headphone Enable" }, 953 { "Right Headphone Mixer", NULL, "Headphone Enable" }, 954 955 { "Earpiece Mixer", "Right DAC2 Switch", "Right DAC2" }, 956 { "Earpiece Mixer", "Left DAC2 Switch", "Left DAC2" }, 957 { "Earpiece Mixer", "Right DAC1 Switch", "Right DAC1" }, 958 { "Earpiece Mixer", "Left DAC1 Switch", "Left DAC1" }, 959 { "Earpiece Mixer", "Input 1 Bypass Switch", "IN1PGA" }, 960 { "Earpiece Mixer", "Input 2 Bypass Switch", "IN2PGA" }, 961 { "Earpiece Mixer", "Input 3 Bypass Switch", "IN3PGA" }, 962 { "Earpiece Mixer", "Input 4 Bypass Switch", "IN4PGA" }, 963 964 { "LOUT1L", NULL, "Left Lineout1 Mixer" }, 965 { "LOUT1R", NULL, "Right Lineout1 Mixer" }, 966 { "LOUT2L", NULL, "Left Lineout2 Mixer" }, 967 { "LOUT2R", NULL, "Right Lineout2 Mixer" }, 968 { "SPKL", NULL, "Left Speaker Mixer" }, 969 { "SPKR", NULL, "Right Speaker Mixer" }, 970 { "HPL", NULL, "Left Headphone Mixer" }, 971 { "HPR", NULL, "Right Headphone Mixer" }, 972 { "EP", NULL, "Earpiece Mixer" }, 973 974 { "IN1PGA", NULL, "AIN1L" }, 975 { "IN2PGA", NULL, "AIN2L" }, 976 { "IN3PGA", NULL, "AIN3L" }, 977 { "IN4PGA", NULL, "AIN4L" }, 978 { "IN1PGA", NULL, "AIN1R" }, 979 { "IN2PGA", NULL, "AIN2R" }, 980 { "IN3PGA", NULL, "AIN3R" }, 981 { "IN4PGA", NULL, "AIN4R" }, 982 983 { "SYSCLK1", NULL, "PLL1" }, 984 { "SYSCLK2", NULL, "PLL2" }, 985 986 { "Left DAC1", NULL, "SYSCLK1" }, 987 { "Right DAC1", NULL, "SYSCLK1" }, 988 { "Left DAC2", NULL, "SYSCLK1" }, 989 { "Right DAC2", NULL, "SYSCLK1" }, 990 { "Left ADC", NULL, "SYSCLK1" }, 991 { "Right ADC", NULL, "SYSCLK1" }, 992 993 { "DSP", NULL, "SYSCLK1" }, 994 995 { "AIF1 Mixer", NULL, "DSP" }, 996 { "AIF2 Mixer", NULL, "DSP" }, 997 { "AIF3 Mixer", NULL, "DSP" }, 998 { "DAC1 Mixer", NULL, "DSP" }, 999 { "DAC2 Mixer", NULL, "DSP" }, 1000 { "DAC1 Mixer", NULL, "Playback Engine A" }, 1001 { "DAC2 Mixer", NULL, "Playback Engine B" }, 1002 { "Left ADC Mixer", NULL, "Recording Engine A" }, 1003 { "Right ADC Mixer", NULL, "Recording Engine A" }, 1004 1005 { "AIF1 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk }, 1006 { "AIF2 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk }, 1007 { "AIF3 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk }, 1008 { "AIF1 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk }, 1009 { "AIF2 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk }, 1010 { "AIF3 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk }, 1011 1012 { "AIF1 IN", NULL, "AIF1 CLK" }, 1013 { "AIF1 OUT", NULL, "AIF1 CLK" }, 1014 { "AIF2 IN", NULL, "AIF2 CLK" }, 1015 { "AIF2 OUT", NULL, "AIF2 CLK" }, 1016 { "AIF3 IN", NULL, "AIF3 CLK" }, 1017 { "AIF3 OUT", NULL, "AIF3 CLK" }, 1018 { "AIF1 IN", NULL, "AIF1 IN SRC", adau1373_check_src }, 1019 { "AIF1 OUT", NULL, "AIF1 OUT SRC", adau1373_check_src }, 1020 { "AIF2 IN", NULL, "AIF2 IN SRC", adau1373_check_src }, 1021 { "AIF2 OUT", NULL, "AIF2 OUT SRC", adau1373_check_src }, 1022 { "AIF3 IN", NULL, "AIF3 IN SRC", adau1373_check_src }, 1023 { "AIF3 OUT", NULL, "AIF3 OUT SRC", adau1373_check_src }, 1024 1025 { "DMIC1", NULL, "DMIC1DAT" }, 1026 { "DMIC1", NULL, "SYSCLK1" }, 1027 { "DMIC1", NULL, "Recording Engine A" }, 1028 { "DMIC2", NULL, "DMIC2DAT" }, 1029 { "DMIC2", NULL, "SYSCLK1" }, 1030 { "DMIC2", NULL, "Recording Engine B" }, 1031 }; 1032 1033 static int adau1373_hw_params(struct snd_pcm_substream *substream, 1034 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1035 { 1036 struct snd_soc_codec *codec = dai->codec; 1037 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 1038 struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id]; 1039 unsigned int div; 1040 unsigned int freq; 1041 unsigned int ctrl; 1042 1043 freq = adau1373_dai->sysclk; 1044 1045 if (freq % params_rate(params) != 0) 1046 return -EINVAL; 1047 1048 switch (freq / params_rate(params)) { 1049 case 1024: /* sysclk / 256 */ 1050 div = 0; 1051 break; 1052 case 1536: /* 2/3 sysclk / 256 */ 1053 div = 1; 1054 break; 1055 case 2048: /* 1/2 sysclk / 256 */ 1056 div = 2; 1057 break; 1058 case 3072: /* 1/3 sysclk / 256 */ 1059 div = 3; 1060 break; 1061 case 4096: /* 1/4 sysclk / 256 */ 1062 div = 4; 1063 break; 1064 case 6144: /* 1/6 sysclk / 256 */ 1065 div = 5; 1066 break; 1067 case 5632: /* 2/11 sysclk / 256 */ 1068 div = 6; 1069 break; 1070 default: 1071 return -EINVAL; 1072 } 1073 1074 adau1373_dai->enable_src = (div != 0); 1075 1076 regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id), 1077 ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK, 1078 (div << 2) | ADAU1373_BCLKDIV_64); 1079 1080 switch (params_width(params)) { 1081 case 16: 1082 ctrl = ADAU1373_DAI_WLEN_16; 1083 break; 1084 case 20: 1085 ctrl = ADAU1373_DAI_WLEN_20; 1086 break; 1087 case 24: 1088 ctrl = ADAU1373_DAI_WLEN_24; 1089 break; 1090 case 32: 1091 ctrl = ADAU1373_DAI_WLEN_32; 1092 break; 1093 default: 1094 return -EINVAL; 1095 } 1096 1097 return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id), 1098 ADAU1373_DAI_WLEN_MASK, ctrl); 1099 } 1100 1101 static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1102 { 1103 struct snd_soc_codec *codec = dai->codec; 1104 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 1105 struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id]; 1106 unsigned int ctrl; 1107 1108 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1109 case SND_SOC_DAIFMT_CBM_CFM: 1110 ctrl = ADAU1373_DAI_MASTER; 1111 adau1373_dai->master = true; 1112 break; 1113 case SND_SOC_DAIFMT_CBS_CFS: 1114 ctrl = 0; 1115 adau1373_dai->master = false; 1116 break; 1117 default: 1118 return -EINVAL; 1119 } 1120 1121 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1122 case SND_SOC_DAIFMT_I2S: 1123 ctrl |= ADAU1373_DAI_FORMAT_I2S; 1124 break; 1125 case SND_SOC_DAIFMT_LEFT_J: 1126 ctrl |= ADAU1373_DAI_FORMAT_LEFT_J; 1127 break; 1128 case SND_SOC_DAIFMT_RIGHT_J: 1129 ctrl |= ADAU1373_DAI_FORMAT_RIGHT_J; 1130 break; 1131 case SND_SOC_DAIFMT_DSP_B: 1132 ctrl |= ADAU1373_DAI_FORMAT_DSP; 1133 break; 1134 default: 1135 return -EINVAL; 1136 } 1137 1138 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1139 case SND_SOC_DAIFMT_NB_NF: 1140 break; 1141 case SND_SOC_DAIFMT_IB_NF: 1142 ctrl |= ADAU1373_DAI_INVERT_BCLK; 1143 break; 1144 case SND_SOC_DAIFMT_NB_IF: 1145 ctrl |= ADAU1373_DAI_INVERT_LRCLK; 1146 break; 1147 case SND_SOC_DAIFMT_IB_IF: 1148 ctrl |= ADAU1373_DAI_INVERT_LRCLK | ADAU1373_DAI_INVERT_BCLK; 1149 break; 1150 default: 1151 return -EINVAL; 1152 } 1153 1154 regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id), 1155 ~ADAU1373_DAI_WLEN_MASK, ctrl); 1156 1157 return 0; 1158 } 1159 1160 static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai, 1161 int clk_id, unsigned int freq, int dir) 1162 { 1163 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(dai->codec); 1164 struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id]; 1165 1166 switch (clk_id) { 1167 case ADAU1373_CLK_SRC_PLL1: 1168 case ADAU1373_CLK_SRC_PLL2: 1169 break; 1170 default: 1171 return -EINVAL; 1172 } 1173 1174 adau1373_dai->sysclk = freq; 1175 adau1373_dai->clk_src = clk_id; 1176 1177 regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id), 1178 ADAU1373_BCLKDIV_SOURCE, clk_id << 5); 1179 1180 return 0; 1181 } 1182 1183 static const struct snd_soc_dai_ops adau1373_dai_ops = { 1184 .hw_params = adau1373_hw_params, 1185 .set_sysclk = adau1373_set_dai_sysclk, 1186 .set_fmt = adau1373_set_dai_fmt, 1187 }; 1188 1189 #define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1190 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1191 1192 static struct snd_soc_dai_driver adau1373_dai_driver[] = { 1193 { 1194 .id = 0, 1195 .name = "adau1373-aif1", 1196 .playback = { 1197 .stream_name = "AIF1 Playback", 1198 .channels_min = 2, 1199 .channels_max = 2, 1200 .rates = SNDRV_PCM_RATE_8000_48000, 1201 .formats = ADAU1373_FORMATS, 1202 }, 1203 .capture = { 1204 .stream_name = "AIF1 Capture", 1205 .channels_min = 2, 1206 .channels_max = 2, 1207 .rates = SNDRV_PCM_RATE_8000_48000, 1208 .formats = ADAU1373_FORMATS, 1209 }, 1210 .ops = &adau1373_dai_ops, 1211 .symmetric_rates = 1, 1212 }, 1213 { 1214 .id = 1, 1215 .name = "adau1373-aif2", 1216 .playback = { 1217 .stream_name = "AIF2 Playback", 1218 .channels_min = 2, 1219 .channels_max = 2, 1220 .rates = SNDRV_PCM_RATE_8000_48000, 1221 .formats = ADAU1373_FORMATS, 1222 }, 1223 .capture = { 1224 .stream_name = "AIF2 Capture", 1225 .channels_min = 2, 1226 .channels_max = 2, 1227 .rates = SNDRV_PCM_RATE_8000_48000, 1228 .formats = ADAU1373_FORMATS, 1229 }, 1230 .ops = &adau1373_dai_ops, 1231 .symmetric_rates = 1, 1232 }, 1233 { 1234 .id = 2, 1235 .name = "adau1373-aif3", 1236 .playback = { 1237 .stream_name = "AIF3 Playback", 1238 .channels_min = 2, 1239 .channels_max = 2, 1240 .rates = SNDRV_PCM_RATE_8000_48000, 1241 .formats = ADAU1373_FORMATS, 1242 }, 1243 .capture = { 1244 .stream_name = "AIF3 Capture", 1245 .channels_min = 2, 1246 .channels_max = 2, 1247 .rates = SNDRV_PCM_RATE_8000_48000, 1248 .formats = ADAU1373_FORMATS, 1249 }, 1250 .ops = &adau1373_dai_ops, 1251 .symmetric_rates = 1, 1252 }, 1253 }; 1254 1255 static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id, 1256 int source, unsigned int freq_in, unsigned int freq_out) 1257 { 1258 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 1259 unsigned int dpll_div = 0; 1260 unsigned int x, r, n, m, i, j, mode; 1261 1262 switch (pll_id) { 1263 case ADAU1373_PLL1: 1264 case ADAU1373_PLL2: 1265 break; 1266 default: 1267 return -EINVAL; 1268 } 1269 1270 switch (source) { 1271 case ADAU1373_PLL_SRC_BCLK1: 1272 case ADAU1373_PLL_SRC_BCLK2: 1273 case ADAU1373_PLL_SRC_BCLK3: 1274 case ADAU1373_PLL_SRC_LRCLK1: 1275 case ADAU1373_PLL_SRC_LRCLK2: 1276 case ADAU1373_PLL_SRC_LRCLK3: 1277 case ADAU1373_PLL_SRC_MCLK1: 1278 case ADAU1373_PLL_SRC_MCLK2: 1279 case ADAU1373_PLL_SRC_GPIO1: 1280 case ADAU1373_PLL_SRC_GPIO2: 1281 case ADAU1373_PLL_SRC_GPIO3: 1282 case ADAU1373_PLL_SRC_GPIO4: 1283 break; 1284 default: 1285 return -EINVAL; 1286 } 1287 1288 if (freq_in < 7813 || freq_in > 27000000) 1289 return -EINVAL; 1290 1291 if (freq_out < 45158000 || freq_out > 49152000) 1292 return -EINVAL; 1293 1294 /* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the 1295 * DPLL to get it there. DPLL_out = (DPLL_in / div) * 1024 */ 1296 while (freq_in < 8000000) { 1297 freq_in *= 2; 1298 dpll_div++; 1299 } 1300 1301 if (freq_out % freq_in != 0) { 1302 /* fout = fin * (r + (n/m)) / x */ 1303 x = DIV_ROUND_UP(freq_in, 13500000); 1304 freq_in /= x; 1305 r = freq_out / freq_in; 1306 i = freq_out % freq_in; 1307 j = gcd(i, freq_in); 1308 n = i / j; 1309 m = freq_in / j; 1310 x--; 1311 mode = 1; 1312 } else { 1313 /* fout = fin / r */ 1314 r = freq_out / freq_in; 1315 n = 0; 1316 m = 0; 1317 x = 0; 1318 mode = 0; 1319 } 1320 1321 if (r < 2 || r > 8 || x > 3 || m > 0xffff || n > 0xffff) 1322 return -EINVAL; 1323 1324 if (dpll_div) { 1325 dpll_div = 11 - dpll_div; 1326 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id), 1327 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0); 1328 } else { 1329 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id), 1330 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 1331 ADAU1373_PLL_CTRL6_DPLL_BYPASS); 1332 } 1333 1334 regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id), 1335 (source << 4) | dpll_div); 1336 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), (m >> 8) & 0xff); 1337 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), m & 0xff); 1338 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), (n >> 8) & 0xff); 1339 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), n & 0xff); 1340 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), 1341 (r << 3) | (x << 1) | mode); 1342 1343 /* Set sysclk to pll_rate / 4 */ 1344 regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09); 1345 1346 return 0; 1347 } 1348 1349 static void adau1373_load_drc_settings(struct adau1373 *adau1373, 1350 unsigned int nr, uint8_t *drc) 1351 { 1352 unsigned int i; 1353 1354 for (i = 0; i < ADAU1373_DRC_SIZE; ++i) 1355 regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]); 1356 } 1357 1358 static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias) 1359 { 1360 switch (micbias) { 1361 case ADAU1373_MICBIAS_2_9V: 1362 case ADAU1373_MICBIAS_2_2V: 1363 case ADAU1373_MICBIAS_2_6V: 1364 case ADAU1373_MICBIAS_1_8V: 1365 return true; 1366 default: 1367 break; 1368 } 1369 return false; 1370 } 1371 1372 static int adau1373_probe(struct snd_soc_codec *codec) 1373 { 1374 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 1375 struct adau1373_platform_data *pdata = codec->dev->platform_data; 1376 bool lineout_differential = false; 1377 unsigned int val; 1378 int i; 1379 1380 if (pdata) { 1381 if (pdata->num_drc > ARRAY_SIZE(pdata->drc_setting)) 1382 return -EINVAL; 1383 1384 if (!adau1373_valid_micbias(pdata->micbias1) || 1385 !adau1373_valid_micbias(pdata->micbias2)) 1386 return -EINVAL; 1387 1388 for (i = 0; i < pdata->num_drc; ++i) { 1389 adau1373_load_drc_settings(adau1373, i, 1390 pdata->drc_setting[i]); 1391 } 1392 1393 snd_soc_add_codec_controls(codec, adau1373_drc_controls, 1394 pdata->num_drc); 1395 1396 val = 0; 1397 for (i = 0; i < 4; ++i) { 1398 if (pdata->input_differential[i]) 1399 val |= BIT(i); 1400 } 1401 regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val); 1402 1403 val = 0; 1404 if (pdata->lineout_differential) 1405 val |= ADAU1373_OUTPUT_CTRL_LDIFF; 1406 if (pdata->lineout_ground_sense) 1407 val |= ADAU1373_OUTPUT_CTRL_LNFBEN; 1408 regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val); 1409 1410 lineout_differential = pdata->lineout_differential; 1411 1412 regmap_write(adau1373->regmap, ADAU1373_EP_CTRL, 1413 (pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) | 1414 (pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET)); 1415 } 1416 1417 if (!lineout_differential) { 1418 snd_soc_add_codec_controls(codec, adau1373_lineout2_controls, 1419 ARRAY_SIZE(adau1373_lineout2_controls)); 1420 } 1421 1422 regmap_write(adau1373->regmap, ADAU1373_ADC_CTRL, 1423 ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT); 1424 1425 return 0; 1426 } 1427 1428 static int adau1373_set_bias_level(struct snd_soc_codec *codec, 1429 enum snd_soc_bias_level level) 1430 { 1431 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 1432 1433 switch (level) { 1434 case SND_SOC_BIAS_ON: 1435 break; 1436 case SND_SOC_BIAS_PREPARE: 1437 break; 1438 case SND_SOC_BIAS_STANDBY: 1439 regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3, 1440 ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN); 1441 break; 1442 case SND_SOC_BIAS_OFF: 1443 regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3, 1444 ADAU1373_PWDN_CTRL3_PWR_EN, 0); 1445 break; 1446 } 1447 codec->dapm.bias_level = level; 1448 return 0; 1449 } 1450 1451 static int adau1373_resume(struct snd_soc_codec *codec) 1452 { 1453 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec); 1454 1455 regcache_sync(adau1373->regmap); 1456 1457 return 0; 1458 } 1459 1460 static bool adau1373_register_volatile(struct device *dev, unsigned int reg) 1461 { 1462 switch (reg) { 1463 case ADAU1373_SOFT_RESET: 1464 case ADAU1373_ADC_DAC_STATUS: 1465 return true; 1466 default: 1467 return false; 1468 } 1469 } 1470 1471 static const struct regmap_config adau1373_regmap_config = { 1472 .val_bits = 8, 1473 .reg_bits = 8, 1474 1475 .volatile_reg = adau1373_register_volatile, 1476 .max_register = ADAU1373_SOFT_RESET, 1477 1478 .cache_type = REGCACHE_RBTREE, 1479 .reg_defaults = adau1373_reg_defaults, 1480 .num_reg_defaults = ARRAY_SIZE(adau1373_reg_defaults), 1481 }; 1482 1483 static struct snd_soc_codec_driver adau1373_codec_driver = { 1484 .probe = adau1373_probe, 1485 .resume = adau1373_resume, 1486 .set_bias_level = adau1373_set_bias_level, 1487 .idle_bias_off = true, 1488 1489 .set_pll = adau1373_set_pll, 1490 1491 .controls = adau1373_controls, 1492 .num_controls = ARRAY_SIZE(adau1373_controls), 1493 .dapm_widgets = adau1373_dapm_widgets, 1494 .num_dapm_widgets = ARRAY_SIZE(adau1373_dapm_widgets), 1495 .dapm_routes = adau1373_dapm_routes, 1496 .num_dapm_routes = ARRAY_SIZE(adau1373_dapm_routes), 1497 }; 1498 1499 static int adau1373_i2c_probe(struct i2c_client *client, 1500 const struct i2c_device_id *id) 1501 { 1502 struct adau1373 *adau1373; 1503 int ret; 1504 1505 adau1373 = devm_kzalloc(&client->dev, sizeof(*adau1373), GFP_KERNEL); 1506 if (!adau1373) 1507 return -ENOMEM; 1508 1509 adau1373->regmap = devm_regmap_init_i2c(client, 1510 &adau1373_regmap_config); 1511 if (IS_ERR(adau1373->regmap)) 1512 return PTR_ERR(adau1373->regmap); 1513 1514 regmap_write(adau1373->regmap, ADAU1373_SOFT_RESET, 0x00); 1515 1516 dev_set_drvdata(&client->dev, adau1373); 1517 1518 ret = snd_soc_register_codec(&client->dev, &adau1373_codec_driver, 1519 adau1373_dai_driver, ARRAY_SIZE(adau1373_dai_driver)); 1520 return ret; 1521 } 1522 1523 static int adau1373_i2c_remove(struct i2c_client *client) 1524 { 1525 snd_soc_unregister_codec(&client->dev); 1526 return 0; 1527 } 1528 1529 static const struct i2c_device_id adau1373_i2c_id[] = { 1530 { "adau1373", 0 }, 1531 { } 1532 }; 1533 MODULE_DEVICE_TABLE(i2c, adau1373_i2c_id); 1534 1535 static struct i2c_driver adau1373_i2c_driver = { 1536 .driver = { 1537 .name = "adau1373", 1538 .owner = THIS_MODULE, 1539 }, 1540 .probe = adau1373_i2c_probe, 1541 .remove = adau1373_i2c_remove, 1542 .id_table = adau1373_i2c_id, 1543 }; 1544 1545 module_i2c_driver(adau1373_i2c_driver); 1546 1547 MODULE_DESCRIPTION("ASoC ADAU1373 driver"); 1548 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1549 MODULE_LICENSE("GPL"); 1550