1 /* 2 * Copyright (C) ST-Ericsson SA 2012 3 * 4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 5 * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>, 6 * Roger Nilsson <roger.xr.nilsson@stericsson.com>, 7 * for ST-Ericsson. 8 * 9 * Based on the early work done by: 10 * Mikko J. Lehto <mikko.lehto@symbio.com>, 11 * Mikko Sarmanne <mikko.sarmanne@symbio.com>, 12 * Jarmo K. Kuronen <jarmo.kuronen@symbio.com>, 13 * for ST-Ericsson. 14 * 15 * License terms: 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License version 2 as published 19 * by the Free Software Foundation. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/device.h> 25 #include <linux/slab.h> 26 #include <linux/moduleparam.h> 27 #include <linux/init.h> 28 #include <linux/delay.h> 29 #include <linux/pm.h> 30 #include <linux/platform_device.h> 31 #include <linux/mutex.h> 32 #include <linux/mfd/abx500/ab8500.h> 33 #include <linux/mfd/abx500.h> 34 #include <linux/mfd/abx500/ab8500-sysctrl.h> 35 #include <linux/mfd/abx500/ab8500-codec.h> 36 #include <linux/regulator/consumer.h> 37 #include <linux/of.h> 38 39 #include <sound/core.h> 40 #include <sound/pcm.h> 41 #include <sound/pcm_params.h> 42 #include <sound/initval.h> 43 #include <sound/soc.h> 44 #include <sound/soc-dapm.h> 45 #include <sound/tlv.h> 46 47 #include "ab8500-codec.h" 48 49 /* Macrocell value definitions */ 50 #define CLK_32K_OUT2_DISABLE 0x01 51 #define INACTIVE_RESET_AUDIO 0x02 52 #define ENABLE_AUDIO_CLK_TO_AUDIO_BLK 0x10 53 #define ENABLE_VINTCORE12_SUPPLY 0x04 54 #define GPIO27_DIR_OUTPUT 0x04 55 #define GPIO29_DIR_OUTPUT 0x10 56 #define GPIO31_DIR_OUTPUT 0x40 57 58 /* Macrocell register definitions */ 59 #define AB8500_GPIO_DIR4_REG 0x13 /* Bank AB8500_MISC */ 60 61 /* Nr of FIR/IIR-coeff banks in ANC-block */ 62 #define AB8500_NR_OF_ANC_COEFF_BANKS 2 63 64 /* Minimum duration to keep ANC IIR Init bit high or 65 low before proceeding with the configuration sequence */ 66 #define AB8500_ANC_SM_DELAY 2000 67 68 #define AB8500_FILTER_CONTROL(xname, xcount, xmin, xmax) \ 69 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 70 .info = filter_control_info, \ 71 .get = filter_control_get, .put = filter_control_put, \ 72 .private_value = (unsigned long)&(struct filter_control) \ 73 {.count = xcount, .min = xmin, .max = xmax} } 74 75 struct filter_control { 76 long min, max; 77 unsigned int count; 78 long value[128]; 79 }; 80 81 /* Sidetone states */ 82 static const char * const enum_sid_state[] = { 83 "Unconfigured", 84 "Apply FIR", 85 "FIR is configured", 86 }; 87 enum sid_state { 88 SID_UNCONFIGURED = 0, 89 SID_APPLY_FIR = 1, 90 SID_FIR_CONFIGURED = 2, 91 }; 92 93 static const char * const enum_anc_state[] = { 94 "Unconfigured", 95 "Apply FIR and IIR", 96 "FIR and IIR are configured", 97 "Apply FIR", 98 "FIR is configured", 99 "Apply IIR", 100 "IIR is configured" 101 }; 102 enum anc_state { 103 ANC_UNCONFIGURED = 0, 104 ANC_APPLY_FIR_IIR = 1, 105 ANC_FIR_IIR_CONFIGURED = 2, 106 ANC_APPLY_FIR = 3, 107 ANC_FIR_CONFIGURED = 4, 108 ANC_APPLY_IIR = 5, 109 ANC_IIR_CONFIGURED = 6 110 }; 111 112 /* Analog microphones */ 113 enum amic_idx { 114 AMIC_IDX_1A, 115 AMIC_IDX_1B, 116 AMIC_IDX_2 117 }; 118 119 struct ab8500_codec_drvdata_dbg { 120 struct regulator *vaud; 121 struct regulator *vamic1; 122 struct regulator *vamic2; 123 struct regulator *vdmic; 124 }; 125 126 /* Private data for AB8500 device-driver */ 127 struct ab8500_codec_drvdata { 128 struct regmap *regmap; 129 struct mutex ctrl_lock; 130 131 /* Sidetone */ 132 long *sid_fir_values; 133 enum sid_state sid_status; 134 135 /* ANC */ 136 long *anc_fir_values; 137 long *anc_iir_values; 138 enum anc_state anc_status; 139 }; 140 141 static inline const char *amic_micbias_str(enum amic_micbias micbias) 142 { 143 switch (micbias) { 144 case AMIC_MICBIAS_VAMIC1: 145 return "VAMIC1"; 146 case AMIC_MICBIAS_VAMIC2: 147 return "VAMIC2"; 148 default: 149 return "Unknown"; 150 } 151 } 152 153 static inline const char *amic_type_str(enum amic_type type) 154 { 155 switch (type) { 156 case AMIC_TYPE_DIFFERENTIAL: 157 return "DIFFERENTIAL"; 158 case AMIC_TYPE_SINGLE_ENDED: 159 return "SINGLE ENDED"; 160 default: 161 return "Unknown"; 162 } 163 } 164 165 /* 166 * Read'n'write functions 167 */ 168 169 /* Read a register from the audio-bank of AB8500 */ 170 static int ab8500_codec_read_reg(void *context, unsigned int reg, 171 unsigned int *value) 172 { 173 struct device *dev = context; 174 int status; 175 176 u8 value8; 177 status = abx500_get_register_interruptible(dev, AB8500_AUDIO, 178 reg, &value8); 179 *value = (unsigned int)value8; 180 181 return status; 182 } 183 184 /* Write to a register in the audio-bank of AB8500 */ 185 static int ab8500_codec_write_reg(void *context, unsigned int reg, 186 unsigned int value) 187 { 188 struct device *dev = context; 189 190 return abx500_set_register_interruptible(dev, AB8500_AUDIO, 191 reg, value); 192 } 193 194 static const struct regmap_config ab8500_codec_regmap = { 195 .reg_read = ab8500_codec_read_reg, 196 .reg_write = ab8500_codec_write_reg, 197 }; 198 199 /* 200 * Controls - DAPM 201 */ 202 203 /* Earpiece */ 204 205 /* Earpiece source selector */ 206 static const char * const enum_ear_lineout_source[] = {"Headset Left", 207 "Speaker Left"}; 208 static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF, 209 AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source); 210 static const struct snd_kcontrol_new dapm_ear_lineout_source = 211 SOC_DAPM_ENUM("Earpiece or LineOut Mono Source", 212 dapm_enum_ear_lineout_source); 213 214 /* LineOut */ 215 216 /* LineOut source selector */ 217 static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"}; 218 static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5, 219 AB8500_ANACONF5_HSLDACTOLOL, 220 AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source); 221 static const struct snd_kcontrol_new dapm_lineout_source[] = { 222 SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source), 223 }; 224 225 /* Handsfree */ 226 227 /* Speaker Left - ANC selector */ 228 static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"}; 229 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2, 230 AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel); 231 static const struct snd_kcontrol_new dapm_HFl_select[] = { 232 SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel), 233 }; 234 235 /* Speaker Right - ANC selector */ 236 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2, 237 AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel); 238 static const struct snd_kcontrol_new dapm_HFr_select[] = { 239 SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel), 240 }; 241 242 /* Mic 1 */ 243 244 /* Mic 1 - Mic 1a or 1b selector */ 245 static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"}; 246 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3, 247 AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel); 248 static const struct snd_kcontrol_new dapm_mic1ab_mux[] = { 249 SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel), 250 }; 251 252 /* Mic 1 - AD3 - Mic 1 or DMic 3 selector */ 253 static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"}; 254 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1, 255 AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel); 256 static const struct snd_kcontrol_new dapm_ad3_select[] = { 257 SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel), 258 }; 259 260 /* Mic 1 - AD6 - Mic 1 or DMic 6 selector */ 261 static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"}; 262 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1, 263 AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel); 264 static const struct snd_kcontrol_new dapm_ad6_select[] = { 265 SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel), 266 }; 267 268 /* Mic 2 */ 269 270 /* Mic 2 - AD5 - Mic 2 or DMic 5 selector */ 271 static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"}; 272 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1, 273 AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel); 274 static const struct snd_kcontrol_new dapm_ad5_select[] = { 275 SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel), 276 }; 277 278 /* LineIn */ 279 280 /* LineIn left - AD1 - LineIn Left or DMic 1 selector */ 281 static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"}; 282 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1, 283 AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel); 284 static const struct snd_kcontrol_new dapm_ad1_select[] = { 285 SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel), 286 }; 287 288 /* LineIn right - Mic 2 or LineIn Right selector */ 289 static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"}; 290 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3, 291 AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel); 292 static const struct snd_kcontrol_new dapm_mic2lr_select[] = { 293 SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel), 294 }; 295 296 /* LineIn right - AD2 - LineIn Right or DMic2 selector */ 297 static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"}; 298 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1, 299 AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel); 300 static const struct snd_kcontrol_new dapm_ad2_select[] = { 301 SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel), 302 }; 303 304 305 /* ANC */ 306 307 static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6", 308 "Mic 2 / DMic 5"}; 309 static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF, 310 AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel); 311 static const struct snd_kcontrol_new dapm_anc_in_select[] = { 312 SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel), 313 }; 314 315 /* ANC - Enable/Disable */ 316 static const struct snd_kcontrol_new dapm_anc_enable[] = { 317 SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1, 318 AB8500_ANCCONF1_ENANC, 0, 0), 319 }; 320 321 /* ANC to Earpiece - Mute */ 322 static const struct snd_kcontrol_new dapm_anc_ear_mute[] = { 323 SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1, 324 AB8500_DIGMULTCONF1_ANCSEL, 1, 0), 325 }; 326 327 328 329 /* Sidetone left */ 330 331 /* Sidetone left - Input selector */ 332 static const char * const enum_stfir1_in_sel[] = { 333 "LineIn Left", "LineIn Right", "Mic 1", "Headset Left" 334 }; 335 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2, 336 AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel); 337 static const struct snd_kcontrol_new dapm_stfir1_in_select[] = { 338 SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel), 339 }; 340 341 /* Sidetone right path */ 342 343 /* Sidetone right - Input selector */ 344 static const char * const enum_stfir2_in_sel[] = { 345 "LineIn Right", "Mic 1", "DMic 4", "Headset Right" 346 }; 347 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2, 348 AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel); 349 static const struct snd_kcontrol_new dapm_stfir2_in_select[] = { 350 SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel), 351 }; 352 353 /* Vibra */ 354 355 static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"}; 356 357 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1, 358 AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx); 359 360 static const struct snd_kcontrol_new dapm_pwm2vib1[] = { 361 SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1), 362 }; 363 364 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1, 365 AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx); 366 367 static const struct snd_kcontrol_new dapm_pwm2vib2[] = { 368 SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2), 369 }; 370 371 /* 372 * DAPM-widgets 373 */ 374 375 static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = { 376 377 /* Clocks */ 378 SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"), 379 380 /* Regulators */ 381 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0), 382 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0), 383 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0), 384 SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0), 385 386 /* Power */ 387 SND_SOC_DAPM_SUPPLY("Audio Power", 388 AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0, 389 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 390 SND_SOC_DAPM_SUPPLY("Audio Analog Power", 391 AB8500_POWERUP, AB8500_POWERUP_ENANA, 0, 392 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 393 394 /* Main supply node */ 395 SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0, 396 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 397 398 /* DA/AD */ 399 400 SND_SOC_DAPM_INPUT("ADC Input"), 401 SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0), 402 403 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 404 SND_SOC_DAPM_OUTPUT("DAC Output"), 405 406 SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0), 407 SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0), 408 SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0), 409 SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0), 410 SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0), 411 SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0), 412 SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0), 413 SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0), 414 SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0), 415 SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0), 416 SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0), 417 SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0), 418 419 /* Headset path */ 420 421 SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5, 422 AB8500_ANACONF5_ENCPHS, 0, NULL, 0), 423 424 SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p", 425 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0), 426 SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p", 427 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0), 428 429 SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0, 430 NULL, 0), 431 SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0, 432 NULL, 0), 433 434 SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p", 435 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0), 436 SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p", 437 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0), 438 SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF, 439 AB8500_MUTECONF_MUTDACHSL, 1, 440 NULL, 0), 441 SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF, 442 AB8500_MUTECONF_MUTDACHSR, 1, 443 NULL, 0), 444 SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p", 445 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0), 446 SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p", 447 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0), 448 449 SND_SOC_DAPM_MIXER("HSL Mute", 450 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1, 451 NULL, 0), 452 SND_SOC_DAPM_MIXER("HSR Mute", 453 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1, 454 NULL, 0), 455 SND_SOC_DAPM_MIXER("HSL Enable", 456 AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0, 457 NULL, 0), 458 SND_SOC_DAPM_MIXER("HSR Enable", 459 AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0, 460 NULL, 0), 461 SND_SOC_DAPM_PGA("HSL Volume", 462 SND_SOC_NOPM, 0, 0, 463 NULL, 0), 464 SND_SOC_DAPM_PGA("HSR Volume", 465 SND_SOC_NOPM, 0, 0, 466 NULL, 0), 467 468 SND_SOC_DAPM_OUTPUT("Headset Left"), 469 SND_SOC_DAPM_OUTPUT("Headset Right"), 470 471 /* LineOut path */ 472 473 SND_SOC_DAPM_MUX("LineOut Source", 474 SND_SOC_NOPM, 0, 0, dapm_lineout_source), 475 476 SND_SOC_DAPM_MIXER("LOL Disable HFL", 477 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1, 478 NULL, 0), 479 SND_SOC_DAPM_MIXER("LOR Disable HFR", 480 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1, 481 NULL, 0), 482 483 SND_SOC_DAPM_MIXER("LOL Enable", 484 AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0, 485 NULL, 0), 486 SND_SOC_DAPM_MIXER("LOR Enable", 487 AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0, 488 NULL, 0), 489 490 SND_SOC_DAPM_OUTPUT("LineOut Left"), 491 SND_SOC_DAPM_OUTPUT("LineOut Right"), 492 493 /* Earpiece path */ 494 495 SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source", 496 SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source), 497 SND_SOC_DAPM_MIXER("EAR DAC", 498 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0, 499 NULL, 0), 500 SND_SOC_DAPM_MIXER("EAR Mute", 501 AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1, 502 NULL, 0), 503 SND_SOC_DAPM_MIXER("EAR Enable", 504 AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0, 505 NULL, 0), 506 507 SND_SOC_DAPM_OUTPUT("Earpiece"), 508 509 /* Handsfree path */ 510 511 SND_SOC_DAPM_MIXER("DA3 Channel Volume", 512 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0, 513 NULL, 0), 514 SND_SOC_DAPM_MIXER("DA4 Channel Volume", 515 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0, 516 NULL, 0), 517 SND_SOC_DAPM_MUX("Speaker Left Source", 518 SND_SOC_NOPM, 0, 0, dapm_HFl_select), 519 SND_SOC_DAPM_MUX("Speaker Right Source", 520 SND_SOC_NOPM, 0, 0, dapm_HFr_select), 521 SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF, 522 AB8500_DAPATHCONF_ENDACHFL, 0, 523 NULL, 0), 524 SND_SOC_DAPM_MIXER("HFR DAC", 525 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0, 526 NULL, 0), 527 SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR", 528 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0, 529 NULL, 0), 530 SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL", 531 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0, 532 NULL, 0), 533 SND_SOC_DAPM_MIXER("HFL Enable", 534 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0, 535 NULL, 0), 536 SND_SOC_DAPM_MIXER("HFR Enable", 537 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0, 538 NULL, 0), 539 540 SND_SOC_DAPM_OUTPUT("Speaker Left"), 541 SND_SOC_DAPM_OUTPUT("Speaker Right"), 542 543 /* Vibrator path */ 544 545 SND_SOC_DAPM_INPUT("PWMGEN1"), 546 SND_SOC_DAPM_INPUT("PWMGEN2"), 547 548 SND_SOC_DAPM_MIXER("DA5 Channel Volume", 549 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0, 550 NULL, 0), 551 SND_SOC_DAPM_MIXER("DA6 Channel Volume", 552 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0, 553 NULL, 0), 554 SND_SOC_DAPM_MIXER("VIB1 DAC", 555 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0, 556 NULL, 0), 557 SND_SOC_DAPM_MIXER("VIB2 DAC", 558 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0, 559 NULL, 0), 560 SND_SOC_DAPM_MUX("Vibra 1 Controller", 561 SND_SOC_NOPM, 0, 0, dapm_pwm2vib1), 562 SND_SOC_DAPM_MUX("Vibra 2 Controller", 563 SND_SOC_NOPM, 0, 0, dapm_pwm2vib2), 564 SND_SOC_DAPM_MIXER("VIB1 Enable", 565 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0, 566 NULL, 0), 567 SND_SOC_DAPM_MIXER("VIB2 Enable", 568 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0, 569 NULL, 0), 570 571 SND_SOC_DAPM_OUTPUT("Vibra 1"), 572 SND_SOC_DAPM_OUTPUT("Vibra 2"), 573 574 /* Mic 1 */ 575 576 SND_SOC_DAPM_INPUT("Mic 1"), 577 578 SND_SOC_DAPM_MUX("Mic 1a or 1b Select", 579 SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux), 580 SND_SOC_DAPM_MIXER("MIC1 Mute", 581 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1, 582 NULL, 0), 583 SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable", 584 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0, 585 NULL, 0), 586 SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable", 587 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0, 588 NULL, 0), 589 SND_SOC_DAPM_MIXER("MIC1 ADC", 590 AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0, 591 NULL, 0), 592 SND_SOC_DAPM_MUX("AD3 Source Select", 593 SND_SOC_NOPM, 0, 0, dapm_ad3_select), 594 SND_SOC_DAPM_MIXER("AD3 Channel Volume", 595 SND_SOC_NOPM, 0, 0, 596 NULL, 0), 597 SND_SOC_DAPM_MIXER("AD3 Enable", 598 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0, 599 NULL, 0), 600 601 /* Mic 2 */ 602 603 SND_SOC_DAPM_INPUT("Mic 2"), 604 605 SND_SOC_DAPM_MIXER("MIC2 Mute", 606 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1, 607 NULL, 0), 608 SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2, 609 AB8500_ANACONF2_ENMIC2, 0, 610 NULL, 0), 611 612 /* LineIn */ 613 614 SND_SOC_DAPM_INPUT("LineIn Left"), 615 SND_SOC_DAPM_INPUT("LineIn Right"), 616 617 SND_SOC_DAPM_MIXER("LINL Mute", 618 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1, 619 NULL, 0), 620 SND_SOC_DAPM_MIXER("LINR Mute", 621 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1, 622 NULL, 0), 623 SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2, 624 AB8500_ANACONF2_ENLINL, 0, 625 NULL, 0), 626 SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2, 627 AB8500_ANACONF2_ENLINR, 0, 628 NULL, 0), 629 630 /* LineIn Bypass path */ 631 SND_SOC_DAPM_MIXER("LINL to HSL Volume", 632 SND_SOC_NOPM, 0, 0, 633 NULL, 0), 634 SND_SOC_DAPM_MIXER("LINR to HSR Volume", 635 SND_SOC_NOPM, 0, 0, 636 NULL, 0), 637 638 /* LineIn, Mic 2 */ 639 SND_SOC_DAPM_MUX("Mic 2 or LINR Select", 640 SND_SOC_NOPM, 0, 0, dapm_mic2lr_select), 641 SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3, 642 AB8500_ANACONF3_ENADCLINL, 0, 643 NULL, 0), 644 SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3, 645 AB8500_ANACONF3_ENADCLINR, 0, 646 NULL, 0), 647 SND_SOC_DAPM_MUX("AD1 Source Select", 648 SND_SOC_NOPM, 0, 0, dapm_ad1_select), 649 SND_SOC_DAPM_MUX("AD2 Source Select", 650 SND_SOC_NOPM, 0, 0, dapm_ad2_select), 651 SND_SOC_DAPM_MIXER("AD1 Channel Volume", 652 SND_SOC_NOPM, 0, 0, 653 NULL, 0), 654 SND_SOC_DAPM_MIXER("AD2 Channel Volume", 655 SND_SOC_NOPM, 0, 0, 656 NULL, 0), 657 658 SND_SOC_DAPM_MIXER("AD12 Enable", 659 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0, 660 NULL, 0), 661 662 /* HD Capture path */ 663 664 SND_SOC_DAPM_MUX("AD5 Source Select", 665 SND_SOC_NOPM, 0, 0, dapm_ad5_select), 666 SND_SOC_DAPM_MUX("AD6 Source Select", 667 SND_SOC_NOPM, 0, 0, dapm_ad6_select), 668 SND_SOC_DAPM_MIXER("AD5 Channel Volume", 669 SND_SOC_NOPM, 0, 0, 670 NULL, 0), 671 SND_SOC_DAPM_MIXER("AD6 Channel Volume", 672 SND_SOC_NOPM, 0, 0, 673 NULL, 0), 674 SND_SOC_DAPM_MIXER("AD57 Enable", 675 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0, 676 NULL, 0), 677 SND_SOC_DAPM_MIXER("AD68 Enable", 678 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0, 679 NULL, 0), 680 681 /* Digital Microphone path */ 682 683 SND_SOC_DAPM_INPUT("DMic 1"), 684 SND_SOC_DAPM_INPUT("DMic 2"), 685 SND_SOC_DAPM_INPUT("DMic 3"), 686 SND_SOC_DAPM_INPUT("DMic 4"), 687 SND_SOC_DAPM_INPUT("DMic 5"), 688 SND_SOC_DAPM_INPUT("DMic 6"), 689 690 SND_SOC_DAPM_MIXER("DMIC1", 691 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0, 692 NULL, 0), 693 SND_SOC_DAPM_MIXER("DMIC2", 694 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0, 695 NULL, 0), 696 SND_SOC_DAPM_MIXER("DMIC3", 697 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0, 698 NULL, 0), 699 SND_SOC_DAPM_MIXER("DMIC4", 700 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0, 701 NULL, 0), 702 SND_SOC_DAPM_MIXER("DMIC5", 703 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0, 704 NULL, 0), 705 SND_SOC_DAPM_MIXER("DMIC6", 706 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0, 707 NULL, 0), 708 SND_SOC_DAPM_MIXER("AD4 Channel Volume", 709 SND_SOC_NOPM, 0, 0, 710 NULL, 0), 711 SND_SOC_DAPM_MIXER("AD4 Enable", 712 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 713 0, NULL, 0), 714 715 /* Acoustical Noise Cancellation path */ 716 717 SND_SOC_DAPM_INPUT("ANC Configure Input"), 718 SND_SOC_DAPM_OUTPUT("ANC Configure Output"), 719 720 SND_SOC_DAPM_MUX("ANC Source", 721 SND_SOC_NOPM, 0, 0, 722 dapm_anc_in_select), 723 SND_SOC_DAPM_SWITCH("ANC", 724 SND_SOC_NOPM, 0, 0, 725 dapm_anc_enable), 726 SND_SOC_DAPM_SWITCH("ANC to Earpiece", 727 SND_SOC_NOPM, 0, 0, 728 dapm_anc_ear_mute), 729 730 /* Sidetone Filter path */ 731 732 SND_SOC_DAPM_MUX("Sidetone Left Source", 733 SND_SOC_NOPM, 0, 0, 734 dapm_stfir1_in_select), 735 SND_SOC_DAPM_MUX("Sidetone Right Source", 736 SND_SOC_NOPM, 0, 0, 737 dapm_stfir2_in_select), 738 SND_SOC_DAPM_MIXER("STFIR1 Control", 739 SND_SOC_NOPM, 0, 0, 740 NULL, 0), 741 SND_SOC_DAPM_MIXER("STFIR2 Control", 742 SND_SOC_NOPM, 0, 0, 743 NULL, 0), 744 SND_SOC_DAPM_MIXER("STFIR1 Volume", 745 SND_SOC_NOPM, 0, 0, 746 NULL, 0), 747 SND_SOC_DAPM_MIXER("STFIR2 Volume", 748 SND_SOC_NOPM, 0, 0, 749 NULL, 0), 750 }; 751 752 /* 753 * DAPM-routes 754 */ 755 static const struct snd_soc_dapm_route ab8500_dapm_routes[] = { 756 /* Power AB8500 audio-block when AD/DA is active */ 757 {"Main Supply", NULL, "V-AUD"}, 758 {"Main Supply", NULL, "audioclk"}, 759 {"Main Supply", NULL, "Audio Power"}, 760 {"Main Supply", NULL, "Audio Analog Power"}, 761 762 {"DAC", NULL, "ab8500_0p"}, 763 {"DAC", NULL, "Main Supply"}, 764 {"ADC", NULL, "ab8500_0c"}, 765 {"ADC", NULL, "Main Supply"}, 766 767 /* ANC Configure */ 768 {"ANC Configure Input", NULL, "Main Supply"}, 769 {"ANC Configure Output", NULL, "ANC Configure Input"}, 770 771 /* AD/DA */ 772 {"ADC", NULL, "ADC Input"}, 773 {"DAC Output", NULL, "DAC"}, 774 775 /* Powerup charge pump if DA1/2 is in use */ 776 777 {"DA_IN1", NULL, "ab8500_0p"}, 778 {"DA_IN1", NULL, "Charge Pump"}, 779 {"DA_IN2", NULL, "ab8500_0p"}, 780 {"DA_IN2", NULL, "Charge Pump"}, 781 782 /* Headset path */ 783 784 {"DA1 Enable", NULL, "DA_IN1"}, 785 {"DA2 Enable", NULL, "DA_IN2"}, 786 787 {"HSL Digital Volume", NULL, "DA1 Enable"}, 788 {"HSR Digital Volume", NULL, "DA2 Enable"}, 789 790 {"HSL DAC", NULL, "HSL Digital Volume"}, 791 {"HSR DAC", NULL, "HSR Digital Volume"}, 792 793 {"HSL DAC Mute", NULL, "HSL DAC"}, 794 {"HSR DAC Mute", NULL, "HSR DAC"}, 795 796 {"HSL DAC Driver", NULL, "HSL DAC Mute"}, 797 {"HSR DAC Driver", NULL, "HSR DAC Mute"}, 798 799 {"HSL Mute", NULL, "HSL DAC Driver"}, 800 {"HSR Mute", NULL, "HSR DAC Driver"}, 801 802 {"HSL Enable", NULL, "HSL Mute"}, 803 {"HSR Enable", NULL, "HSR Mute"}, 804 805 {"HSL Volume", NULL, "HSL Enable"}, 806 {"HSR Volume", NULL, "HSR Enable"}, 807 808 {"Headset Left", NULL, "HSL Volume"}, 809 {"Headset Right", NULL, "HSR Volume"}, 810 811 /* HF or LineOut path */ 812 813 {"DA_IN3", NULL, "ab8500_0p"}, 814 {"DA3 Channel Volume", NULL, "DA_IN3"}, 815 {"DA_IN4", NULL, "ab8500_0p"}, 816 {"DA4 Channel Volume", NULL, "DA_IN4"}, 817 818 {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"}, 819 {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"}, 820 821 {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"}, 822 {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"}, 823 824 /* HF path */ 825 826 {"HFL DAC", NULL, "DA3 or ANC path to HfL"}, 827 {"HFR DAC", NULL, "DA4 or ANC path to HfR"}, 828 829 {"HFL Enable", NULL, "HFL DAC"}, 830 {"HFR Enable", NULL, "HFR DAC"}, 831 832 {"Speaker Left", NULL, "HFL Enable"}, 833 {"Speaker Right", NULL, "HFR Enable"}, 834 835 /* Earpiece path */ 836 837 {"Earpiece or LineOut Mono Source", "Headset Left", 838 "HSL Digital Volume"}, 839 {"Earpiece or LineOut Mono Source", "Speaker Left", 840 "DA3 or ANC path to HfL"}, 841 842 {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"}, 843 844 {"EAR Mute", NULL, "EAR DAC"}, 845 846 {"EAR Enable", NULL, "EAR Mute"}, 847 848 {"Earpiece", NULL, "EAR Enable"}, 849 850 /* LineOut path stereo */ 851 852 {"LineOut Source", "Stereo Path", "HSL DAC Driver"}, 853 {"LineOut Source", "Stereo Path", "HSR DAC Driver"}, 854 855 /* LineOut path mono */ 856 857 {"LineOut Source", "Mono Path", "EAR DAC"}, 858 859 /* LineOut path */ 860 861 {"LOL Disable HFL", NULL, "LineOut Source"}, 862 {"LOR Disable HFR", NULL, "LineOut Source"}, 863 864 {"LOL Enable", NULL, "LOL Disable HFL"}, 865 {"LOR Enable", NULL, "LOR Disable HFR"}, 866 867 {"LineOut Left", NULL, "LOL Enable"}, 868 {"LineOut Right", NULL, "LOR Enable"}, 869 870 /* Vibrator path */ 871 872 {"DA_IN5", NULL, "ab8500_0p"}, 873 {"DA5 Channel Volume", NULL, "DA_IN5"}, 874 {"DA_IN6", NULL, "ab8500_0p"}, 875 {"DA6 Channel Volume", NULL, "DA_IN6"}, 876 877 {"VIB1 DAC", NULL, "DA5 Channel Volume"}, 878 {"VIB2 DAC", NULL, "DA6 Channel Volume"}, 879 880 {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"}, 881 {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"}, 882 {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"}, 883 {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"}, 884 885 {"VIB1 Enable", NULL, "Vibra 1 Controller"}, 886 {"VIB2 Enable", NULL, "Vibra 2 Controller"}, 887 888 {"Vibra 1", NULL, "VIB1 Enable"}, 889 {"Vibra 2", NULL, "VIB2 Enable"}, 890 891 892 /* Mic 2 */ 893 894 {"MIC2 V-AMICx Enable", NULL, "Mic 2"}, 895 896 /* LineIn */ 897 {"LINL Mute", NULL, "LineIn Left"}, 898 {"LINR Mute", NULL, "LineIn Right"}, 899 900 {"LINL Enable", NULL, "LINL Mute"}, 901 {"LINR Enable", NULL, "LINR Mute"}, 902 903 /* LineIn, Mic 2 */ 904 {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"}, 905 {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"}, 906 907 {"LINL ADC", NULL, "LINL Enable"}, 908 {"LINR ADC", NULL, "Mic 2 or LINR Select"}, 909 910 {"AD1 Source Select", "LineIn Left", "LINL ADC"}, 911 {"AD2 Source Select", "LineIn Right", "LINR ADC"}, 912 913 {"AD1 Channel Volume", NULL, "AD1 Source Select"}, 914 {"AD2 Channel Volume", NULL, "AD2 Source Select"}, 915 916 {"AD12 Enable", NULL, "AD1 Channel Volume"}, 917 {"AD12 Enable", NULL, "AD2 Channel Volume"}, 918 919 {"AD_OUT1", NULL, "ab8500_0c"}, 920 {"AD_OUT1", NULL, "AD12 Enable"}, 921 {"AD_OUT2", NULL, "ab8500_0c"}, 922 {"AD_OUT2", NULL, "AD12 Enable"}, 923 924 /* Mic 1 */ 925 926 {"MIC1 Mute", NULL, "Mic 1"}, 927 928 {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"}, 929 {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"}, 930 931 {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"}, 932 {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"}, 933 934 {"MIC1 ADC", NULL, "Mic 1a or 1b Select"}, 935 936 {"AD3 Source Select", "Mic 1", "MIC1 ADC"}, 937 938 {"AD3 Channel Volume", NULL, "AD3 Source Select"}, 939 940 {"AD3 Enable", NULL, "AD3 Channel Volume"}, 941 942 {"AD_OUT3", NULL, "ab8500_0c"}, 943 {"AD_OUT3", NULL, "AD3 Enable"}, 944 945 /* HD Capture path */ 946 947 {"AD5 Source Select", "Mic 2", "LINR ADC"}, 948 {"AD6 Source Select", "Mic 1", "MIC1 ADC"}, 949 950 {"AD5 Channel Volume", NULL, "AD5 Source Select"}, 951 {"AD6 Channel Volume", NULL, "AD6 Source Select"}, 952 953 {"AD57 Enable", NULL, "AD5 Channel Volume"}, 954 {"AD68 Enable", NULL, "AD6 Channel Volume"}, 955 956 {"AD_OUT57", NULL, "ab8500_0c"}, 957 {"AD_OUT57", NULL, "AD57 Enable"}, 958 {"AD_OUT68", NULL, "ab8500_0c"}, 959 {"AD_OUT68", NULL, "AD68 Enable"}, 960 961 /* Digital Microphone path */ 962 963 {"DMic 1", NULL, "V-DMIC"}, 964 {"DMic 2", NULL, "V-DMIC"}, 965 {"DMic 3", NULL, "V-DMIC"}, 966 {"DMic 4", NULL, "V-DMIC"}, 967 {"DMic 5", NULL, "V-DMIC"}, 968 {"DMic 6", NULL, "V-DMIC"}, 969 970 {"AD1 Source Select", NULL, "DMic 1"}, 971 {"AD2 Source Select", NULL, "DMic 2"}, 972 {"AD3 Source Select", NULL, "DMic 3"}, 973 {"AD5 Source Select", NULL, "DMic 5"}, 974 {"AD6 Source Select", NULL, "DMic 6"}, 975 976 {"AD4 Channel Volume", NULL, "DMic 4"}, 977 {"AD4 Enable", NULL, "AD4 Channel Volume"}, 978 979 {"AD_OUT4", NULL, "ab8500_0c"}, 980 {"AD_OUT4", NULL, "AD4 Enable"}, 981 982 /* LineIn Bypass path */ 983 984 {"LINL to HSL Volume", NULL, "LINL Enable"}, 985 {"LINR to HSR Volume", NULL, "LINR Enable"}, 986 987 {"HSL DAC Driver", NULL, "LINL to HSL Volume"}, 988 {"HSR DAC Driver", NULL, "LINR to HSR Volume"}, 989 990 /* ANC path (Acoustic Noise Cancellation) */ 991 992 {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"}, 993 {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"}, 994 995 {"ANC", "Switch", "ANC Source"}, 996 997 {"Speaker Left Source", "ANC", "ANC"}, 998 {"Speaker Right Source", "ANC", "ANC"}, 999 {"ANC to Earpiece", "Switch", "ANC"}, 1000 1001 {"HSL Digital Volume", NULL, "ANC to Earpiece"}, 1002 1003 /* Sidetone Filter path */ 1004 1005 {"Sidetone Left Source", "LineIn Left", "AD12 Enable"}, 1006 {"Sidetone Left Source", "LineIn Right", "AD12 Enable"}, 1007 {"Sidetone Left Source", "Mic 1", "AD3 Enable"}, 1008 {"Sidetone Left Source", "Headset Left", "DA_IN1"}, 1009 {"Sidetone Right Source", "LineIn Right", "AD12 Enable"}, 1010 {"Sidetone Right Source", "Mic 1", "AD3 Enable"}, 1011 {"Sidetone Right Source", "DMic 4", "AD4 Enable"}, 1012 {"Sidetone Right Source", "Headset Right", "DA_IN2"}, 1013 1014 {"STFIR1 Control", NULL, "Sidetone Left Source"}, 1015 {"STFIR2 Control", NULL, "Sidetone Right Source"}, 1016 1017 {"STFIR1 Volume", NULL, "STFIR1 Control"}, 1018 {"STFIR2 Volume", NULL, "STFIR2 Control"}, 1019 1020 {"DA1 Enable", NULL, "STFIR1 Volume"}, 1021 {"DA2 Enable", NULL, "STFIR2 Volume"}, 1022 }; 1023 1024 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = { 1025 {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"}, 1026 {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"}, 1027 }; 1028 1029 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = { 1030 {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"}, 1031 {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"}, 1032 }; 1033 1034 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = { 1035 {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"}, 1036 {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"}, 1037 }; 1038 1039 /* ANC FIR-coefficients configuration sequence */ 1040 static void anc_fir(struct snd_soc_codec *codec, 1041 unsigned int bnk, unsigned int par, unsigned int val) 1042 { 1043 if (par == 0 && bnk == 0) 1044 snd_soc_update_bits(codec, AB8500_ANCCONF1, 1045 BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 1046 BIT(AB8500_ANCCONF1_ANCFIRUPDATE)); 1047 1048 snd_soc_write(codec, AB8500_ANCCONF5, val >> 8 & 0xff); 1049 snd_soc_write(codec, AB8500_ANCCONF6, val & 0xff); 1050 1051 if (par == AB8500_ANC_FIR_COEFFS - 1 && bnk == 1) 1052 snd_soc_update_bits(codec, AB8500_ANCCONF1, 1053 BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0); 1054 } 1055 1056 /* ANC IIR-coefficients configuration sequence */ 1057 static void anc_iir(struct snd_soc_codec *codec, unsigned int bnk, 1058 unsigned int par, unsigned int val) 1059 { 1060 if (par == 0) { 1061 if (bnk == 0) { 1062 snd_soc_update_bits(codec, AB8500_ANCCONF1, 1063 BIT(AB8500_ANCCONF1_ANCIIRINIT), 1064 BIT(AB8500_ANCCONF1_ANCIIRINIT)); 1065 usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY); 1066 snd_soc_update_bits(codec, AB8500_ANCCONF1, 1067 BIT(AB8500_ANCCONF1_ANCIIRINIT), 0); 1068 usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY); 1069 } else { 1070 snd_soc_update_bits(codec, AB8500_ANCCONF1, 1071 BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 1072 BIT(AB8500_ANCCONF1_ANCIIRUPDATE)); 1073 } 1074 } else if (par > 3) { 1075 snd_soc_write(codec, AB8500_ANCCONF7, 0); 1076 snd_soc_write(codec, AB8500_ANCCONF8, val >> 16 & 0xff); 1077 } 1078 1079 snd_soc_write(codec, AB8500_ANCCONF7, val >> 8 & 0xff); 1080 snd_soc_write(codec, AB8500_ANCCONF8, val & 0xff); 1081 1082 if (par == AB8500_ANC_IIR_COEFFS - 1 && bnk == 1) 1083 snd_soc_update_bits(codec, AB8500_ANCCONF1, 1084 BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0); 1085 } 1086 1087 /* ANC IIR-/FIR-coefficients configuration sequence */ 1088 static void anc_configure(struct snd_soc_codec *codec, 1089 bool apply_fir, bool apply_iir) 1090 { 1091 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev); 1092 unsigned int bnk, par, val; 1093 1094 dev_dbg(codec->dev, "%s: Enter.\n", __func__); 1095 1096 if (apply_fir) 1097 snd_soc_update_bits(codec, AB8500_ANCCONF1, 1098 BIT(AB8500_ANCCONF1_ENANC), 0); 1099 1100 snd_soc_update_bits(codec, AB8500_ANCCONF1, 1101 BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC)); 1102 1103 if (apply_fir) 1104 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++) 1105 for (par = 0; par < AB8500_ANC_FIR_COEFFS; par++) { 1106 val = snd_soc_read(codec, 1107 drvdata->anc_fir_values[par]); 1108 anc_fir(codec, bnk, par, val); 1109 } 1110 1111 if (apply_iir) 1112 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++) 1113 for (par = 0; par < AB8500_ANC_IIR_COEFFS; par++) { 1114 val = snd_soc_read(codec, 1115 drvdata->anc_iir_values[par]); 1116 anc_iir(codec, bnk, par, val); 1117 } 1118 1119 dev_dbg(codec->dev, "%s: Exit.\n", __func__); 1120 } 1121 1122 /* 1123 * Control-events 1124 */ 1125 1126 static int sid_status_control_get(struct snd_kcontrol *kcontrol, 1127 struct snd_ctl_elem_value *ucontrol) 1128 { 1129 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1130 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev); 1131 1132 mutex_lock(&drvdata->ctrl_lock); 1133 ucontrol->value.integer.value[0] = drvdata->sid_status; 1134 mutex_unlock(&drvdata->ctrl_lock); 1135 1136 return 0; 1137 } 1138 1139 /* Write sidetone FIR-coefficients configuration sequence */ 1140 static int sid_status_control_put(struct snd_kcontrol *kcontrol, 1141 struct snd_ctl_elem_value *ucontrol) 1142 { 1143 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1144 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev); 1145 unsigned int param, sidconf, val; 1146 int status = 1; 1147 1148 dev_dbg(codec->dev, "%s: Enter\n", __func__); 1149 1150 if (ucontrol->value.integer.value[0] != SID_APPLY_FIR) { 1151 dev_err(codec->dev, 1152 "%s: ERROR: This control supports '%s' only!\n", 1153 __func__, enum_sid_state[SID_APPLY_FIR]); 1154 return -EIO; 1155 } 1156 1157 mutex_lock(&drvdata->ctrl_lock); 1158 1159 sidconf = snd_soc_read(codec, AB8500_SIDFIRCONF); 1160 if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) { 1161 if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) { 1162 dev_err(codec->dev, "%s: Sidetone busy while off!\n", 1163 __func__); 1164 status = -EPERM; 1165 } else { 1166 status = -EBUSY; 1167 } 1168 goto out; 1169 } 1170 1171 snd_soc_write(codec, AB8500_SIDFIRADR, 0); 1172 1173 for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) { 1174 val = snd_soc_read(codec, drvdata->sid_fir_values[param]); 1175 snd_soc_write(codec, AB8500_SIDFIRCOEF1, val >> 8 & 0xff); 1176 snd_soc_write(codec, AB8500_SIDFIRCOEF2, val & 0xff); 1177 } 1178 1179 snd_soc_update_bits(codec, AB8500_SIDFIRADR, 1180 BIT(AB8500_SIDFIRADR_FIRSIDSET), 1181 BIT(AB8500_SIDFIRADR_FIRSIDSET)); 1182 snd_soc_update_bits(codec, AB8500_SIDFIRADR, 1183 BIT(AB8500_SIDFIRADR_FIRSIDSET), 0); 1184 1185 drvdata->sid_status = SID_FIR_CONFIGURED; 1186 1187 out: 1188 mutex_unlock(&drvdata->ctrl_lock); 1189 1190 dev_dbg(codec->dev, "%s: Exit\n", __func__); 1191 1192 return status; 1193 } 1194 1195 static int anc_status_control_get(struct snd_kcontrol *kcontrol, 1196 struct snd_ctl_elem_value *ucontrol) 1197 { 1198 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1199 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev); 1200 1201 mutex_lock(&drvdata->ctrl_lock); 1202 ucontrol->value.integer.value[0] = drvdata->anc_status; 1203 mutex_unlock(&drvdata->ctrl_lock); 1204 1205 return 0; 1206 } 1207 1208 static int anc_status_control_put(struct snd_kcontrol *kcontrol, 1209 struct snd_ctl_elem_value *ucontrol) 1210 { 1211 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1212 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev); 1213 struct device *dev = codec->dev; 1214 bool apply_fir, apply_iir; 1215 unsigned int req; 1216 int status; 1217 1218 dev_dbg(dev, "%s: Enter.\n", __func__); 1219 1220 mutex_lock(&drvdata->ctrl_lock); 1221 1222 req = ucontrol->value.integer.value[0]; 1223 if (req >= ARRAY_SIZE(enum_anc_state)) { 1224 status = -EINVAL; 1225 goto cleanup; 1226 } 1227 if (req != ANC_APPLY_FIR_IIR && req != ANC_APPLY_FIR && 1228 req != ANC_APPLY_IIR) { 1229 dev_err(dev, "%s: ERROR: Unsupported status to set '%s'!\n", 1230 __func__, enum_anc_state[req]); 1231 status = -EINVAL; 1232 goto cleanup; 1233 } 1234 apply_fir = req == ANC_APPLY_FIR || req == ANC_APPLY_FIR_IIR; 1235 apply_iir = req == ANC_APPLY_IIR || req == ANC_APPLY_FIR_IIR; 1236 1237 status = snd_soc_dapm_force_enable_pin(&codec->dapm, 1238 "ANC Configure Input"); 1239 if (status < 0) { 1240 dev_err(dev, 1241 "%s: ERROR: Failed to enable power (status = %d)!\n", 1242 __func__, status); 1243 goto cleanup; 1244 } 1245 snd_soc_dapm_sync(&codec->dapm); 1246 1247 anc_configure(codec, apply_fir, apply_iir); 1248 1249 if (apply_fir) { 1250 if (drvdata->anc_status == ANC_IIR_CONFIGURED) 1251 drvdata->anc_status = ANC_FIR_IIR_CONFIGURED; 1252 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED) 1253 drvdata->anc_status = ANC_FIR_CONFIGURED; 1254 } 1255 if (apply_iir) { 1256 if (drvdata->anc_status == ANC_FIR_CONFIGURED) 1257 drvdata->anc_status = ANC_FIR_IIR_CONFIGURED; 1258 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED) 1259 drvdata->anc_status = ANC_IIR_CONFIGURED; 1260 } 1261 1262 status = snd_soc_dapm_disable_pin(&codec->dapm, "ANC Configure Input"); 1263 snd_soc_dapm_sync(&codec->dapm); 1264 1265 cleanup: 1266 mutex_unlock(&drvdata->ctrl_lock); 1267 1268 if (status < 0) 1269 dev_err(dev, "%s: Unable to configure ANC! (status = %d)\n", 1270 __func__, status); 1271 1272 dev_dbg(dev, "%s: Exit.\n", __func__); 1273 1274 return (status < 0) ? status : 1; 1275 } 1276 1277 static int filter_control_info(struct snd_kcontrol *kcontrol, 1278 struct snd_ctl_elem_info *uinfo) 1279 { 1280 struct filter_control *fc = 1281 (struct filter_control *)kcontrol->private_value; 1282 1283 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1284 uinfo->count = fc->count; 1285 uinfo->value.integer.min = fc->min; 1286 uinfo->value.integer.max = fc->max; 1287 1288 return 0; 1289 } 1290 1291 static int filter_control_get(struct snd_kcontrol *kcontrol, 1292 struct snd_ctl_elem_value *ucontrol) 1293 { 1294 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1295 struct ab8500_codec_drvdata *drvdata = snd_soc_codec_get_drvdata(codec); 1296 struct filter_control *fc = 1297 (struct filter_control *)kcontrol->private_value; 1298 unsigned int i; 1299 1300 mutex_lock(&drvdata->ctrl_lock); 1301 for (i = 0; i < fc->count; i++) 1302 ucontrol->value.integer.value[i] = fc->value[i]; 1303 mutex_unlock(&drvdata->ctrl_lock); 1304 1305 return 0; 1306 } 1307 1308 static int filter_control_put(struct snd_kcontrol *kcontrol, 1309 struct snd_ctl_elem_value *ucontrol) 1310 { 1311 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1312 struct ab8500_codec_drvdata *drvdata = snd_soc_codec_get_drvdata(codec); 1313 struct filter_control *fc = 1314 (struct filter_control *)kcontrol->private_value; 1315 unsigned int i; 1316 1317 mutex_lock(&drvdata->ctrl_lock); 1318 for (i = 0; i < fc->count; i++) 1319 fc->value[i] = ucontrol->value.integer.value[i]; 1320 mutex_unlock(&drvdata->ctrl_lock); 1321 1322 return 0; 1323 } 1324 1325 /* 1326 * Controls - Non-DAPM ASoC 1327 */ 1328 1329 static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1); 1330 /* -32dB = Mute */ 1331 1332 static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1); 1333 /* -63dB = Mute */ 1334 1335 static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1); 1336 /* -1dB = Mute */ 1337 1338 static const unsigned int hs_gain_tlv[] = { 1339 TLV_DB_RANGE_HEAD(2), 1340 0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0), 1341 4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0), 1342 }; 1343 1344 static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0); 1345 1346 static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0); 1347 1348 static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1); 1349 /* -38dB = Mute */ 1350 1351 static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms", 1352 "5ms"}; 1353 static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed, 1354 AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed); 1355 1356 static const char * const enum_envdetthre[] = { 1357 "250mV", "300mV", "350mV", "400mV", 1358 "450mV", "500mV", "550mV", "600mV", 1359 "650mV", "700mV", "750mV", "800mV", 1360 "850mV", "900mV", "950mV", "1.00V" }; 1361 static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre, 1362 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre); 1363 static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre, 1364 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre); 1365 static const char * const enum_envdettime[] = { 1366 "26.6us", "53.2us", "106us", "213us", 1367 "426us", "851us", "1.70ms", "3.40ms", 1368 "6.81ms", "13.6ms", "27.2ms", "54.5ms", 1369 "109ms", "218ms", "436ms", "872ms" }; 1370 static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime, 1371 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime); 1372 1373 static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"}; 1374 static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN, 1375 AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31); 1376 1377 static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"}; 1378 static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN, 1379 AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed); 1380 1381 /* Earpiece */ 1382 1383 static const char * const enum_lowpow[] = {"Normal", "Low Power"}; 1384 static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1, 1385 AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow); 1386 static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1, 1387 AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow); 1388 1389 static const char * const enum_av_mode[] = {"Audio", "Voice"}; 1390 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF, 1391 AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode); 1392 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF, 1393 AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode); 1394 1395 /* DA */ 1396 1397 static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice, 1398 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE, 1399 enum_av_mode); 1400 static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice, 1401 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE, 1402 enum_av_mode); 1403 static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice, 1404 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE, 1405 enum_av_mode); 1406 1407 static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"}; 1408 static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1, 1409 AB8500_DIGMULTCONF1_DATOHSLEN, 1410 AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr); 1411 1412 static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"}; 1413 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF, 1414 AB8500_DMICFILTCONF_DMIC1SINC3, 1415 AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53); 1416 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF, 1417 AB8500_DMICFILTCONF_DMIC3SINC3, 1418 AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53); 1419 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF, 1420 AB8500_DMICFILTCONF_DMIC5SINC3, 1421 AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53); 1422 1423 /* Digital interface - DA from slot mapping */ 1424 static const char * const enum_da_from_slot_map[] = {"SLOT0", 1425 "SLOT1", 1426 "SLOT2", 1427 "SLOT3", 1428 "SLOT4", 1429 "SLOT5", 1430 "SLOT6", 1431 "SLOT7", 1432 "SLOT8", 1433 "SLOT9", 1434 "SLOT10", 1435 "SLOT11", 1436 "SLOT12", 1437 "SLOT13", 1438 "SLOT14", 1439 "SLOT15", 1440 "SLOT16", 1441 "SLOT17", 1442 "SLOT18", 1443 "SLOT19", 1444 "SLOT20", 1445 "SLOT21", 1446 "SLOT22", 1447 "SLOT23", 1448 "SLOT24", 1449 "SLOT25", 1450 "SLOT26", 1451 "SLOT27", 1452 "SLOT28", 1453 "SLOT29", 1454 "SLOT30", 1455 "SLOT31"}; 1456 static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap, 1457 AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1458 enum_da_from_slot_map); 1459 static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap, 1460 AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1461 enum_da_from_slot_map); 1462 static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap, 1463 AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1464 enum_da_from_slot_map); 1465 static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap, 1466 AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1467 enum_da_from_slot_map); 1468 static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap, 1469 AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1470 enum_da_from_slot_map); 1471 static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap, 1472 AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1473 enum_da_from_slot_map); 1474 static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap, 1475 AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1476 enum_da_from_slot_map); 1477 static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap, 1478 AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1479 enum_da_from_slot_map); 1480 1481 /* Digital interface - AD to slot mapping */ 1482 static const char * const enum_ad_to_slot_map[] = {"AD_OUT1", 1483 "AD_OUT2", 1484 "AD_OUT3", 1485 "AD_OUT4", 1486 "AD_OUT5", 1487 "AD_OUT6", 1488 "AD_OUT7", 1489 "AD_OUT8", 1490 "zeroes", 1491 "zeroes", 1492 "zeroes", 1493 "zeroes", 1494 "tristate", 1495 "tristate", 1496 "tristate", 1497 "tristate"}; 1498 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map, 1499 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT, 1500 enum_ad_to_slot_map); 1501 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map, 1502 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT, 1503 enum_ad_to_slot_map); 1504 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map, 1505 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT, 1506 enum_ad_to_slot_map); 1507 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map, 1508 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT, 1509 enum_ad_to_slot_map); 1510 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map, 1511 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT, 1512 enum_ad_to_slot_map); 1513 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map, 1514 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT, 1515 enum_ad_to_slot_map); 1516 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map, 1517 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT, 1518 enum_ad_to_slot_map); 1519 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map, 1520 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT, 1521 enum_ad_to_slot_map); 1522 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map, 1523 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT, 1524 enum_ad_to_slot_map); 1525 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map, 1526 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT, 1527 enum_ad_to_slot_map); 1528 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map, 1529 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT, 1530 enum_ad_to_slot_map); 1531 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map, 1532 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT, 1533 enum_ad_to_slot_map); 1534 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map, 1535 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT, 1536 enum_ad_to_slot_map); 1537 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map, 1538 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT, 1539 enum_ad_to_slot_map); 1540 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map, 1541 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT, 1542 enum_ad_to_slot_map); 1543 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map, 1544 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT, 1545 enum_ad_to_slot_map); 1546 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map, 1547 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT, 1548 enum_ad_to_slot_map); 1549 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map, 1550 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT, 1551 enum_ad_to_slot_map); 1552 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map, 1553 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT, 1554 enum_ad_to_slot_map); 1555 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map, 1556 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT, 1557 enum_ad_to_slot_map); 1558 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map, 1559 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT, 1560 enum_ad_to_slot_map); 1561 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map, 1562 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT, 1563 enum_ad_to_slot_map); 1564 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map, 1565 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT, 1566 enum_ad_to_slot_map); 1567 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map, 1568 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT, 1569 enum_ad_to_slot_map); 1570 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map, 1571 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT, 1572 enum_ad_to_slot_map); 1573 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map, 1574 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT, 1575 enum_ad_to_slot_map); 1576 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map, 1577 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT, 1578 enum_ad_to_slot_map); 1579 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map, 1580 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT, 1581 enum_ad_to_slot_map); 1582 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map, 1583 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT, 1584 enum_ad_to_slot_map); 1585 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map, 1586 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT, 1587 enum_ad_to_slot_map); 1588 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map, 1589 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT, 1590 enum_ad_to_slot_map); 1591 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map, 1592 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT, 1593 enum_ad_to_slot_map); 1594 1595 /* Digital interface - Burst mode */ 1596 static const char * const enum_mask[] = {"Unmasked", "Masked"}; 1597 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask, 1598 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK, 1599 enum_mask); 1600 static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"}; 1601 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2, 1602 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2, 1603 enum_bitclk0); 1604 static const char * const enum_slavemaster[] = {"Slave", "Master"}; 1605 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast, 1606 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT, 1607 enum_slavemaster); 1608 1609 /* Sidetone */ 1610 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state); 1611 1612 /* ANC */ 1613 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_ancstate, enum_anc_state); 1614 1615 static struct snd_kcontrol_new ab8500_ctrls[] = { 1616 /* Charge pump */ 1617 SOC_ENUM("Charge Pump High Threshold For Low Voltage", 1618 soc_enum_envdeththre), 1619 SOC_ENUM("Charge Pump Low Threshold For Low Voltage", 1620 soc_enum_envdetlthre), 1621 SOC_SINGLE("Charge Pump Envelope Detection Switch", 1622 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN, 1623 1, 0), 1624 SOC_ENUM("Charge Pump Envelope Detection Decay Time", 1625 soc_enum_envdettime), 1626 1627 /* Headset */ 1628 SOC_ENUM("Headset Mode", soc_enum_da12voice), 1629 SOC_SINGLE("Headset High Pass Switch", 1630 AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN, 1631 1, 0), 1632 SOC_SINGLE("Headset Low Power Switch", 1633 AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW, 1634 1, 0), 1635 SOC_SINGLE("Headset DAC Low Power Switch", 1636 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1, 1637 1, 0), 1638 SOC_SINGLE("Headset DAC Drv Low Power Switch", 1639 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0, 1640 1, 0), 1641 SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed), 1642 SOC_ENUM("Headset Source", soc_enum_da2hslr), 1643 SOC_ENUM("Headset Filter", soc_enum_hsesinc), 1644 SOC_DOUBLE_R_TLV("Headset Master Volume", 1645 AB8500_DADIGGAIN1, AB8500_DADIGGAIN2, 1646 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv), 1647 SOC_DOUBLE_R_TLV("Headset Digital Volume", 1648 AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN, 1649 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv), 1650 SOC_DOUBLE_TLV("Headset Volume", 1651 AB8500_ANAGAIN3, 1652 AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN, 1653 AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv), 1654 1655 /* Earpiece */ 1656 SOC_ENUM("Earpiece DAC Mode", 1657 soc_enum_eardaclowpow), 1658 SOC_ENUM("Earpiece DAC Drv Mode", 1659 soc_enum_eardrvlowpow), 1660 1661 /* HandsFree */ 1662 SOC_ENUM("HF Mode", soc_enum_da34voice), 1663 SOC_SINGLE("HF and Headset Swap Switch", 1664 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34, 1665 1, 0), 1666 SOC_DOUBLE("HF Low EMI Mode Switch", 1667 AB8500_CLASSDCONF1, 1668 AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN, 1669 1, 0), 1670 SOC_DOUBLE("HF FIR Bypass Switch", 1671 AB8500_CLASSDCONF2, 1672 AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1, 1673 1, 0), 1674 SOC_DOUBLE("HF High Volume Switch", 1675 AB8500_CLASSDCONF2, 1676 AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1, 1677 1, 0), 1678 SOC_SINGLE("HF L and R Bridge Switch", 1679 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF, 1680 1, 0), 1681 SOC_DOUBLE_R_TLV("HF Master Volume", 1682 AB8500_DADIGGAIN3, AB8500_DADIGGAIN4, 1683 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv), 1684 1685 /* Vibra */ 1686 SOC_DOUBLE("Vibra High Volume Switch", 1687 AB8500_CLASSDCONF2, 1688 AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3, 1689 1, 0), 1690 SOC_DOUBLE("Vibra Low EMI Mode Switch", 1691 AB8500_CLASSDCONF1, 1692 AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN, 1693 1, 0), 1694 SOC_DOUBLE("Vibra FIR Bypass Switch", 1695 AB8500_CLASSDCONF2, 1696 AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3, 1697 1, 0), 1698 SOC_ENUM("Vibra Mode", soc_enum_da56voice), 1699 SOC_DOUBLE_R("Vibra PWM Duty Cycle N", 1700 AB8500_PWMGENCONF3, AB8500_PWMGENCONF5, 1701 AB8500_PWMGENCONFX_PWMVIBXDUTCYC, 1702 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0), 1703 SOC_DOUBLE_R("Vibra PWM Duty Cycle P", 1704 AB8500_PWMGENCONF2, AB8500_PWMGENCONF4, 1705 AB8500_PWMGENCONFX_PWMVIBXDUTCYC, 1706 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0), 1707 SOC_SINGLE("Vibra 1 and 2 Bridge Switch", 1708 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB, 1709 1, 0), 1710 SOC_DOUBLE_R_TLV("Vibra Master Volume", 1711 AB8500_DADIGGAIN5, AB8500_DADIGGAIN6, 1712 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv), 1713 1714 /* HandsFree, Vibra */ 1715 SOC_SINGLE("ClassD High Pass Volume", 1716 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN, 1717 AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0), 1718 SOC_SINGLE("ClassD White Volume", 1719 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN, 1720 AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0), 1721 1722 /* Mic 1, Mic 2, LineIn */ 1723 SOC_DOUBLE_R_TLV("Mic Master Volume", 1724 AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4, 1725 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv), 1726 1727 /* Mic 1 */ 1728 SOC_SINGLE_TLV("Mic 1", 1729 AB8500_ANAGAIN1, 1730 AB8500_ANAGAINX_MICXGAIN, 1731 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv), 1732 SOC_SINGLE("Mic 1 Low Power Switch", 1733 AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX, 1734 1, 0), 1735 1736 /* Mic 2 */ 1737 SOC_DOUBLE("Mic High Pass Switch", 1738 AB8500_ADFILTCONF, 1739 AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH, 1740 1, 1), 1741 SOC_ENUM("Mic Mode", soc_enum_ad34voice), 1742 SOC_ENUM("Mic Filter", soc_enum_dmic34sinc), 1743 SOC_SINGLE_TLV("Mic 2", 1744 AB8500_ANAGAIN2, 1745 AB8500_ANAGAINX_MICXGAIN, 1746 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv), 1747 SOC_SINGLE("Mic 2 Low Power Switch", 1748 AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX, 1749 1, 0), 1750 1751 /* LineIn */ 1752 SOC_DOUBLE("LineIn High Pass Switch", 1753 AB8500_ADFILTCONF, 1754 AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH, 1755 1, 1), 1756 SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc), 1757 SOC_ENUM("LineIn Mode", soc_enum_ad12voice), 1758 SOC_DOUBLE_R_TLV("LineIn Master Volume", 1759 AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2, 1760 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv), 1761 SOC_DOUBLE_TLV("LineIn", 1762 AB8500_ANAGAIN4, 1763 AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN, 1764 AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv), 1765 SOC_DOUBLE_R_TLV("LineIn to Headset Volume", 1766 AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN, 1767 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN, 1768 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX, 1769 1, lin2hs_gain_tlv), 1770 1771 /* DMic */ 1772 SOC_ENUM("DMic Filter", soc_enum_dmic56sinc), 1773 SOC_DOUBLE_R_TLV("DMic Master Volume", 1774 AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6, 1775 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv), 1776 1777 /* Digital gains */ 1778 SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed), 1779 1780 /* Analog loopback */ 1781 SOC_DOUBLE_R_TLV("Analog Loopback Volume", 1782 AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2, 1783 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv), 1784 1785 /* Digital interface - DA from slot mapping */ 1786 SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap), 1787 SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap), 1788 SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap), 1789 SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap), 1790 SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap), 1791 SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap), 1792 SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap), 1793 SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap), 1794 1795 /* Digital interface - AD to slot mapping */ 1796 SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map), 1797 SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map), 1798 SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map), 1799 SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map), 1800 SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map), 1801 SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map), 1802 SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map), 1803 SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map), 1804 SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map), 1805 SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map), 1806 SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map), 1807 SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map), 1808 SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map), 1809 SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map), 1810 SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map), 1811 SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map), 1812 SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map), 1813 SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map), 1814 SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map), 1815 SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map), 1816 SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map), 1817 SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map), 1818 SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map), 1819 SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map), 1820 SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map), 1821 SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map), 1822 SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map), 1823 SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map), 1824 SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map), 1825 SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map), 1826 SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map), 1827 SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map), 1828 1829 /* Digital interface - Loopback */ 1830 SOC_SINGLE("Digital Interface AD 1 Loopback Switch", 1831 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1, 1832 1, 0), 1833 SOC_SINGLE("Digital Interface AD 2 Loopback Switch", 1834 AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2, 1835 1, 0), 1836 SOC_SINGLE("Digital Interface AD 3 Loopback Switch", 1837 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3, 1838 1, 0), 1839 SOC_SINGLE("Digital Interface AD 4 Loopback Switch", 1840 AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4, 1841 1, 0), 1842 SOC_SINGLE("Digital Interface AD 5 Loopback Switch", 1843 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5, 1844 1, 0), 1845 SOC_SINGLE("Digital Interface AD 6 Loopback Switch", 1846 AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6, 1847 1, 0), 1848 SOC_SINGLE("Digital Interface AD 7 Loopback Switch", 1849 AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7, 1850 1, 0), 1851 SOC_SINGLE("Digital Interface AD 8 Loopback Switch", 1852 AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8, 1853 1, 0), 1854 1855 /* Digital interface - Burst FIFO */ 1856 SOC_SINGLE("Digital Interface 0 FIFO Enable Switch", 1857 AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN, 1858 1, 0), 1859 SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask), 1860 SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2), 1861 SOC_SINGLE("Burst FIFO Threshold", 1862 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT, 1863 AB8500_FIFOCONF1_BFIFOINT_MAX, 0), 1864 SOC_SINGLE("Burst FIFO Length", 1865 AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT, 1866 AB8500_FIFOCONF2_BFIFOTX_MAX, 0), 1867 SOC_SINGLE("Burst FIFO EOS Extra Slots", 1868 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT, 1869 AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0), 1870 SOC_SINGLE("Burst FIFO FS Extra Bit-clocks", 1871 AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT, 1872 AB8500_FIFOCONF3_PREBITCLK0_MAX, 0), 1873 SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast), 1874 1875 SOC_SINGLE("Burst FIFO Interface Switch", 1876 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT, 1877 1, 0), 1878 SOC_SINGLE("Burst FIFO Switch Frame Number", 1879 AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT, 1880 AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0), 1881 SOC_SINGLE("Burst FIFO Wake Up Delay", 1882 AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT, 1883 AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0), 1884 SOC_SINGLE("Burst FIFO Samples In FIFO", 1885 AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT, 1886 AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0), 1887 1888 /* ANC */ 1889 SOC_ENUM_EXT("ANC Status", soc_enum_ancstate, 1890 anc_status_control_get, anc_status_control_put), 1891 SOC_SINGLE_XR_SX("ANC Warp Delay Shift", 1892 AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT, 1893 AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0), 1894 SOC_SINGLE_XR_SX("ANC FIR Output Shift", 1895 AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT, 1896 AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0), 1897 SOC_SINGLE_XR_SX("ANC IIR Output Shift", 1898 AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT, 1899 AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0), 1900 SOC_SINGLE_XR_SX("ANC Warp Delay", 1901 AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT, 1902 AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0), 1903 1904 /* Sidetone */ 1905 SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate, 1906 sid_status_control_get, sid_status_control_put), 1907 SOC_SINGLE_STROBE("Sidetone Reset", 1908 AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0), 1909 }; 1910 1911 static struct snd_kcontrol_new ab8500_filter_controls[] = { 1912 AB8500_FILTER_CONTROL("ANC FIR Coefficients", AB8500_ANC_FIR_COEFFS, 1913 AB8500_ANC_FIR_COEFF_MIN, AB8500_ANC_FIR_COEFF_MAX), 1914 AB8500_FILTER_CONTROL("ANC IIR Coefficients", AB8500_ANC_IIR_COEFFS, 1915 AB8500_ANC_IIR_COEFF_MIN, AB8500_ANC_IIR_COEFF_MAX), 1916 AB8500_FILTER_CONTROL("Sidetone FIR Coefficients", 1917 AB8500_SID_FIR_COEFFS, AB8500_SID_FIR_COEFF_MIN, 1918 AB8500_SID_FIR_COEFF_MAX) 1919 }; 1920 enum ab8500_filter { 1921 AB8500_FILTER_ANC_FIR = 0, 1922 AB8500_FILTER_ANC_IIR = 1, 1923 AB8500_FILTER_SID_FIR = 2, 1924 }; 1925 1926 /* 1927 * Extended interface for codec-driver 1928 */ 1929 1930 static int ab8500_audio_init_audioblock(struct snd_soc_codec *codec) 1931 { 1932 int status; 1933 1934 dev_dbg(codec->dev, "%s: Enter.\n", __func__); 1935 1936 /* Reset audio-registers and disable 32kHz-clock output 2 */ 1937 status = ab8500_sysctrl_write(AB8500_STW4500CTRL3, 1938 AB8500_STW4500CTRL3_CLK32KOUT2DIS | 1939 AB8500_STW4500CTRL3_RESETAUDN, 1940 AB8500_STW4500CTRL3_RESETAUDN); 1941 if (status < 0) 1942 return status; 1943 1944 return 0; 1945 } 1946 1947 static int ab8500_audio_setup_mics(struct snd_soc_codec *codec, 1948 struct amic_settings *amics) 1949 { 1950 u8 value8; 1951 unsigned int value; 1952 int status; 1953 const struct snd_soc_dapm_route *route; 1954 1955 dev_dbg(codec->dev, "%s: Enter.\n", __func__); 1956 1957 /* Set DMic-clocks to outputs */ 1958 status = abx500_get_register_interruptible(codec->dev, AB8500_MISC, 1959 AB8500_GPIO_DIR4_REG, 1960 &value8); 1961 if (status < 0) 1962 return status; 1963 value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT | 1964 GPIO31_DIR_OUTPUT; 1965 status = abx500_set_register_interruptible(codec->dev, 1966 AB8500_MISC, 1967 AB8500_GPIO_DIR4_REG, 1968 value); 1969 if (status < 0) 1970 return status; 1971 1972 /* Attach regulators to AMic DAPM-paths */ 1973 dev_dbg(codec->dev, "%s: Mic 1a regulator: %s\n", __func__, 1974 amic_micbias_str(amics->mic1a_micbias)); 1975 route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias]; 1976 status = snd_soc_dapm_add_routes(&codec->dapm, route, 1); 1977 dev_dbg(codec->dev, "%s: Mic 1b regulator: %s\n", __func__, 1978 amic_micbias_str(amics->mic1b_micbias)); 1979 route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias]; 1980 status |= snd_soc_dapm_add_routes(&codec->dapm, route, 1); 1981 dev_dbg(codec->dev, "%s: Mic 2 regulator: %s\n", __func__, 1982 amic_micbias_str(amics->mic2_micbias)); 1983 route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias]; 1984 status |= snd_soc_dapm_add_routes(&codec->dapm, route, 1); 1985 if (status < 0) { 1986 dev_err(codec->dev, 1987 "%s: Failed to add AMic-regulator DAPM-routes (%d).\n", 1988 __func__, status); 1989 return status; 1990 } 1991 1992 /* Set AMic-configuration */ 1993 dev_dbg(codec->dev, "%s: Mic 1 mic-type: %s\n", __func__, 1994 amic_type_str(amics->mic1_type)); 1995 snd_soc_update_bits(codec, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX, 1996 amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ? 1997 0 : AB8500_ANAGAINX_ENSEMICX); 1998 dev_dbg(codec->dev, "%s: Mic 2 mic-type: %s\n", __func__, 1999 amic_type_str(amics->mic2_type)); 2000 snd_soc_update_bits(codec, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX, 2001 amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ? 2002 0 : AB8500_ANAGAINX_ENSEMICX); 2003 2004 return 0; 2005 } 2006 EXPORT_SYMBOL_GPL(ab8500_audio_setup_mics); 2007 2008 static int ab8500_audio_set_ear_cmv(struct snd_soc_codec *codec, 2009 enum ear_cm_voltage ear_cmv) 2010 { 2011 char *cmv_str; 2012 2013 switch (ear_cmv) { 2014 case EAR_CMV_0_95V: 2015 cmv_str = "0.95V"; 2016 break; 2017 case EAR_CMV_1_10V: 2018 cmv_str = "1.10V"; 2019 break; 2020 case EAR_CMV_1_27V: 2021 cmv_str = "1.27V"; 2022 break; 2023 case EAR_CMV_1_58V: 2024 cmv_str = "1.58V"; 2025 break; 2026 default: 2027 dev_err(codec->dev, 2028 "%s: Unknown earpiece CM-voltage (%d)!\n", 2029 __func__, (int)ear_cmv); 2030 return -EINVAL; 2031 } 2032 dev_dbg(codec->dev, "%s: Earpiece CM-voltage: %s\n", __func__, 2033 cmv_str); 2034 snd_soc_update_bits(codec, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM, 2035 ear_cmv); 2036 2037 return 0; 2038 } 2039 EXPORT_SYMBOL_GPL(ab8500_audio_set_ear_cmv); 2040 2041 static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai, 2042 unsigned int delay) 2043 { 2044 unsigned int mask, val; 2045 struct snd_soc_codec *codec = dai->codec; 2046 2047 mask = BIT(AB8500_DIGIFCONF2_IF0DEL); 2048 val = 0; 2049 2050 switch (delay) { 2051 case 0: 2052 break; 2053 case 1: 2054 val |= BIT(AB8500_DIGIFCONF2_IF0DEL); 2055 break; 2056 default: 2057 dev_err(dai->codec->dev, 2058 "%s: ERROR: Unsupported bit-delay (0x%x)!\n", 2059 __func__, delay); 2060 return -EINVAL; 2061 } 2062 2063 dev_dbg(dai->codec->dev, "%s: IF0 Bit-delay: %d bits.\n", 2064 __func__, delay); 2065 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val); 2066 2067 return 0; 2068 } 2069 2070 /* Gates clocking according format mask */ 2071 static int ab8500_codec_set_dai_clock_gate(struct snd_soc_codec *codec, 2072 unsigned int fmt) 2073 { 2074 unsigned int mask; 2075 unsigned int val; 2076 2077 mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) | 2078 BIT(AB8500_DIGIFCONF1_ENFSBITCLK0); 2079 2080 val = BIT(AB8500_DIGIFCONF1_ENMASTGEN); 2081 2082 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) { 2083 case SND_SOC_DAIFMT_CONT: /* continuous clock */ 2084 dev_dbg(codec->dev, "%s: IF0 Clock is continuous.\n", 2085 __func__); 2086 val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0); 2087 break; 2088 case SND_SOC_DAIFMT_GATED: /* clock is gated */ 2089 dev_dbg(codec->dev, "%s: IF0 Clock is gated.\n", 2090 __func__); 2091 break; 2092 default: 2093 dev_err(codec->dev, 2094 "%s: ERROR: Unsupported clock mask (0x%x)!\n", 2095 __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK); 2096 return -EINVAL; 2097 } 2098 2099 snd_soc_update_bits(codec, AB8500_DIGIFCONF1, mask, val); 2100 2101 return 0; 2102 } 2103 2104 static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2105 { 2106 unsigned int mask; 2107 unsigned int val; 2108 struct snd_soc_codec *codec = dai->codec; 2109 int status; 2110 2111 dev_dbg(codec->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt); 2112 2113 mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) | 2114 BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) | 2115 BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) | 2116 BIT(AB8500_DIGIFCONF3_IF0MASTER); 2117 val = 0; 2118 2119 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2120 case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & FRM master */ 2121 dev_dbg(dai->codec->dev, 2122 "%s: IF0 Master-mode: AB8500 master.\n", __func__); 2123 val |= BIT(AB8500_DIGIFCONF3_IF0MASTER); 2124 break; 2125 case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & FRM slave */ 2126 dev_dbg(dai->codec->dev, 2127 "%s: IF0 Master-mode: AB8500 slave.\n", __func__); 2128 break; 2129 case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & FRM master */ 2130 case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */ 2131 dev_err(dai->codec->dev, 2132 "%s: ERROR: The device is either a master or a slave.\n", 2133 __func__); 2134 default: 2135 dev_err(dai->codec->dev, 2136 "%s: ERROR: Unsupporter master mask 0x%x\n", 2137 __func__, fmt & SND_SOC_DAIFMT_MASTER_MASK); 2138 return -EINVAL; 2139 break; 2140 } 2141 2142 snd_soc_update_bits(codec, AB8500_DIGIFCONF3, mask, val); 2143 2144 /* Set clock gating */ 2145 status = ab8500_codec_set_dai_clock_gate(codec, fmt); 2146 if (status) { 2147 dev_err(dai->codec->dev, 2148 "%s: ERROR: Failed to set clock gate (%d).\n", 2149 __func__, status); 2150 return status; 2151 } 2152 2153 /* Setting data transfer format */ 2154 2155 mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) | 2156 BIT(AB8500_DIGIFCONF2_IF0FORMAT1) | 2157 BIT(AB8500_DIGIFCONF2_FSYNC0P) | 2158 BIT(AB8500_DIGIFCONF2_BITCLK0P); 2159 val = 0; 2160 2161 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2162 case SND_SOC_DAIFMT_I2S: /* I2S mode */ 2163 dev_dbg(dai->codec->dev, "%s: IF0 Protocol: I2S\n", __func__); 2164 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1); 2165 ab8500_audio_set_bit_delay(dai, 0); 2166 break; 2167 2168 case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */ 2169 dev_dbg(dai->codec->dev, 2170 "%s: IF0 Protocol: DSP A (TDM)\n", __func__); 2171 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0); 2172 ab8500_audio_set_bit_delay(dai, 1); 2173 break; 2174 2175 case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */ 2176 dev_dbg(dai->codec->dev, 2177 "%s: IF0 Protocol: DSP B (TDM)\n", __func__); 2178 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0); 2179 ab8500_audio_set_bit_delay(dai, 0); 2180 break; 2181 2182 default: 2183 dev_err(dai->codec->dev, 2184 "%s: ERROR: Unsupported format (0x%x)!\n", 2185 __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 2186 return -EINVAL; 2187 } 2188 2189 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2190 case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */ 2191 dev_dbg(dai->codec->dev, 2192 "%s: IF0: Normal bit clock, normal frame\n", 2193 __func__); 2194 break; 2195 case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */ 2196 dev_dbg(dai->codec->dev, 2197 "%s: IF0: Normal bit clock, inverted frame\n", 2198 __func__); 2199 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P); 2200 break; 2201 case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */ 2202 dev_dbg(dai->codec->dev, 2203 "%s: IF0: Inverted bit clock, normal frame\n", 2204 __func__); 2205 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P); 2206 break; 2207 case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */ 2208 dev_dbg(dai->codec->dev, 2209 "%s: IF0: Inverted bit clock, inverted frame\n", 2210 __func__); 2211 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P); 2212 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P); 2213 break; 2214 default: 2215 dev_err(dai->codec->dev, 2216 "%s: ERROR: Unsupported INV mask 0x%x\n", 2217 __func__, fmt & SND_SOC_DAIFMT_INV_MASK); 2218 return -EINVAL; 2219 } 2220 2221 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val); 2222 2223 return 0; 2224 } 2225 2226 static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai, 2227 unsigned int tx_mask, unsigned int rx_mask, 2228 int slots, int slot_width) 2229 { 2230 struct snd_soc_codec *codec = dai->codec; 2231 unsigned int val, mask, slot, slots_active; 2232 2233 mask = BIT(AB8500_DIGIFCONF2_IF0WL0) | 2234 BIT(AB8500_DIGIFCONF2_IF0WL1); 2235 val = 0; 2236 2237 switch (slot_width) { 2238 case 16: 2239 break; 2240 case 20: 2241 val |= BIT(AB8500_DIGIFCONF2_IF0WL0); 2242 break; 2243 case 24: 2244 val |= BIT(AB8500_DIGIFCONF2_IF0WL1); 2245 break; 2246 case 32: 2247 val |= BIT(AB8500_DIGIFCONF2_IF0WL1) | 2248 BIT(AB8500_DIGIFCONF2_IF0WL0); 2249 break; 2250 default: 2251 dev_err(dai->codec->dev, "%s: Unsupported slot-width 0x%x\n", 2252 __func__, slot_width); 2253 return -EINVAL; 2254 } 2255 2256 dev_dbg(dai->codec->dev, "%s: IF0 slot-width: %d bits.\n", 2257 __func__, slot_width); 2258 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val); 2259 2260 /* Setup TDM clocking according to slot count */ 2261 dev_dbg(dai->codec->dev, "%s: Slots, total: %d\n", __func__, slots); 2262 mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) | 2263 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); 2264 switch (slots) { 2265 case 2: 2266 val = AB8500_MASK_NONE; 2267 break; 2268 case 4: 2269 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0); 2270 break; 2271 case 8: 2272 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); 2273 break; 2274 case 16: 2275 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) | 2276 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); 2277 break; 2278 default: 2279 dev_err(dai->codec->dev, 2280 "%s: ERROR: Unsupported number of slots (%d)!\n", 2281 __func__, slots); 2282 return -EINVAL; 2283 } 2284 snd_soc_update_bits(codec, AB8500_DIGIFCONF1, mask, val); 2285 2286 /* Setup TDM DA according to active tx slots */ 2287 2288 if (tx_mask & ~0xff) 2289 return -EINVAL; 2290 2291 mask = AB8500_DASLOTCONFX_SLTODAX_MASK; 2292 tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET; 2293 slots_active = hweight32(tx_mask); 2294 2295 dev_dbg(dai->codec->dev, "%s: Slots, active, TX: %d\n", __func__, 2296 slots_active); 2297 2298 switch (slots_active) { 2299 case 0: 2300 break; 2301 case 1: 2302 slot = ffs(tx_mask); 2303 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot); 2304 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot); 2305 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot); 2306 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot); 2307 break; 2308 case 2: 2309 slot = ffs(tx_mask); 2310 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot); 2311 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot); 2312 slot = fls(tx_mask); 2313 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot); 2314 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot); 2315 break; 2316 case 8: 2317 dev_dbg(dai->codec->dev, 2318 "%s: In 8-channel mode DA-from-slot mapping is set manually.", 2319 __func__); 2320 break; 2321 default: 2322 dev_err(dai->codec->dev, 2323 "%s: Unsupported number of active TX-slots (%d)!\n", 2324 __func__, slots_active); 2325 return -EINVAL; 2326 } 2327 2328 /* Setup TDM AD according to active RX-slots */ 2329 2330 if (rx_mask & ~0xff) 2331 return -EINVAL; 2332 2333 rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET; 2334 slots_active = hweight32(rx_mask); 2335 2336 dev_dbg(dai->codec->dev, "%s: Slots, active, RX: %d\n", __func__, 2337 slots_active); 2338 2339 switch (slots_active) { 2340 case 0: 2341 break; 2342 case 1: 2343 slot = ffs(rx_mask); 2344 snd_soc_update_bits(codec, AB8500_ADSLOTSEL(slot), 2345 AB8500_MASK_SLOT(slot), 2346 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot)); 2347 break; 2348 case 2: 2349 slot = ffs(rx_mask); 2350 snd_soc_update_bits(codec, 2351 AB8500_ADSLOTSEL(slot), 2352 AB8500_MASK_SLOT(slot), 2353 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot)); 2354 slot = fls(rx_mask); 2355 snd_soc_update_bits(codec, 2356 AB8500_ADSLOTSEL(slot), 2357 AB8500_MASK_SLOT(slot), 2358 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot)); 2359 break; 2360 case 8: 2361 dev_dbg(dai->codec->dev, 2362 "%s: In 8-channel mode AD-to-slot mapping is set manually.", 2363 __func__); 2364 break; 2365 default: 2366 dev_err(dai->codec->dev, 2367 "%s: Unsupported number of active RX-slots (%d)!\n", 2368 __func__, slots_active); 2369 return -EINVAL; 2370 } 2371 2372 return 0; 2373 } 2374 2375 static const struct snd_soc_dai_ops ab8500_codec_ops = { 2376 .set_fmt = ab8500_codec_set_dai_fmt, 2377 .set_tdm_slot = ab8500_codec_set_dai_tdm_slot, 2378 }; 2379 2380 static struct snd_soc_dai_driver ab8500_codec_dai[] = { 2381 { 2382 .name = "ab8500-codec-dai.0", 2383 .id = 0, 2384 .playback = { 2385 .stream_name = "ab8500_0p", 2386 .channels_min = 1, 2387 .channels_max = 8, 2388 .rates = AB8500_SUPPORTED_RATE, 2389 .formats = AB8500_SUPPORTED_FMT, 2390 }, 2391 .ops = &ab8500_codec_ops, 2392 .symmetric_rates = 1 2393 }, 2394 { 2395 .name = "ab8500-codec-dai.1", 2396 .id = 1, 2397 .capture = { 2398 .stream_name = "ab8500_0c", 2399 .channels_min = 1, 2400 .channels_max = 8, 2401 .rates = AB8500_SUPPORTED_RATE, 2402 .formats = AB8500_SUPPORTED_FMT, 2403 }, 2404 .ops = &ab8500_codec_ops, 2405 .symmetric_rates = 1 2406 } 2407 }; 2408 2409 static void ab8500_codec_of_probe(struct device *dev, struct device_node *np, 2410 struct ab8500_codec_platform_data *codec) 2411 { 2412 u32 value; 2413 2414 if (of_get_property(np, "stericsson,amic1-type-single-ended", NULL)) 2415 codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED; 2416 else 2417 codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL; 2418 2419 if (of_get_property(np, "stericsson,amic2-type-single-ended", NULL)) 2420 codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED; 2421 else 2422 codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL; 2423 2424 /* Has a non-standard Vamic been requested? */ 2425 if (of_get_property(np, "stericsson,amic1a-bias-vamic2", NULL)) 2426 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2; 2427 else 2428 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1; 2429 2430 if (of_get_property(np, "stericsson,amic1b-bias-vamic2", NULL)) 2431 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2; 2432 else 2433 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1; 2434 2435 if (of_get_property(np, "stericsson,amic2-bias-vamic1", NULL)) 2436 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1; 2437 else 2438 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2; 2439 2440 if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) { 2441 switch (value) { 2442 case 950 : 2443 codec->ear_cmv = EAR_CMV_0_95V; 2444 break; 2445 case 1100 : 2446 codec->ear_cmv = EAR_CMV_1_10V; 2447 break; 2448 case 1270 : 2449 codec->ear_cmv = EAR_CMV_1_27V; 2450 break; 2451 case 1580 : 2452 codec->ear_cmv = EAR_CMV_1_58V; 2453 break; 2454 default : 2455 codec->ear_cmv = EAR_CMV_UNKNOWN; 2456 dev_err(dev, "Unsuitable earpiece voltage found in DT\n"); 2457 } 2458 } else { 2459 dev_warn(dev, "No earpiece voltage found in DT - using default\n"); 2460 codec->ear_cmv = EAR_CMV_0_95V; 2461 } 2462 } 2463 2464 static int ab8500_codec_probe(struct snd_soc_codec *codec) 2465 { 2466 struct device *dev = codec->dev; 2467 struct device_node *np = dev->of_node; 2468 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev); 2469 struct ab8500_platform_data *pdata; 2470 struct filter_control *fc; 2471 int status; 2472 2473 dev_dbg(dev, "%s: Enter.\n", __func__); 2474 2475 /* Setup AB8500 according to board-settings */ 2476 pdata = dev_get_platdata(dev->parent); 2477 2478 if (np) { 2479 if (!pdata) 2480 pdata = devm_kzalloc(dev, 2481 sizeof(struct ab8500_platform_data), 2482 GFP_KERNEL); 2483 2484 if (pdata && !pdata->codec) 2485 pdata->codec 2486 = devm_kzalloc(dev, 2487 sizeof(struct ab8500_codec_platform_data), 2488 GFP_KERNEL); 2489 2490 if (!(pdata && pdata->codec)) 2491 return -ENOMEM; 2492 2493 ab8500_codec_of_probe(dev, np, pdata->codec); 2494 2495 } else { 2496 if (!(pdata && pdata->codec)) { 2497 dev_err(dev, "No codec platform data or DT found\n"); 2498 return -EINVAL; 2499 } 2500 } 2501 2502 status = ab8500_audio_setup_mics(codec, &pdata->codec->amics); 2503 if (status < 0) { 2504 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status); 2505 return status; 2506 } 2507 status = ab8500_audio_set_ear_cmv(codec, pdata->codec->ear_cmv); 2508 if (status < 0) { 2509 pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n", 2510 __func__, status); 2511 return status; 2512 } 2513 2514 status = ab8500_audio_init_audioblock(codec); 2515 if (status < 0) { 2516 dev_err(dev, "%s: failed to init audio-block (%d)!\n", 2517 __func__, status); 2518 return status; 2519 } 2520 2521 /* Override HW-defaults */ 2522 snd_soc_write(codec, AB8500_ANACONF5, 2523 BIT(AB8500_ANACONF5_HSAUTOEN)); 2524 snd_soc_write(codec, AB8500_SHORTCIRCONF, 2525 BIT(AB8500_SHORTCIRCONF_HSZCDDIS)); 2526 2527 /* Add filter controls */ 2528 status = snd_soc_add_codec_controls(codec, ab8500_filter_controls, 2529 ARRAY_SIZE(ab8500_filter_controls)); 2530 if (status < 0) { 2531 dev_err(dev, 2532 "%s: failed to add ab8500 filter controls (%d).\n", 2533 __func__, status); 2534 return status; 2535 } 2536 fc = (struct filter_control *) 2537 &ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value; 2538 drvdata->anc_fir_values = (long *)fc->value; 2539 fc = (struct filter_control *) 2540 &ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value; 2541 drvdata->anc_iir_values = (long *)fc->value; 2542 fc = (struct filter_control *) 2543 &ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value; 2544 drvdata->sid_fir_values = (long *)fc->value; 2545 2546 (void)snd_soc_dapm_disable_pin(&codec->dapm, "ANC Configure Input"); 2547 2548 mutex_init(&drvdata->ctrl_lock); 2549 2550 return status; 2551 } 2552 2553 static struct snd_soc_codec_driver ab8500_codec_driver = { 2554 .probe = ab8500_codec_probe, 2555 .controls = ab8500_ctrls, 2556 .num_controls = ARRAY_SIZE(ab8500_ctrls), 2557 .dapm_widgets = ab8500_dapm_widgets, 2558 .num_dapm_widgets = ARRAY_SIZE(ab8500_dapm_widgets), 2559 .dapm_routes = ab8500_dapm_routes, 2560 .num_dapm_routes = ARRAY_SIZE(ab8500_dapm_routes), 2561 }; 2562 2563 static int ab8500_codec_driver_probe(struct platform_device *pdev) 2564 { 2565 int status; 2566 struct ab8500_codec_drvdata *drvdata; 2567 2568 dev_dbg(&pdev->dev, "%s: Enter.\n", __func__); 2569 2570 /* Create driver private-data struct */ 2571 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata), 2572 GFP_KERNEL); 2573 if (!drvdata) 2574 return -ENOMEM; 2575 drvdata->sid_status = SID_UNCONFIGURED; 2576 drvdata->anc_status = ANC_UNCONFIGURED; 2577 dev_set_drvdata(&pdev->dev, drvdata); 2578 2579 drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev, 2580 &ab8500_codec_regmap); 2581 if (IS_ERR(drvdata->regmap)) { 2582 status = PTR_ERR(drvdata->regmap); 2583 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n", 2584 __func__, status); 2585 return status; 2586 } 2587 2588 dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__); 2589 status = snd_soc_register_codec(&pdev->dev, &ab8500_codec_driver, 2590 ab8500_codec_dai, 2591 ARRAY_SIZE(ab8500_codec_dai)); 2592 if (status < 0) 2593 dev_err(&pdev->dev, 2594 "%s: Error: Failed to register codec (%d).\n", 2595 __func__, status); 2596 2597 return status; 2598 } 2599 2600 static int ab8500_codec_driver_remove(struct platform_device *pdev) 2601 { 2602 dev_dbg(&pdev->dev, "%s Enter.\n", __func__); 2603 2604 snd_soc_unregister_codec(&pdev->dev); 2605 2606 return 0; 2607 } 2608 2609 static struct platform_driver ab8500_codec_platform_driver = { 2610 .driver = { 2611 .name = "ab8500-codec", 2612 }, 2613 .probe = ab8500_codec_driver_probe, 2614 .remove = ab8500_codec_driver_remove, 2615 .suspend = NULL, 2616 .resume = NULL, 2617 }; 2618 module_platform_driver(ab8500_codec_platform_driver); 2619 2620 MODULE_LICENSE("GPL v2"); 2621