1 /* 2 * linux/sound/soc/ep93xx-i2s.c 3 * EP93xx I2S driver 4 * 5 * Copyright (C) 2010 Ryan Mallon 6 * 7 * Based on the original driver by: 8 * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail> 9 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 */ 16 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/slab.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 23 #include <sound/core.h> 24 #include <sound/dmaengine_pcm.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/initval.h> 28 #include <sound/soc.h> 29 30 #include <mach/hardware.h> 31 #include <mach/ep93xx-regs.h> 32 #include <linux/platform_data/dma-ep93xx.h> 33 34 #include "ep93xx-pcm.h" 35 36 #define EP93XX_I2S_TXCLKCFG 0x00 37 #define EP93XX_I2S_RXCLKCFG 0x04 38 #define EP93XX_I2S_GLSTS 0x08 39 #define EP93XX_I2S_GLCTRL 0x0C 40 41 #define EP93XX_I2S_I2STX0LFT 0x10 42 #define EP93XX_I2S_I2STX0RT 0x14 43 44 #define EP93XX_I2S_TXLINCTRLDATA 0x28 45 #define EP93XX_I2S_TXCTRL 0x2C 46 #define EP93XX_I2S_TXWRDLEN 0x30 47 #define EP93XX_I2S_TX0EN 0x34 48 49 #define EP93XX_I2S_RXLINCTRLDATA 0x58 50 #define EP93XX_I2S_RXCTRL 0x5C 51 #define EP93XX_I2S_RXWRDLEN 0x60 52 #define EP93XX_I2S_RX0EN 0x64 53 54 #define EP93XX_I2S_WRDLEN_16 (0 << 0) 55 #define EP93XX_I2S_WRDLEN_24 (1 << 0) 56 #define EP93XX_I2S_WRDLEN_32 (2 << 0) 57 58 #define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */ 59 60 #define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */ 61 62 /* 63 * Transmit empty interrupt level select: 64 * 0 - Generate interrupt when FIFO is half empty 65 * 1 - Generate interrupt when FIFO is empty 66 */ 67 #define EP93XX_I2S_TXCTRL_TXEMPTY_LVL BIT(0) 68 #define EP93XX_I2S_TXCTRL_TXUFIE BIT(1) /* Transmit interrupt enable */ 69 70 #define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */ 71 #define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */ 72 #define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */ 73 #define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */ 74 #define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */ 75 76 #define EP93XX_I2S_GLSTS_TX0_FIFO_FULL BIT(12) 77 78 struct ep93xx_i2s_info { 79 struct clk *mclk; 80 struct clk *sclk; 81 struct clk *lrclk; 82 void __iomem *regs; 83 struct snd_dmaengine_dai_dma_data dma_params_rx; 84 struct snd_dmaengine_dai_dma_data dma_params_tx; 85 }; 86 87 static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = { 88 [SNDRV_PCM_STREAM_PLAYBACK] = { 89 .name = "i2s-pcm-out", 90 .port = EP93XX_DMA_I2S1, 91 .direction = DMA_MEM_TO_DEV, 92 }, 93 [SNDRV_PCM_STREAM_CAPTURE] = { 94 .name = "i2s-pcm-in", 95 .port = EP93XX_DMA_I2S1, 96 .direction = DMA_DEV_TO_MEM, 97 }, 98 }; 99 100 static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info, 101 unsigned reg, unsigned val) 102 { 103 __raw_writel(val, info->regs + reg); 104 } 105 106 static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info, 107 unsigned reg) 108 { 109 return __raw_readl(info->regs + reg); 110 } 111 112 static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream) 113 { 114 unsigned base_reg; 115 116 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 && 117 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) { 118 /* Enable clocks */ 119 clk_enable(info->mclk); 120 clk_enable(info->sclk); 121 clk_enable(info->lrclk); 122 123 /* Enable i2s */ 124 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1); 125 } 126 127 /* Enable fifo */ 128 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 129 base_reg = EP93XX_I2S_TX0EN; 130 else 131 base_reg = EP93XX_I2S_RX0EN; 132 ep93xx_i2s_write_reg(info, base_reg, 1); 133 134 /* Enable TX IRQs (FIFO empty or underflow) */ 135 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) && 136 stream == SNDRV_PCM_STREAM_PLAYBACK) 137 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 138 EP93XX_I2S_TXCTRL_TXEMPTY_LVL | 139 EP93XX_I2S_TXCTRL_TXUFIE); 140 } 141 142 static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream) 143 { 144 unsigned base_reg; 145 146 /* Disable IRQs */ 147 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) && 148 stream == SNDRV_PCM_STREAM_PLAYBACK) 149 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 0); 150 151 /* Disable fifo */ 152 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 153 base_reg = EP93XX_I2S_TX0EN; 154 else 155 base_reg = EP93XX_I2S_RX0EN; 156 ep93xx_i2s_write_reg(info, base_reg, 0); 157 158 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 && 159 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) { 160 /* Disable i2s */ 161 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0); 162 163 /* Disable clocks */ 164 clk_disable(info->lrclk); 165 clk_disable(info->sclk); 166 clk_disable(info->mclk); 167 } 168 } 169 170 /* 171 * According to documentation I2S controller can handle underflow conditions 172 * just fine, but in reality the state machine is sometimes confused so that 173 * the whole stream is shifted by one byte. The watchdog below disables the TX 174 * FIFO, fills the buffer with zeroes and re-enables the FIFO. State machine 175 * is being reset and by filling the buffer we get some time before next 176 * underflow happens. 177 */ 178 static irqreturn_t ep93xx_i2s_interrupt(int irq, void *dev_id) 179 { 180 struct ep93xx_i2s_info *info = dev_id; 181 182 /* Disable FIFO */ 183 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 0); 184 /* 185 * Fill TX FIFO with zeroes, this way we can defer next IRQs as much as 186 * possible and get more time for DMA to catch up. Actually there are 187 * only 8 samples in this FIFO, so even on 8kHz maximum deferral here is 188 * 1ms. 189 */ 190 while (!(ep93xx_i2s_read_reg(info, EP93XX_I2S_GLSTS) & 191 EP93XX_I2S_GLSTS_TX0_FIFO_FULL)) { 192 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0LFT, 0); 193 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0RT, 0); 194 } 195 /* Re-enable FIFO */ 196 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 1); 197 198 return IRQ_HANDLED; 199 } 200 201 static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai) 202 { 203 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 204 205 info->dma_params_tx.filter_data = 206 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 207 info->dma_params_rx.filter_data = 208 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE]; 209 210 dai->playback_dma_data = &info->dma_params_tx; 211 dai->capture_dma_data = &info->dma_params_rx; 212 213 return 0; 214 } 215 216 static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream, 217 struct snd_soc_dai *dai) 218 { 219 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 220 221 ep93xx_i2s_disable(info, substream->stream); 222 } 223 224 static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, 225 unsigned int fmt) 226 { 227 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai); 228 unsigned int clk_cfg; 229 unsigned int txlin_ctrl = 0; 230 unsigned int rxlin_ctrl = 0; 231 232 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG); 233 234 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 235 case SND_SOC_DAIFMT_I2S: 236 clk_cfg |= EP93XX_I2S_CLKCFG_REL; 237 break; 238 239 case SND_SOC_DAIFMT_LEFT_J: 240 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL; 241 break; 242 243 case SND_SOC_DAIFMT_RIGHT_J: 244 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL; 245 rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST; 246 txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST; 247 break; 248 249 default: 250 return -EINVAL; 251 } 252 253 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 254 case SND_SOC_DAIFMT_CBS_CFS: 255 /* CPU is master */ 256 clk_cfg |= EP93XX_I2S_CLKCFG_MASTER; 257 break; 258 259 case SND_SOC_DAIFMT_CBM_CFM: 260 /* Codec is master */ 261 clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER; 262 break; 263 264 default: 265 return -EINVAL; 266 } 267 268 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 269 case SND_SOC_DAIFMT_NB_NF: 270 /* Negative bit clock, lrclk low on left word */ 271 clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS); 272 break; 273 274 case SND_SOC_DAIFMT_NB_IF: 275 /* Negative bit clock, lrclk low on right word */ 276 clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP; 277 clk_cfg |= EP93XX_I2S_CLKCFG_LRS; 278 break; 279 280 case SND_SOC_DAIFMT_IB_NF: 281 /* Positive bit clock, lrclk low on left word */ 282 clk_cfg |= EP93XX_I2S_CLKCFG_CKP; 283 clk_cfg &= ~EP93XX_I2S_CLKCFG_LRS; 284 break; 285 286 case SND_SOC_DAIFMT_IB_IF: 287 /* Positive bit clock, lrclk low on right word */ 288 clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS; 289 break; 290 } 291 292 /* Write new register values */ 293 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg); 294 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg); 295 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl); 296 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl); 297 return 0; 298 } 299 300 static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream, 301 struct snd_pcm_hw_params *params, 302 struct snd_soc_dai *dai) 303 { 304 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 305 unsigned word_len, div, sdiv, lrdiv; 306 int err; 307 308 switch (params_format(params)) { 309 case SNDRV_PCM_FORMAT_S16_LE: 310 word_len = EP93XX_I2S_WRDLEN_16; 311 break; 312 313 case SNDRV_PCM_FORMAT_S24_LE: 314 word_len = EP93XX_I2S_WRDLEN_24; 315 break; 316 317 case SNDRV_PCM_FORMAT_S32_LE: 318 word_len = EP93XX_I2S_WRDLEN_32; 319 break; 320 321 default: 322 return -EINVAL; 323 } 324 325 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 326 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len); 327 else 328 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len); 329 330 /* 331 * EP93xx I2S module can be setup so SCLK / LRCLK value can be 332 * 32, 64, 128. MCLK / SCLK value can be 2 and 4. 333 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK 334 * value is 64, because our sample size is 32 bit * 2 channels. 335 * I2S standard permits us to transmit more bits than 336 * the codec uses. 337 */ 338 div = clk_get_rate(info->mclk) / params_rate(params); 339 sdiv = 4; 340 if (div > (256 + 512) / 2) { 341 lrdiv = 128; 342 } else { 343 lrdiv = 64; 344 if (div < (128 + 256) / 2) 345 sdiv = 2; 346 } 347 348 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); 349 if (err) 350 return err; 351 352 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv); 353 if (err) 354 return err; 355 356 ep93xx_i2s_enable(info, substream->stream); 357 return 0; 358 } 359 360 static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 361 unsigned int freq, int dir) 362 { 363 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai); 364 365 if (dir == SND_SOC_CLOCK_IN || clk_id != 0) 366 return -EINVAL; 367 368 return clk_set_rate(info->mclk, freq); 369 } 370 371 #ifdef CONFIG_PM 372 static int ep93xx_i2s_suspend(struct snd_soc_dai *dai) 373 { 374 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 375 376 if (!dai->active) 377 return 0; 378 379 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK); 380 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE); 381 382 return 0; 383 } 384 385 static int ep93xx_i2s_resume(struct snd_soc_dai *dai) 386 { 387 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 388 389 if (!dai->active) 390 return 0; 391 392 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK); 393 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE); 394 395 return 0; 396 } 397 #else 398 #define ep93xx_i2s_suspend NULL 399 #define ep93xx_i2s_resume NULL 400 #endif 401 402 static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = { 403 .shutdown = ep93xx_i2s_shutdown, 404 .hw_params = ep93xx_i2s_hw_params, 405 .set_sysclk = ep93xx_i2s_set_sysclk, 406 .set_fmt = ep93xx_i2s_set_dai_fmt, 407 }; 408 409 #define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) 410 411 static struct snd_soc_dai_driver ep93xx_i2s_dai = { 412 .symmetric_rates= 1, 413 .probe = ep93xx_i2s_dai_probe, 414 .suspend = ep93xx_i2s_suspend, 415 .resume = ep93xx_i2s_resume, 416 .playback = { 417 .channels_min = 2, 418 .channels_max = 2, 419 .rates = SNDRV_PCM_RATE_8000_192000, 420 .formats = EP93XX_I2S_FORMATS, 421 }, 422 .capture = { 423 .channels_min = 2, 424 .channels_max = 2, 425 .rates = SNDRV_PCM_RATE_8000_192000, 426 .formats = EP93XX_I2S_FORMATS, 427 }, 428 .ops = &ep93xx_i2s_dai_ops, 429 }; 430 431 static const struct snd_soc_component_driver ep93xx_i2s_component = { 432 .name = "ep93xx-i2s", 433 }; 434 435 static int ep93xx_i2s_probe(struct platform_device *pdev) 436 { 437 struct ep93xx_i2s_info *info; 438 struct resource *res; 439 int err; 440 441 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 442 if (!info) 443 return -ENOMEM; 444 445 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 446 info->regs = devm_ioremap_resource(&pdev->dev, res); 447 if (IS_ERR(info->regs)) 448 return PTR_ERR(info->regs); 449 450 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG)) { 451 int irq = platform_get_irq(pdev, 0); 452 if (irq <= 0) 453 return irq < 0 ? irq : -ENODEV; 454 455 err = devm_request_irq(&pdev->dev, irq, ep93xx_i2s_interrupt, 0, 456 pdev->name, info); 457 if (err) 458 return err; 459 } 460 461 info->mclk = clk_get(&pdev->dev, "mclk"); 462 if (IS_ERR(info->mclk)) { 463 err = PTR_ERR(info->mclk); 464 goto fail; 465 } 466 467 info->sclk = clk_get(&pdev->dev, "sclk"); 468 if (IS_ERR(info->sclk)) { 469 err = PTR_ERR(info->sclk); 470 goto fail_put_mclk; 471 } 472 473 info->lrclk = clk_get(&pdev->dev, "lrclk"); 474 if (IS_ERR(info->lrclk)) { 475 err = PTR_ERR(info->lrclk); 476 goto fail_put_sclk; 477 } 478 479 dev_set_drvdata(&pdev->dev, info); 480 481 err = snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component, 482 &ep93xx_i2s_dai, 1); 483 if (err) 484 goto fail_put_lrclk; 485 486 err = devm_ep93xx_pcm_platform_register(&pdev->dev); 487 if (err) 488 goto fail_unregister; 489 490 return 0; 491 492 fail_unregister: 493 snd_soc_unregister_component(&pdev->dev); 494 fail_put_lrclk: 495 clk_put(info->lrclk); 496 fail_put_sclk: 497 clk_put(info->sclk); 498 fail_put_mclk: 499 clk_put(info->mclk); 500 fail: 501 return err; 502 } 503 504 static int ep93xx_i2s_remove(struct platform_device *pdev) 505 { 506 struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev); 507 508 snd_soc_unregister_component(&pdev->dev); 509 clk_put(info->lrclk); 510 clk_put(info->sclk); 511 clk_put(info->mclk); 512 return 0; 513 } 514 515 static struct platform_driver ep93xx_i2s_driver = { 516 .probe = ep93xx_i2s_probe, 517 .remove = ep93xx_i2s_remove, 518 .driver = { 519 .name = "ep93xx-i2s", 520 }, 521 }; 522 523 module_platform_driver(ep93xx_i2s_driver); 524 525 MODULE_ALIAS("platform:ep93xx-i2s"); 526 MODULE_AUTHOR("Ryan Mallon"); 527 MODULE_DESCRIPTION("EP93XX I2S driver"); 528 MODULE_LICENSE("GPL"); 529