1 /* 2 * linux/sound/soc/ep93xx-i2s.c 3 * EP93xx I2S driver 4 * 5 * Copyright (C) 2010 Ryan Mallon 6 * 7 * Based on the original driver by: 8 * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail> 9 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 */ 16 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/slab.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 23 #include <sound/core.h> 24 #include <sound/dmaengine_pcm.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/initval.h> 28 #include <sound/soc.h> 29 30 #include <linux/platform_data/dma-ep93xx.h> 31 #include <linux/soc/cirrus/ep93xx.h> 32 33 #include "ep93xx-pcm.h" 34 35 #define EP93XX_I2S_TXCLKCFG 0x00 36 #define EP93XX_I2S_RXCLKCFG 0x04 37 #define EP93XX_I2S_GLSTS 0x08 38 #define EP93XX_I2S_GLCTRL 0x0C 39 40 #define EP93XX_I2S_I2STX0LFT 0x10 41 #define EP93XX_I2S_I2STX0RT 0x14 42 43 #define EP93XX_I2S_TXLINCTRLDATA 0x28 44 #define EP93XX_I2S_TXCTRL 0x2C 45 #define EP93XX_I2S_TXWRDLEN 0x30 46 #define EP93XX_I2S_TX0EN 0x34 47 48 #define EP93XX_I2S_RXLINCTRLDATA 0x58 49 #define EP93XX_I2S_RXCTRL 0x5C 50 #define EP93XX_I2S_RXWRDLEN 0x60 51 #define EP93XX_I2S_RX0EN 0x64 52 53 #define EP93XX_I2S_WRDLEN_16 (0 << 0) 54 #define EP93XX_I2S_WRDLEN_24 (1 << 0) 55 #define EP93XX_I2S_WRDLEN_32 (2 << 0) 56 57 #define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */ 58 59 #define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */ 60 61 /* 62 * Transmit empty interrupt level select: 63 * 0 - Generate interrupt when FIFO is half empty 64 * 1 - Generate interrupt when FIFO is empty 65 */ 66 #define EP93XX_I2S_TXCTRL_TXEMPTY_LVL BIT(0) 67 #define EP93XX_I2S_TXCTRL_TXUFIE BIT(1) /* Transmit interrupt enable */ 68 69 #define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */ 70 #define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */ 71 #define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */ 72 #define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */ 73 #define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */ 74 75 #define EP93XX_I2S_GLSTS_TX0_FIFO_FULL BIT(12) 76 77 struct ep93xx_i2s_info { 78 struct clk *mclk; 79 struct clk *sclk; 80 struct clk *lrclk; 81 void __iomem *regs; 82 struct snd_dmaengine_dai_dma_data dma_params_rx; 83 struct snd_dmaengine_dai_dma_data dma_params_tx; 84 }; 85 86 static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = { 87 [SNDRV_PCM_STREAM_PLAYBACK] = { 88 .name = "i2s-pcm-out", 89 .port = EP93XX_DMA_I2S1, 90 .direction = DMA_MEM_TO_DEV, 91 }, 92 [SNDRV_PCM_STREAM_CAPTURE] = { 93 .name = "i2s-pcm-in", 94 .port = EP93XX_DMA_I2S1, 95 .direction = DMA_DEV_TO_MEM, 96 }, 97 }; 98 99 static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info, 100 unsigned reg, unsigned val) 101 { 102 __raw_writel(val, info->regs + reg); 103 } 104 105 static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info, 106 unsigned reg) 107 { 108 return __raw_readl(info->regs + reg); 109 } 110 111 static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream) 112 { 113 unsigned base_reg; 114 115 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 && 116 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) { 117 /* Enable clocks */ 118 clk_enable(info->mclk); 119 clk_enable(info->sclk); 120 clk_enable(info->lrclk); 121 122 /* Enable i2s */ 123 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1); 124 } 125 126 /* Enable fifo */ 127 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 128 base_reg = EP93XX_I2S_TX0EN; 129 else 130 base_reg = EP93XX_I2S_RX0EN; 131 ep93xx_i2s_write_reg(info, base_reg, 1); 132 133 /* Enable TX IRQs (FIFO empty or underflow) */ 134 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) && 135 stream == SNDRV_PCM_STREAM_PLAYBACK) 136 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 137 EP93XX_I2S_TXCTRL_TXEMPTY_LVL | 138 EP93XX_I2S_TXCTRL_TXUFIE); 139 } 140 141 static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream) 142 { 143 unsigned base_reg; 144 145 /* Disable IRQs */ 146 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) && 147 stream == SNDRV_PCM_STREAM_PLAYBACK) 148 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 0); 149 150 /* Disable fifo */ 151 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 152 base_reg = EP93XX_I2S_TX0EN; 153 else 154 base_reg = EP93XX_I2S_RX0EN; 155 ep93xx_i2s_write_reg(info, base_reg, 0); 156 157 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 && 158 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) { 159 /* Disable i2s */ 160 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0); 161 162 /* Disable clocks */ 163 clk_disable(info->lrclk); 164 clk_disable(info->sclk); 165 clk_disable(info->mclk); 166 } 167 } 168 169 /* 170 * According to documentation I2S controller can handle underflow conditions 171 * just fine, but in reality the state machine is sometimes confused so that 172 * the whole stream is shifted by one byte. The watchdog below disables the TX 173 * FIFO, fills the buffer with zeroes and re-enables the FIFO. State machine 174 * is being reset and by filling the buffer we get some time before next 175 * underflow happens. 176 */ 177 static irqreturn_t ep93xx_i2s_interrupt(int irq, void *dev_id) 178 { 179 struct ep93xx_i2s_info *info = dev_id; 180 181 /* Disable FIFO */ 182 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 0); 183 /* 184 * Fill TX FIFO with zeroes, this way we can defer next IRQs as much as 185 * possible and get more time for DMA to catch up. Actually there are 186 * only 8 samples in this FIFO, so even on 8kHz maximum deferral here is 187 * 1ms. 188 */ 189 while (!(ep93xx_i2s_read_reg(info, EP93XX_I2S_GLSTS) & 190 EP93XX_I2S_GLSTS_TX0_FIFO_FULL)) { 191 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0LFT, 0); 192 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0RT, 0); 193 } 194 /* Re-enable FIFO */ 195 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 1); 196 197 return IRQ_HANDLED; 198 } 199 200 static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai) 201 { 202 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 203 204 info->dma_params_tx.filter_data = 205 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 206 info->dma_params_rx.filter_data = 207 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE]; 208 209 dai->playback_dma_data = &info->dma_params_tx; 210 dai->capture_dma_data = &info->dma_params_rx; 211 212 return 0; 213 } 214 215 static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream, 216 struct snd_soc_dai *dai) 217 { 218 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 219 220 ep93xx_i2s_disable(info, substream->stream); 221 } 222 223 static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, 224 unsigned int fmt) 225 { 226 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai); 227 unsigned int clk_cfg; 228 unsigned int txlin_ctrl = 0; 229 unsigned int rxlin_ctrl = 0; 230 231 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG); 232 233 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 234 case SND_SOC_DAIFMT_I2S: 235 clk_cfg |= EP93XX_I2S_CLKCFG_REL; 236 break; 237 238 case SND_SOC_DAIFMT_LEFT_J: 239 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL; 240 break; 241 242 case SND_SOC_DAIFMT_RIGHT_J: 243 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL; 244 rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST; 245 txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST; 246 break; 247 248 default: 249 return -EINVAL; 250 } 251 252 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 253 case SND_SOC_DAIFMT_CBS_CFS: 254 /* CPU is master */ 255 clk_cfg |= EP93XX_I2S_CLKCFG_MASTER; 256 break; 257 258 case SND_SOC_DAIFMT_CBM_CFM: 259 /* Codec is master */ 260 clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER; 261 break; 262 263 default: 264 return -EINVAL; 265 } 266 267 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 268 case SND_SOC_DAIFMT_NB_NF: 269 /* Negative bit clock, lrclk low on left word */ 270 clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS); 271 break; 272 273 case SND_SOC_DAIFMT_NB_IF: 274 /* Negative bit clock, lrclk low on right word */ 275 clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP; 276 clk_cfg |= EP93XX_I2S_CLKCFG_LRS; 277 break; 278 279 case SND_SOC_DAIFMT_IB_NF: 280 /* Positive bit clock, lrclk low on left word */ 281 clk_cfg |= EP93XX_I2S_CLKCFG_CKP; 282 clk_cfg &= ~EP93XX_I2S_CLKCFG_LRS; 283 break; 284 285 case SND_SOC_DAIFMT_IB_IF: 286 /* Positive bit clock, lrclk low on right word */ 287 clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS; 288 break; 289 } 290 291 /* Write new register values */ 292 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg); 293 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg); 294 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl); 295 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl); 296 return 0; 297 } 298 299 static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream, 300 struct snd_pcm_hw_params *params, 301 struct snd_soc_dai *dai) 302 { 303 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 304 unsigned word_len, div, sdiv, lrdiv; 305 int err; 306 307 switch (params_format(params)) { 308 case SNDRV_PCM_FORMAT_S16_LE: 309 word_len = EP93XX_I2S_WRDLEN_16; 310 break; 311 312 case SNDRV_PCM_FORMAT_S24_LE: 313 word_len = EP93XX_I2S_WRDLEN_24; 314 break; 315 316 case SNDRV_PCM_FORMAT_S32_LE: 317 word_len = EP93XX_I2S_WRDLEN_32; 318 break; 319 320 default: 321 return -EINVAL; 322 } 323 324 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 325 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len); 326 else 327 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len); 328 329 /* 330 * EP93xx I2S module can be setup so SCLK / LRCLK value can be 331 * 32, 64, 128. MCLK / SCLK value can be 2 and 4. 332 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK 333 * value is 64, because our sample size is 32 bit * 2 channels. 334 * I2S standard permits us to transmit more bits than 335 * the codec uses. 336 */ 337 div = clk_get_rate(info->mclk) / params_rate(params); 338 sdiv = 4; 339 if (div > (256 + 512) / 2) { 340 lrdiv = 128; 341 } else { 342 lrdiv = 64; 343 if (div < (128 + 256) / 2) 344 sdiv = 2; 345 } 346 347 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); 348 if (err) 349 return err; 350 351 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv); 352 if (err) 353 return err; 354 355 ep93xx_i2s_enable(info, substream->stream); 356 return 0; 357 } 358 359 static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 360 unsigned int freq, int dir) 361 { 362 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai); 363 364 if (dir == SND_SOC_CLOCK_IN || clk_id != 0) 365 return -EINVAL; 366 367 return clk_set_rate(info->mclk, freq); 368 } 369 370 #ifdef CONFIG_PM 371 static int ep93xx_i2s_suspend(struct snd_soc_dai *dai) 372 { 373 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 374 375 if (!dai->active) 376 return 0; 377 378 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK); 379 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE); 380 381 return 0; 382 } 383 384 static int ep93xx_i2s_resume(struct snd_soc_dai *dai) 385 { 386 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 387 388 if (!dai->active) 389 return 0; 390 391 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK); 392 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE); 393 394 return 0; 395 } 396 #else 397 #define ep93xx_i2s_suspend NULL 398 #define ep93xx_i2s_resume NULL 399 #endif 400 401 static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = { 402 .shutdown = ep93xx_i2s_shutdown, 403 .hw_params = ep93xx_i2s_hw_params, 404 .set_sysclk = ep93xx_i2s_set_sysclk, 405 .set_fmt = ep93xx_i2s_set_dai_fmt, 406 }; 407 408 #define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) 409 410 static struct snd_soc_dai_driver ep93xx_i2s_dai = { 411 .symmetric_rates= 1, 412 .probe = ep93xx_i2s_dai_probe, 413 .suspend = ep93xx_i2s_suspend, 414 .resume = ep93xx_i2s_resume, 415 .playback = { 416 .channels_min = 2, 417 .channels_max = 2, 418 .rates = SNDRV_PCM_RATE_8000_192000, 419 .formats = EP93XX_I2S_FORMATS, 420 }, 421 .capture = { 422 .channels_min = 2, 423 .channels_max = 2, 424 .rates = SNDRV_PCM_RATE_8000_192000, 425 .formats = EP93XX_I2S_FORMATS, 426 }, 427 .ops = &ep93xx_i2s_dai_ops, 428 }; 429 430 static const struct snd_soc_component_driver ep93xx_i2s_component = { 431 .name = "ep93xx-i2s", 432 }; 433 434 static int ep93xx_i2s_probe(struct platform_device *pdev) 435 { 436 struct ep93xx_i2s_info *info; 437 struct resource *res; 438 int err; 439 440 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 441 if (!info) 442 return -ENOMEM; 443 444 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 445 info->regs = devm_ioremap_resource(&pdev->dev, res); 446 if (IS_ERR(info->regs)) 447 return PTR_ERR(info->regs); 448 449 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG)) { 450 int irq = platform_get_irq(pdev, 0); 451 if (irq <= 0) 452 return irq < 0 ? irq : -ENODEV; 453 454 err = devm_request_irq(&pdev->dev, irq, ep93xx_i2s_interrupt, 0, 455 pdev->name, info); 456 if (err) 457 return err; 458 } 459 460 info->mclk = clk_get(&pdev->dev, "mclk"); 461 if (IS_ERR(info->mclk)) { 462 err = PTR_ERR(info->mclk); 463 goto fail; 464 } 465 466 info->sclk = clk_get(&pdev->dev, "sclk"); 467 if (IS_ERR(info->sclk)) { 468 err = PTR_ERR(info->sclk); 469 goto fail_put_mclk; 470 } 471 472 info->lrclk = clk_get(&pdev->dev, "lrclk"); 473 if (IS_ERR(info->lrclk)) { 474 err = PTR_ERR(info->lrclk); 475 goto fail_put_sclk; 476 } 477 478 dev_set_drvdata(&pdev->dev, info); 479 480 err = snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component, 481 &ep93xx_i2s_dai, 1); 482 if (err) 483 goto fail_put_lrclk; 484 485 err = devm_ep93xx_pcm_platform_register(&pdev->dev); 486 if (err) 487 goto fail_unregister; 488 489 return 0; 490 491 fail_unregister: 492 snd_soc_unregister_component(&pdev->dev); 493 fail_put_lrclk: 494 clk_put(info->lrclk); 495 fail_put_sclk: 496 clk_put(info->sclk); 497 fail_put_mclk: 498 clk_put(info->mclk); 499 fail: 500 return err; 501 } 502 503 static int ep93xx_i2s_remove(struct platform_device *pdev) 504 { 505 struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev); 506 507 snd_soc_unregister_component(&pdev->dev); 508 clk_put(info->lrclk); 509 clk_put(info->sclk); 510 clk_put(info->mclk); 511 return 0; 512 } 513 514 static struct platform_driver ep93xx_i2s_driver = { 515 .probe = ep93xx_i2s_probe, 516 .remove = ep93xx_i2s_remove, 517 .driver = { 518 .name = "ep93xx-i2s", 519 }, 520 }; 521 522 module_platform_driver(ep93xx_i2s_driver); 523 524 MODULE_ALIAS("platform:ep93xx-i2s"); 525 MODULE_AUTHOR("Ryan Mallon"); 526 MODULE_DESCRIPTION("EP93XX I2S driver"); 527 MODULE_LICENSE("GPL"); 528