1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip S/PDIF TX Controller 4 // 5 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <linux/clk.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/spinlock.h> 13 14 #include <sound/asoundef.h> 15 #include <sound/dmaengine_pcm.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 19 /* 20 * ---- S/PDIF Transmitter Controller Register map ---- 21 */ 22 #define SPDIFTX_CR 0x00 /* Control Register */ 23 #define SPDIFTX_MR 0x04 /* Mode Register */ 24 #define SPDIFTX_CDR 0x0C /* Common Data Register */ 25 26 #define SPDIFTX_IER 0x14 /* Interrupt Enable Register */ 27 #define SPDIFTX_IDR 0x18 /* Interrupt Disable Register */ 28 #define SPDIFTX_IMR 0x1C /* Interrupt Mask Register */ 29 #define SPDIFTX_ISR 0x20 /* Interrupt Status Register */ 30 31 #define SPDIFTX_CH1UD(reg) (0x50 + (reg) * 4) /* User Data 1 Register x */ 32 #define SPDIFTX_CH1S(reg) (0x80 + (reg) * 4) /* Channel Status 1 Register x */ 33 34 #define SPDIFTX_VERSION 0xF0 35 36 /* 37 * ---- Control Register (Write-only) ---- 38 */ 39 #define SPDIFTX_CR_SWRST BIT(0) /* Software Reset */ 40 #define SPDIFTX_CR_FCLR BIT(1) /* FIFO clear */ 41 42 /* 43 * ---- Mode Register (Read/Write) ---- 44 */ 45 /* Transmit Enable */ 46 #define SPDIFTX_MR_TXEN_MASK GENMASK(0, 0) 47 #define SPDIFTX_MR_TXEN_DISABLE (0 << 0) 48 #define SPDIFTX_MR_TXEN_ENABLE (1 << 0) 49 50 /* Multichannel Transfer */ 51 #define SPDIFTX_MR_MULTICH_MASK GENAMSK(1, 1) 52 #define SPDIFTX_MR_MULTICH_MONO (0 << 1) 53 #define SPDIFTX_MR_MULTICH_DUAL (1 << 1) 54 55 /* Data Word Endian Mode */ 56 #define SPDIFTX_MR_ENDIAN_MASK GENMASK(2, 2) 57 #define SPDIFTX_MR_ENDIAN_LITTLE (0 << 2) 58 #define SPDIFTX_MR_ENDIAN_BIG (1 << 2) 59 60 /* Data Justification */ 61 #define SPDIFTX_MR_JUSTIFY_MASK GENMASK(3, 3) 62 #define SPDIFTX_MR_JUSTIFY_LSB (0 << 3) 63 #define SPDIFTX_MR_JUSTIFY_MSB (1 << 3) 64 65 /* Common Audio Register Transfer Mode */ 66 #define SPDIFTX_MR_CMODE_MASK GENMASK(5, 4) 67 #define SPDIFTX_MR_CMODE_INDEX_ACCESS (0 << 4) 68 #define SPDIFTX_MR_CMODE_TOGGLE_ACCESS (1 << 4) 69 #define SPDIFTX_MR_CMODE_INTERLVD_ACCESS (2 << 4) 70 71 /* Valid Bits per Sample */ 72 #define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8) 73 #define SPDIFTX_MR_VBPS(bps) (((bps) << 8) & SPDIFTX_MR_VBPS_MASK) 74 75 /* Chunk Size */ 76 #define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16) 77 #define SPDIFTX_MR_CHUNK(size) (((size) << 16) & SPDIFTX_MR_CHUNK_MASK) 78 79 /* Validity Bits for Channels 1 and 2 */ 80 #define SPDIFTX_MR_VALID1 BIT(24) 81 #define SPDIFTX_MR_VALID2 BIT(25) 82 83 /* Disable Null Frame on underrun */ 84 #define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27) 85 #define SPDIFTX_MR_DNFR_INVALID (0 << 27) 86 #define SPDIFTX_MR_DNFR_VALID (1 << 27) 87 88 /* Bytes per Sample */ 89 #define SPDIFTX_MR_BPS_MASK GENMASK(29, 28) 90 #define SPDIFTX_MR_BPS(bytes) \ 91 ((((bytes) - 1) << 28) & SPDIFTX_MR_BPS_MASK) 92 93 /* 94 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ---- 95 */ 96 #define SPDIFTX_IR_TXRDY BIT(0) 97 #define SPDIFTX_IR_TXEMPTY BIT(1) 98 #define SPDIFTX_IR_TXFULL BIT(2) 99 #define SPDIFTX_IR_TXCHUNK BIT(3) 100 #define SPDIFTX_IR_TXUDR BIT(4) 101 #define SPDIFTX_IR_TXOVR BIT(5) 102 #define SPDIFTX_IR_CSRDY BIT(6) 103 #define SPDIFTX_IR_UDRDY BIT(7) 104 #define SPDIFTX_IR_TXRDYCH(ch) BIT((ch) + 8) 105 #define SPDIFTX_IR_SECE BIT(10) 106 #define SPDIFTX_IR_TXUDRCH(ch) BIT((ch) + 11) 107 #define SPDIFTX_IR_BEND BIT(13) 108 109 static bool mchp_spdiftx_readable_reg(struct device *dev, unsigned int reg) 110 { 111 switch (reg) { 112 case SPDIFTX_MR: 113 case SPDIFTX_IMR: 114 case SPDIFTX_ISR: 115 case SPDIFTX_CH1UD(0): 116 case SPDIFTX_CH1UD(1): 117 case SPDIFTX_CH1UD(2): 118 case SPDIFTX_CH1UD(3): 119 case SPDIFTX_CH1UD(4): 120 case SPDIFTX_CH1UD(5): 121 case SPDIFTX_CH1S(0): 122 case SPDIFTX_CH1S(1): 123 case SPDIFTX_CH1S(2): 124 case SPDIFTX_CH1S(3): 125 case SPDIFTX_CH1S(4): 126 case SPDIFTX_CH1S(5): 127 return true; 128 default: 129 return false; 130 } 131 } 132 133 static bool mchp_spdiftx_writeable_reg(struct device *dev, unsigned int reg) 134 { 135 switch (reg) { 136 case SPDIFTX_CR: 137 case SPDIFTX_MR: 138 case SPDIFTX_CDR: 139 case SPDIFTX_IER: 140 case SPDIFTX_IDR: 141 case SPDIFTX_CH1UD(0): 142 case SPDIFTX_CH1UD(1): 143 case SPDIFTX_CH1UD(2): 144 case SPDIFTX_CH1UD(3): 145 case SPDIFTX_CH1UD(4): 146 case SPDIFTX_CH1UD(5): 147 case SPDIFTX_CH1S(0): 148 case SPDIFTX_CH1S(1): 149 case SPDIFTX_CH1S(2): 150 case SPDIFTX_CH1S(3): 151 case SPDIFTX_CH1S(4): 152 case SPDIFTX_CH1S(5): 153 return true; 154 default: 155 return false; 156 } 157 } 158 159 static bool mchp_spdiftx_precious_reg(struct device *dev, unsigned int reg) 160 { 161 switch (reg) { 162 case SPDIFTX_CDR: 163 case SPDIFTX_ISR: 164 return true; 165 default: 166 return false; 167 } 168 } 169 170 static const struct regmap_config mchp_spdiftx_regmap_config = { 171 .reg_bits = 32, 172 .reg_stride = 4, 173 .val_bits = 32, 174 .max_register = SPDIFTX_VERSION, 175 .readable_reg = mchp_spdiftx_readable_reg, 176 .writeable_reg = mchp_spdiftx_writeable_reg, 177 .precious_reg = mchp_spdiftx_precious_reg, 178 }; 179 180 #define SPDIFTX_GCLK_RATIO 128 181 182 #define SPDIFTX_CS_BITS 192 183 #define SPDIFTX_UD_BITS 192 184 185 struct mchp_spdiftx_mixer_control { 186 unsigned char ch_stat[SPDIFTX_CS_BITS / 8]; 187 unsigned char user_data[SPDIFTX_UD_BITS / 8]; 188 spinlock_t lock; /* exclusive access to control data */ 189 }; 190 191 struct mchp_spdiftx_dev { 192 struct mchp_spdiftx_mixer_control control; 193 struct snd_dmaengine_dai_dma_data playback; 194 struct device *dev; 195 struct regmap *regmap; 196 struct clk *pclk; 197 struct clk *gclk; 198 unsigned int fmt; 199 const struct mchp_i2s_caps *caps; 200 int gclk_enabled:1; 201 }; 202 203 static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev) 204 { 205 u32 mr; 206 207 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 208 return !!(mr & SPDIFTX_MR_TXEN_ENABLE); 209 } 210 211 static void mchp_spdiftx_channel_status_write(struct mchp_spdiftx_dev *dev) 212 { 213 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 214 u32 val; 215 int i; 216 217 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat) / 4; i++) { 218 val = (ctrl->ch_stat[(i * 4) + 0] << 0) | 219 (ctrl->ch_stat[(i * 4) + 1] << 8) | 220 (ctrl->ch_stat[(i * 4) + 2] << 16) | 221 (ctrl->ch_stat[(i * 4) + 3] << 24); 222 223 regmap_write(dev->regmap, SPDIFTX_CH1S(i), val); 224 } 225 } 226 227 static void mchp_spdiftx_user_data_write(struct mchp_spdiftx_dev *dev) 228 { 229 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 230 u32 val; 231 int i; 232 233 for (i = 0; i < ARRAY_SIZE(ctrl->user_data) / 4; i++) { 234 val = (ctrl->user_data[(i * 4) + 0] << 0) | 235 (ctrl->user_data[(i * 4) + 1] << 8) | 236 (ctrl->user_data[(i * 4) + 2] << 16) | 237 (ctrl->user_data[(i * 4) + 3] << 24); 238 239 regmap_write(dev->regmap, SPDIFTX_CH1UD(i), val); 240 } 241 } 242 243 static irqreturn_t mchp_spdiftx_interrupt(int irq, void *dev_id) 244 { 245 struct mchp_spdiftx_dev *dev = dev_id; 246 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 247 u32 sr, imr, pending, idr = 0; 248 249 regmap_read(dev->regmap, SPDIFTX_ISR, &sr); 250 regmap_read(dev->regmap, SPDIFTX_IMR, &imr); 251 pending = sr & imr; 252 253 if (!pending) 254 return IRQ_NONE; 255 256 if (pending & SPDIFTX_IR_TXUDR) { 257 dev_warn(dev->dev, "underflow detected\n"); 258 idr |= SPDIFTX_IR_TXUDR; 259 } 260 261 if (pending & SPDIFTX_IR_TXOVR) { 262 dev_warn(dev->dev, "overflow detected\n"); 263 idr |= SPDIFTX_IR_TXOVR; 264 } 265 266 if (pending & SPDIFTX_IR_UDRDY) { 267 spin_lock(&ctrl->lock); 268 mchp_spdiftx_user_data_write(dev); 269 spin_unlock(&ctrl->lock); 270 idr |= SPDIFTX_IR_UDRDY; 271 } 272 273 if (pending & SPDIFTX_IR_CSRDY) { 274 spin_lock(&ctrl->lock); 275 mchp_spdiftx_channel_status_write(dev); 276 spin_unlock(&ctrl->lock); 277 idr |= SPDIFTX_IR_CSRDY; 278 } 279 280 regmap_write(dev->regmap, SPDIFTX_IDR, idr); 281 282 return IRQ_HANDLED; 283 } 284 285 static int mchp_spdiftx_dai_startup(struct snd_pcm_substream *substream, 286 struct snd_soc_dai *dai) 287 { 288 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 289 290 /* Software reset the IP */ 291 regmap_write(dev->regmap, SPDIFTX_CR, 292 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); 293 294 return 0; 295 } 296 297 static void mchp_spdiftx_dai_shutdown(struct snd_pcm_substream *substream, 298 struct snd_soc_dai *dai) 299 { 300 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 301 302 /* Disable interrupts */ 303 regmap_write(dev->regmap, SPDIFTX_IDR, 0xffffffff); 304 } 305 306 static int mchp_spdiftx_trigger(struct snd_pcm_substream *substream, int cmd, 307 struct snd_soc_dai *dai) 308 { 309 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 310 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 311 u32 mr; 312 int running; 313 int ret; 314 315 /* do not start/stop while channel status or user data is updated */ 316 spin_lock(&ctrl->lock); 317 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 318 running = !!(mr & SPDIFTX_MR_TXEN_ENABLE); 319 320 switch (cmd) { 321 case SNDRV_PCM_TRIGGER_START: 322 case SNDRV_PCM_TRIGGER_RESUME: 323 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 324 if (!running) { 325 mr &= ~SPDIFTX_MR_TXEN_MASK; 326 mr |= SPDIFTX_MR_TXEN_ENABLE; 327 } 328 break; 329 case SNDRV_PCM_TRIGGER_STOP: 330 case SNDRV_PCM_TRIGGER_SUSPEND: 331 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 332 if (running) { 333 mr &= ~SPDIFTX_MR_TXEN_MASK; 334 mr |= SPDIFTX_MR_TXEN_DISABLE; 335 } 336 break; 337 default: 338 spin_unlock(&ctrl->lock); 339 return -EINVAL; 340 } 341 342 ret = regmap_write(dev->regmap, SPDIFTX_MR, mr); 343 spin_unlock(&ctrl->lock); 344 if (ret) 345 dev_err(dev->dev, "unable to disable TX: %d\n", ret); 346 347 return ret; 348 } 349 350 static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream, 351 struct snd_pcm_hw_params *params, 352 struct snd_soc_dai *dai) 353 { 354 unsigned long flags; 355 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 356 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 357 u32 mr; 358 unsigned int bps = params_physical_width(params) / 8; 359 int ret; 360 361 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 362 __func__, params_rate(params), params_format(params), 363 params_width(params), params_channels(params)); 364 365 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 366 dev_err(dev->dev, "Capture is not supported\n"); 367 return -EINVAL; 368 } 369 370 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 371 372 if (mr & SPDIFTX_MR_TXEN_ENABLE) { 373 dev_err(dev->dev, "PCM already running\n"); 374 return -EBUSY; 375 } 376 377 /* Defaults: Toggle mode, justify to LSB, chunksize 1 */ 378 mr = SPDIFTX_MR_CMODE_TOGGLE_ACCESS | SPDIFTX_MR_JUSTIFY_LSB; 379 dev->playback.maxburst = 1; 380 switch (params_channels(params)) { 381 case 1: 382 mr |= SPDIFTX_MR_MULTICH_MONO; 383 break; 384 case 2: 385 mr |= SPDIFTX_MR_MULTICH_DUAL; 386 if (bps > 2) 387 dev->playback.maxburst = 2; 388 break; 389 default: 390 dev_err(dev->dev, "unsupported number of channels: %d\n", 391 params_channels(params)); 392 return -EINVAL; 393 } 394 mr |= SPDIFTX_MR_CHUNK(dev->playback.maxburst); 395 396 switch (params_format(params)) { 397 case SNDRV_PCM_FORMAT_S8: 398 mr |= SPDIFTX_MR_VBPS(8); 399 break; 400 case SNDRV_PCM_FORMAT_S16_BE: 401 mr |= SPDIFTX_MR_ENDIAN_BIG; 402 fallthrough; 403 case SNDRV_PCM_FORMAT_S16_LE: 404 mr |= SPDIFTX_MR_VBPS(16); 405 break; 406 case SNDRV_PCM_FORMAT_S18_3BE: 407 mr |= SPDIFTX_MR_ENDIAN_BIG; 408 fallthrough; 409 case SNDRV_PCM_FORMAT_S18_3LE: 410 mr |= SPDIFTX_MR_VBPS(18); 411 break; 412 case SNDRV_PCM_FORMAT_S20_3BE: 413 mr |= SPDIFTX_MR_ENDIAN_BIG; 414 fallthrough; 415 case SNDRV_PCM_FORMAT_S20_3LE: 416 mr |= SPDIFTX_MR_VBPS(20); 417 break; 418 case SNDRV_PCM_FORMAT_S24_3BE: 419 mr |= SPDIFTX_MR_ENDIAN_BIG; 420 fallthrough; 421 case SNDRV_PCM_FORMAT_S24_3LE: 422 mr |= SPDIFTX_MR_VBPS(24); 423 break; 424 case SNDRV_PCM_FORMAT_S24_BE: 425 mr |= SPDIFTX_MR_ENDIAN_BIG; 426 fallthrough; 427 case SNDRV_PCM_FORMAT_S24_LE: 428 mr |= SPDIFTX_MR_VBPS(24); 429 break; 430 case SNDRV_PCM_FORMAT_S32_BE: 431 mr |= SPDIFTX_MR_ENDIAN_BIG; 432 fallthrough; 433 case SNDRV_PCM_FORMAT_S32_LE: 434 mr |= SPDIFTX_MR_VBPS(32); 435 break; 436 default: 437 dev_err(dev->dev, "unsupported PCM format: %d\n", 438 params_format(params)); 439 return -EINVAL; 440 } 441 442 mr |= SPDIFTX_MR_BPS(bps); 443 444 spin_lock_irqsave(&ctrl->lock, flags); 445 ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS; 446 switch (params_rate(params)) { 447 case 22050: 448 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_22050; 449 break; 450 case 24000: 451 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_24000; 452 break; 453 case 32000: 454 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_32000; 455 break; 456 case 44100: 457 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_44100; 458 break; 459 case 48000: 460 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_48000; 461 break; 462 case 88200: 463 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_88200; 464 break; 465 case 96000: 466 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_96000; 467 break; 468 case 176400: 469 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_176400; 470 break; 471 case 192000: 472 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_192000; 473 break; 474 case 8000: 475 case 11025: 476 case 16000: 477 case 64000: 478 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_NOTID; 479 break; 480 default: 481 dev_err(dev->dev, "unsupported sample frequency: %u\n", 482 params_rate(params)); 483 spin_unlock_irqrestore(&ctrl->lock, flags); 484 return -EINVAL; 485 } 486 mchp_spdiftx_channel_status_write(dev); 487 spin_unlock_irqrestore(&ctrl->lock, flags); 488 489 if (dev->gclk_enabled) { 490 clk_disable_unprepare(dev->gclk); 491 dev->gclk_enabled = 0; 492 } 493 ret = clk_set_rate(dev->gclk, params_rate(params) * 494 SPDIFTX_GCLK_RATIO); 495 if (ret) { 496 dev_err(dev->dev, 497 "unable to change gclk rate to: rate %u * ratio %u\n", 498 params_rate(params), SPDIFTX_GCLK_RATIO); 499 return ret; 500 } 501 ret = clk_prepare_enable(dev->gclk); 502 if (ret) { 503 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); 504 return ret; 505 } 506 dev->gclk_enabled = 1; 507 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, 508 params_rate(params) * SPDIFTX_GCLK_RATIO); 509 510 /* Enable interrupts */ 511 regmap_write(dev->regmap, SPDIFTX_IER, 512 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); 513 514 regmap_write(dev->regmap, SPDIFTX_MR, mr); 515 516 return 0; 517 } 518 519 static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream, 520 struct snd_soc_dai *dai) 521 { 522 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 523 524 regmap_write(dev->regmap, SPDIFTX_IDR, 525 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); 526 if (dev->gclk_enabled) { 527 clk_disable_unprepare(dev->gclk); 528 dev->gclk_enabled = 0; 529 } 530 531 return regmap_write(dev->regmap, SPDIFTX_CR, 532 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); 533 } 534 535 static const struct snd_soc_dai_ops mchp_spdiftx_dai_ops = { 536 .startup = mchp_spdiftx_dai_startup, 537 .shutdown = mchp_spdiftx_dai_shutdown, 538 .trigger = mchp_spdiftx_trigger, 539 .hw_params = mchp_spdiftx_hw_params, 540 .hw_free = mchp_spdiftx_hw_free, 541 }; 542 543 #define MCHP_SPDIFTX_RATES SNDRV_PCM_RATE_8000_192000 544 545 #define MCHP_SPDIFTX_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 546 SNDRV_PCM_FMTBIT_S16_LE | \ 547 SNDRV_PCM_FMTBIT_U16_BE | \ 548 SNDRV_PCM_FMTBIT_S18_3LE | \ 549 SNDRV_PCM_FMTBIT_S18_3BE | \ 550 SNDRV_PCM_FMTBIT_S20_3LE | \ 551 SNDRV_PCM_FMTBIT_S20_3BE | \ 552 SNDRV_PCM_FMTBIT_S24_3LE | \ 553 SNDRV_PCM_FMTBIT_S24_3BE | \ 554 SNDRV_PCM_FMTBIT_S24_LE | \ 555 SNDRV_PCM_FMTBIT_S24_BE | \ 556 SNDRV_PCM_FMTBIT_S32_LE | \ 557 SNDRV_PCM_FMTBIT_S32_BE \ 558 ) 559 560 static int mchp_spdiftx_info(struct snd_kcontrol *kcontrol, 561 struct snd_ctl_elem_info *uinfo) 562 { 563 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 564 uinfo->count = 1; 565 566 return 0; 567 } 568 569 static int mchp_spdiftx_cs_get(struct snd_kcontrol *kcontrol, 570 struct snd_ctl_elem_value *uvalue) 571 { 572 unsigned long flags; 573 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 574 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 575 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 576 577 spin_lock_irqsave(&ctrl->lock, flags); 578 memcpy(uvalue->value.iec958.status, ctrl->ch_stat, 579 sizeof(ctrl->ch_stat)); 580 spin_unlock_irqrestore(&ctrl->lock, flags); 581 582 return 0; 583 } 584 585 static int mchp_spdiftx_cs_put(struct snd_kcontrol *kcontrol, 586 struct snd_ctl_elem_value *uvalue) 587 { 588 unsigned long flags; 589 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 590 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 591 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 592 int changed = 0; 593 int i; 594 595 spin_lock_irqsave(&ctrl->lock, flags); 596 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat); i++) { 597 if (ctrl->ch_stat[i] != uvalue->value.iec958.status[i]) 598 changed = 1; 599 ctrl->ch_stat[i] = uvalue->value.iec958.status[i]; 600 } 601 602 if (changed) { 603 /* don't enable IP while we copy the channel status */ 604 if (mchp_spdiftx_is_running(dev)) { 605 /* 606 * if SPDIF is running, wait for interrupt to write 607 * channel status 608 */ 609 regmap_write(dev->regmap, SPDIFTX_IER, 610 SPDIFTX_IR_CSRDY); 611 } else { 612 mchp_spdiftx_channel_status_write(dev); 613 } 614 } 615 spin_unlock_irqrestore(&ctrl->lock, flags); 616 617 return changed; 618 } 619 620 static int mchp_spdiftx_cs_mask(struct snd_kcontrol *kcontrol, 621 struct snd_ctl_elem_value *uvalue) 622 { 623 memset(uvalue->value.iec958.status, 0xff, 624 sizeof(uvalue->value.iec958.status)); 625 626 return 0; 627 } 628 629 static int mchp_spdiftx_subcode_get(struct snd_kcontrol *kcontrol, 630 struct snd_ctl_elem_value *uvalue) 631 { 632 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 633 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 634 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 635 unsigned long flags; 636 637 spin_lock_irqsave(&ctrl->lock, flags); 638 memcpy(uvalue->value.iec958.subcode, ctrl->user_data, 639 sizeof(ctrl->user_data)); 640 spin_unlock_irqrestore(&ctrl->lock, flags); 641 642 return 0; 643 } 644 645 static int mchp_spdiftx_subcode_put(struct snd_kcontrol *kcontrol, 646 struct snd_ctl_elem_value *uvalue) 647 { 648 unsigned long flags; 649 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 650 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 651 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 652 int changed = 0; 653 int i; 654 655 spin_lock_irqsave(&ctrl->lock, flags); 656 for (i = 0; i < ARRAY_SIZE(ctrl->user_data); i++) { 657 if (ctrl->user_data[i] != uvalue->value.iec958.subcode[i]) 658 changed = 1; 659 660 ctrl->user_data[i] = uvalue->value.iec958.subcode[i]; 661 } 662 if (changed) { 663 if (mchp_spdiftx_is_running(dev)) { 664 /* 665 * if SPDIF is running, wait for interrupt to write 666 * user data 667 */ 668 regmap_write(dev->regmap, SPDIFTX_IER, 669 SPDIFTX_IR_UDRDY); 670 } else { 671 mchp_spdiftx_user_data_write(dev); 672 } 673 } 674 spin_unlock_irqrestore(&ctrl->lock, flags); 675 676 return changed; 677 } 678 679 static struct snd_kcontrol_new mchp_spdiftx_ctrls[] = { 680 /* Channel status controller */ 681 { 682 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 683 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 684 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 685 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 686 .info = mchp_spdiftx_info, 687 .get = mchp_spdiftx_cs_get, 688 .put = mchp_spdiftx_cs_put, 689 }, 690 { 691 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 692 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 693 .access = SNDRV_CTL_ELEM_ACCESS_READ, 694 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 695 .info = mchp_spdiftx_info, 696 .get = mchp_spdiftx_cs_mask, 697 }, 698 /* User bits controller */ 699 { 700 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 701 .name = "IEC958 Subcode Playback Default", 702 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 703 .info = mchp_spdiftx_info, 704 .get = mchp_spdiftx_subcode_get, 705 .put = mchp_spdiftx_subcode_put, 706 }, 707 }; 708 709 static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai) 710 { 711 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 712 int ret; 713 714 snd_soc_dai_init_dma_data(dai, &dev->playback, NULL); 715 716 ret = clk_prepare_enable(dev->pclk); 717 if (ret) { 718 dev_err(dev->dev, 719 "failed to enable the peripheral clock: %d\n", ret); 720 return ret; 721 } 722 723 /* Add controls */ 724 snd_soc_add_dai_controls(dai, mchp_spdiftx_ctrls, 725 ARRAY_SIZE(mchp_spdiftx_ctrls)); 726 727 return 0; 728 } 729 730 static int mchp_spdiftx_dai_remove(struct snd_soc_dai *dai) 731 { 732 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 733 734 clk_disable_unprepare(dev->pclk); 735 736 return 0; 737 } 738 739 static struct snd_soc_dai_driver mchp_spdiftx_dai = { 740 .name = "mchp-spdiftx", 741 .probe = mchp_spdiftx_dai_probe, 742 .remove = mchp_spdiftx_dai_remove, 743 .playback = { 744 .stream_name = "S/PDIF Playback", 745 .channels_min = 1, 746 .channels_max = 2, 747 .rates = MCHP_SPDIFTX_RATES, 748 .formats = MCHP_SPDIFTX_FORMATS, 749 }, 750 .ops = &mchp_spdiftx_dai_ops, 751 }; 752 753 static const struct snd_soc_component_driver mchp_spdiftx_component = { 754 .name = "mchp-spdiftx", 755 }; 756 757 static const struct of_device_id mchp_spdiftx_dt_ids[] = { 758 { 759 .compatible = "microchip,sama7g5-spdiftx", 760 }, 761 { /* sentinel */ } 762 }; 763 MODULE_DEVICE_TABLE(of, mchp_spdiftx_dt_ids); 764 765 static int mchp_spdiftx_probe(struct platform_device *pdev) 766 { 767 struct device_node *np = pdev->dev.of_node; 768 const struct of_device_id *match; 769 struct mchp_spdiftx_dev *dev; 770 struct resource *mem; 771 struct regmap *regmap; 772 void __iomem *base; 773 struct mchp_spdiftx_mixer_control *ctrl; 774 int irq; 775 int err; 776 777 /* Get memory for driver data. */ 778 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 779 if (!dev) 780 return -ENOMEM; 781 782 /* Get hardware capabilities. */ 783 match = of_match_node(mchp_spdiftx_dt_ids, np); 784 if (match) 785 dev->caps = match->data; 786 787 /* Map I/O registers. */ 788 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 789 if (IS_ERR(base)) 790 return PTR_ERR(base); 791 792 regmap = devm_regmap_init_mmio(&pdev->dev, base, 793 &mchp_spdiftx_regmap_config); 794 if (IS_ERR(regmap)) 795 return PTR_ERR(regmap); 796 797 /* Request IRQ */ 798 irq = platform_get_irq(pdev, 0); 799 if (irq < 0) 800 return irq; 801 802 err = devm_request_irq(&pdev->dev, irq, mchp_spdiftx_interrupt, 0, 803 dev_name(&pdev->dev), dev); 804 if (err) 805 return err; 806 807 /* Get the peripheral clock */ 808 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 809 if (IS_ERR(dev->pclk)) { 810 err = PTR_ERR(dev->pclk); 811 dev_err(&pdev->dev, 812 "failed to get the peripheral clock: %d\n", err); 813 return err; 814 } 815 816 /* Get the generic clock */ 817 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 818 if (IS_ERR(dev->gclk)) { 819 err = PTR_ERR(dev->gclk); 820 dev_err(&pdev->dev, 821 "failed to get the PMC generic clock: %d\n", err); 822 return err; 823 } 824 825 ctrl = &dev->control; 826 spin_lock_init(&ctrl->lock); 827 828 /* Init channel status */ 829 ctrl->ch_stat[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 830 IEC958_AES0_CON_EMPHASIS_NONE; 831 832 dev->dev = &pdev->dev; 833 dev->regmap = regmap; 834 platform_set_drvdata(pdev, dev); 835 836 dev->playback.addr = (dma_addr_t)mem->start + SPDIFTX_CDR; 837 dev->playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 838 839 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 840 if (err) { 841 dev_err(&pdev->dev, "failed to register PMC: %d\n", err); 842 return err; 843 } 844 845 err = devm_snd_soc_register_component(&pdev->dev, 846 &mchp_spdiftx_component, 847 &mchp_spdiftx_dai, 1); 848 if (err) 849 dev_err(&pdev->dev, "failed to register component: %d\n", err); 850 851 return err; 852 } 853 854 static struct platform_driver mchp_spdiftx_driver = { 855 .probe = mchp_spdiftx_probe, 856 .driver = { 857 .name = "mchp_spdiftx", 858 .of_match_table = of_match_ptr(mchp_spdiftx_dt_ids), 859 }, 860 }; 861 862 module_platform_driver(mchp_spdiftx_driver); 863 864 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 865 MODULE_DESCRIPTION("Microchip S/PDIF TX Controller Driver"); 866 MODULE_LICENSE("GPL v2"); 867