1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip S/PDIF TX Controller 4 // 5 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <linux/clk.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/spinlock.h> 13 14 #include <sound/asoundef.h> 15 #include <sound/dmaengine_pcm.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 19 /* 20 * ---- S/PDIF Transmitter Controller Register map ---- 21 */ 22 #define SPDIFTX_CR 0x00 /* Control Register */ 23 #define SPDIFTX_MR 0x04 /* Mode Register */ 24 #define SPDIFTX_CDR 0x0C /* Common Data Register */ 25 26 #define SPDIFTX_IER 0x14 /* Interrupt Enable Register */ 27 #define SPDIFTX_IDR 0x18 /* Interrupt Disable Register */ 28 #define SPDIFTX_IMR 0x1C /* Interrupt Mask Register */ 29 #define SPDIFTX_ISR 0x20 /* Interrupt Status Register */ 30 31 #define SPDIFTX_CH1UD(reg) (0x50 + (reg) * 4) /* User Data 1 Register x */ 32 #define SPDIFTX_CH1S(reg) (0x80 + (reg) * 4) /* Channel Status 1 Register x */ 33 34 #define SPDIFTX_VERSION 0xF0 35 36 /* 37 * ---- Control Register (Write-only) ---- 38 */ 39 #define SPDIFTX_CR_SWRST BIT(0) /* Software Reset */ 40 #define SPDIFTX_CR_FCLR BIT(1) /* FIFO clear */ 41 42 /* 43 * ---- Mode Register (Read/Write) ---- 44 */ 45 /* Transmit Enable */ 46 #define SPDIFTX_MR_TXEN_MASK GENMASK(0, 0) 47 #define SPDIFTX_MR_TXEN_DISABLE (0 << 0) 48 #define SPDIFTX_MR_TXEN_ENABLE (1 << 0) 49 50 /* Multichannel Transfer */ 51 #define SPDIFTX_MR_MULTICH_MASK GENAMSK(1, 1) 52 #define SPDIFTX_MR_MULTICH_MONO (0 << 1) 53 #define SPDIFTX_MR_MULTICH_DUAL (1 << 1) 54 55 /* Data Word Endian Mode */ 56 #define SPDIFTX_MR_ENDIAN_MASK GENMASK(2, 2) 57 #define SPDIFTX_MR_ENDIAN_LITTLE (0 << 2) 58 #define SPDIFTX_MR_ENDIAN_BIG (1 << 2) 59 60 /* Data Justification */ 61 #define SPDIFTX_MR_JUSTIFY_MASK GENMASK(3, 3) 62 #define SPDIFTX_MR_JUSTIFY_LSB (0 << 3) 63 #define SPDIFTX_MR_JUSTIFY_MSB (1 << 3) 64 65 /* Common Audio Register Transfer Mode */ 66 #define SPDIFTX_MR_CMODE_MASK GENMASK(5, 4) 67 #define SPDIFTX_MR_CMODE_INDEX_ACCESS (0 << 4) 68 #define SPDIFTX_MR_CMODE_TOGGLE_ACCESS (1 << 4) 69 #define SPDIFTX_MR_CMODE_INTERLVD_ACCESS (2 << 4) 70 71 /* Valid Bits per Sample */ 72 #define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8) 73 #define SPDIFTX_MR_VBPS(bps) (((bps) << 8) & SPDIFTX_MR_VBPS_MASK) 74 75 /* Chunk Size */ 76 #define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16) 77 #define SPDIFTX_MR_CHUNK(size) (((size) << 16) & SPDIFTX_MR_CHUNK_MASK) 78 79 /* Validity Bits for Channels 1 and 2 */ 80 #define SPDIFTX_MR_VALID1 BIT(24) 81 #define SPDIFTX_MR_VALID2 BIT(25) 82 83 /* Disable Null Frame on underrun */ 84 #define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27) 85 #define SPDIFTX_MR_DNFR_INVALID (0 << 27) 86 #define SPDIFTX_MR_DNFR_VALID (1 << 27) 87 88 /* Bytes per Sample */ 89 #define SPDIFTX_MR_BPS_MASK GENMASK(29, 28) 90 #define SPDIFTX_MR_BPS(bytes) \ 91 ((((bytes) - 1) << 28) & SPDIFTX_MR_BPS_MASK) 92 93 /* 94 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ---- 95 */ 96 #define SPDIFTX_IR_TXRDY BIT(0) 97 #define SPDIFTX_IR_TXEMPTY BIT(1) 98 #define SPDIFTX_IR_TXFULL BIT(2) 99 #define SPDIFTX_IR_TXCHUNK BIT(3) 100 #define SPDIFTX_IR_TXUDR BIT(4) 101 #define SPDIFTX_IR_TXOVR BIT(5) 102 #define SPDIFTX_IR_CSRDY BIT(6) 103 #define SPDIFTX_IR_UDRDY BIT(7) 104 #define SPDIFTX_IR_TXRDYCH(ch) BIT((ch) + 8) 105 #define SPDIFTX_IR_SECE BIT(10) 106 #define SPDIFTX_IR_TXUDRCH(ch) BIT((ch) + 11) 107 #define SPDIFTX_IR_BEND BIT(13) 108 109 static bool mchp_spdiftx_readable_reg(struct device *dev, unsigned int reg) 110 { 111 switch (reg) { 112 case SPDIFTX_MR: 113 case SPDIFTX_IMR: 114 case SPDIFTX_ISR: 115 case SPDIFTX_CH1UD(0): 116 case SPDIFTX_CH1UD(1): 117 case SPDIFTX_CH1UD(2): 118 case SPDIFTX_CH1UD(3): 119 case SPDIFTX_CH1UD(4): 120 case SPDIFTX_CH1UD(5): 121 case SPDIFTX_CH1S(0): 122 case SPDIFTX_CH1S(1): 123 case SPDIFTX_CH1S(2): 124 case SPDIFTX_CH1S(3): 125 case SPDIFTX_CH1S(4): 126 case SPDIFTX_CH1S(5): 127 return true; 128 default: 129 return false; 130 } 131 } 132 133 static bool mchp_spdiftx_writeable_reg(struct device *dev, unsigned int reg) 134 { 135 switch (reg) { 136 case SPDIFTX_CR: 137 case SPDIFTX_MR: 138 case SPDIFTX_CDR: 139 case SPDIFTX_IER: 140 case SPDIFTX_IDR: 141 case SPDIFTX_CH1UD(0): 142 case SPDIFTX_CH1UD(1): 143 case SPDIFTX_CH1UD(2): 144 case SPDIFTX_CH1UD(3): 145 case SPDIFTX_CH1UD(4): 146 case SPDIFTX_CH1UD(5): 147 case SPDIFTX_CH1S(0): 148 case SPDIFTX_CH1S(1): 149 case SPDIFTX_CH1S(2): 150 case SPDIFTX_CH1S(3): 151 case SPDIFTX_CH1S(4): 152 case SPDIFTX_CH1S(5): 153 return true; 154 default: 155 return false; 156 } 157 } 158 159 static bool mchp_spdiftx_precious_reg(struct device *dev, unsigned int reg) 160 { 161 switch (reg) { 162 case SPDIFTX_CDR: 163 case SPDIFTX_ISR: 164 return true; 165 default: 166 return false; 167 } 168 } 169 170 static const struct regmap_config mchp_spdiftx_regmap_config = { 171 .reg_bits = 32, 172 .reg_stride = 4, 173 .val_bits = 32, 174 .max_register = SPDIFTX_VERSION, 175 .readable_reg = mchp_spdiftx_readable_reg, 176 .writeable_reg = mchp_spdiftx_writeable_reg, 177 .precious_reg = mchp_spdiftx_precious_reg, 178 }; 179 180 #define SPDIFTX_GCLK_RATIO 128 181 182 #define SPDIFTX_CS_BITS 192 183 #define SPDIFTX_UD_BITS 192 184 185 struct mchp_spdiftx_mixer_control { 186 unsigned char ch_stat[SPDIFTX_CS_BITS / 8]; 187 unsigned char user_data[SPDIFTX_UD_BITS / 8]; 188 spinlock_t lock; /* exclusive access to control data */ 189 }; 190 191 struct mchp_spdiftx_dev { 192 struct mchp_spdiftx_mixer_control control; 193 struct snd_dmaengine_dai_dma_data playback; 194 struct device *dev; 195 struct regmap *regmap; 196 struct clk *pclk; 197 struct clk *gclk; 198 unsigned int fmt; 199 int gclk_enabled:1; 200 }; 201 202 static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev) 203 { 204 u32 mr; 205 206 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 207 return !!(mr & SPDIFTX_MR_TXEN_ENABLE); 208 } 209 210 static void mchp_spdiftx_channel_status_write(struct mchp_spdiftx_dev *dev) 211 { 212 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 213 u32 val; 214 int i; 215 216 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat) / 4; i++) { 217 val = (ctrl->ch_stat[(i * 4) + 0] << 0) | 218 (ctrl->ch_stat[(i * 4) + 1] << 8) | 219 (ctrl->ch_stat[(i * 4) + 2] << 16) | 220 (ctrl->ch_stat[(i * 4) + 3] << 24); 221 222 regmap_write(dev->regmap, SPDIFTX_CH1S(i), val); 223 } 224 } 225 226 static void mchp_spdiftx_user_data_write(struct mchp_spdiftx_dev *dev) 227 { 228 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 229 u32 val; 230 int i; 231 232 for (i = 0; i < ARRAY_SIZE(ctrl->user_data) / 4; i++) { 233 val = (ctrl->user_data[(i * 4) + 0] << 0) | 234 (ctrl->user_data[(i * 4) + 1] << 8) | 235 (ctrl->user_data[(i * 4) + 2] << 16) | 236 (ctrl->user_data[(i * 4) + 3] << 24); 237 238 regmap_write(dev->regmap, SPDIFTX_CH1UD(i), val); 239 } 240 } 241 242 static irqreturn_t mchp_spdiftx_interrupt(int irq, void *dev_id) 243 { 244 struct mchp_spdiftx_dev *dev = dev_id; 245 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 246 u32 sr, imr, pending, idr = 0; 247 248 regmap_read(dev->regmap, SPDIFTX_ISR, &sr); 249 regmap_read(dev->regmap, SPDIFTX_IMR, &imr); 250 pending = sr & imr; 251 252 if (!pending) 253 return IRQ_NONE; 254 255 if (pending & SPDIFTX_IR_TXUDR) { 256 dev_warn(dev->dev, "underflow detected\n"); 257 idr |= SPDIFTX_IR_TXUDR; 258 } 259 260 if (pending & SPDIFTX_IR_TXOVR) { 261 dev_warn(dev->dev, "overflow detected\n"); 262 idr |= SPDIFTX_IR_TXOVR; 263 } 264 265 if (pending & SPDIFTX_IR_UDRDY) { 266 spin_lock(&ctrl->lock); 267 mchp_spdiftx_user_data_write(dev); 268 spin_unlock(&ctrl->lock); 269 idr |= SPDIFTX_IR_UDRDY; 270 } 271 272 if (pending & SPDIFTX_IR_CSRDY) { 273 spin_lock(&ctrl->lock); 274 mchp_spdiftx_channel_status_write(dev); 275 spin_unlock(&ctrl->lock); 276 idr |= SPDIFTX_IR_CSRDY; 277 } 278 279 regmap_write(dev->regmap, SPDIFTX_IDR, idr); 280 281 return IRQ_HANDLED; 282 } 283 284 static int mchp_spdiftx_dai_startup(struct snd_pcm_substream *substream, 285 struct snd_soc_dai *dai) 286 { 287 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 288 289 /* Software reset the IP */ 290 regmap_write(dev->regmap, SPDIFTX_CR, 291 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); 292 293 return 0; 294 } 295 296 static void mchp_spdiftx_dai_shutdown(struct snd_pcm_substream *substream, 297 struct snd_soc_dai *dai) 298 { 299 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 300 301 /* Disable interrupts */ 302 regmap_write(dev->regmap, SPDIFTX_IDR, 0xffffffff); 303 } 304 305 static int mchp_spdiftx_trigger(struct snd_pcm_substream *substream, int cmd, 306 struct snd_soc_dai *dai) 307 { 308 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 309 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 310 u32 mr; 311 int running; 312 int ret; 313 314 /* do not start/stop while channel status or user data is updated */ 315 spin_lock(&ctrl->lock); 316 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 317 running = !!(mr & SPDIFTX_MR_TXEN_ENABLE); 318 319 switch (cmd) { 320 case SNDRV_PCM_TRIGGER_START: 321 case SNDRV_PCM_TRIGGER_RESUME: 322 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 323 if (!running) { 324 mr &= ~SPDIFTX_MR_TXEN_MASK; 325 mr |= SPDIFTX_MR_TXEN_ENABLE; 326 } 327 break; 328 case SNDRV_PCM_TRIGGER_STOP: 329 case SNDRV_PCM_TRIGGER_SUSPEND: 330 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 331 if (running) { 332 mr &= ~SPDIFTX_MR_TXEN_MASK; 333 mr |= SPDIFTX_MR_TXEN_DISABLE; 334 } 335 break; 336 default: 337 spin_unlock(&ctrl->lock); 338 return -EINVAL; 339 } 340 341 ret = regmap_write(dev->regmap, SPDIFTX_MR, mr); 342 spin_unlock(&ctrl->lock); 343 if (ret) 344 dev_err(dev->dev, "unable to disable TX: %d\n", ret); 345 346 return ret; 347 } 348 349 static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream, 350 struct snd_pcm_hw_params *params, 351 struct snd_soc_dai *dai) 352 { 353 unsigned long flags; 354 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 355 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 356 u32 mr; 357 unsigned int bps = params_physical_width(params) / 8; 358 int ret; 359 360 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 361 __func__, params_rate(params), params_format(params), 362 params_width(params), params_channels(params)); 363 364 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 365 dev_err(dev->dev, "Capture is not supported\n"); 366 return -EINVAL; 367 } 368 369 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 370 371 if (mr & SPDIFTX_MR_TXEN_ENABLE) { 372 dev_err(dev->dev, "PCM already running\n"); 373 return -EBUSY; 374 } 375 376 /* Defaults: Toggle mode, justify to LSB, chunksize 1 */ 377 mr = SPDIFTX_MR_CMODE_TOGGLE_ACCESS | SPDIFTX_MR_JUSTIFY_LSB; 378 dev->playback.maxburst = 1; 379 switch (params_channels(params)) { 380 case 1: 381 mr |= SPDIFTX_MR_MULTICH_MONO; 382 break; 383 case 2: 384 mr |= SPDIFTX_MR_MULTICH_DUAL; 385 if (bps > 2) 386 dev->playback.maxburst = 2; 387 break; 388 default: 389 dev_err(dev->dev, "unsupported number of channels: %d\n", 390 params_channels(params)); 391 return -EINVAL; 392 } 393 mr |= SPDIFTX_MR_CHUNK(dev->playback.maxburst); 394 395 switch (params_format(params)) { 396 case SNDRV_PCM_FORMAT_S8: 397 mr |= SPDIFTX_MR_VBPS(8); 398 break; 399 case SNDRV_PCM_FORMAT_S16_BE: 400 mr |= SPDIFTX_MR_ENDIAN_BIG; 401 fallthrough; 402 case SNDRV_PCM_FORMAT_S16_LE: 403 mr |= SPDIFTX_MR_VBPS(16); 404 break; 405 case SNDRV_PCM_FORMAT_S18_3BE: 406 mr |= SPDIFTX_MR_ENDIAN_BIG; 407 fallthrough; 408 case SNDRV_PCM_FORMAT_S18_3LE: 409 mr |= SPDIFTX_MR_VBPS(18); 410 break; 411 case SNDRV_PCM_FORMAT_S20_3BE: 412 mr |= SPDIFTX_MR_ENDIAN_BIG; 413 fallthrough; 414 case SNDRV_PCM_FORMAT_S20_3LE: 415 mr |= SPDIFTX_MR_VBPS(20); 416 break; 417 case SNDRV_PCM_FORMAT_S24_3BE: 418 mr |= SPDIFTX_MR_ENDIAN_BIG; 419 fallthrough; 420 case SNDRV_PCM_FORMAT_S24_3LE: 421 mr |= SPDIFTX_MR_VBPS(24); 422 break; 423 case SNDRV_PCM_FORMAT_S24_BE: 424 mr |= SPDIFTX_MR_ENDIAN_BIG; 425 fallthrough; 426 case SNDRV_PCM_FORMAT_S24_LE: 427 mr |= SPDIFTX_MR_VBPS(24); 428 break; 429 case SNDRV_PCM_FORMAT_S32_BE: 430 mr |= SPDIFTX_MR_ENDIAN_BIG; 431 fallthrough; 432 case SNDRV_PCM_FORMAT_S32_LE: 433 mr |= SPDIFTX_MR_VBPS(32); 434 break; 435 default: 436 dev_err(dev->dev, "unsupported PCM format: %d\n", 437 params_format(params)); 438 return -EINVAL; 439 } 440 441 mr |= SPDIFTX_MR_BPS(bps); 442 443 spin_lock_irqsave(&ctrl->lock, flags); 444 ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS; 445 switch (params_rate(params)) { 446 case 22050: 447 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_22050; 448 break; 449 case 24000: 450 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_24000; 451 break; 452 case 32000: 453 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_32000; 454 break; 455 case 44100: 456 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_44100; 457 break; 458 case 48000: 459 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_48000; 460 break; 461 case 88200: 462 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_88200; 463 break; 464 case 96000: 465 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_96000; 466 break; 467 case 176400: 468 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_176400; 469 break; 470 case 192000: 471 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_192000; 472 break; 473 case 8000: 474 case 11025: 475 case 16000: 476 case 64000: 477 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_NOTID; 478 break; 479 default: 480 dev_err(dev->dev, "unsupported sample frequency: %u\n", 481 params_rate(params)); 482 spin_unlock_irqrestore(&ctrl->lock, flags); 483 return -EINVAL; 484 } 485 mchp_spdiftx_channel_status_write(dev); 486 spin_unlock_irqrestore(&ctrl->lock, flags); 487 488 if (dev->gclk_enabled) { 489 clk_disable_unprepare(dev->gclk); 490 dev->gclk_enabled = 0; 491 } 492 ret = clk_set_rate(dev->gclk, params_rate(params) * 493 SPDIFTX_GCLK_RATIO); 494 if (ret) { 495 dev_err(dev->dev, 496 "unable to change gclk rate to: rate %u * ratio %u\n", 497 params_rate(params), SPDIFTX_GCLK_RATIO); 498 return ret; 499 } 500 ret = clk_prepare_enable(dev->gclk); 501 if (ret) { 502 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); 503 return ret; 504 } 505 dev->gclk_enabled = 1; 506 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, 507 params_rate(params) * SPDIFTX_GCLK_RATIO); 508 509 /* Enable interrupts */ 510 regmap_write(dev->regmap, SPDIFTX_IER, 511 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); 512 513 regmap_write(dev->regmap, SPDIFTX_MR, mr); 514 515 return 0; 516 } 517 518 static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream, 519 struct snd_soc_dai *dai) 520 { 521 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 522 523 regmap_write(dev->regmap, SPDIFTX_IDR, 524 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); 525 if (dev->gclk_enabled) { 526 clk_disable_unprepare(dev->gclk); 527 dev->gclk_enabled = 0; 528 } 529 530 return regmap_write(dev->regmap, SPDIFTX_CR, 531 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); 532 } 533 534 static const struct snd_soc_dai_ops mchp_spdiftx_dai_ops = { 535 .startup = mchp_spdiftx_dai_startup, 536 .shutdown = mchp_spdiftx_dai_shutdown, 537 .trigger = mchp_spdiftx_trigger, 538 .hw_params = mchp_spdiftx_hw_params, 539 .hw_free = mchp_spdiftx_hw_free, 540 }; 541 542 #define MCHP_SPDIFTX_RATES SNDRV_PCM_RATE_8000_192000 543 544 #define MCHP_SPDIFTX_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 545 SNDRV_PCM_FMTBIT_S16_LE | \ 546 SNDRV_PCM_FMTBIT_U16_BE | \ 547 SNDRV_PCM_FMTBIT_S18_3LE | \ 548 SNDRV_PCM_FMTBIT_S18_3BE | \ 549 SNDRV_PCM_FMTBIT_S20_3LE | \ 550 SNDRV_PCM_FMTBIT_S20_3BE | \ 551 SNDRV_PCM_FMTBIT_S24_3LE | \ 552 SNDRV_PCM_FMTBIT_S24_3BE | \ 553 SNDRV_PCM_FMTBIT_S24_LE | \ 554 SNDRV_PCM_FMTBIT_S24_BE | \ 555 SNDRV_PCM_FMTBIT_S32_LE | \ 556 SNDRV_PCM_FMTBIT_S32_BE \ 557 ) 558 559 static int mchp_spdiftx_info(struct snd_kcontrol *kcontrol, 560 struct snd_ctl_elem_info *uinfo) 561 { 562 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 563 uinfo->count = 1; 564 565 return 0; 566 } 567 568 static int mchp_spdiftx_cs_get(struct snd_kcontrol *kcontrol, 569 struct snd_ctl_elem_value *uvalue) 570 { 571 unsigned long flags; 572 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 573 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 574 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 575 576 spin_lock_irqsave(&ctrl->lock, flags); 577 memcpy(uvalue->value.iec958.status, ctrl->ch_stat, 578 sizeof(ctrl->ch_stat)); 579 spin_unlock_irqrestore(&ctrl->lock, flags); 580 581 return 0; 582 } 583 584 static int mchp_spdiftx_cs_put(struct snd_kcontrol *kcontrol, 585 struct snd_ctl_elem_value *uvalue) 586 { 587 unsigned long flags; 588 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 589 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 590 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 591 int changed = 0; 592 int i; 593 594 spin_lock_irqsave(&ctrl->lock, flags); 595 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat); i++) { 596 if (ctrl->ch_stat[i] != uvalue->value.iec958.status[i]) 597 changed = 1; 598 ctrl->ch_stat[i] = uvalue->value.iec958.status[i]; 599 } 600 601 if (changed) { 602 /* don't enable IP while we copy the channel status */ 603 if (mchp_spdiftx_is_running(dev)) { 604 /* 605 * if SPDIF is running, wait for interrupt to write 606 * channel status 607 */ 608 regmap_write(dev->regmap, SPDIFTX_IER, 609 SPDIFTX_IR_CSRDY); 610 } else { 611 mchp_spdiftx_channel_status_write(dev); 612 } 613 } 614 spin_unlock_irqrestore(&ctrl->lock, flags); 615 616 return changed; 617 } 618 619 static int mchp_spdiftx_cs_mask(struct snd_kcontrol *kcontrol, 620 struct snd_ctl_elem_value *uvalue) 621 { 622 memset(uvalue->value.iec958.status, 0xff, 623 sizeof(uvalue->value.iec958.status)); 624 625 return 0; 626 } 627 628 static int mchp_spdiftx_subcode_get(struct snd_kcontrol *kcontrol, 629 struct snd_ctl_elem_value *uvalue) 630 { 631 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 632 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 633 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 634 unsigned long flags; 635 636 spin_lock_irqsave(&ctrl->lock, flags); 637 memcpy(uvalue->value.iec958.subcode, ctrl->user_data, 638 sizeof(ctrl->user_data)); 639 spin_unlock_irqrestore(&ctrl->lock, flags); 640 641 return 0; 642 } 643 644 static int mchp_spdiftx_subcode_put(struct snd_kcontrol *kcontrol, 645 struct snd_ctl_elem_value *uvalue) 646 { 647 unsigned long flags; 648 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 649 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 650 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 651 int changed = 0; 652 int i; 653 654 spin_lock_irqsave(&ctrl->lock, flags); 655 for (i = 0; i < ARRAY_SIZE(ctrl->user_data); i++) { 656 if (ctrl->user_data[i] != uvalue->value.iec958.subcode[i]) 657 changed = 1; 658 659 ctrl->user_data[i] = uvalue->value.iec958.subcode[i]; 660 } 661 if (changed) { 662 if (mchp_spdiftx_is_running(dev)) { 663 /* 664 * if SPDIF is running, wait for interrupt to write 665 * user data 666 */ 667 regmap_write(dev->regmap, SPDIFTX_IER, 668 SPDIFTX_IR_UDRDY); 669 } else { 670 mchp_spdiftx_user_data_write(dev); 671 } 672 } 673 spin_unlock_irqrestore(&ctrl->lock, flags); 674 675 return changed; 676 } 677 678 static struct snd_kcontrol_new mchp_spdiftx_ctrls[] = { 679 /* Channel status controller */ 680 { 681 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 682 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 683 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 684 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 685 .info = mchp_spdiftx_info, 686 .get = mchp_spdiftx_cs_get, 687 .put = mchp_spdiftx_cs_put, 688 }, 689 { 690 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 691 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 692 .access = SNDRV_CTL_ELEM_ACCESS_READ, 693 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 694 .info = mchp_spdiftx_info, 695 .get = mchp_spdiftx_cs_mask, 696 }, 697 /* User bits controller */ 698 { 699 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 700 .name = "IEC958 Subcode Playback Default", 701 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 702 .info = mchp_spdiftx_info, 703 .get = mchp_spdiftx_subcode_get, 704 .put = mchp_spdiftx_subcode_put, 705 }, 706 }; 707 708 static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai) 709 { 710 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 711 int ret; 712 713 snd_soc_dai_init_dma_data(dai, &dev->playback, NULL); 714 715 ret = clk_prepare_enable(dev->pclk); 716 if (ret) { 717 dev_err(dev->dev, 718 "failed to enable the peripheral clock: %d\n", ret); 719 return ret; 720 } 721 722 /* Add controls */ 723 snd_soc_add_dai_controls(dai, mchp_spdiftx_ctrls, 724 ARRAY_SIZE(mchp_spdiftx_ctrls)); 725 726 return 0; 727 } 728 729 static int mchp_spdiftx_dai_remove(struct snd_soc_dai *dai) 730 { 731 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 732 733 clk_disable_unprepare(dev->pclk); 734 735 return 0; 736 } 737 738 static struct snd_soc_dai_driver mchp_spdiftx_dai = { 739 .name = "mchp-spdiftx", 740 .probe = mchp_spdiftx_dai_probe, 741 .remove = mchp_spdiftx_dai_remove, 742 .playback = { 743 .stream_name = "S/PDIF Playback", 744 .channels_min = 1, 745 .channels_max = 2, 746 .rates = MCHP_SPDIFTX_RATES, 747 .formats = MCHP_SPDIFTX_FORMATS, 748 }, 749 .ops = &mchp_spdiftx_dai_ops, 750 }; 751 752 static const struct snd_soc_component_driver mchp_spdiftx_component = { 753 .name = "mchp-spdiftx", 754 .legacy_dai_naming = 1, 755 }; 756 757 static const struct of_device_id mchp_spdiftx_dt_ids[] = { 758 { 759 .compatible = "microchip,sama7g5-spdiftx", 760 }, 761 { /* sentinel */ } 762 }; 763 MODULE_DEVICE_TABLE(of, mchp_spdiftx_dt_ids); 764 765 static int mchp_spdiftx_probe(struct platform_device *pdev) 766 { 767 struct mchp_spdiftx_dev *dev; 768 struct resource *mem; 769 struct regmap *regmap; 770 void __iomem *base; 771 struct mchp_spdiftx_mixer_control *ctrl; 772 int irq; 773 int err; 774 775 /* Get memory for driver data. */ 776 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 777 if (!dev) 778 return -ENOMEM; 779 780 /* Map I/O registers. */ 781 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 782 if (IS_ERR(base)) 783 return PTR_ERR(base); 784 785 regmap = devm_regmap_init_mmio(&pdev->dev, base, 786 &mchp_spdiftx_regmap_config); 787 if (IS_ERR(regmap)) 788 return PTR_ERR(regmap); 789 790 /* Request IRQ */ 791 irq = platform_get_irq(pdev, 0); 792 if (irq < 0) 793 return irq; 794 795 err = devm_request_irq(&pdev->dev, irq, mchp_spdiftx_interrupt, 0, 796 dev_name(&pdev->dev), dev); 797 if (err) 798 return err; 799 800 /* Get the peripheral clock */ 801 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 802 if (IS_ERR(dev->pclk)) { 803 err = PTR_ERR(dev->pclk); 804 dev_err(&pdev->dev, 805 "failed to get the peripheral clock: %d\n", err); 806 return err; 807 } 808 809 /* Get the generic clock */ 810 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 811 if (IS_ERR(dev->gclk)) { 812 err = PTR_ERR(dev->gclk); 813 dev_err(&pdev->dev, 814 "failed to get the PMC generic clock: %d\n", err); 815 return err; 816 } 817 818 ctrl = &dev->control; 819 spin_lock_init(&ctrl->lock); 820 821 /* Init channel status */ 822 ctrl->ch_stat[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 823 IEC958_AES0_CON_EMPHASIS_NONE; 824 825 dev->dev = &pdev->dev; 826 dev->regmap = regmap; 827 platform_set_drvdata(pdev, dev); 828 829 dev->playback.addr = (dma_addr_t)mem->start + SPDIFTX_CDR; 830 dev->playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 831 832 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 833 if (err) { 834 dev_err(&pdev->dev, "failed to register PMC: %d\n", err); 835 return err; 836 } 837 838 err = devm_snd_soc_register_component(&pdev->dev, 839 &mchp_spdiftx_component, 840 &mchp_spdiftx_dai, 1); 841 if (err) 842 dev_err(&pdev->dev, "failed to register component: %d\n", err); 843 844 return err; 845 } 846 847 static struct platform_driver mchp_spdiftx_driver = { 848 .probe = mchp_spdiftx_probe, 849 .driver = { 850 .name = "mchp_spdiftx", 851 .of_match_table = of_match_ptr(mchp_spdiftx_dt_ids), 852 }, 853 }; 854 855 module_platform_driver(mchp_spdiftx_driver); 856 857 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 858 MODULE_DESCRIPTION("Microchip S/PDIF TX Controller Driver"); 859 MODULE_LICENSE("GPL v2"); 860