1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip S/PDIF TX Controller 4 // 5 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/spinlock.h> 15 16 #include <sound/asoundef.h> 17 #include <sound/dmaengine_pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc.h> 20 21 /* 22 * ---- S/PDIF Transmitter Controller Register map ---- 23 */ 24 #define SPDIFTX_CR 0x00 /* Control Register */ 25 #define SPDIFTX_MR 0x04 /* Mode Register */ 26 #define SPDIFTX_CDR 0x0C /* Common Data Register */ 27 28 #define SPDIFTX_IER 0x14 /* Interrupt Enable Register */ 29 #define SPDIFTX_IDR 0x18 /* Interrupt Disable Register */ 30 #define SPDIFTX_IMR 0x1C /* Interrupt Mask Register */ 31 #define SPDIFTX_ISR 0x20 /* Interrupt Status Register */ 32 33 #define SPDIFTX_CH1UD(reg) (0x50 + (reg) * 4) /* User Data 1 Register x */ 34 #define SPDIFTX_CH1S(reg) (0x80 + (reg) * 4) /* Channel Status 1 Register x */ 35 36 #define SPDIFTX_VERSION 0xF0 37 38 /* 39 * ---- Control Register (Write-only) ---- 40 */ 41 #define SPDIFTX_CR_SWRST BIT(0) /* Software Reset */ 42 #define SPDIFTX_CR_FCLR BIT(1) /* FIFO clear */ 43 44 /* 45 * ---- Mode Register (Read/Write) ---- 46 */ 47 /* Transmit Enable */ 48 #define SPDIFTX_MR_TXEN_MASK GENMASK(0, 0) 49 #define SPDIFTX_MR_TXEN_DISABLE (0 << 0) 50 #define SPDIFTX_MR_TXEN_ENABLE (1 << 0) 51 52 /* Multichannel Transfer */ 53 #define SPDIFTX_MR_MULTICH_MASK GENAMSK(1, 1) 54 #define SPDIFTX_MR_MULTICH_MONO (0 << 1) 55 #define SPDIFTX_MR_MULTICH_DUAL (1 << 1) 56 57 /* Data Word Endian Mode */ 58 #define SPDIFTX_MR_ENDIAN_MASK GENMASK(2, 2) 59 #define SPDIFTX_MR_ENDIAN_LITTLE (0 << 2) 60 #define SPDIFTX_MR_ENDIAN_BIG (1 << 2) 61 62 /* Data Justification */ 63 #define SPDIFTX_MR_JUSTIFY_MASK GENMASK(3, 3) 64 #define SPDIFTX_MR_JUSTIFY_LSB (0 << 3) 65 #define SPDIFTX_MR_JUSTIFY_MSB (1 << 3) 66 67 /* Common Audio Register Transfer Mode */ 68 #define SPDIFTX_MR_CMODE_MASK GENMASK(5, 4) 69 #define SPDIFTX_MR_CMODE_INDEX_ACCESS (0 << 4) 70 #define SPDIFTX_MR_CMODE_TOGGLE_ACCESS (1 << 4) 71 #define SPDIFTX_MR_CMODE_INTERLVD_ACCESS (2 << 4) 72 73 /* Valid Bits per Sample */ 74 #define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8) 75 76 /* Chunk Size */ 77 #define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16) 78 79 /* Validity Bits for Channels 1 and 2 */ 80 #define SPDIFTX_MR_VALID1 BIT(24) 81 #define SPDIFTX_MR_VALID2 BIT(25) 82 83 /* Disable Null Frame on underrun */ 84 #define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27) 85 #define SPDIFTX_MR_DNFR_INVALID (0 << 27) 86 #define SPDIFTX_MR_DNFR_VALID (1 << 27) 87 88 /* Bytes per Sample */ 89 #define SPDIFTX_MR_BPS_MASK GENMASK(29, 28) 90 91 /* 92 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ---- 93 */ 94 #define SPDIFTX_IR_TXRDY BIT(0) 95 #define SPDIFTX_IR_TXEMPTY BIT(1) 96 #define SPDIFTX_IR_TXFULL BIT(2) 97 #define SPDIFTX_IR_TXCHUNK BIT(3) 98 #define SPDIFTX_IR_TXUDR BIT(4) 99 #define SPDIFTX_IR_TXOVR BIT(5) 100 #define SPDIFTX_IR_CSRDY BIT(6) 101 #define SPDIFTX_IR_UDRDY BIT(7) 102 #define SPDIFTX_IR_TXRDYCH(ch) BIT((ch) + 8) 103 #define SPDIFTX_IR_SECE BIT(10) 104 #define SPDIFTX_IR_TXUDRCH(ch) BIT((ch) + 11) 105 #define SPDIFTX_IR_BEND BIT(13) 106 107 static bool mchp_spdiftx_readable_reg(struct device *dev, unsigned int reg) 108 { 109 switch (reg) { 110 case SPDIFTX_MR: 111 case SPDIFTX_IMR: 112 case SPDIFTX_ISR: 113 case SPDIFTX_CH1UD(0): 114 case SPDIFTX_CH1UD(1): 115 case SPDIFTX_CH1UD(2): 116 case SPDIFTX_CH1UD(3): 117 case SPDIFTX_CH1UD(4): 118 case SPDIFTX_CH1UD(5): 119 case SPDIFTX_CH1S(0): 120 case SPDIFTX_CH1S(1): 121 case SPDIFTX_CH1S(2): 122 case SPDIFTX_CH1S(3): 123 case SPDIFTX_CH1S(4): 124 case SPDIFTX_CH1S(5): 125 return true; 126 default: 127 return false; 128 } 129 } 130 131 static bool mchp_spdiftx_writeable_reg(struct device *dev, unsigned int reg) 132 { 133 switch (reg) { 134 case SPDIFTX_CR: 135 case SPDIFTX_MR: 136 case SPDIFTX_CDR: 137 case SPDIFTX_IER: 138 case SPDIFTX_IDR: 139 case SPDIFTX_CH1UD(0): 140 case SPDIFTX_CH1UD(1): 141 case SPDIFTX_CH1UD(2): 142 case SPDIFTX_CH1UD(3): 143 case SPDIFTX_CH1UD(4): 144 case SPDIFTX_CH1UD(5): 145 case SPDIFTX_CH1S(0): 146 case SPDIFTX_CH1S(1): 147 case SPDIFTX_CH1S(2): 148 case SPDIFTX_CH1S(3): 149 case SPDIFTX_CH1S(4): 150 case SPDIFTX_CH1S(5): 151 return true; 152 default: 153 return false; 154 } 155 } 156 157 static bool mchp_spdiftx_precious_reg(struct device *dev, unsigned int reg) 158 { 159 switch (reg) { 160 case SPDIFTX_CDR: 161 case SPDIFTX_ISR: 162 return true; 163 default: 164 return false; 165 } 166 } 167 168 static const struct regmap_config mchp_spdiftx_regmap_config = { 169 .reg_bits = 32, 170 .reg_stride = 4, 171 .val_bits = 32, 172 .max_register = SPDIFTX_VERSION, 173 .readable_reg = mchp_spdiftx_readable_reg, 174 .writeable_reg = mchp_spdiftx_writeable_reg, 175 .precious_reg = mchp_spdiftx_precious_reg, 176 .cache_type = REGCACHE_FLAT, 177 }; 178 179 #define SPDIFTX_GCLK_RATIO 128 180 181 #define SPDIFTX_CS_BITS 192 182 #define SPDIFTX_UD_BITS 192 183 184 struct mchp_spdiftx_mixer_control { 185 unsigned char ch_stat[SPDIFTX_CS_BITS / 8]; 186 unsigned char user_data[SPDIFTX_UD_BITS / 8]; 187 spinlock_t lock; /* exclusive access to control data */ 188 }; 189 190 struct mchp_spdiftx_dev { 191 struct mchp_spdiftx_mixer_control control; 192 struct snd_dmaengine_dai_dma_data playback; 193 struct device *dev; 194 struct regmap *regmap; 195 struct clk *pclk; 196 struct clk *gclk; 197 unsigned int fmt; 198 unsigned int suspend_irq; 199 }; 200 201 static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev) 202 { 203 u32 mr; 204 205 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 206 return !!(mr & SPDIFTX_MR_TXEN_ENABLE); 207 } 208 209 static void mchp_spdiftx_channel_status_write(struct mchp_spdiftx_dev *dev) 210 { 211 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 212 u32 val; 213 int i; 214 215 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat) / 4; i++) { 216 val = (ctrl->ch_stat[(i * 4) + 0] << 0) | 217 (ctrl->ch_stat[(i * 4) + 1] << 8) | 218 (ctrl->ch_stat[(i * 4) + 2] << 16) | 219 (ctrl->ch_stat[(i * 4) + 3] << 24); 220 221 regmap_write(dev->regmap, SPDIFTX_CH1S(i), val); 222 } 223 } 224 225 static void mchp_spdiftx_user_data_write(struct mchp_spdiftx_dev *dev) 226 { 227 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 228 u32 val; 229 int i; 230 231 for (i = 0; i < ARRAY_SIZE(ctrl->user_data) / 4; i++) { 232 val = (ctrl->user_data[(i * 4) + 0] << 0) | 233 (ctrl->user_data[(i * 4) + 1] << 8) | 234 (ctrl->user_data[(i * 4) + 2] << 16) | 235 (ctrl->user_data[(i * 4) + 3] << 24); 236 237 regmap_write(dev->regmap, SPDIFTX_CH1UD(i), val); 238 } 239 } 240 241 static irqreturn_t mchp_spdiftx_interrupt(int irq, void *dev_id) 242 { 243 struct mchp_spdiftx_dev *dev = dev_id; 244 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 245 u32 sr, imr, pending, idr = 0; 246 247 regmap_read(dev->regmap, SPDIFTX_ISR, &sr); 248 regmap_read(dev->regmap, SPDIFTX_IMR, &imr); 249 pending = sr & imr; 250 251 if (!pending) 252 return IRQ_NONE; 253 254 if (pending & SPDIFTX_IR_TXUDR) { 255 dev_warn(dev->dev, "underflow detected\n"); 256 idr |= SPDIFTX_IR_TXUDR; 257 } 258 259 if (pending & SPDIFTX_IR_TXOVR) { 260 dev_warn(dev->dev, "overflow detected\n"); 261 idr |= SPDIFTX_IR_TXOVR; 262 } 263 264 if (pending & SPDIFTX_IR_UDRDY) { 265 spin_lock(&ctrl->lock); 266 mchp_spdiftx_user_data_write(dev); 267 spin_unlock(&ctrl->lock); 268 idr |= SPDIFTX_IR_UDRDY; 269 } 270 271 if (pending & SPDIFTX_IR_CSRDY) { 272 spin_lock(&ctrl->lock); 273 mchp_spdiftx_channel_status_write(dev); 274 spin_unlock(&ctrl->lock); 275 idr |= SPDIFTX_IR_CSRDY; 276 } 277 278 regmap_write(dev->regmap, SPDIFTX_IDR, idr); 279 280 return IRQ_HANDLED; 281 } 282 283 static int mchp_spdiftx_dai_startup(struct snd_pcm_substream *substream, 284 struct snd_soc_dai *dai) 285 { 286 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 287 288 /* Software reset the IP */ 289 regmap_write(dev->regmap, SPDIFTX_CR, 290 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); 291 292 return 0; 293 } 294 295 static void mchp_spdiftx_dai_shutdown(struct snd_pcm_substream *substream, 296 struct snd_soc_dai *dai) 297 { 298 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 299 300 /* Disable interrupts */ 301 regmap_write(dev->regmap, SPDIFTX_IDR, 0xffffffff); 302 } 303 304 static int mchp_spdiftx_trigger(struct snd_pcm_substream *substream, int cmd, 305 struct snd_soc_dai *dai) 306 { 307 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 308 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 309 u32 mr; 310 int running; 311 int ret; 312 313 /* do not start/stop while channel status or user data is updated */ 314 spin_lock(&ctrl->lock); 315 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 316 running = !!(mr & SPDIFTX_MR_TXEN_ENABLE); 317 318 switch (cmd) { 319 case SNDRV_PCM_TRIGGER_RESUME: 320 case SNDRV_PCM_TRIGGER_START: 321 regmap_write(dev->regmap, SPDIFTX_IER, dev->suspend_irq | 322 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); 323 dev->suspend_irq = 0; 324 fallthrough; 325 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 326 if (!running) { 327 mr &= ~SPDIFTX_MR_TXEN_MASK; 328 mr |= SPDIFTX_MR_TXEN_ENABLE; 329 } 330 break; 331 case SNDRV_PCM_TRIGGER_SUSPEND: 332 regmap_read(dev->regmap, SPDIFTX_IMR, &dev->suspend_irq); 333 fallthrough; 334 case SNDRV_PCM_TRIGGER_STOP: 335 regmap_write(dev->regmap, SPDIFTX_IDR, dev->suspend_irq | 336 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); 337 fallthrough; 338 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 339 if (running) { 340 mr &= ~SPDIFTX_MR_TXEN_MASK; 341 mr |= SPDIFTX_MR_TXEN_DISABLE; 342 } 343 break; 344 default: 345 spin_unlock(&ctrl->lock); 346 return -EINVAL; 347 } 348 349 ret = regmap_write(dev->regmap, SPDIFTX_MR, mr); 350 spin_unlock(&ctrl->lock); 351 if (ret) 352 dev_err(dev->dev, "unable to disable TX: %d\n", ret); 353 354 return ret; 355 } 356 357 static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream, 358 struct snd_pcm_hw_params *params, 359 struct snd_soc_dai *dai) 360 { 361 unsigned long flags; 362 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 363 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 364 u32 mr; 365 unsigned int bps = params_physical_width(params) / 8; 366 unsigned char aes3; 367 int ret; 368 369 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 370 __func__, params_rate(params), params_format(params), 371 params_width(params), params_channels(params)); 372 373 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 374 dev_err(dev->dev, "Capture is not supported\n"); 375 return -EINVAL; 376 } 377 378 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 379 380 if (mr & SPDIFTX_MR_TXEN_ENABLE) { 381 dev_err(dev->dev, "PCM already running\n"); 382 return -EBUSY; 383 } 384 385 /* Defaults: Toggle mode, justify to LSB, chunksize 1 */ 386 mr = SPDIFTX_MR_CMODE_TOGGLE_ACCESS | SPDIFTX_MR_JUSTIFY_LSB; 387 dev->playback.maxburst = 1; 388 switch (params_channels(params)) { 389 case 1: 390 mr |= SPDIFTX_MR_MULTICH_MONO; 391 break; 392 case 2: 393 mr |= SPDIFTX_MR_MULTICH_DUAL; 394 if (bps > 2) 395 dev->playback.maxburst = 2; 396 break; 397 default: 398 dev_err(dev->dev, "unsupported number of channels: %d\n", 399 params_channels(params)); 400 return -EINVAL; 401 } 402 mr |= FIELD_PREP(SPDIFTX_MR_CHUNK_MASK, dev->playback.maxburst); 403 404 switch (params_format(params)) { 405 case SNDRV_PCM_FORMAT_S8: 406 mr |= FIELD_PREP(SPDIFTX_MR_VBPS_MASK, 8); 407 break; 408 case SNDRV_PCM_FORMAT_S16_BE: 409 mr |= SPDIFTX_MR_ENDIAN_BIG; 410 fallthrough; 411 case SNDRV_PCM_FORMAT_S16_LE: 412 mr |= FIELD_PREP(SPDIFTX_MR_VBPS_MASK, 16); 413 break; 414 case SNDRV_PCM_FORMAT_S18_3BE: 415 mr |= SPDIFTX_MR_ENDIAN_BIG; 416 fallthrough; 417 case SNDRV_PCM_FORMAT_S18_3LE: 418 mr |= FIELD_PREP(SPDIFTX_MR_VBPS_MASK, 18); 419 break; 420 case SNDRV_PCM_FORMAT_S20_3BE: 421 mr |= SPDIFTX_MR_ENDIAN_BIG; 422 fallthrough; 423 case SNDRV_PCM_FORMAT_S20_3LE: 424 mr |= FIELD_PREP(SPDIFTX_MR_VBPS_MASK, 20); 425 break; 426 case SNDRV_PCM_FORMAT_S24_3BE: 427 mr |= SPDIFTX_MR_ENDIAN_BIG; 428 fallthrough; 429 case SNDRV_PCM_FORMAT_S24_3LE: 430 mr |= FIELD_PREP(SPDIFTX_MR_VBPS_MASK, 24); 431 break; 432 case SNDRV_PCM_FORMAT_S24_BE: 433 mr |= SPDIFTX_MR_ENDIAN_BIG; 434 fallthrough; 435 case SNDRV_PCM_FORMAT_S24_LE: 436 mr |= FIELD_PREP(SPDIFTX_MR_VBPS_MASK, 24); 437 break; 438 case SNDRV_PCM_FORMAT_S32_BE: 439 mr |= SPDIFTX_MR_ENDIAN_BIG; 440 fallthrough; 441 case SNDRV_PCM_FORMAT_S32_LE: 442 mr |= FIELD_PREP(SPDIFTX_MR_VBPS_MASK, 32); 443 break; 444 default: 445 dev_err(dev->dev, "unsupported PCM format: %d\n", 446 params_format(params)); 447 return -EINVAL; 448 } 449 450 mr |= FIELD_PREP(SPDIFTX_MR_BPS_MASK, bps - 1); 451 452 switch (params_rate(params)) { 453 case 22050: 454 aes3 = IEC958_AES3_CON_FS_22050; 455 break; 456 case 24000: 457 aes3 = IEC958_AES3_CON_FS_24000; 458 break; 459 case 32000: 460 aes3 = IEC958_AES3_CON_FS_32000; 461 break; 462 case 44100: 463 aes3 = IEC958_AES3_CON_FS_44100; 464 break; 465 case 48000: 466 aes3 = IEC958_AES3_CON_FS_48000; 467 break; 468 case 88200: 469 aes3 = IEC958_AES3_CON_FS_88200; 470 break; 471 case 96000: 472 aes3 = IEC958_AES3_CON_FS_96000; 473 break; 474 case 176400: 475 aes3 = IEC958_AES3_CON_FS_176400; 476 break; 477 case 192000: 478 aes3 = IEC958_AES3_CON_FS_192000; 479 break; 480 case 8000: 481 case 11025: 482 case 16000: 483 case 64000: 484 aes3 = IEC958_AES3_CON_FS_NOTID; 485 break; 486 default: 487 dev_err(dev->dev, "unsupported sample frequency: %u\n", 488 params_rate(params)); 489 return -EINVAL; 490 } 491 spin_lock_irqsave(&ctrl->lock, flags); 492 ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS; 493 ctrl->ch_stat[3] |= aes3; 494 mchp_spdiftx_channel_status_write(dev); 495 spin_unlock_irqrestore(&ctrl->lock, flags); 496 497 /* GCLK is enabled by runtime PM. */ 498 clk_disable_unprepare(dev->gclk); 499 500 ret = clk_set_rate(dev->gclk, params_rate(params) * 501 SPDIFTX_GCLK_RATIO); 502 if (ret) { 503 dev_err(dev->dev, 504 "unable to change gclk rate to: rate %u * ratio %u\n", 505 params_rate(params), SPDIFTX_GCLK_RATIO); 506 return ret; 507 } 508 ret = clk_prepare_enable(dev->gclk); 509 if (ret) { 510 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); 511 return ret; 512 } 513 514 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, 515 params_rate(params) * SPDIFTX_GCLK_RATIO); 516 517 regmap_write(dev->regmap, SPDIFTX_MR, mr); 518 519 return 0; 520 } 521 522 static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream, 523 struct snd_soc_dai *dai) 524 { 525 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 526 527 return regmap_write(dev->regmap, SPDIFTX_CR, 528 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); 529 } 530 531 static const struct snd_soc_dai_ops mchp_spdiftx_dai_ops = { 532 .startup = mchp_spdiftx_dai_startup, 533 .shutdown = mchp_spdiftx_dai_shutdown, 534 .trigger = mchp_spdiftx_trigger, 535 .hw_params = mchp_spdiftx_hw_params, 536 .hw_free = mchp_spdiftx_hw_free, 537 }; 538 539 #define MCHP_SPDIFTX_RATES SNDRV_PCM_RATE_8000_192000 540 541 #define MCHP_SPDIFTX_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 542 SNDRV_PCM_FMTBIT_S16_LE | \ 543 SNDRV_PCM_FMTBIT_U16_BE | \ 544 SNDRV_PCM_FMTBIT_S18_3LE | \ 545 SNDRV_PCM_FMTBIT_S18_3BE | \ 546 SNDRV_PCM_FMTBIT_S20_3LE | \ 547 SNDRV_PCM_FMTBIT_S20_3BE | \ 548 SNDRV_PCM_FMTBIT_S24_3LE | \ 549 SNDRV_PCM_FMTBIT_S24_3BE | \ 550 SNDRV_PCM_FMTBIT_S24_LE | \ 551 SNDRV_PCM_FMTBIT_S24_BE | \ 552 SNDRV_PCM_FMTBIT_S32_LE | \ 553 SNDRV_PCM_FMTBIT_S32_BE \ 554 ) 555 556 static int mchp_spdiftx_info(struct snd_kcontrol *kcontrol, 557 struct snd_ctl_elem_info *uinfo) 558 { 559 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 560 uinfo->count = 1; 561 562 return 0; 563 } 564 565 static int mchp_spdiftx_cs_get(struct snd_kcontrol *kcontrol, 566 struct snd_ctl_elem_value *uvalue) 567 { 568 unsigned long flags; 569 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 570 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 571 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 572 573 spin_lock_irqsave(&ctrl->lock, flags); 574 memcpy(uvalue->value.iec958.status, ctrl->ch_stat, 575 sizeof(ctrl->ch_stat)); 576 spin_unlock_irqrestore(&ctrl->lock, flags); 577 578 return 0; 579 } 580 581 static int mchp_spdiftx_cs_put(struct snd_kcontrol *kcontrol, 582 struct snd_ctl_elem_value *uvalue) 583 { 584 unsigned long flags; 585 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 586 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 587 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 588 int changed = 0; 589 int i; 590 591 spin_lock_irqsave(&ctrl->lock, flags); 592 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat); i++) { 593 if (ctrl->ch_stat[i] != uvalue->value.iec958.status[i]) 594 changed = 1; 595 ctrl->ch_stat[i] = uvalue->value.iec958.status[i]; 596 } 597 598 if (changed) { 599 /* don't enable IP while we copy the channel status */ 600 if (mchp_spdiftx_is_running(dev)) { 601 /* 602 * if SPDIF is running, wait for interrupt to write 603 * channel status 604 */ 605 regmap_write(dev->regmap, SPDIFTX_IER, 606 SPDIFTX_IR_CSRDY); 607 } else { 608 mchp_spdiftx_channel_status_write(dev); 609 } 610 } 611 spin_unlock_irqrestore(&ctrl->lock, flags); 612 613 return changed; 614 } 615 616 static int mchp_spdiftx_cs_mask(struct snd_kcontrol *kcontrol, 617 struct snd_ctl_elem_value *uvalue) 618 { 619 memset(uvalue->value.iec958.status, 0xff, 620 sizeof(uvalue->value.iec958.status)); 621 622 return 0; 623 } 624 625 static int mchp_spdiftx_subcode_get(struct snd_kcontrol *kcontrol, 626 struct snd_ctl_elem_value *uvalue) 627 { 628 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 629 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 630 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 631 unsigned long flags; 632 633 spin_lock_irqsave(&ctrl->lock, flags); 634 memcpy(uvalue->value.iec958.subcode, ctrl->user_data, 635 sizeof(ctrl->user_data)); 636 spin_unlock_irqrestore(&ctrl->lock, flags); 637 638 return 0; 639 } 640 641 static int mchp_spdiftx_subcode_put(struct snd_kcontrol *kcontrol, 642 struct snd_ctl_elem_value *uvalue) 643 { 644 unsigned long flags; 645 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 646 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 647 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 648 int changed = 0; 649 int i; 650 651 spin_lock_irqsave(&ctrl->lock, flags); 652 for (i = 0; i < ARRAY_SIZE(ctrl->user_data); i++) { 653 if (ctrl->user_data[i] != uvalue->value.iec958.subcode[i]) 654 changed = 1; 655 656 ctrl->user_data[i] = uvalue->value.iec958.subcode[i]; 657 } 658 if (changed) { 659 if (mchp_spdiftx_is_running(dev)) { 660 /* 661 * if SPDIF is running, wait for interrupt to write 662 * user data 663 */ 664 regmap_write(dev->regmap, SPDIFTX_IER, 665 SPDIFTX_IR_UDRDY); 666 } else { 667 mchp_spdiftx_user_data_write(dev); 668 } 669 } 670 spin_unlock_irqrestore(&ctrl->lock, flags); 671 672 return changed; 673 } 674 675 static struct snd_kcontrol_new mchp_spdiftx_ctrls[] = { 676 /* Channel status controller */ 677 { 678 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 679 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 680 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 681 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 682 .info = mchp_spdiftx_info, 683 .get = mchp_spdiftx_cs_get, 684 .put = mchp_spdiftx_cs_put, 685 }, 686 { 687 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 688 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 689 .access = SNDRV_CTL_ELEM_ACCESS_READ, 690 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 691 .info = mchp_spdiftx_info, 692 .get = mchp_spdiftx_cs_mask, 693 }, 694 /* User bits controller */ 695 { 696 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 697 .name = "IEC958 Subcode Playback Default", 698 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 699 .info = mchp_spdiftx_info, 700 .get = mchp_spdiftx_subcode_get, 701 .put = mchp_spdiftx_subcode_put, 702 }, 703 }; 704 705 static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai) 706 { 707 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 708 709 snd_soc_dai_init_dma_data(dai, &dev->playback, NULL); 710 711 /* Add controls */ 712 snd_soc_add_dai_controls(dai, mchp_spdiftx_ctrls, 713 ARRAY_SIZE(mchp_spdiftx_ctrls)); 714 715 return 0; 716 } 717 718 static struct snd_soc_dai_driver mchp_spdiftx_dai = { 719 .name = "mchp-spdiftx", 720 .probe = mchp_spdiftx_dai_probe, 721 .playback = { 722 .stream_name = "S/PDIF Playback", 723 .channels_min = 1, 724 .channels_max = 2, 725 .rates = MCHP_SPDIFTX_RATES, 726 .formats = MCHP_SPDIFTX_FORMATS, 727 }, 728 .ops = &mchp_spdiftx_dai_ops, 729 }; 730 731 static const struct snd_soc_component_driver mchp_spdiftx_component = { 732 .name = "mchp-spdiftx", 733 .legacy_dai_naming = 1, 734 }; 735 736 static const struct of_device_id mchp_spdiftx_dt_ids[] = { 737 { 738 .compatible = "microchip,sama7g5-spdiftx", 739 }, 740 { /* sentinel */ } 741 }; 742 MODULE_DEVICE_TABLE(of, mchp_spdiftx_dt_ids); 743 744 static int mchp_spdiftx_runtime_suspend(struct device *dev) 745 { 746 struct mchp_spdiftx_dev *spdiftx = dev_get_drvdata(dev); 747 748 regcache_cache_only(spdiftx->regmap, true); 749 750 clk_disable_unprepare(spdiftx->gclk); 751 clk_disable_unprepare(spdiftx->pclk); 752 753 return 0; 754 } 755 756 static int mchp_spdiftx_runtime_resume(struct device *dev) 757 { 758 struct mchp_spdiftx_dev *spdiftx = dev_get_drvdata(dev); 759 int ret; 760 761 ret = clk_prepare_enable(spdiftx->pclk); 762 if (ret) { 763 dev_err(spdiftx->dev, 764 "failed to enable the peripheral clock: %d\n", ret); 765 return ret; 766 } 767 ret = clk_prepare_enable(spdiftx->gclk); 768 if (ret) { 769 dev_err(spdiftx->dev, 770 "failed to enable generic clock: %d\n", ret); 771 goto disable_pclk; 772 } 773 774 regcache_cache_only(spdiftx->regmap, false); 775 regcache_mark_dirty(spdiftx->regmap); 776 ret = regcache_sync(spdiftx->regmap); 777 if (ret) { 778 regcache_cache_only(spdiftx->regmap, true); 779 clk_disable_unprepare(spdiftx->gclk); 780 disable_pclk: 781 clk_disable_unprepare(spdiftx->pclk); 782 } 783 784 return ret; 785 } 786 787 static const struct dev_pm_ops mchp_spdiftx_pm_ops = { 788 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 789 RUNTIME_PM_OPS(mchp_spdiftx_runtime_suspend, mchp_spdiftx_runtime_resume, 790 NULL) 791 }; 792 793 static int mchp_spdiftx_probe(struct platform_device *pdev) 794 { 795 struct mchp_spdiftx_dev *dev; 796 struct resource *mem; 797 struct regmap *regmap; 798 void __iomem *base; 799 struct mchp_spdiftx_mixer_control *ctrl; 800 int irq; 801 int err; 802 803 /* Get memory for driver data. */ 804 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 805 if (!dev) 806 return -ENOMEM; 807 808 /* Map I/O registers. */ 809 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 810 if (IS_ERR(base)) 811 return PTR_ERR(base); 812 813 regmap = devm_regmap_init_mmio(&pdev->dev, base, 814 &mchp_spdiftx_regmap_config); 815 if (IS_ERR(regmap)) 816 return PTR_ERR(regmap); 817 818 /* Request IRQ */ 819 irq = platform_get_irq(pdev, 0); 820 if (irq < 0) 821 return irq; 822 823 err = devm_request_irq(&pdev->dev, irq, mchp_spdiftx_interrupt, 0, 824 dev_name(&pdev->dev), dev); 825 if (err) 826 return err; 827 828 /* Get the peripheral clock */ 829 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 830 if (IS_ERR(dev->pclk)) { 831 err = PTR_ERR(dev->pclk); 832 dev_err(&pdev->dev, 833 "failed to get the peripheral clock: %d\n", err); 834 return err; 835 } 836 837 /* Get the generic clock */ 838 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 839 if (IS_ERR(dev->gclk)) { 840 err = PTR_ERR(dev->gclk); 841 dev_err(&pdev->dev, 842 "failed to get the PMC generic clock: %d\n", err); 843 return err; 844 } 845 846 ctrl = &dev->control; 847 spin_lock_init(&ctrl->lock); 848 849 /* Init channel status */ 850 ctrl->ch_stat[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 851 IEC958_AES0_CON_EMPHASIS_NONE; 852 853 dev->dev = &pdev->dev; 854 dev->regmap = regmap; 855 platform_set_drvdata(pdev, dev); 856 857 pm_runtime_enable(dev->dev); 858 if (!pm_runtime_enabled(dev->dev)) { 859 err = mchp_spdiftx_runtime_resume(dev->dev); 860 if (err) 861 return err; 862 } 863 864 dev->playback.addr = (dma_addr_t)mem->start + SPDIFTX_CDR; 865 dev->playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 866 867 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 868 if (err) { 869 dev_err(&pdev->dev, "failed to register PMC: %d\n", err); 870 goto pm_runtime_suspend; 871 } 872 873 err = devm_snd_soc_register_component(&pdev->dev, 874 &mchp_spdiftx_component, 875 &mchp_spdiftx_dai, 1); 876 if (err) { 877 dev_err(&pdev->dev, "failed to register component: %d\n", err); 878 goto pm_runtime_suspend; 879 } 880 881 return 0; 882 883 pm_runtime_suspend: 884 if (!pm_runtime_status_suspended(dev->dev)) 885 mchp_spdiftx_runtime_suspend(dev->dev); 886 pm_runtime_disable(dev->dev); 887 888 return err; 889 } 890 891 static int mchp_spdiftx_remove(struct platform_device *pdev) 892 { 893 struct mchp_spdiftx_dev *dev = platform_get_drvdata(pdev); 894 895 if (!pm_runtime_status_suspended(dev->dev)) 896 mchp_spdiftx_runtime_suspend(dev->dev); 897 898 pm_runtime_disable(dev->dev); 899 900 return 0; 901 } 902 903 static struct platform_driver mchp_spdiftx_driver = { 904 .probe = mchp_spdiftx_probe, 905 .remove = mchp_spdiftx_remove, 906 .driver = { 907 .name = "mchp_spdiftx", 908 .of_match_table = of_match_ptr(mchp_spdiftx_dt_ids), 909 .pm = pm_ptr(&mchp_spdiftx_pm_ops) 910 }, 911 }; 912 913 module_platform_driver(mchp_spdiftx_driver); 914 915 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 916 MODULE_DESCRIPTION("Microchip S/PDIF TX Controller Driver"); 917 MODULE_LICENSE("GPL v2"); 918