1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip S/PDIF TX Controller 4 // 5 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <linux/clk.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/spinlock.h> 13 14 #include <sound/asoundef.h> 15 #include <sound/dmaengine_pcm.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 19 /* 20 * ---- S/PDIF Transmitter Controller Register map ---- 21 */ 22 #define SPDIFTX_CR 0x00 /* Control Register */ 23 #define SPDIFTX_MR 0x04 /* Mode Register */ 24 #define SPDIFTX_CDR 0x0C /* Common Data Register */ 25 26 #define SPDIFTX_IER 0x14 /* Interrupt Enable Register */ 27 #define SPDIFTX_IDR 0x18 /* Interrupt Disable Register */ 28 #define SPDIFTX_IMR 0x1C /* Interrupt Mask Register */ 29 #define SPDIFTX_ISR 0x20 /* Interrupt Status Register */ 30 31 #define SPDIFTX_CH1UD(reg) (0x50 + (reg) * 4) /* User Data 1 Register x */ 32 #define SPDIFTX_CH1S(reg) (0x80 + (reg) * 4) /* Channel Status 1 Register x */ 33 34 #define SPDIFTX_VERSION 0xF0 35 36 /* 37 * ---- Control Register (Write-only) ---- 38 */ 39 #define SPDIFTX_CR_SWRST BIT(0) /* Software Reset */ 40 #define SPDIFTX_CR_FCLR BIT(1) /* FIFO clear */ 41 42 /* 43 * ---- Mode Register (Read/Write) ---- 44 */ 45 /* Transmit Enable */ 46 #define SPDIFTX_MR_TXEN_MASK GENMASK(0, 0) 47 #define SPDIFTX_MR_TXEN_DISABLE (0 << 0) 48 #define SPDIFTX_MR_TXEN_ENABLE (1 << 0) 49 50 /* Multichannel Transfer */ 51 #define SPDIFTX_MR_MULTICH_MASK GENAMSK(1, 1) 52 #define SPDIFTX_MR_MULTICH_MONO (0 << 1) 53 #define SPDIFTX_MR_MULTICH_DUAL (1 << 1) 54 55 /* Data Word Endian Mode */ 56 #define SPDIFTX_MR_ENDIAN_MASK GENMASK(2, 2) 57 #define SPDIFTX_MR_ENDIAN_LITTLE (0 << 2) 58 #define SPDIFTX_MR_ENDIAN_BIG (1 << 2) 59 60 /* Data Justification */ 61 #define SPDIFTX_MR_JUSTIFY_MASK GENMASK(3, 3) 62 #define SPDIFTX_MR_JUSTIFY_LSB (0 << 3) 63 #define SPDIFTX_MR_JUSTIFY_MSB (1 << 3) 64 65 /* Common Audio Register Transfer Mode */ 66 #define SPDIFTX_MR_CMODE_MASK GENMASK(5, 4) 67 #define SPDIFTX_MR_CMODE_INDEX_ACCESS (0 << 4) 68 #define SPDIFTX_MR_CMODE_TOGGLE_ACCESS (1 << 4) 69 #define SPDIFTX_MR_CMODE_INTERLVD_ACCESS (2 << 4) 70 71 /* Valid Bits per Sample */ 72 #define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8) 73 #define SPDIFTX_MR_VBPS(bps) (((bps) << 8) & SPDIFTX_MR_VBPS_MASK) 74 75 /* Chunk Size */ 76 #define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16) 77 #define SPDIFTX_MR_CHUNK(size) (((size) << 16) & SPDIFTX_MR_CHUNK_MASK) 78 79 /* Validity Bits for Channels 1 and 2 */ 80 #define SPDIFTX_MR_VALID1 BIT(24) 81 #define SPDIFTX_MR_VALID2 BIT(25) 82 83 /* Disable Null Frame on underrrun */ 84 #define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27) 85 #define SPDIFTX_MR_DNFR_INVALID (0 << 27) 86 #define SPDIFTX_MR_DNFR_VALID (1 << 27) 87 88 /* Bytes per Sample */ 89 #define SPDIFTX_MR_BPS_MASK GENMASK(29, 28) 90 #define SPDIFTX_MR_BPS(bytes) \ 91 ((((bytes) - 1) << 28) & SPDIFTX_MR_BPS_MASK) 92 93 /* 94 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ---- 95 */ 96 #define SPDIFTX_IR_TXRDY BIT(0) 97 #define SPDIFTX_IR_TXEMPTY BIT(1) 98 #define SPDIFTX_IR_TXFULL BIT(2) 99 #define SPDIFTX_IR_TXCHUNK BIT(3) 100 #define SPDIFTX_IR_TXUDR BIT(4) 101 #define SPDIFTX_IR_TXOVR BIT(5) 102 #define SPDIFTX_IR_CSRDY BIT(6) 103 #define SPDIFTX_IR_UDRDY BIT(7) 104 #define SPDIFTX_IR_TXRDYCH(ch) BIT((ch) + 8) 105 #define SPDIFTX_IR_SECE BIT(10) 106 #define SPDIFTX_IR_TXUDRCH(ch) BIT((ch) + 11) 107 #define SPDIFTX_IR_BEND BIT(13) 108 109 static bool mchp_spdiftx_readable_reg(struct device *dev, unsigned int reg) 110 { 111 switch (reg) { 112 case SPDIFTX_MR: 113 case SPDIFTX_IMR: 114 case SPDIFTX_ISR: 115 case SPDIFTX_CH1UD(0): 116 case SPDIFTX_CH1UD(1): 117 case SPDIFTX_CH1UD(2): 118 case SPDIFTX_CH1UD(3): 119 case SPDIFTX_CH1UD(4): 120 case SPDIFTX_CH1UD(5): 121 case SPDIFTX_CH1S(0): 122 case SPDIFTX_CH1S(1): 123 case SPDIFTX_CH1S(2): 124 case SPDIFTX_CH1S(3): 125 case SPDIFTX_CH1S(4): 126 case SPDIFTX_CH1S(5): 127 return true; 128 default: 129 return false; 130 } 131 } 132 133 static bool mchp_spdiftx_writeable_reg(struct device *dev, unsigned int reg) 134 { 135 switch (reg) { 136 case SPDIFTX_CR: 137 case SPDIFTX_MR: 138 case SPDIFTX_CDR: 139 case SPDIFTX_IER: 140 case SPDIFTX_IDR: 141 case SPDIFTX_CH1UD(0): 142 case SPDIFTX_CH1UD(1): 143 case SPDIFTX_CH1UD(2): 144 case SPDIFTX_CH1UD(3): 145 case SPDIFTX_CH1UD(4): 146 case SPDIFTX_CH1UD(5): 147 case SPDIFTX_CH1S(0): 148 case SPDIFTX_CH1S(1): 149 case SPDIFTX_CH1S(2): 150 case SPDIFTX_CH1S(3): 151 case SPDIFTX_CH1S(4): 152 case SPDIFTX_CH1S(5): 153 return true; 154 default: 155 return false; 156 } 157 } 158 159 static bool mchp_spdiftx_precious_reg(struct device *dev, unsigned int reg) 160 { 161 switch (reg) { 162 case SPDIFTX_CDR: 163 case SPDIFTX_ISR: 164 return true; 165 default: 166 return false; 167 } 168 } 169 170 static const struct regmap_config mchp_spdiftx_regmap_config = { 171 .reg_bits = 32, 172 .reg_stride = 4, 173 .val_bits = 32, 174 .max_register = SPDIFTX_VERSION, 175 .readable_reg = mchp_spdiftx_readable_reg, 176 .writeable_reg = mchp_spdiftx_writeable_reg, 177 .precious_reg = mchp_spdiftx_precious_reg, 178 }; 179 180 #define SPDIFTX_GCLK_RATIO 128 181 182 #define SPDIFTX_CS_BITS 192 183 #define SPDIFTX_UD_BITS 192 184 185 struct mchp_spdiftx_mixer_control { 186 unsigned char ch_stat[SPDIFTX_CS_BITS / 8]; 187 unsigned char user_data[SPDIFTX_UD_BITS / 8]; 188 spinlock_t lock; /* exclusive access to control data */ 189 }; 190 191 struct mchp_spdiftx_dev { 192 struct mchp_spdiftx_mixer_control control; 193 struct snd_dmaengine_dai_dma_data playback; 194 struct device *dev; 195 struct regmap *regmap; 196 struct clk *pclk; 197 struct clk *gclk; 198 unsigned int fmt; 199 const struct mchp_i2s_caps *caps; 200 int gclk_enabled:1; 201 }; 202 203 static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev) 204 { 205 u32 mr; 206 207 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 208 return !!(mr & SPDIFTX_MR_TXEN_ENABLE); 209 } 210 211 static void mchp_spdiftx_channel_status_write(struct mchp_spdiftx_dev *dev) 212 { 213 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 214 u32 val; 215 int i; 216 217 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat) / 4; i++) { 218 val = (ctrl->ch_stat[(i * 4) + 0] << 0) | 219 (ctrl->ch_stat[(i * 4) + 1] << 8) | 220 (ctrl->ch_stat[(i * 4) + 2] << 16) | 221 (ctrl->ch_stat[(i * 4) + 3] << 24); 222 223 regmap_write(dev->regmap, SPDIFTX_CH1S(i), val); 224 } 225 } 226 227 static void mchp_spdiftx_user_data_write(struct mchp_spdiftx_dev *dev) 228 { 229 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 230 u32 val; 231 int i; 232 233 for (i = 0; i < ARRAY_SIZE(ctrl->user_data) / 4; i++) { 234 val = (ctrl->user_data[(i * 4) + 0] << 0) | 235 (ctrl->user_data[(i * 4) + 1] << 8) | 236 (ctrl->user_data[(i * 4) + 2] << 16) | 237 (ctrl->user_data[(i * 4) + 3] << 24); 238 239 regmap_write(dev->regmap, SPDIFTX_CH1UD(i), val); 240 } 241 } 242 243 static irqreturn_t mchp_spdiftx_interrupt(int irq, void *dev_id) 244 { 245 struct mchp_spdiftx_dev *dev = dev_id; 246 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 247 u32 sr, imr, pending, idr = 0; 248 249 regmap_read(dev->regmap, SPDIFTX_ISR, &sr); 250 regmap_read(dev->regmap, SPDIFTX_IMR, &imr); 251 pending = sr & imr; 252 253 if (!pending) 254 return IRQ_NONE; 255 256 if (pending & SPDIFTX_IR_TXUDR) { 257 dev_warn(dev->dev, "underflow detected\n"); 258 idr |= SPDIFTX_IR_TXUDR; 259 } 260 261 if (pending & SPDIFTX_IR_TXOVR) { 262 dev_warn(dev->dev, "overflow detected\n"); 263 idr |= SPDIFTX_IR_TXOVR; 264 } 265 266 if (pending & SPDIFTX_IR_UDRDY) { 267 spin_lock(&ctrl->lock); 268 mchp_spdiftx_user_data_write(dev); 269 spin_unlock(&ctrl->lock); 270 idr |= SPDIFTX_IR_UDRDY; 271 } 272 273 if (pending & SPDIFTX_IR_CSRDY) { 274 spin_lock(&ctrl->lock); 275 mchp_spdiftx_channel_status_write(dev); 276 spin_unlock(&ctrl->lock); 277 idr |= SPDIFTX_IR_CSRDY; 278 } 279 280 regmap_write(dev->regmap, SPDIFTX_IDR, idr); 281 282 return IRQ_HANDLED; 283 } 284 285 static int mchp_spdiftx_dai_startup(struct snd_pcm_substream *substream, 286 struct snd_soc_dai *dai) 287 { 288 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 289 290 /* Software reset the IP */ 291 regmap_write(dev->regmap, SPDIFTX_CR, 292 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); 293 294 return 0; 295 } 296 297 static void mchp_spdiftx_dai_shutdown(struct snd_pcm_substream *substream, 298 struct snd_soc_dai *dai) 299 { 300 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 301 302 /* Disable interrupts */ 303 regmap_write(dev->regmap, SPDIFTX_IDR, 0xffffffff); 304 } 305 306 static int mchp_spdiftx_trigger(struct snd_pcm_substream *substream, int cmd, 307 struct snd_soc_dai *dai) 308 { 309 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 310 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 311 u32 mr; 312 int running; 313 int ret; 314 315 /* do not start/stop while channel status or user data is updated */ 316 spin_lock(&ctrl->lock); 317 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 318 running = !!(mr & SPDIFTX_MR_TXEN_ENABLE); 319 320 switch (cmd) { 321 case SNDRV_PCM_TRIGGER_START: 322 case SNDRV_PCM_TRIGGER_RESUME: 323 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 324 if (!running) { 325 mr &= ~SPDIFTX_MR_TXEN_MASK; 326 mr |= SPDIFTX_MR_TXEN_ENABLE; 327 } 328 break; 329 case SNDRV_PCM_TRIGGER_STOP: 330 case SNDRV_PCM_TRIGGER_SUSPEND: 331 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 332 if (running) { 333 mr &= ~SPDIFTX_MR_TXEN_MASK; 334 mr |= SPDIFTX_MR_TXEN_DISABLE; 335 } 336 break; 337 default: 338 spin_unlock(&ctrl->lock); 339 return -EINVAL; 340 } 341 342 ret = regmap_write(dev->regmap, SPDIFTX_MR, mr); 343 spin_unlock(&ctrl->lock); 344 if (ret) { 345 dev_err(dev->dev, "unable to disable TX: %d\n", ret); 346 return ret; 347 } 348 349 return 0; 350 } 351 352 static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream, 353 struct snd_pcm_hw_params *params, 354 struct snd_soc_dai *dai) 355 { 356 unsigned long flags; 357 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 358 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 359 u32 mr; 360 unsigned int bps = params_physical_width(params) / 8; 361 int ret; 362 363 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 364 __func__, params_rate(params), params_format(params), 365 params_width(params), params_channels(params)); 366 367 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 368 dev_err(dev->dev, "Capture is not supported\n"); 369 return -EINVAL; 370 } 371 372 regmap_read(dev->regmap, SPDIFTX_MR, &mr); 373 374 if (mr & SPDIFTX_MR_TXEN_ENABLE) { 375 dev_err(dev->dev, "PCM already running\n"); 376 return -EBUSY; 377 } 378 379 /* Defaults: Toggle mode, justify to LSB, chunksize 1 */ 380 mr = SPDIFTX_MR_CMODE_TOGGLE_ACCESS | SPDIFTX_MR_JUSTIFY_LSB; 381 dev->playback.maxburst = 1; 382 switch (params_channels(params)) { 383 case 1: 384 mr |= SPDIFTX_MR_MULTICH_MONO; 385 break; 386 case 2: 387 mr |= SPDIFTX_MR_MULTICH_DUAL; 388 if (bps > 2) 389 dev->playback.maxburst = 2; 390 break; 391 default: 392 dev_err(dev->dev, "unsupported number of channels: %d\n", 393 params_channels(params)); 394 return -EINVAL; 395 } 396 mr |= SPDIFTX_MR_CHUNK(dev->playback.maxburst); 397 398 switch (params_format(params)) { 399 case SNDRV_PCM_FORMAT_S8: 400 mr |= SPDIFTX_MR_VBPS(8); 401 break; 402 case SNDRV_PCM_FORMAT_S16_BE: 403 mr |= SPDIFTX_MR_ENDIAN_BIG; 404 fallthrough; 405 case SNDRV_PCM_FORMAT_S16_LE: 406 mr |= SPDIFTX_MR_VBPS(16); 407 break; 408 case SNDRV_PCM_FORMAT_S18_3BE: 409 mr |= SPDIFTX_MR_ENDIAN_BIG; 410 fallthrough; 411 case SNDRV_PCM_FORMAT_S18_3LE: 412 mr |= SPDIFTX_MR_VBPS(18); 413 break; 414 case SNDRV_PCM_FORMAT_S20_3BE: 415 mr |= SPDIFTX_MR_ENDIAN_BIG; 416 fallthrough; 417 case SNDRV_PCM_FORMAT_S20_3LE: 418 mr |= SPDIFTX_MR_VBPS(20); 419 break; 420 case SNDRV_PCM_FORMAT_S24_3BE: 421 mr |= SPDIFTX_MR_ENDIAN_BIG; 422 fallthrough; 423 case SNDRV_PCM_FORMAT_S24_3LE: 424 mr |= SPDIFTX_MR_VBPS(24); 425 break; 426 case SNDRV_PCM_FORMAT_S24_BE: 427 mr |= SPDIFTX_MR_ENDIAN_BIG; 428 fallthrough; 429 case SNDRV_PCM_FORMAT_S24_LE: 430 mr |= SPDIFTX_MR_VBPS(24); 431 break; 432 case SNDRV_PCM_FORMAT_S32_BE: 433 mr |= SPDIFTX_MR_ENDIAN_BIG; 434 fallthrough; 435 case SNDRV_PCM_FORMAT_S32_LE: 436 mr |= SPDIFTX_MR_VBPS(32); 437 break; 438 default: 439 dev_err(dev->dev, "unsupported PCM format: %d\n", 440 params_format(params)); 441 return -EINVAL; 442 } 443 444 mr |= SPDIFTX_MR_BPS(bps); 445 446 spin_lock_irqsave(&ctrl->lock, flags); 447 ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS; 448 switch (params_rate(params)) { 449 case 22050: 450 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_22050; 451 break; 452 case 24000: 453 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_24000; 454 break; 455 case 32000: 456 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_32000; 457 break; 458 case 44100: 459 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_44100; 460 break; 461 case 48000: 462 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_48000; 463 break; 464 case 88200: 465 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_88200; 466 break; 467 case 96000: 468 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_96000; 469 break; 470 case 176400: 471 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_176400; 472 break; 473 case 192000: 474 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_192000; 475 break; 476 case 8000: 477 case 11025: 478 case 16000: 479 case 64000: 480 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_NOTID; 481 break; 482 default: 483 dev_err(dev->dev, "unsupported sample frequency: %u\n", 484 params_rate(params)); 485 spin_unlock_irqrestore(&ctrl->lock, flags); 486 return -EINVAL; 487 } 488 mchp_spdiftx_channel_status_write(dev); 489 spin_unlock_irqrestore(&ctrl->lock, flags); 490 mr |= SPDIFTX_MR_VALID1 | SPDIFTX_MR_VALID2; 491 492 if (dev->gclk_enabled) { 493 clk_disable_unprepare(dev->gclk); 494 dev->gclk_enabled = 0; 495 } 496 ret = clk_set_rate(dev->gclk, params_rate(params) * 497 SPDIFTX_GCLK_RATIO); 498 if (ret) { 499 dev_err(dev->dev, 500 "unable to change gclk rate to: rate %u * ratio %u\n", 501 params_rate(params), SPDIFTX_GCLK_RATIO); 502 return ret; 503 } 504 ret = clk_prepare_enable(dev->gclk); 505 if (ret) { 506 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); 507 return ret; 508 } 509 dev->gclk_enabled = 1; 510 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, 511 params_rate(params) * SPDIFTX_GCLK_RATIO); 512 513 /* Enable interrupts */ 514 regmap_write(dev->regmap, SPDIFTX_IER, 515 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); 516 517 regmap_write(dev->regmap, SPDIFTX_MR, mr); 518 519 return 0; 520 } 521 522 static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream, 523 struct snd_soc_dai *dai) 524 { 525 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 526 527 regmap_write(dev->regmap, SPDIFTX_IDR, 528 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); 529 if (dev->gclk_enabled) { 530 clk_disable_unprepare(dev->gclk); 531 dev->gclk_enabled = 0; 532 } 533 534 return regmap_write(dev->regmap, SPDIFTX_CR, 535 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); 536 } 537 538 static const struct snd_soc_dai_ops mchp_spdiftx_dai_ops = { 539 .startup = mchp_spdiftx_dai_startup, 540 .shutdown = mchp_spdiftx_dai_shutdown, 541 .trigger = mchp_spdiftx_trigger, 542 .hw_params = mchp_spdiftx_hw_params, 543 .hw_free = mchp_spdiftx_hw_free, 544 }; 545 546 #define MCHP_SPDIFTX_RATES SNDRV_PCM_RATE_8000_192000 547 548 #define MCHP_SPDIFTX_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 549 SNDRV_PCM_FMTBIT_S16_LE | \ 550 SNDRV_PCM_FMTBIT_U16_BE | \ 551 SNDRV_PCM_FMTBIT_S18_3LE | \ 552 SNDRV_PCM_FMTBIT_S18_3BE | \ 553 SNDRV_PCM_FMTBIT_S20_3LE | \ 554 SNDRV_PCM_FMTBIT_S20_3BE | \ 555 SNDRV_PCM_FMTBIT_S24_3LE | \ 556 SNDRV_PCM_FMTBIT_S24_3BE | \ 557 SNDRV_PCM_FMTBIT_S24_LE | \ 558 SNDRV_PCM_FMTBIT_S24_BE | \ 559 SNDRV_PCM_FMTBIT_S32_LE | \ 560 SNDRV_PCM_FMTBIT_S32_BE \ 561 ) 562 563 static int mchp_spdiftx_info(struct snd_kcontrol *kcontrol, 564 struct snd_ctl_elem_info *uinfo) 565 { 566 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 567 uinfo->count = 1; 568 569 return 0; 570 } 571 572 static int mchp_spdiftx_cs_get(struct snd_kcontrol *kcontrol, 573 struct snd_ctl_elem_value *uvalue) 574 { 575 unsigned long flags; 576 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 577 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 578 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 579 580 spin_lock_irqsave(&ctrl->lock, flags); 581 memcpy(uvalue->value.iec958.status, ctrl->ch_stat, 582 sizeof(ctrl->ch_stat)); 583 spin_unlock_irqrestore(&ctrl->lock, flags); 584 585 return 0; 586 } 587 588 static int mchp_spdiftx_cs_put(struct snd_kcontrol *kcontrol, 589 struct snd_ctl_elem_value *uvalue) 590 { 591 unsigned long flags; 592 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 593 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 594 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 595 int changed = 0; 596 int i; 597 598 spin_lock_irqsave(&ctrl->lock, flags); 599 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat); i++) { 600 if (ctrl->ch_stat[i] != uvalue->value.iec958.status[i]) 601 changed = 1; 602 ctrl->ch_stat[i] = uvalue->value.iec958.status[i]; 603 } 604 605 if (changed) { 606 /* don't enable IP while we copy the channel status */ 607 if (mchp_spdiftx_is_running(dev)) { 608 /* 609 * if SPDIF is running, wait for interrupt to write 610 * channel status 611 */ 612 regmap_write(dev->regmap, SPDIFTX_IER, 613 SPDIFTX_IR_CSRDY); 614 } else { 615 mchp_spdiftx_channel_status_write(dev); 616 } 617 } 618 spin_unlock_irqrestore(&ctrl->lock, flags); 619 620 return changed; 621 } 622 623 static int mchp_spdiftx_cs_mask(struct snd_kcontrol *kcontrol, 624 struct snd_ctl_elem_value *uvalue) 625 { 626 memset(uvalue->value.iec958.status, 0xff, 627 sizeof(uvalue->value.iec958.status)); 628 629 return 0; 630 } 631 632 static int mchp_spdiftx_subcode_get(struct snd_kcontrol *kcontrol, 633 struct snd_ctl_elem_value *uvalue) 634 { 635 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 636 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 637 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 638 unsigned long flags; 639 640 spin_lock_irqsave(&ctrl->lock, flags); 641 memcpy(uvalue->value.iec958.subcode, ctrl->user_data, 642 sizeof(ctrl->user_data)); 643 spin_unlock_irqrestore(&ctrl->lock, flags); 644 645 return 0; 646 } 647 648 static int mchp_spdiftx_subcode_put(struct snd_kcontrol *kcontrol, 649 struct snd_ctl_elem_value *uvalue) 650 { 651 unsigned long flags; 652 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 653 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 654 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; 655 int changed = 0; 656 int i; 657 658 spin_lock_irqsave(&ctrl->lock, flags); 659 for (i = 0; i < ARRAY_SIZE(ctrl->user_data); i++) { 660 if (ctrl->user_data[i] != uvalue->value.iec958.subcode[i]) 661 changed = 1; 662 663 ctrl->user_data[i] = uvalue->value.iec958.subcode[i]; 664 } 665 if (changed) { 666 if (mchp_spdiftx_is_running(dev)) { 667 /* 668 * if SPDIF is running, wait for interrupt to write 669 * user data 670 */ 671 regmap_write(dev->regmap, SPDIFTX_IER, 672 SPDIFTX_IR_UDRDY); 673 } else { 674 mchp_spdiftx_user_data_write(dev); 675 } 676 } 677 spin_unlock_irqrestore(&ctrl->lock, flags); 678 679 return changed; 680 } 681 682 static struct snd_kcontrol_new mchp_spdiftx_ctrls[] = { 683 /* Channel status controller */ 684 { 685 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 686 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 687 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 688 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 689 .info = mchp_spdiftx_info, 690 .get = mchp_spdiftx_cs_get, 691 .put = mchp_spdiftx_cs_put, 692 }, 693 { 694 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 695 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 696 .access = SNDRV_CTL_ELEM_ACCESS_READ, 697 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 698 .info = mchp_spdiftx_info, 699 .get = mchp_spdiftx_cs_mask, 700 }, 701 /* User bits controller */ 702 { 703 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 704 .name = "IEC958 Subcode Playback Default", 705 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 706 .info = mchp_spdiftx_info, 707 .get = mchp_spdiftx_subcode_get, 708 .put = mchp_spdiftx_subcode_put, 709 }, 710 }; 711 712 static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai) 713 { 714 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 715 int ret; 716 717 snd_soc_dai_init_dma_data(dai, &dev->playback, NULL); 718 719 ret = clk_prepare_enable(dev->pclk); 720 if (ret) { 721 dev_err(dev->dev, 722 "failed to enable the peripheral clock: %d\n", ret); 723 return ret; 724 } 725 726 /* Add controls */ 727 snd_soc_add_dai_controls(dai, mchp_spdiftx_ctrls, 728 ARRAY_SIZE(mchp_spdiftx_ctrls)); 729 730 return 0; 731 } 732 733 static int mchp_spdiftx_dai_remove(struct snd_soc_dai *dai) 734 { 735 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); 736 737 clk_disable_unprepare(dev->pclk); 738 739 return 0; 740 } 741 742 static struct snd_soc_dai_driver mchp_spdiftx_dai = { 743 .name = "mchp-spdiftx", 744 .probe = mchp_spdiftx_dai_probe, 745 .remove = mchp_spdiftx_dai_remove, 746 .playback = { 747 .stream_name = "S/PDIF TX Playback", 748 .channels_min = 1, 749 .channels_max = 2, 750 .rates = MCHP_SPDIFTX_RATES, 751 .formats = MCHP_SPDIFTX_FORMATS, 752 }, 753 .ops = &mchp_spdiftx_dai_ops, 754 }; 755 756 static const struct snd_soc_component_driver mchp_spdiftx_component = { 757 .name = "mchp-spdiftx", 758 }; 759 760 static const struct of_device_id mchp_spdiftx_dt_ids[] = { 761 { 762 .compatible = "microchip,sama7g5-spdiftx", 763 }, 764 { /* sentinel */ } 765 }; 766 767 MODULE_DEVICE_TABLE(of, mchp_spdiftx_dt_ids); 768 static int mchp_spdiftx_probe(struct platform_device *pdev) 769 { 770 struct device_node *np = pdev->dev.of_node; 771 const struct of_device_id *match; 772 struct mchp_spdiftx_dev *dev; 773 struct resource *mem; 774 struct regmap *regmap; 775 void __iomem *base; 776 struct mchp_spdiftx_mixer_control *ctrl; 777 int irq; 778 int err; 779 780 /* Get memory for driver data. */ 781 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 782 if (!dev) 783 return -ENOMEM; 784 785 /* Get hardware capabilities. */ 786 match = of_match_node(mchp_spdiftx_dt_ids, np); 787 if (match) 788 dev->caps = match->data; 789 790 /* Map I/O registers. */ 791 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 792 if (IS_ERR(base)) 793 return PTR_ERR(base); 794 795 regmap = devm_regmap_init_mmio(&pdev->dev, base, 796 &mchp_spdiftx_regmap_config); 797 if (IS_ERR(regmap)) 798 return PTR_ERR(regmap); 799 800 /* Request IRQ */ 801 irq = platform_get_irq(pdev, 0); 802 if (irq < 0) 803 return irq; 804 805 err = devm_request_irq(&pdev->dev, irq, mchp_spdiftx_interrupt, 0, 806 dev_name(&pdev->dev), dev); 807 if (err) 808 return err; 809 810 /* Get the peripheral clock */ 811 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 812 if (IS_ERR(dev->pclk)) { 813 err = PTR_ERR(dev->pclk); 814 dev_err(&pdev->dev, 815 "failed to get the peripheral clock: %d\n", err); 816 return err; 817 } 818 819 /* Get the generic clock */ 820 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 821 if (IS_ERR(dev->gclk)) { 822 err = PTR_ERR(dev->gclk); 823 dev_err(&pdev->dev, 824 "failed to get the PMC generic clock: %d\n", err); 825 return err; 826 } 827 828 ctrl = &dev->control; 829 spin_lock_init(&ctrl->lock); 830 831 /* Init channel status */ 832 ctrl->ch_stat[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 833 IEC958_AES0_CON_EMPHASIS_NONE; 834 835 dev->dev = &pdev->dev; 836 dev->regmap = regmap; 837 platform_set_drvdata(pdev, dev); 838 839 dev->playback.addr = (dma_addr_t)mem->start + SPDIFTX_CDR; 840 dev->playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 841 842 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 843 if (err) { 844 dev_err(&pdev->dev, "failed to register PMC: %d\n", err); 845 return err; 846 } 847 848 err = devm_snd_soc_register_component(&pdev->dev, 849 &mchp_spdiftx_component, 850 &mchp_spdiftx_dai, 1); 851 if (err) { 852 dev_err(&pdev->dev, "failed to register component: %d\n", err); 853 return err; 854 } 855 856 return 0; 857 } 858 859 static struct platform_driver mchp_spdiftx_driver = { 860 .probe = mchp_spdiftx_probe, 861 .driver = { 862 .name = "mchp_spdiftx", 863 .of_match_table = of_match_ptr(mchp_spdiftx_dt_ids), 864 }, 865 }; 866 867 module_platform_driver(mchp_spdiftx_driver); 868 869 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 870 MODULE_DESCRIPTION("Microchip S/PDIF TX Controller Driver"); 871 MODULE_LICENSE("GPL v2"); 872