1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip S/PDIF RX Controller 4 // 5 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <linux/clk.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <linux/spinlock.h> 14 15 #include <sound/dmaengine_pcm.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 19 /* 20 * ---- S/PDIF Receiver Controller Register map ---- 21 */ 22 #define SPDIFRX_CR 0x00 /* Control Register */ 23 #define SPDIFRX_MR 0x04 /* Mode Register */ 24 25 #define SPDIFRX_IER 0x10 /* Interrupt Enable Register */ 26 #define SPDIFRX_IDR 0x14 /* Interrupt Disable Register */ 27 #define SPDIFRX_IMR 0x18 /* Interrupt Mask Register */ 28 #define SPDIFRX_ISR 0x1c /* Interrupt Status Register */ 29 #define SPDIFRX_RSR 0x20 /* Status Register */ 30 #define SPDIFRX_RHR 0x24 /* Holding Register */ 31 32 #define SPDIFRX_CHSR(channel, reg) \ 33 (0x30 + (channel) * 0x30 + (reg) * 4) /* Channel x Status Registers */ 34 35 #define SPDIFRX_CHUD(channel, reg) \ 36 (0x48 + (channel) * 0x30 + (reg) * 4) /* Channel x User Data Registers */ 37 38 #define SPDIFRX_WPMR 0xE4 /* Write Protection Mode Register */ 39 #define SPDIFRX_WPSR 0xE8 /* Write Protection Status Register */ 40 41 #define SPDIFRX_VERSION 0xFC /* Version Register */ 42 43 /* 44 * ---- Control Register (Write-only) ---- 45 */ 46 #define SPDIFRX_CR_SWRST BIT(0) /* Software Reset */ 47 48 /* 49 * ---- Mode Register (Read/Write) ---- 50 */ 51 /* Receive Enable */ 52 #define SPDIFRX_MR_RXEN_MASK GENMASK(0, 0) 53 #define SPDIFRX_MR_RXEN_DISABLE (0 << 0) /* SPDIF Receiver Disabled */ 54 #define SPDIFRX_MR_RXEN_ENABLE (1 << 0) /* SPDIF Receiver Enabled */ 55 56 /* Validity Bit Mode */ 57 #define SPDIFRX_MR_VBMODE_MASK GENAMSK(1, 1) 58 #define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \ 59 (0 << 1) /* Load sample regardless of validity bit value */ 60 #define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \ 61 (1 << 1) /* Load sample only if validity bit is 0 */ 62 63 /* Data Word Endian Mode */ 64 #define SPDIFRX_MR_ENDIAN_MASK GENMASK(2, 2) 65 #define SPDIFRX_MR_ENDIAN_LITTLE (0 << 2) /* Little Endian Mode */ 66 #define SPDIFRX_MR_ENDIAN_BIG (1 << 2) /* Big Endian Mode */ 67 68 /* Parity Bit Mode */ 69 #define SPDIFRX_MR_PBMODE_MASK GENMASK(3, 3) 70 #define SPDIFRX_MR_PBMODE_PARCHECK (0 << 3) /* Parity Check Enabled */ 71 #define SPDIFRX_MR_PBMODE_NOPARCHECK (1 << 3) /* Parity Check Disabled */ 72 73 /* Sample Data Width */ 74 #define SPDIFRX_MR_DATAWIDTH_MASK GENMASK(5, 4) 75 #define SPDIFRX_MR_DATAWIDTH(width) \ 76 (((6 - (width) / 4) << 4) & SPDIFRX_MR_DATAWIDTH_MASK) 77 78 /* Packed Data Mode in Receive Holding Register */ 79 #define SPDIFRX_MR_PACK_MASK GENMASK(7, 7) 80 #define SPDIFRX_MR_PACK_DISABLED (0 << 7) 81 #define SPDIFRX_MR_PACK_ENABLED (1 << 7) 82 83 /* Start of Block Bit Mode */ 84 #define SPDIFRX_MR_SBMODE_MASK GENMASK(8, 8) 85 #define SPDIFRX_MR_SBMODE_ALWAYS_LOAD (0 << 8) 86 #define SPDIFRX_MR_SBMODE_DISCARD (1 << 8) 87 88 /* Consecutive Preamble Error Threshold Automatic Restart */ 89 #define SPDIFRX_MR_AUTORST_MASK GENMASK(24, 24) 90 #define SPDIFRX_MR_AUTORST_NOACTION (0 << 24) 91 #define SPDIFRX_MR_AUTORST_UNLOCK_ON_PRE_ERR (1 << 24) 92 93 /* 94 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ---- 95 */ 96 #define SPDIFRX_IR_RXRDY BIT(0) 97 #define SPDIFRX_IR_LOCKED BIT(1) 98 #define SPDIFRX_IR_LOSS BIT(2) 99 #define SPDIFRX_IR_BLOCKEND BIT(3) 100 #define SPDIFRX_IR_SFE BIT(4) 101 #define SPDIFRX_IR_PAR_ERR BIT(5) 102 #define SPDIFRX_IR_OVERRUN BIT(6) 103 #define SPDIFRX_IR_RXFULL BIT(7) 104 #define SPDIFRX_IR_CSC(ch) BIT((ch) + 8) 105 #define SPDIFRX_IR_SECE BIT(10) 106 #define SPDIFRX_IR_BLOCKST BIT(11) 107 #define SPDIFRX_IR_NRZ_ERR BIT(12) 108 #define SPDIFRX_IR_PRE_ERR BIT(13) 109 #define SPDIFRX_IR_CP_ERR BIT(14) 110 111 /* 112 * ---- Receiver Status Register (Read/Write) ---- 113 */ 114 /* Enable Status */ 115 #define SPDIFRX_RSR_ULOCK BIT(0) 116 #define SPDIFRX_RSR_BADF BIT(1) 117 #define SPDIFRX_RSR_LOWF BIT(2) 118 #define SPDIFRX_RSR_NOSIGNAL BIT(3) 119 #define SPDIFRX_RSR_IFS_MASK GENMASK(27, 16) 120 #define SPDIFRX_RSR_IFS(reg) \ 121 (((reg) & SPDIFRX_RSR_IFS_MASK) >> 16) 122 123 /* 124 * ---- Version Register (Read-only) ---- 125 */ 126 #define SPDIFRX_VERSION_MASK GENMASK(11, 0) 127 #define SPDIFRX_VERSION_MFN_MASK GENMASK(18, 16) 128 #define SPDIFRX_VERSION_MFN(reg) (((reg) & SPDIFRX_VERSION_MFN_MASK) >> 16) 129 130 static bool mchp_spdifrx_readable_reg(struct device *dev, unsigned int reg) 131 { 132 switch (reg) { 133 case SPDIFRX_MR: 134 case SPDIFRX_IMR: 135 case SPDIFRX_ISR: 136 case SPDIFRX_RSR: 137 case SPDIFRX_CHSR(0, 0): 138 case SPDIFRX_CHSR(0, 1): 139 case SPDIFRX_CHSR(0, 2): 140 case SPDIFRX_CHSR(0, 3): 141 case SPDIFRX_CHSR(0, 4): 142 case SPDIFRX_CHSR(0, 5): 143 case SPDIFRX_CHUD(0, 0): 144 case SPDIFRX_CHUD(0, 1): 145 case SPDIFRX_CHUD(0, 2): 146 case SPDIFRX_CHUD(0, 3): 147 case SPDIFRX_CHUD(0, 4): 148 case SPDIFRX_CHUD(0, 5): 149 case SPDIFRX_CHSR(1, 0): 150 case SPDIFRX_CHSR(1, 1): 151 case SPDIFRX_CHSR(1, 2): 152 case SPDIFRX_CHSR(1, 3): 153 case SPDIFRX_CHSR(1, 4): 154 case SPDIFRX_CHSR(1, 5): 155 case SPDIFRX_CHUD(1, 0): 156 case SPDIFRX_CHUD(1, 1): 157 case SPDIFRX_CHUD(1, 2): 158 case SPDIFRX_CHUD(1, 3): 159 case SPDIFRX_CHUD(1, 4): 160 case SPDIFRX_CHUD(1, 5): 161 case SPDIFRX_WPMR: 162 case SPDIFRX_WPSR: 163 case SPDIFRX_VERSION: 164 return true; 165 default: 166 return false; 167 } 168 } 169 170 static bool mchp_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 171 { 172 switch (reg) { 173 case SPDIFRX_CR: 174 case SPDIFRX_MR: 175 case SPDIFRX_IER: 176 case SPDIFRX_IDR: 177 case SPDIFRX_WPMR: 178 return true; 179 default: 180 return false; 181 } 182 } 183 184 static bool mchp_spdifrx_precious_reg(struct device *dev, unsigned int reg) 185 { 186 switch (reg) { 187 case SPDIFRX_ISR: 188 case SPDIFRX_RHR: 189 return true; 190 default: 191 return false; 192 } 193 } 194 195 static const struct regmap_config mchp_spdifrx_regmap_config = { 196 .reg_bits = 32, 197 .reg_stride = 4, 198 .val_bits = 32, 199 .max_register = SPDIFRX_VERSION, 200 .readable_reg = mchp_spdifrx_readable_reg, 201 .writeable_reg = mchp_spdifrx_writeable_reg, 202 .precious_reg = mchp_spdifrx_precious_reg, 203 }; 204 205 #define SPDIFRX_GCLK_RATIO_MIN (12 * 64) 206 207 #define SPDIFRX_CS_BITS 192 208 #define SPDIFRX_UD_BITS 192 209 210 #define SPDIFRX_CHANNELS 2 211 212 struct mchp_spdifrx_ch_stat { 213 unsigned char data[SPDIFRX_CS_BITS / 8]; 214 struct completion done; 215 }; 216 217 struct mchp_spdifrx_user_data { 218 unsigned char data[SPDIFRX_UD_BITS / 8]; 219 struct completion done; 220 spinlock_t lock; /* protect access to user data */ 221 }; 222 223 struct mchp_spdifrx_mixer_control { 224 struct mchp_spdifrx_ch_stat ch_stat[SPDIFRX_CHANNELS]; 225 struct mchp_spdifrx_user_data user_data[SPDIFRX_CHANNELS]; 226 bool ulock; 227 bool badf; 228 bool signal; 229 }; 230 231 struct mchp_spdifrx_dev { 232 struct snd_dmaengine_dai_dma_data capture; 233 struct mchp_spdifrx_mixer_control control; 234 spinlock_t blockend_lock; /* protect access to blockend_refcount */ 235 int blockend_refcount; 236 struct device *dev; 237 struct regmap *regmap; 238 struct clk *pclk; 239 struct clk *gclk; 240 unsigned int fmt; 241 unsigned int gclk_enabled:1; 242 }; 243 244 static void mchp_spdifrx_channel_status_read(struct mchp_spdifrx_dev *dev, 245 int channel) 246 { 247 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 248 u8 *ch_stat = &ctrl->ch_stat[channel].data[0]; 249 u32 val; 250 int i; 251 252 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat[channel].data) / 4; i++) { 253 regmap_read(dev->regmap, SPDIFRX_CHSR(channel, i), &val); 254 *ch_stat++ = val & 0xFF; 255 *ch_stat++ = (val >> 8) & 0xFF; 256 *ch_stat++ = (val >> 16) & 0xFF; 257 *ch_stat++ = (val >> 24) & 0xFF; 258 } 259 } 260 261 static void mchp_spdifrx_channel_user_data_read(struct mchp_spdifrx_dev *dev, 262 int channel) 263 { 264 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 265 u8 *user_data = &ctrl->user_data[channel].data[0]; 266 u32 val; 267 int i; 268 269 for (i = 0; i < ARRAY_SIZE(ctrl->user_data[channel].data) / 4; i++) { 270 regmap_read(dev->regmap, SPDIFRX_CHUD(channel, i), &val); 271 *user_data++ = val & 0xFF; 272 *user_data++ = (val >> 8) & 0xFF; 273 *user_data++ = (val >> 16) & 0xFF; 274 *user_data++ = (val >> 24) & 0xFF; 275 } 276 } 277 278 /* called from non-atomic context only */ 279 static void mchp_spdifrx_isr_blockend_en(struct mchp_spdifrx_dev *dev) 280 { 281 unsigned long flags; 282 283 spin_lock_irqsave(&dev->blockend_lock, flags); 284 dev->blockend_refcount++; 285 /* don't enable BLOCKEND interrupt if it's already enabled */ 286 if (dev->blockend_refcount == 1) 287 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_BLOCKEND); 288 spin_unlock_irqrestore(&dev->blockend_lock, flags); 289 } 290 291 /* called from atomic/non-atomic context */ 292 static void mchp_spdifrx_isr_blockend_dis(struct mchp_spdifrx_dev *dev) 293 { 294 unsigned long flags; 295 296 spin_lock_irqsave(&dev->blockend_lock, flags); 297 dev->blockend_refcount--; 298 /* don't enable BLOCKEND interrupt if it's already enabled */ 299 if (dev->blockend_refcount == 0) 300 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND); 301 spin_unlock_irqrestore(&dev->blockend_lock, flags); 302 } 303 304 static irqreturn_t mchp_spdif_interrupt(int irq, void *dev_id) 305 { 306 struct mchp_spdifrx_dev *dev = dev_id; 307 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 308 u32 sr, imr, pending, idr = 0; 309 irqreturn_t ret = IRQ_NONE; 310 int ch; 311 312 regmap_read(dev->regmap, SPDIFRX_ISR, &sr); 313 regmap_read(dev->regmap, SPDIFRX_IMR, &imr); 314 pending = sr & imr; 315 dev_dbg(dev->dev, "ISR: %#x, IMR: %#x, pending: %#x\n", sr, imr, 316 pending); 317 318 if (!pending) 319 return IRQ_NONE; 320 321 if (pending & SPDIFRX_IR_BLOCKEND) { 322 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 323 spin_lock(&ctrl->user_data[ch].lock); 324 mchp_spdifrx_channel_user_data_read(dev, ch); 325 spin_unlock(&ctrl->user_data[ch].lock); 326 327 complete(&ctrl->user_data[ch].done); 328 } 329 mchp_spdifrx_isr_blockend_dis(dev); 330 ret = IRQ_HANDLED; 331 } 332 333 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 334 if (pending & SPDIFRX_IR_CSC(ch)) { 335 mchp_spdifrx_channel_status_read(dev, ch); 336 complete(&ctrl->ch_stat[ch].done); 337 idr |= SPDIFRX_IR_CSC(ch); 338 ret = IRQ_HANDLED; 339 } 340 } 341 342 if (pending & SPDIFRX_IR_OVERRUN) { 343 dev_warn(dev->dev, "Overrun detected\n"); 344 ret = IRQ_HANDLED; 345 } 346 347 regmap_write(dev->regmap, SPDIFRX_IDR, idr); 348 349 return ret; 350 } 351 352 static int mchp_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 353 struct snd_soc_dai *dai) 354 { 355 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 356 u32 mr; 357 int running; 358 int ret; 359 360 regmap_read(dev->regmap, SPDIFRX_MR, &mr); 361 running = !!(mr & SPDIFRX_MR_RXEN_ENABLE); 362 363 switch (cmd) { 364 case SNDRV_PCM_TRIGGER_START: 365 case SNDRV_PCM_TRIGGER_RESUME: 366 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 367 if (!running) { 368 mr &= ~SPDIFRX_MR_RXEN_MASK; 369 mr |= SPDIFRX_MR_RXEN_ENABLE; 370 /* enable overrun interrupts */ 371 regmap_write(dev->regmap, SPDIFRX_IER, 372 SPDIFRX_IR_OVERRUN); 373 } 374 break; 375 case SNDRV_PCM_TRIGGER_STOP: 376 case SNDRV_PCM_TRIGGER_SUSPEND: 377 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 378 if (running) { 379 mr &= ~SPDIFRX_MR_RXEN_MASK; 380 mr |= SPDIFRX_MR_RXEN_DISABLE; 381 /* disable overrun interrupts */ 382 regmap_write(dev->regmap, SPDIFRX_IDR, 383 SPDIFRX_IR_OVERRUN); 384 } 385 break; 386 default: 387 return -EINVAL; 388 } 389 390 ret = regmap_write(dev->regmap, SPDIFRX_MR, mr); 391 if (ret) { 392 dev_err(dev->dev, "unable to enable/disable RX: %d\n", ret); 393 return ret; 394 } 395 396 return 0; 397 } 398 399 static int mchp_spdifrx_hw_params(struct snd_pcm_substream *substream, 400 struct snd_pcm_hw_params *params, 401 struct snd_soc_dai *dai) 402 { 403 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 404 u32 mr; 405 int ret; 406 407 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 408 __func__, params_rate(params), params_format(params), 409 params_width(params), params_channels(params)); 410 411 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 412 dev_err(dev->dev, "Playback is not supported\n"); 413 return -EINVAL; 414 } 415 416 regmap_read(dev->regmap, SPDIFRX_MR, &mr); 417 418 if (mr & SPDIFRX_MR_RXEN_ENABLE) { 419 dev_err(dev->dev, "PCM already running\n"); 420 return -EBUSY; 421 } 422 423 if (params_channels(params) != SPDIFRX_CHANNELS) { 424 dev_err(dev->dev, "unsupported number of channels: %d\n", 425 params_channels(params)); 426 return -EINVAL; 427 } 428 429 switch (params_format(params)) { 430 case SNDRV_PCM_FORMAT_S16_BE: 431 case SNDRV_PCM_FORMAT_S20_3BE: 432 case SNDRV_PCM_FORMAT_S24_3BE: 433 case SNDRV_PCM_FORMAT_S24_BE: 434 mr |= SPDIFRX_MR_ENDIAN_BIG; 435 fallthrough; 436 case SNDRV_PCM_FORMAT_S16_LE: 437 case SNDRV_PCM_FORMAT_S20_3LE: 438 case SNDRV_PCM_FORMAT_S24_3LE: 439 case SNDRV_PCM_FORMAT_S24_LE: 440 mr |= SPDIFRX_MR_DATAWIDTH(params_width(params)); 441 break; 442 default: 443 dev_err(dev->dev, "unsupported PCM format: %d\n", 444 params_format(params)); 445 return -EINVAL; 446 } 447 448 if (dev->gclk_enabled) { 449 clk_disable_unprepare(dev->gclk); 450 dev->gclk_enabled = 0; 451 } 452 ret = clk_set_min_rate(dev->gclk, params_rate(params) * 453 SPDIFRX_GCLK_RATIO_MIN + 1); 454 if (ret) { 455 dev_err(dev->dev, 456 "unable to set gclk min rate: rate %u * ratio %u + 1\n", 457 params_rate(params), SPDIFRX_GCLK_RATIO_MIN); 458 return ret; 459 } 460 ret = clk_prepare_enable(dev->gclk); 461 if (ret) { 462 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); 463 return ret; 464 } 465 dev->gclk_enabled = 1; 466 467 dev_dbg(dev->dev, "GCLK range min set to %d\n", 468 params_rate(params) * SPDIFRX_GCLK_RATIO_MIN + 1); 469 470 return regmap_write(dev->regmap, SPDIFRX_MR, mr); 471 } 472 473 static int mchp_spdifrx_hw_free(struct snd_pcm_substream *substream, 474 struct snd_soc_dai *dai) 475 { 476 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 477 478 if (dev->gclk_enabled) { 479 clk_disable_unprepare(dev->gclk); 480 dev->gclk_enabled = 0; 481 } 482 return 0; 483 } 484 485 static const struct snd_soc_dai_ops mchp_spdifrx_dai_ops = { 486 .trigger = mchp_spdifrx_trigger, 487 .hw_params = mchp_spdifrx_hw_params, 488 .hw_free = mchp_spdifrx_hw_free, 489 }; 490 491 #define MCHP_SPDIF_RATES SNDRV_PCM_RATE_8000_192000 492 493 #define MCHP_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 494 SNDRV_PCM_FMTBIT_U16_BE | \ 495 SNDRV_PCM_FMTBIT_S20_3LE | \ 496 SNDRV_PCM_FMTBIT_S20_3BE | \ 497 SNDRV_PCM_FMTBIT_S24_3LE | \ 498 SNDRV_PCM_FMTBIT_S24_3BE | \ 499 SNDRV_PCM_FMTBIT_S24_LE | \ 500 SNDRV_PCM_FMTBIT_S24_BE \ 501 ) 502 503 static int mchp_spdifrx_info(struct snd_kcontrol *kcontrol, 504 struct snd_ctl_elem_info *uinfo) 505 { 506 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 507 uinfo->count = 1; 508 509 return 0; 510 } 511 512 static int mchp_spdifrx_cs_get(struct mchp_spdifrx_dev *dev, 513 int channel, 514 struct snd_ctl_elem_value *uvalue) 515 { 516 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 517 struct mchp_spdifrx_ch_stat *ch_stat = &ctrl->ch_stat[channel]; 518 int ret; 519 520 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_CSC(channel)); 521 /* check for new data available */ 522 ret = wait_for_completion_interruptible_timeout(&ch_stat->done, 523 msecs_to_jiffies(100)); 524 /* IP might not be started or valid stream might not be present */ 525 if (ret < 0) { 526 dev_dbg(dev->dev, "channel status for channel %d timeout\n", 527 channel); 528 } 529 530 memcpy(uvalue->value.iec958.status, ch_stat->data, 531 sizeof(ch_stat->data)); 532 533 return 0; 534 } 535 536 static int mchp_spdifrx_cs1_get(struct snd_kcontrol *kcontrol, 537 struct snd_ctl_elem_value *uvalue) 538 { 539 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 540 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 541 542 return mchp_spdifrx_cs_get(dev, 0, uvalue); 543 } 544 545 static int mchp_spdifrx_cs2_get(struct snd_kcontrol *kcontrol, 546 struct snd_ctl_elem_value *uvalue) 547 { 548 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 549 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 550 551 return mchp_spdifrx_cs_get(dev, 1, uvalue); 552 } 553 554 static int mchp_spdifrx_cs_mask(struct snd_kcontrol *kcontrol, 555 struct snd_ctl_elem_value *uvalue) 556 { 557 memset(uvalue->value.iec958.status, 0xff, 558 sizeof(uvalue->value.iec958.status)); 559 560 return 0; 561 } 562 563 static int mchp_spdifrx_subcode_ch_get(struct mchp_spdifrx_dev *dev, 564 int channel, 565 struct snd_ctl_elem_value *uvalue) 566 { 567 unsigned long flags; 568 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 569 struct mchp_spdifrx_user_data *user_data = &ctrl->user_data[channel]; 570 int ret; 571 572 reinit_completion(&user_data->done); 573 mchp_spdifrx_isr_blockend_en(dev); 574 ret = wait_for_completion_interruptible_timeout(&user_data->done, 575 msecs_to_jiffies(100)); 576 /* IP might not be started or valid stream might not be present */ 577 if (ret <= 0) { 578 dev_dbg(dev->dev, "user data for channel %d timeout\n", 579 channel); 580 mchp_spdifrx_isr_blockend_dis(dev); 581 return ret; 582 } 583 584 spin_lock_irqsave(&user_data->lock, flags); 585 memcpy(uvalue->value.iec958.subcode, user_data->data, 586 sizeof(user_data->data)); 587 spin_unlock_irqrestore(&user_data->lock, flags); 588 589 return 0; 590 } 591 592 static int mchp_spdifrx_subcode_ch1_get(struct snd_kcontrol *kcontrol, 593 struct snd_ctl_elem_value *uvalue) 594 { 595 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 596 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 597 598 return mchp_spdifrx_subcode_ch_get(dev, 0, uvalue); 599 } 600 601 static int mchp_spdifrx_subcode_ch2_get(struct snd_kcontrol *kcontrol, 602 struct snd_ctl_elem_value *uvalue) 603 { 604 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 605 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 606 607 return mchp_spdifrx_subcode_ch_get(dev, 1, uvalue); 608 } 609 610 static int mchp_spdifrx_boolean_info(struct snd_kcontrol *kcontrol, 611 struct snd_ctl_elem_info *uinfo) 612 { 613 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 614 uinfo->count = 1; 615 uinfo->value.integer.min = 0; 616 uinfo->value.integer.max = 1; 617 618 return 0; 619 } 620 621 static int mchp_spdifrx_ulock_get(struct snd_kcontrol *kcontrol, 622 struct snd_ctl_elem_value *uvalue) 623 { 624 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 625 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 626 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 627 u32 val; 628 bool ulock_old = ctrl->ulock; 629 630 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 631 ctrl->ulock = !(val & SPDIFRX_RSR_ULOCK); 632 uvalue->value.integer.value[0] = ctrl->ulock; 633 634 return ulock_old != ctrl->ulock; 635 } 636 637 static int mchp_spdifrx_badf_get(struct snd_kcontrol *kcontrol, 638 struct snd_ctl_elem_value *uvalue) 639 { 640 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 641 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 642 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 643 u32 val; 644 bool badf_old = ctrl->badf; 645 646 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 647 ctrl->badf = !!(val & SPDIFRX_RSR_BADF); 648 uvalue->value.integer.value[0] = ctrl->badf; 649 650 return badf_old != ctrl->badf; 651 } 652 653 static int mchp_spdifrx_signal_get(struct snd_kcontrol *kcontrol, 654 struct snd_ctl_elem_value *uvalue) 655 { 656 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 657 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 658 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 659 u32 val; 660 bool signal_old = ctrl->signal; 661 662 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 663 ctrl->signal = !(val & SPDIFRX_RSR_NOSIGNAL); 664 uvalue->value.integer.value[0] = ctrl->signal; 665 666 return signal_old != ctrl->signal; 667 } 668 669 static int mchp_spdifrx_rate_info(struct snd_kcontrol *kcontrol, 670 struct snd_ctl_elem_info *uinfo) 671 { 672 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 673 uinfo->count = 1; 674 uinfo->value.integer.min = 0; 675 uinfo->value.integer.max = 192000; 676 677 return 0; 678 } 679 680 static int mchp_spdifrx_rate_get(struct snd_kcontrol *kcontrol, 681 struct snd_ctl_elem_value *ucontrol) 682 { 683 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 684 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 685 u32 val; 686 int rate; 687 688 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 689 690 /* if the receiver is not locked, ISF data is invalid */ 691 if (val & SPDIFRX_RSR_ULOCK || !(val & SPDIFRX_RSR_IFS_MASK)) { 692 ucontrol->value.integer.value[0] = 0; 693 return 0; 694 } 695 696 rate = clk_get_rate(dev->gclk); 697 698 ucontrol->value.integer.value[0] = rate / (32 * SPDIFRX_RSR_IFS(val)); 699 700 return 0; 701 } 702 703 static struct snd_kcontrol_new mchp_spdifrx_ctrls[] = { 704 /* Channel status controller */ 705 { 706 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 707 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT) 708 " Channel 1", 709 .access = SNDRV_CTL_ELEM_ACCESS_READ | 710 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 711 .info = mchp_spdifrx_info, 712 .get = mchp_spdifrx_cs1_get, 713 }, 714 { 715 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 716 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT) 717 " Channel 2", 718 .access = SNDRV_CTL_ELEM_ACCESS_READ | 719 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 720 .info = mchp_spdifrx_info, 721 .get = mchp_spdifrx_cs2_get, 722 }, 723 { 724 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 725 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), 726 .access = SNDRV_CTL_ELEM_ACCESS_READ, 727 .info = mchp_spdifrx_info, 728 .get = mchp_spdifrx_cs_mask, 729 }, 730 /* User bits controller */ 731 { 732 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 733 .name = "IEC958 Subcode Capture Default Channel 1", 734 .access = SNDRV_CTL_ELEM_ACCESS_READ | 735 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 736 .info = mchp_spdifrx_info, 737 .get = mchp_spdifrx_subcode_ch1_get, 738 }, 739 { 740 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 741 .name = "IEC958 Subcode Capture Default Channel 2", 742 .access = SNDRV_CTL_ELEM_ACCESS_READ | 743 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 744 .info = mchp_spdifrx_info, 745 .get = mchp_spdifrx_subcode_ch2_get, 746 }, 747 /* Lock status */ 748 { 749 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 750 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Unlocked", 751 .access = SNDRV_CTL_ELEM_ACCESS_READ | 752 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 753 .info = mchp_spdifrx_boolean_info, 754 .get = mchp_spdifrx_ulock_get, 755 }, 756 /* Bad format */ 757 { 758 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 759 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE)"Bad Format", 760 .access = SNDRV_CTL_ELEM_ACCESS_READ | 761 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 762 .info = mchp_spdifrx_boolean_info, 763 .get = mchp_spdifrx_badf_get, 764 }, 765 /* Signal */ 766 { 767 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 768 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Signal", 769 .access = SNDRV_CTL_ELEM_ACCESS_READ | 770 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 771 .info = mchp_spdifrx_boolean_info, 772 .get = mchp_spdifrx_signal_get, 773 }, 774 /* Sampling rate */ 775 { 776 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 777 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Rate", 778 .access = SNDRV_CTL_ELEM_ACCESS_READ | 779 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 780 .info = mchp_spdifrx_rate_info, 781 .get = mchp_spdifrx_rate_get, 782 }, 783 }; 784 785 static int mchp_spdifrx_dai_probe(struct snd_soc_dai *dai) 786 { 787 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 788 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 789 int ch; 790 int err; 791 792 err = clk_prepare_enable(dev->pclk); 793 if (err) { 794 dev_err(dev->dev, 795 "failed to enable the peripheral clock: %d\n", err); 796 return err; 797 } 798 799 snd_soc_dai_init_dma_data(dai, NULL, &dev->capture); 800 801 /* Software reset the IP */ 802 regmap_write(dev->regmap, SPDIFRX_CR, SPDIFRX_CR_SWRST); 803 804 /* Default configuration */ 805 regmap_write(dev->regmap, SPDIFRX_MR, 806 SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 | 807 SPDIFRX_MR_SBMODE_DISCARD | 808 SPDIFRX_MR_AUTORST_NOACTION | 809 SPDIFRX_MR_PACK_DISABLED); 810 811 dev->blockend_refcount = 0; 812 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 813 init_completion(&ctrl->ch_stat[ch].done); 814 init_completion(&ctrl->user_data[ch].done); 815 spin_lock_init(&ctrl->user_data[ch].lock); 816 } 817 818 /* Add controls */ 819 snd_soc_add_dai_controls(dai, mchp_spdifrx_ctrls, 820 ARRAY_SIZE(mchp_spdifrx_ctrls)); 821 822 return 0; 823 } 824 825 static int mchp_spdifrx_dai_remove(struct snd_soc_dai *dai) 826 { 827 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 828 829 /* Disable interrupts */ 830 regmap_write(dev->regmap, SPDIFRX_IDR, 0xFF); 831 832 clk_disable_unprepare(dev->pclk); 833 834 return 0; 835 } 836 837 static struct snd_soc_dai_driver mchp_spdifrx_dai = { 838 .name = "mchp-spdifrx", 839 .probe = mchp_spdifrx_dai_probe, 840 .remove = mchp_spdifrx_dai_remove, 841 .capture = { 842 .stream_name = "S/PDIF Capture", 843 .channels_min = SPDIFRX_CHANNELS, 844 .channels_max = SPDIFRX_CHANNELS, 845 .rates = MCHP_SPDIF_RATES, 846 .formats = MCHP_SPDIF_FORMATS, 847 }, 848 .ops = &mchp_spdifrx_dai_ops, 849 }; 850 851 static const struct snd_soc_component_driver mchp_spdifrx_component = { 852 .name = "mchp-spdifrx", 853 .legacy_dai_naming = 1, 854 }; 855 856 static const struct of_device_id mchp_spdifrx_dt_ids[] = { 857 { 858 .compatible = "microchip,sama7g5-spdifrx", 859 }, 860 { /* sentinel */ } 861 }; 862 MODULE_DEVICE_TABLE(of, mchp_spdifrx_dt_ids); 863 864 static int mchp_spdifrx_probe(struct platform_device *pdev) 865 { 866 struct mchp_spdifrx_dev *dev; 867 struct resource *mem; 868 struct regmap *regmap; 869 void __iomem *base; 870 int irq; 871 int err; 872 u32 vers; 873 874 /* Get memory for driver data. */ 875 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 876 if (!dev) 877 return -ENOMEM; 878 879 /* Map I/O registers. */ 880 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 881 if (IS_ERR(base)) 882 return PTR_ERR(base); 883 884 regmap = devm_regmap_init_mmio(&pdev->dev, base, 885 &mchp_spdifrx_regmap_config); 886 if (IS_ERR(regmap)) 887 return PTR_ERR(regmap); 888 889 /* Request IRQ. */ 890 irq = platform_get_irq(pdev, 0); 891 if (irq < 0) 892 return irq; 893 894 err = devm_request_irq(&pdev->dev, irq, mchp_spdif_interrupt, 0, 895 dev_name(&pdev->dev), dev); 896 if (err) 897 return err; 898 899 /* Get the peripheral clock */ 900 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 901 if (IS_ERR(dev->pclk)) { 902 err = PTR_ERR(dev->pclk); 903 dev_err(&pdev->dev, "failed to get the peripheral clock: %d\n", 904 err); 905 return err; 906 } 907 908 /* Get the generated clock */ 909 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 910 if (IS_ERR(dev->gclk)) { 911 err = PTR_ERR(dev->gclk); 912 dev_err(&pdev->dev, 913 "failed to get the PMC generated clock: %d\n", err); 914 return err; 915 } 916 spin_lock_init(&dev->blockend_lock); 917 918 dev->dev = &pdev->dev; 919 dev->regmap = regmap; 920 platform_set_drvdata(pdev, dev); 921 922 dev->capture.addr = (dma_addr_t)mem->start + SPDIFRX_RHR; 923 dev->capture.maxburst = 1; 924 925 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 926 if (err) { 927 dev_err(&pdev->dev, "failed to register PCM: %d\n", err); 928 return err; 929 } 930 931 err = devm_snd_soc_register_component(&pdev->dev, 932 &mchp_spdifrx_component, 933 &mchp_spdifrx_dai, 1); 934 if (err) { 935 dev_err(&pdev->dev, "fail to register dai\n"); 936 return err; 937 } 938 939 regmap_read(regmap, SPDIFRX_VERSION, &vers); 940 dev_info(&pdev->dev, "hw version: %#lx\n", vers & SPDIFRX_VERSION_MASK); 941 942 return 0; 943 } 944 945 static struct platform_driver mchp_spdifrx_driver = { 946 .probe = mchp_spdifrx_probe, 947 .driver = { 948 .name = "mchp_spdifrx", 949 .of_match_table = of_match_ptr(mchp_spdifrx_dt_ids), 950 }, 951 }; 952 953 module_platform_driver(mchp_spdifrx_driver); 954 955 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 956 MODULE_DESCRIPTION("Microchip S/PDIF RX Controller Driver"); 957 MODULE_LICENSE("GPL v2"); 958