1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip Pulse Density Microphone Controller (PDMC) interfaces 4 // 5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <dt-bindings/sound/microchip,pdmc.h> 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 18 #include <sound/core.h> 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/tlv.h> 22 23 /* 24 * ---- PDMC Register map ---- 25 */ 26 #define MCHP_PDMC_CR 0x00 /* Control Register */ 27 #define MCHP_PDMC_MR 0x04 /* Mode Register */ 28 #define MCHP_PDMC_CFGR 0x08 /* Configuration Register */ 29 #define MCHP_PDMC_RHR 0x0C /* Receive Holding Register */ 30 #define MCHP_PDMC_IER 0x14 /* Interrupt Enable Register */ 31 #define MCHP_PDMC_IDR 0x18 /* Interrupt Disable Register */ 32 #define MCHP_PDMC_IMR 0x1C /* Interrupt Mask Register */ 33 #define MCHP_PDMC_ISR 0x20 /* Interrupt Status Register */ 34 #define MCHP_PDMC_VER 0x50 /* Version Register */ 35 36 /* 37 * ---- Control Register (Write-only) ---- 38 */ 39 #define MCHP_PDMC_CR_SWRST BIT(0) /* Software Reset */ 40 41 /* 42 * ---- Mode Register (Read/Write) ---- 43 */ 44 #define MCHP_PDMC_MR_PDMCEN_MASK GENMASK(3, 0) 45 #define MCHP_PDMC_MR_PDMCEN(ch) (BIT(ch) & MCHP_PDMC_MR_PDMCEN_MASK) 46 47 #define MCHP_PDMC_MR_OSR_MASK GENMASK(17, 16) 48 #define MCHP_PDMC_MR_OSR64 (1 << 16) 49 #define MCHP_PDMC_MR_OSR128 (2 << 16) 50 #define MCHP_PDMC_MR_OSR256 (3 << 16) 51 52 #define MCHP_PDMC_MR_SINCORDER_MASK GENMASK(23, 20) 53 54 #define MCHP_PDMC_MR_SINC_OSR_MASK GENMASK(27, 24) 55 #define MCHP_PDMC_MR_SINC_OSR_DIS (0 << 24) 56 #define MCHP_PDMC_MR_SINC_OSR_8 (1 << 24) 57 #define MCHP_PDMC_MR_SINC_OSR_16 (2 << 24) 58 #define MCHP_PDMC_MR_SINC_OSR_32 (3 << 24) 59 #define MCHP_PDMC_MR_SINC_OSR_64 (4 << 24) 60 #define MCHP_PDMC_MR_SINC_OSR_128 (5 << 24) 61 #define MCHP_PDMC_MR_SINC_OSR_256 (6 << 24) 62 63 #define MCHP_PDMC_MR_CHUNK_MASK GENMASK(31, 28) 64 65 /* 66 * ---- Configuration Register (Read/Write) ---- 67 */ 68 #define MCHP_PDMC_CFGR_BSSEL_MASK (BIT(0) | BIT(2) | BIT(4) | BIT(6)) 69 #define MCHP_PDMC_CFGR_BSSEL(ch) BIT((ch) * 2) 70 71 #define MCHP_PDMC_CFGR_PDMSEL_MASK (BIT(16) | BIT(18) | BIT(20) | BIT(22)) 72 #define MCHP_PDMC_CFGR_PDMSEL(ch) BIT((ch) * 2 + 16) 73 74 /* 75 * ---- Interrupt Enable/Disable/Mask/Status Registers ---- 76 */ 77 #define MCHP_PDMC_IR_RXRDY BIT(0) 78 #define MCHP_PDMC_IR_RXEMPTY BIT(1) 79 #define MCHP_PDMC_IR_RXFULL BIT(2) 80 #define MCHP_PDMC_IR_RXCHUNK BIT(3) 81 #define MCHP_PDMC_IR_RXUDR BIT(4) 82 #define MCHP_PDMC_IR_RXOVR BIT(5) 83 84 /* 85 * ---- Version Register (Read-only) ---- 86 */ 87 #define MCHP_PDMC_VER_VERSION GENMASK(11, 0) 88 89 #define MCHP_PDMC_MAX_CHANNELS 4 90 #define MCHP_PDMC_DS_NO 2 91 #define MCHP_PDMC_EDGE_NO 2 92 93 struct mic_map { 94 int ds_pos; 95 int clk_edge; 96 }; 97 98 struct mchp_pdmc_chmap { 99 struct snd_pcm_chmap_elem *chmap; 100 struct mchp_pdmc *dd; 101 struct snd_pcm *pcm; 102 struct snd_kcontrol *kctl; 103 }; 104 105 struct mchp_pdmc { 106 struct mic_map channel_mic_map[MCHP_PDMC_MAX_CHANNELS]; 107 struct device *dev; 108 struct snd_dmaengine_dai_dma_data addr; 109 struct regmap *regmap; 110 struct clk *pclk; 111 struct clk *gclk; 112 u32 pdmcen; 113 u32 suspend_irq; 114 u32 startup_delay_us; 115 int mic_no; 116 int sinc_order; 117 bool audio_filter_en; 118 }; 119 120 static const char *const mchp_pdmc_sinc_filter_order_text[] = { 121 "1", "2", "3", "4", "5" 122 }; 123 124 static const unsigned int mchp_pdmc_sinc_filter_order_values[] = { 125 1, 2, 3, 4, 5, 126 }; 127 128 static const struct soc_enum mchp_pdmc_sinc_filter_order_enum = { 129 .items = ARRAY_SIZE(mchp_pdmc_sinc_filter_order_text), 130 .texts = mchp_pdmc_sinc_filter_order_text, 131 .values = mchp_pdmc_sinc_filter_order_values, 132 }; 133 134 static int mchp_pdmc_sinc_order_get(struct snd_kcontrol *kcontrol, 135 struct snd_ctl_elem_value *uvalue) 136 { 137 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 138 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 139 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 140 unsigned int item; 141 142 item = snd_soc_enum_val_to_item(e, dd->sinc_order); 143 uvalue->value.enumerated.item[0] = item; 144 145 return 0; 146 } 147 148 static int mchp_pdmc_sinc_order_put(struct snd_kcontrol *kcontrol, 149 struct snd_ctl_elem_value *uvalue) 150 { 151 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 152 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 153 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 154 unsigned int *item = uvalue->value.enumerated.item; 155 unsigned int val; 156 157 if (item[0] >= e->items) 158 return -EINVAL; 159 160 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 161 if (val == dd->sinc_order) 162 return 0; 163 164 dd->sinc_order = val; 165 166 return 1; 167 } 168 169 static int mchp_pdmc_af_get(struct snd_kcontrol *kcontrol, 170 struct snd_ctl_elem_value *uvalue) 171 { 172 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 173 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 174 175 uvalue->value.integer.value[0] = !!dd->audio_filter_en; 176 177 return 0; 178 } 179 180 static int mchp_pdmc_af_put(struct snd_kcontrol *kcontrol, 181 struct snd_ctl_elem_value *uvalue) 182 { 183 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 184 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 185 bool af = uvalue->value.integer.value[0] ? true : false; 186 187 if (dd->audio_filter_en == af) 188 return 0; 189 190 dd->audio_filter_en = af; 191 192 return 1; 193 } 194 195 static int mchp_pdmc_chmap_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 196 { 197 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 198 199 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 200 uinfo->count = info->dd->mic_no; 201 uinfo->value.integer.min = 0; 202 uinfo->value.integer.max = SNDRV_CHMAP_RR; /* maxmimum 4 channels */ 203 return 0; 204 } 205 206 static inline struct snd_pcm_substream * 207 mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap *info, unsigned int idx) 208 { 209 struct snd_pcm_substream *s; 210 211 for (s = info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; s; s = s->next) 212 if (s->number == idx) 213 return s; 214 return NULL; 215 } 216 217 static struct snd_pcm_chmap_elem *mchp_pdmc_chmap_get(struct snd_pcm_substream *substream, 218 struct mchp_pdmc_chmap *ch_info) 219 { 220 struct snd_pcm_chmap_elem *map; 221 222 for (map = ch_info->chmap; map->channels; map++) { 223 if (map->channels == substream->runtime->channels) 224 return map; 225 } 226 return NULL; 227 } 228 229 static int mchp_pdmc_chmap_ctl_get(struct snd_kcontrol *kcontrol, 230 struct snd_ctl_elem_value *ucontrol) 231 { 232 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 233 struct mchp_pdmc *dd = info->dd; 234 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 235 struct snd_pcm_substream *substream; 236 const struct snd_pcm_chmap_elem *map; 237 int i; 238 u32 cfgr_val = 0; 239 240 if (!info->chmap) 241 return -EINVAL; 242 substream = mchp_pdmc_chmap_substream(info, idx); 243 if (!substream) 244 return -ENODEV; 245 memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no); 246 if (!substream->runtime) 247 return 0; /* no channels set */ 248 249 map = mchp_pdmc_chmap_get(substream, info); 250 if (!map) 251 return -EINVAL; 252 253 for (i = 0; i < map->channels; i++) { 254 int map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO : 255 map->map[i] - SNDRV_CHMAP_FL; 256 257 /* make sure the reported channel map is the real one, so write the map */ 258 if (dd->channel_mic_map[map_idx].ds_pos) 259 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 260 if (dd->channel_mic_map[map_idx].clk_edge) 261 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 262 263 ucontrol->value.integer.value[i] = map->map[i]; 264 } 265 266 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val); 267 268 return 0; 269 } 270 271 static int mchp_pdmc_chmap_ctl_put(struct snd_kcontrol *kcontrol, 272 struct snd_ctl_elem_value *ucontrol) 273 { 274 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 275 struct mchp_pdmc *dd = info->dd; 276 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 277 struct snd_pcm_substream *substream; 278 struct snd_pcm_chmap_elem *map; 279 u32 cfgr_val = 0; 280 int i; 281 282 if (!info->chmap) 283 return -EINVAL; 284 substream = mchp_pdmc_chmap_substream(info, idx); 285 if (!substream) 286 return -ENODEV; 287 288 if (!substream->runtime) 289 return 0; /* just for avoiding error from alsactl restore */ 290 291 map = mchp_pdmc_chmap_get(substream, info); 292 if (!map) 293 return -EINVAL; 294 295 for (i = 0; i < map->channels; i++) { 296 int map_idx; 297 298 map->map[i] = ucontrol->value.integer.value[i]; 299 map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO : 300 map->map[i] - SNDRV_CHMAP_FL; 301 302 /* configure IP for the desired channel map */ 303 if (dd->channel_mic_map[map_idx].ds_pos) 304 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 305 if (dd->channel_mic_map[map_idx].clk_edge) 306 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 307 } 308 309 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val); 310 311 return 0; 312 } 313 314 static void mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol *kcontrol) 315 { 316 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 317 318 info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = NULL; 319 kfree(info); 320 } 321 322 static int mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, 323 unsigned int size, unsigned int __user *tlv) 324 { 325 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 326 const struct snd_pcm_chmap_elem *map; 327 unsigned int __user *dst; 328 int c, count = 0; 329 330 if (!info->chmap) 331 return -EINVAL; 332 if (size < 8) 333 return -ENOMEM; 334 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv)) 335 return -EFAULT; 336 size -= 8; 337 dst = tlv + 2; 338 for (map = info->chmap; map->channels; map++) { 339 int chs_bytes = map->channels * 4; 340 341 if (size < 8) 342 return -ENOMEM; 343 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) || 344 put_user(chs_bytes, dst + 1)) 345 return -EFAULT; 346 dst += 2; 347 size -= 8; 348 count += 8; 349 if (size < chs_bytes) 350 return -ENOMEM; 351 size -= chs_bytes; 352 count += chs_bytes; 353 for (c = 0; c < map->channels; c++) { 354 if (put_user(map->map[c], dst)) 355 return -EFAULT; 356 dst++; 357 } 358 } 359 if (put_user(count, tlv + 1)) 360 return -EFAULT; 361 return 0; 362 } 363 364 static const struct snd_kcontrol_new mchp_pdmc_snd_controls[] = { 365 SOC_SINGLE_BOOL_EXT("Audio Filter", 0, &mchp_pdmc_af_get, &mchp_pdmc_af_put), 366 { 367 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 368 .name = "SINC Filter Order", 369 .info = snd_soc_info_enum_double, 370 .get = mchp_pdmc_sinc_order_get, 371 .put = mchp_pdmc_sinc_order_put, 372 .private_value = (unsigned long)&mchp_pdmc_sinc_filter_order_enum, 373 }, 374 }; 375 376 static int mchp_pdmc_close(struct snd_soc_component *component, 377 struct snd_pcm_substream *substream) 378 { 379 return snd_soc_add_component_controls(component, mchp_pdmc_snd_controls, 380 ARRAY_SIZE(mchp_pdmc_snd_controls)); 381 } 382 383 static int mchp_pdmc_open(struct snd_soc_component *component, 384 struct snd_pcm_substream *substream) 385 { 386 int i; 387 388 /* remove controls that can't be changed at runtime */ 389 for (i = 0; i < ARRAY_SIZE(mchp_pdmc_snd_controls); i++) { 390 const struct snd_kcontrol_new *control = &mchp_pdmc_snd_controls[i]; 391 struct snd_ctl_elem_id id; 392 int err; 393 394 if (component->name_prefix) 395 snprintf(id.name, sizeof(id.name), "%s %s", component->name_prefix, 396 control->name); 397 else 398 strscpy(id.name, control->name, sizeof(id.name)); 399 400 id.numid = 0; 401 id.iface = control->iface; 402 id.device = control->device; 403 id.subdevice = control->subdevice; 404 id.index = control->index; 405 err = snd_ctl_remove_id(component->card->snd_card, &id); 406 if (err < 0) 407 dev_err(component->dev, "%d: Failed to remove %s\n", err, 408 control->name); 409 } 410 411 return 0; 412 } 413 414 static const struct snd_soc_component_driver mchp_pdmc_dai_component = { 415 .name = "mchp-pdmc", 416 .controls = mchp_pdmc_snd_controls, 417 .num_controls = ARRAY_SIZE(mchp_pdmc_snd_controls), 418 .open = &mchp_pdmc_open, 419 .close = &mchp_pdmc_close, 420 .legacy_dai_naming = 1, 421 .trigger_start = SND_SOC_TRIGGER_ORDER_LDC, 422 }; 423 424 static const unsigned int mchp_pdmc_1mic[] = {1}; 425 static const unsigned int mchp_pdmc_2mic[] = {1, 2}; 426 static const unsigned int mchp_pdmc_3mic[] = {1, 2, 3}; 427 static const unsigned int mchp_pdmc_4mic[] = {1, 2, 3, 4}; 428 429 static const struct snd_pcm_hw_constraint_list mchp_pdmc_chan_constr[] = { 430 { 431 .list = mchp_pdmc_1mic, 432 .count = ARRAY_SIZE(mchp_pdmc_1mic), 433 }, 434 { 435 .list = mchp_pdmc_2mic, 436 .count = ARRAY_SIZE(mchp_pdmc_2mic), 437 }, 438 { 439 .list = mchp_pdmc_3mic, 440 .count = ARRAY_SIZE(mchp_pdmc_3mic), 441 }, 442 { 443 .list = mchp_pdmc_4mic, 444 .count = ARRAY_SIZE(mchp_pdmc_4mic), 445 }, 446 }; 447 448 static int mchp_pdmc_startup(struct snd_pcm_substream *substream, 449 struct snd_soc_dai *dai) 450 { 451 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 452 453 regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST); 454 455 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 456 &mchp_pdmc_chan_constr[dd->mic_no - 1]); 457 458 return 0; 459 } 460 461 static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai) 462 { 463 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 464 465 snd_soc_dai_init_dma_data(dai, NULL, &dd->addr); 466 467 return 0; 468 } 469 470 static int mchp_pdmc_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 471 { 472 unsigned int fmt_master = fmt & SND_SOC_DAIFMT_MASTER_MASK; 473 unsigned int fmt_format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 474 475 /* IP needs to be bitclock master */ 476 if (fmt_master != SND_SOC_DAIFMT_BP_FP && 477 fmt_master != SND_SOC_DAIFMT_BP_FC) 478 return -EINVAL; 479 480 /* IP supports only PDM interface */ 481 if (fmt_format != SND_SOC_DAIFMT_PDM) 482 return -EINVAL; 483 484 return 0; 485 } 486 487 static u32 mchp_pdmc_mr_set_osr(int audio_filter_en, unsigned int osr) 488 { 489 if (audio_filter_en) { 490 switch (osr) { 491 case 64: 492 return MCHP_PDMC_MR_OSR64; 493 case 128: 494 return MCHP_PDMC_MR_OSR128; 495 case 256: 496 return MCHP_PDMC_MR_OSR256; 497 } 498 } else { 499 switch (osr) { 500 case 8: 501 return MCHP_PDMC_MR_SINC_OSR_8; 502 case 16: 503 return MCHP_PDMC_MR_SINC_OSR_16; 504 case 32: 505 return MCHP_PDMC_MR_SINC_OSR_32; 506 case 64: 507 return MCHP_PDMC_MR_SINC_OSR_64; 508 case 128: 509 return MCHP_PDMC_MR_SINC_OSR_128; 510 case 256: 511 return MCHP_PDMC_MR_SINC_OSR_256; 512 } 513 } 514 return 0; 515 } 516 517 static inline int mchp_pdmc_period_to_maxburst(int period_size) 518 { 519 if (!(period_size % 8)) 520 return 8; 521 if (!(period_size % 4)) 522 return 4; 523 if (!(period_size % 2)) 524 return 2; 525 return 1; 526 } 527 528 static struct snd_pcm_chmap_elem mchp_pdmc_std_chmaps[] = { 529 { .channels = 1, 530 .map = { SNDRV_CHMAP_MONO } }, 531 { .channels = 2, 532 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 533 { .channels = 3, 534 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 535 SNDRV_CHMAP_RL } }, 536 { .channels = 4, 537 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 538 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 539 { } 540 }; 541 542 static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream, 543 struct snd_pcm_hw_params *params, 544 struct snd_soc_dai *dai) 545 { 546 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 547 struct snd_soc_component *comp = dai->component; 548 unsigned long gclk_rate = 0; 549 unsigned long best_diff_rate = ~0UL; 550 unsigned int channels = params_channels(params); 551 unsigned int osr = 0, osr_start; 552 unsigned int fs = params_rate(params); 553 u32 mr_val = 0; 554 u32 cfgr_val = 0; 555 int i; 556 int ret; 557 558 dev_dbg(comp->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 559 __func__, params_rate(params), params_format(params), 560 params_width(params), params_channels(params)); 561 562 if (channels > dd->mic_no) { 563 dev_err(comp->dev, "more channels %u than microphones %d\n", 564 channels, dd->mic_no); 565 return -EINVAL; 566 } 567 568 dd->pdmcen = 0; 569 for (i = 0; i < channels; i++) { 570 dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i); 571 if (dd->channel_mic_map[i].ds_pos) 572 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 573 if (dd->channel_mic_map[i].clk_edge) 574 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 575 } 576 577 for (osr_start = dd->audio_filter_en ? 64 : 8; 578 osr_start <= 256 && best_diff_rate; osr_start *= 2) { 579 long round_rate; 580 unsigned long diff_rate; 581 582 round_rate = clk_round_rate(dd->gclk, 583 (unsigned long)fs * 16 * osr_start); 584 if (round_rate < 0) 585 continue; 586 diff_rate = abs((fs * 16 * osr_start) - round_rate); 587 if (diff_rate < best_diff_rate) { 588 best_diff_rate = diff_rate; 589 osr = osr_start; 590 gclk_rate = fs * 16 * osr; 591 } 592 } 593 if (!gclk_rate) { 594 dev_err(comp->dev, "invalid sampling rate: %u\n", fs); 595 return -EINVAL; 596 } 597 598 /* CLK is enabled by runtime PM. */ 599 clk_disable_unprepare(dd->gclk); 600 601 /* set the rate */ 602 ret = clk_set_rate(dd->gclk, gclk_rate); 603 clk_prepare_enable(dd->gclk); 604 if (ret) { 605 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n", 606 gclk_rate, ret); 607 return ret; 608 } 609 610 mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr); 611 612 mr_val |= FIELD_PREP(MCHP_PDMC_MR_SINCORDER_MASK, dd->sinc_order); 613 614 dd->addr.maxburst = mchp_pdmc_period_to_maxburst(snd_pcm_lib_period_bytes(substream)); 615 mr_val |= FIELD_PREP(MCHP_PDMC_MR_CHUNK_MASK, dd->addr.maxburst); 616 dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst); 617 618 snd_soc_component_update_bits(comp, MCHP_PDMC_MR, 619 MCHP_PDMC_MR_OSR_MASK | 620 MCHP_PDMC_MR_SINCORDER_MASK | 621 MCHP_PDMC_MR_SINC_OSR_MASK | 622 MCHP_PDMC_MR_CHUNK_MASK, mr_val); 623 624 snd_soc_component_write(comp, MCHP_PDMC_CFGR, cfgr_val); 625 626 return 0; 627 } 628 629 static void mchp_pdmc_noise_filter_workaround(struct mchp_pdmc *dd) 630 { 631 u32 tmp, steps = 16; 632 633 /* 634 * PDMC doesn't wait for microphones' startup time thus the acquisition 635 * may start before the microphones are ready leading to poc noises at 636 * the beginning of capture. To avoid this, we need to wait 50ms (in 637 * normal startup procedure) or 150 ms (worst case after resume from sleep 638 * states) after microphones are enabled and then clear the FIFOs (by 639 * reading the RHR 16 times) and possible interrupts before continuing. 640 * Also, for this to work the DMA needs to be started after interrupts 641 * are enabled. 642 */ 643 usleep_range(dd->startup_delay_us, dd->startup_delay_us + 5); 644 645 while (steps--) 646 regmap_read(dd->regmap, MCHP_PDMC_RHR, &tmp); 647 648 /* Clear interrupts. */ 649 regmap_read(dd->regmap, MCHP_PDMC_ISR, &tmp); 650 } 651 652 static int mchp_pdmc_trigger(struct snd_pcm_substream *substream, 653 int cmd, struct snd_soc_dai *dai) 654 { 655 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 656 struct snd_soc_component *cpu = dai->component; 657 #ifdef DEBUG 658 u32 val; 659 #endif 660 661 switch (cmd) { 662 case SNDRV_PCM_TRIGGER_RESUME: 663 case SNDRV_PCM_TRIGGER_START: 664 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 665 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, 666 MCHP_PDMC_MR_PDMCEN_MASK, 667 dd->pdmcen); 668 669 mchp_pdmc_noise_filter_workaround(dd); 670 671 /* Enable interrupts. */ 672 regmap_write(dd->regmap, MCHP_PDMC_IER, dd->suspend_irq | 673 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); 674 dd->suspend_irq = 0; 675 break; 676 case SNDRV_PCM_TRIGGER_SUSPEND: 677 regmap_read(dd->regmap, MCHP_PDMC_IMR, &dd->suspend_irq); 678 fallthrough; 679 case SNDRV_PCM_TRIGGER_STOP: 680 /* Disable overrun and underrun error interrupts */ 681 regmap_write(dd->regmap, MCHP_PDMC_IDR, dd->suspend_irq | 682 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); 683 fallthrough; 684 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 685 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, 686 MCHP_PDMC_MR_PDMCEN_MASK, 0); 687 break; 688 default: 689 return -EINVAL; 690 } 691 692 #ifdef DEBUG 693 regmap_read(dd->regmap, MCHP_PDMC_MR, &val); 694 dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val); 695 regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val); 696 dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val); 697 regmap_read(dd->regmap, MCHP_PDMC_IMR, &val); 698 dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val); 699 #endif 700 701 return 0; 702 } 703 704 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd) 705 { 706 struct mchp_pdmc_chmap *info; 707 struct snd_kcontrol_new knew = { 708 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 709 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 710 SNDRV_CTL_ELEM_ACCESS_TLV_READ | 711 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, 712 .info = mchp_pdmc_chmap_ctl_info, 713 .get = mchp_pdmc_chmap_ctl_get, 714 .put = mchp_pdmc_chmap_ctl_put, 715 .tlv.c = mchp_pdmc_chmap_ctl_tlv, 716 }; 717 int err; 718 719 if (WARN_ON(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl)) 720 return -EBUSY; 721 info = kzalloc(sizeof(*info), GFP_KERNEL); 722 if (!info) 723 return -ENOMEM; 724 info->pcm = pcm; 725 info->dd = dd; 726 info->chmap = mchp_pdmc_std_chmaps; 727 knew.name = "Capture Channel Map"; 728 knew.device = pcm->device; 729 knew.count = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_count; 730 info->kctl = snd_ctl_new1(&knew, info); 731 if (!info->kctl) { 732 kfree(info); 733 return -ENOMEM; 734 } 735 info->kctl->private_free = mchp_pdmc_chmap_ctl_private_free; 736 err = snd_ctl_add(pcm->card, info->kctl); 737 if (err < 0) 738 return err; 739 pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = info->kctl; 740 return 0; 741 } 742 743 static int mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime *rtd, 744 struct snd_soc_dai *dai) 745 { 746 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 747 int ret; 748 749 ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd); 750 if (ret < 0) 751 dev_err(dd->dev, "failed to add channel map controls: %d\n", ret); 752 753 return ret; 754 } 755 756 static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = { 757 .probe = mchp_pdmc_dai_probe, 758 .set_fmt = mchp_pdmc_set_fmt, 759 .startup = mchp_pdmc_startup, 760 .hw_params = mchp_pdmc_hw_params, 761 .trigger = mchp_pdmc_trigger, 762 .pcm_new = &mchp_pdmc_pcm_new, 763 }; 764 765 static struct snd_soc_dai_driver mchp_pdmc_dai = { 766 .capture = { 767 .stream_name = "Capture", 768 .channels_min = 1, 769 .channels_max = 4, 770 .rate_min = 8000, 771 .rate_max = 192000, 772 .rates = SNDRV_PCM_RATE_KNOT, 773 .formats = SNDRV_PCM_FMTBIT_S24_LE, 774 }, 775 .ops = &mchp_pdmc_dai_ops, 776 }; 777 778 /* PDMC interrupt handler */ 779 static irqreturn_t mchp_pdmc_interrupt(int irq, void *dev_id) 780 { 781 struct mchp_pdmc *dd = dev_id; 782 u32 isr, msr, pending; 783 irqreturn_t ret = IRQ_NONE; 784 785 regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr); 786 regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr); 787 788 pending = isr & msr; 789 dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n", 790 MCHP_PDMC_ISR, isr, MCHP_PDMC_IMR, msr, pending); 791 if (!pending) 792 return IRQ_NONE; 793 794 if (pending & MCHP_PDMC_IR_RXUDR) { 795 dev_warn(dd->dev, "underrun detected\n"); 796 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR); 797 ret = IRQ_HANDLED; 798 } 799 if (pending & MCHP_PDMC_IR_RXOVR) { 800 dev_warn(dd->dev, "overrun detected\n"); 801 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR); 802 ret = IRQ_HANDLED; 803 } 804 805 return ret; 806 } 807 808 /* regmap configuration */ 809 static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg) 810 { 811 switch (reg) { 812 case MCHP_PDMC_MR: 813 case MCHP_PDMC_CFGR: 814 case MCHP_PDMC_IMR: 815 case MCHP_PDMC_ISR: 816 case MCHP_PDMC_RHR: 817 case MCHP_PDMC_VER: 818 return true; 819 default: 820 return false; 821 } 822 } 823 824 static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg) 825 { 826 switch (reg) { 827 case MCHP_PDMC_CR: 828 case MCHP_PDMC_MR: 829 case MCHP_PDMC_CFGR: 830 case MCHP_PDMC_IER: 831 case MCHP_PDMC_IDR: 832 return true; 833 default: 834 return false; 835 } 836 } 837 838 static bool mchp_pdmc_volatile_reg(struct device *dev, unsigned int reg) 839 { 840 switch (reg) { 841 case MCHP_PDMC_ISR: 842 case MCHP_PDMC_RHR: 843 return true; 844 default: 845 return false; 846 } 847 } 848 849 static bool mchp_pdmc_precious_reg(struct device *dev, unsigned int reg) 850 { 851 switch (reg) { 852 case MCHP_PDMC_RHR: 853 case MCHP_PDMC_ISR: 854 return true; 855 default: 856 return false; 857 } 858 } 859 860 static const struct regmap_config mchp_pdmc_regmap_config = { 861 .reg_bits = 32, 862 .reg_stride = 4, 863 .val_bits = 32, 864 .max_register = MCHP_PDMC_VER, 865 .readable_reg = mchp_pdmc_readable_reg, 866 .writeable_reg = mchp_pdmc_writeable_reg, 867 .precious_reg = mchp_pdmc_precious_reg, 868 .volatile_reg = mchp_pdmc_volatile_reg, 869 .cache_type = REGCACHE_FLAT, 870 }; 871 872 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd) 873 { 874 struct device_node *np = dd->dev->of_node; 875 bool mic_ch[MCHP_PDMC_DS_NO][MCHP_PDMC_EDGE_NO] = {0}; 876 int i; 877 int ret; 878 879 if (!np) { 880 dev_err(dd->dev, "device node not found\n"); 881 return -EINVAL; 882 } 883 884 dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos"); 885 if (dd->mic_no < 0) { 886 dev_err(dd->dev, "failed to get microchip,mic-pos: %d", 887 dd->mic_no); 888 return dd->mic_no; 889 } 890 if (!dd->mic_no || dd->mic_no % 2 || 891 dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) { 892 dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d", 893 dd->mic_no); 894 return -EINVAL; 895 } 896 897 dd->mic_no /= 2; 898 899 dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no); 900 901 /* 902 * by default, we consider the order of microphones in 903 * microchip,mic-pos to be the same with the channel mapping; 904 * 1st microphone channel 0, 2nd microphone channel 1, etc. 905 */ 906 for (i = 0; i < dd->mic_no; i++) { 907 int ds; 908 int edge; 909 910 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2, 911 &ds); 912 if (ret) { 913 dev_err(dd->dev, 914 "failed to get value no %d value from microchip,mic-pos: %d", 915 i * 2, ret); 916 return ret; 917 } 918 if (ds >= MCHP_PDMC_DS_NO) { 919 dev_err(dd->dev, 920 "invalid DS index in microchip,mic-pos array: %d", 921 ds); 922 return -EINVAL; 923 } 924 925 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2 + 1, 926 &edge); 927 if (ret) { 928 dev_err(dd->dev, 929 "failed to get value no %d value from microchip,mic-pos: %d", 930 i * 2 + 1, ret); 931 return ret; 932 } 933 934 if (edge != MCHP_PDMC_CLK_POSITIVE && 935 edge != MCHP_PDMC_CLK_NEGATIVE) { 936 dev_err(dd->dev, 937 "invalid edge in microchip,mic-pos array: %d", edge); 938 return -EINVAL; 939 } 940 if (mic_ch[ds][edge]) { 941 dev_err(dd->dev, 942 "duplicated mic (DS %d, edge %d) in microchip,mic-pos array", 943 ds, edge); 944 return -EINVAL; 945 } 946 mic_ch[ds][edge] = true; 947 dd->channel_mic_map[i].ds_pos = ds; 948 dd->channel_mic_map[i].clk_edge = edge; 949 } 950 951 dd->startup_delay_us = 150000; 952 of_property_read_u32(np, "microchip,startup-delay-us", &dd->startup_delay_us); 953 954 return 0; 955 } 956 957 /* used to clean the channel index found on RHR's MSB */ 958 static int mchp_pdmc_process(struct snd_pcm_substream *substream, 959 int channel, unsigned long hwoff, 960 unsigned long bytes) 961 { 962 struct snd_pcm_runtime *runtime = substream->runtime; 963 u8 *dma_ptr = runtime->dma_area + hwoff + 964 channel * (runtime->dma_bytes / runtime->channels); 965 u8 *dma_ptr_end = dma_ptr + bytes; 966 unsigned int sample_size = samples_to_bytes(runtime, 1); 967 968 for (; dma_ptr < dma_ptr_end; dma_ptr += sample_size) 969 *dma_ptr = 0; 970 971 return 0; 972 } 973 974 static struct snd_dmaengine_pcm_config mchp_pdmc_config = { 975 .process = mchp_pdmc_process, 976 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 977 }; 978 979 static int mchp_pdmc_runtime_suspend(struct device *dev) 980 { 981 struct mchp_pdmc *dd = dev_get_drvdata(dev); 982 983 regcache_cache_only(dd->regmap, true); 984 985 clk_disable_unprepare(dd->gclk); 986 clk_disable_unprepare(dd->pclk); 987 988 return 0; 989 } 990 991 static int mchp_pdmc_runtime_resume(struct device *dev) 992 { 993 struct mchp_pdmc *dd = dev_get_drvdata(dev); 994 int ret; 995 996 ret = clk_prepare_enable(dd->pclk); 997 if (ret) { 998 dev_err(dd->dev, 999 "failed to enable the peripheral clock: %d\n", ret); 1000 return ret; 1001 } 1002 ret = clk_prepare_enable(dd->gclk); 1003 if (ret) { 1004 dev_err(dd->dev, 1005 "failed to enable generic clock: %d\n", ret); 1006 goto disable_pclk; 1007 } 1008 1009 regcache_cache_only(dd->regmap, false); 1010 regcache_mark_dirty(dd->regmap); 1011 ret = regcache_sync(dd->regmap); 1012 if (ret) { 1013 regcache_cache_only(dd->regmap, true); 1014 clk_disable_unprepare(dd->gclk); 1015 disable_pclk: 1016 clk_disable_unprepare(dd->pclk); 1017 } 1018 1019 return ret; 1020 } 1021 1022 static int mchp_pdmc_probe(struct platform_device *pdev) 1023 { 1024 struct device *dev = &pdev->dev; 1025 struct mchp_pdmc *dd; 1026 struct resource *res; 1027 void __iomem *io_base; 1028 u32 version; 1029 int irq; 1030 int ret; 1031 1032 dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL); 1033 if (!dd) 1034 return -ENOMEM; 1035 1036 dd->dev = &pdev->dev; 1037 ret = mchp_pdmc_dt_init(dd); 1038 if (ret < 0) 1039 return ret; 1040 1041 irq = platform_get_irq(pdev, 0); 1042 if (irq < 0) 1043 return irq; 1044 1045 dd->pclk = devm_clk_get(dev, "pclk"); 1046 if (IS_ERR(dd->pclk)) { 1047 ret = PTR_ERR(dd->pclk); 1048 dev_err(dev, "failed to get peripheral clock: %d\n", ret); 1049 return ret; 1050 } 1051 1052 dd->gclk = devm_clk_get(dev, "gclk"); 1053 if (IS_ERR(dd->gclk)) { 1054 ret = PTR_ERR(dd->gclk); 1055 dev_err(dev, "failed to get GCK: %d\n", ret); 1056 return ret; 1057 } 1058 1059 io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1060 if (IS_ERR(io_base)) { 1061 ret = PTR_ERR(io_base); 1062 dev_err(dev, "failed to remap register memory: %d\n", ret); 1063 return ret; 1064 } 1065 1066 dd->regmap = devm_regmap_init_mmio(dev, io_base, 1067 &mchp_pdmc_regmap_config); 1068 if (IS_ERR(dd->regmap)) { 1069 ret = PTR_ERR(dd->regmap); 1070 dev_err(dev, "failed to init register map: %d\n", ret); 1071 return ret; 1072 } 1073 1074 ret = devm_request_irq(dev, irq, mchp_pdmc_interrupt, 0, 1075 dev_name(&pdev->dev), dd); 1076 if (ret < 0) { 1077 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 1078 irq, ret); 1079 return ret; 1080 } 1081 1082 /* by default audio filter is enabled and the SINC Filter order 1083 * will be set to the recommended value, 3 1084 */ 1085 dd->audio_filter_en = true; 1086 dd->sinc_order = 3; 1087 1088 dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR; 1089 platform_set_drvdata(pdev, dd); 1090 1091 pm_runtime_enable(dd->dev); 1092 if (!pm_runtime_enabled(dd->dev)) { 1093 ret = mchp_pdmc_runtime_resume(dd->dev); 1094 if (ret) 1095 return ret; 1096 } 1097 1098 /* register platform */ 1099 ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0); 1100 if (ret) { 1101 dev_err(dev, "could not register platform: %d\n", ret); 1102 goto pm_runtime_suspend; 1103 } 1104 1105 ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component, 1106 &mchp_pdmc_dai, 1); 1107 if (ret) { 1108 dev_err(dev, "could not register CPU DAI: %d\n", ret); 1109 goto pm_runtime_suspend; 1110 } 1111 1112 /* print IP version */ 1113 regmap_read(dd->regmap, MCHP_PDMC_VER, &version); 1114 dev_info(dd->dev, "hw version: %#lx\n", 1115 version & MCHP_PDMC_VER_VERSION); 1116 1117 return 0; 1118 1119 pm_runtime_suspend: 1120 if (!pm_runtime_status_suspended(dd->dev)) 1121 mchp_pdmc_runtime_suspend(dd->dev); 1122 pm_runtime_disable(dd->dev); 1123 1124 return ret; 1125 } 1126 1127 static void mchp_pdmc_remove(struct platform_device *pdev) 1128 { 1129 struct mchp_pdmc *dd = platform_get_drvdata(pdev); 1130 1131 if (!pm_runtime_status_suspended(dd->dev)) 1132 mchp_pdmc_runtime_suspend(dd->dev); 1133 1134 pm_runtime_disable(dd->dev); 1135 } 1136 1137 static const struct of_device_id mchp_pdmc_of_match[] = { 1138 { 1139 .compatible = "microchip,sama7g5-pdmc", 1140 }, { 1141 /* sentinel */ 1142 } 1143 }; 1144 MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match); 1145 1146 static const struct dev_pm_ops mchp_pdmc_pm_ops = { 1147 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1148 RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume, 1149 NULL) 1150 }; 1151 1152 static struct platform_driver mchp_pdmc_driver = { 1153 .driver = { 1154 .name = "mchp-pdmc", 1155 .of_match_table = of_match_ptr(mchp_pdmc_of_match), 1156 .pm = pm_ptr(&mchp_pdmc_pm_ops), 1157 }, 1158 .probe = mchp_pdmc_probe, 1159 .remove_new = mchp_pdmc_remove, 1160 }; 1161 module_platform_driver(mchp_pdmc_driver); 1162 1163 MODULE_DESCRIPTION("Microchip PDMC driver under ALSA SoC architecture"); 1164 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 1165 MODULE_LICENSE("GPL v2"); 1166