1 /* 2 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver 3 * 4 * Copyright (C) 2005 SAN People 5 * Copyright (C) 2008 Atmel 6 * 7 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com> 8 * ATMEL CORP. 9 * 10 * Based on at91-ssc.c by 11 * Frank Mandarino <fmandarino@endrelia.com> 12 * Based on pxa2xx Platform drivers by 13 * Liam Girdwood <lrg@slimlogic.co.uk> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30 #include <linux/init.h> 31 #include <linux/module.h> 32 #include <linux/interrupt.h> 33 #include <linux/device.h> 34 #include <linux/delay.h> 35 #include <linux/clk.h> 36 #include <linux/atmel_pdc.h> 37 38 #include <linux/atmel-ssc.h> 39 #include <sound/core.h> 40 #include <sound/pcm.h> 41 #include <sound/pcm_params.h> 42 #include <sound/initval.h> 43 #include <sound/soc.h> 44 45 #include "atmel-pcm.h" 46 #include "atmel_ssc_dai.h" 47 48 49 #define NUM_SSC_DEVICES 3 50 51 /* 52 * SSC PDC registers required by the PCM DMA engine. 53 */ 54 static struct atmel_pdc_regs pdc_tx_reg = { 55 .xpr = ATMEL_PDC_TPR, 56 .xcr = ATMEL_PDC_TCR, 57 .xnpr = ATMEL_PDC_TNPR, 58 .xncr = ATMEL_PDC_TNCR, 59 }; 60 61 static struct atmel_pdc_regs pdc_rx_reg = { 62 .xpr = ATMEL_PDC_RPR, 63 .xcr = ATMEL_PDC_RCR, 64 .xnpr = ATMEL_PDC_RNPR, 65 .xncr = ATMEL_PDC_RNCR, 66 }; 67 68 /* 69 * SSC & PDC status bits for transmit and receive. 70 */ 71 static struct atmel_ssc_mask ssc_tx_mask = { 72 .ssc_enable = SSC_BIT(CR_TXEN), 73 .ssc_disable = SSC_BIT(CR_TXDIS), 74 .ssc_endx = SSC_BIT(SR_ENDTX), 75 .ssc_endbuf = SSC_BIT(SR_TXBUFE), 76 .ssc_error = SSC_BIT(SR_OVRUN), 77 .pdc_enable = ATMEL_PDC_TXTEN, 78 .pdc_disable = ATMEL_PDC_TXTDIS, 79 }; 80 81 static struct atmel_ssc_mask ssc_rx_mask = { 82 .ssc_enable = SSC_BIT(CR_RXEN), 83 .ssc_disable = SSC_BIT(CR_RXDIS), 84 .ssc_endx = SSC_BIT(SR_ENDRX), 85 .ssc_endbuf = SSC_BIT(SR_RXBUFF), 86 .ssc_error = SSC_BIT(SR_OVRUN), 87 .pdc_enable = ATMEL_PDC_RXTEN, 88 .pdc_disable = ATMEL_PDC_RXTDIS, 89 }; 90 91 92 /* 93 * DMA parameters. 94 */ 95 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = { 96 {{ 97 .name = "SSC0 PCM out", 98 .pdc = &pdc_tx_reg, 99 .mask = &ssc_tx_mask, 100 }, 101 { 102 .name = "SSC0 PCM in", 103 .pdc = &pdc_rx_reg, 104 .mask = &ssc_rx_mask, 105 } }, 106 {{ 107 .name = "SSC1 PCM out", 108 .pdc = &pdc_tx_reg, 109 .mask = &ssc_tx_mask, 110 }, 111 { 112 .name = "SSC1 PCM in", 113 .pdc = &pdc_rx_reg, 114 .mask = &ssc_rx_mask, 115 } }, 116 {{ 117 .name = "SSC2 PCM out", 118 .pdc = &pdc_tx_reg, 119 .mask = &ssc_tx_mask, 120 }, 121 { 122 .name = "SSC2 PCM in", 123 .pdc = &pdc_rx_reg, 124 .mask = &ssc_rx_mask, 125 } }, 126 }; 127 128 129 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = { 130 { 131 .name = "ssc0", 132 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock), 133 .dir_mask = SSC_DIR_MASK_UNUSED, 134 .initialized = 0, 135 }, 136 { 137 .name = "ssc1", 138 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock), 139 .dir_mask = SSC_DIR_MASK_UNUSED, 140 .initialized = 0, 141 }, 142 { 143 .name = "ssc2", 144 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock), 145 .dir_mask = SSC_DIR_MASK_UNUSED, 146 .initialized = 0, 147 }, 148 }; 149 150 151 /* 152 * SSC interrupt handler. Passes PDC interrupts to the DMA 153 * interrupt handler in the PCM driver. 154 */ 155 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id) 156 { 157 struct atmel_ssc_info *ssc_p = dev_id; 158 struct atmel_pcm_dma_params *dma_params; 159 u32 ssc_sr; 160 u32 ssc_substream_mask; 161 int i; 162 163 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) 164 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); 165 166 /* 167 * Loop through the substreams attached to this SSC. If 168 * a DMA-related interrupt occurred on that substream, call 169 * the DMA interrupt handler function, if one has been 170 * registered in the dma_params structure by the PCM driver. 171 */ 172 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) { 173 dma_params = ssc_p->dma_params[i]; 174 175 if ((dma_params != NULL) && 176 (dma_params->dma_intr_handler != NULL)) { 177 ssc_substream_mask = (dma_params->mask->ssc_endx | 178 dma_params->mask->ssc_endbuf); 179 if (ssc_sr & ssc_substream_mask) { 180 dma_params->dma_intr_handler(ssc_sr, 181 dma_params-> 182 substream); 183 } 184 } 185 } 186 187 return IRQ_HANDLED; 188 } 189 190 /* 191 * When the bit clock is input, limit the maximum rate according to the 192 * Serial Clock Ratio Considerations section from the SSC documentation: 193 * 194 * The Transmitter and the Receiver can be programmed to operate 195 * with the clock signals provided on either the TK or RK pins. 196 * This allows the SSC to support many slave-mode data transfers. 197 * In this case, the maximum clock speed allowed on the RK pin is: 198 * - Peripheral clock divided by 2 if Receiver Frame Synchro is input 199 * - Peripheral clock divided by 3 if Receiver Frame Synchro is output 200 * In addition, the maximum clock speed allowed on the TK pin is: 201 * - Peripheral clock divided by 6 if Transmit Frame Synchro is input 202 * - Peripheral clock divided by 2 if Transmit Frame Synchro is output 203 * 204 * When the bit clock is output, limit the rate according to the 205 * SSC divider restrictions. 206 */ 207 static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params, 208 struct snd_pcm_hw_rule *rule) 209 { 210 struct atmel_ssc_info *ssc_p = rule->private; 211 struct ssc_device *ssc = ssc_p->ssc; 212 struct snd_interval *i = hw_param_interval(params, rule->var); 213 struct snd_interval t; 214 struct snd_ratnum r = { 215 .den_min = 1, 216 .den_max = 4095, 217 .den_step = 1, 218 }; 219 unsigned int num = 0, den = 0; 220 int frame_size; 221 int mck_div = 2; 222 int ret; 223 224 frame_size = snd_soc_params_to_frame_size(params); 225 if (frame_size < 0) 226 return frame_size; 227 228 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) { 229 case SND_SOC_DAIFMT_CBM_CFS: 230 if ((ssc_p->dir_mask & SSC_DIR_MASK_CAPTURE) 231 && ssc->clk_from_rk_pin) 232 /* Receiver Frame Synchro (i.e. capture) 233 * is output (format is _CFS) and the RK pin 234 * is used for input (format is _CBM_). 235 */ 236 mck_div = 3; 237 break; 238 239 case SND_SOC_DAIFMT_CBM_CFM: 240 if ((ssc_p->dir_mask & SSC_DIR_MASK_PLAYBACK) 241 && !ssc->clk_from_rk_pin) 242 /* Transmit Frame Synchro (i.e. playback) 243 * is input (format is _CFM) and the TK pin 244 * is used for input (format _CBM_ but not 245 * using the RK pin). 246 */ 247 mck_div = 6; 248 break; 249 } 250 251 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) { 252 case SND_SOC_DAIFMT_CBS_CFS: 253 r.num = ssc_p->mck_rate / mck_div / frame_size; 254 255 ret = snd_interval_ratnum(i, 1, &r, &num, &den); 256 if (ret >= 0 && den && rule->var == SNDRV_PCM_HW_PARAM_RATE) { 257 params->rate_num = num; 258 params->rate_den = den; 259 } 260 break; 261 262 case SND_SOC_DAIFMT_CBM_CFS: 263 case SND_SOC_DAIFMT_CBM_CFM: 264 t.min = 8000; 265 t.max = ssc_p->mck_rate / mck_div / frame_size; 266 t.openmin = t.openmax = 0; 267 t.integer = 0; 268 ret = snd_interval_refine(i, &t); 269 break; 270 271 default: 272 ret = -EINVAL; 273 break; 274 } 275 276 return ret; 277 } 278 279 /*-------------------------------------------------------------------------*\ 280 * DAI functions 281 \*-------------------------------------------------------------------------*/ 282 /* 283 * Startup. Only that one substream allowed in each direction. 284 */ 285 static int atmel_ssc_startup(struct snd_pcm_substream *substream, 286 struct snd_soc_dai *dai) 287 { 288 struct platform_device *pdev = to_platform_device(dai->dev); 289 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 290 struct atmel_pcm_dma_params *dma_params; 291 int dir, dir_mask; 292 int ret; 293 294 pr_debug("atmel_ssc_startup: SSC_SR=0x%x\n", 295 ssc_readl(ssc_p->ssc->regs, SR)); 296 297 /* Enable PMC peripheral clock for this SSC */ 298 pr_debug("atmel_ssc_dai: Starting clock\n"); 299 clk_enable(ssc_p->ssc->clk); 300 ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk); 301 302 /* Reset the SSC unless initialized to keep it in a clean state */ 303 if (!ssc_p->initialized) 304 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); 305 306 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 307 dir = 0; 308 dir_mask = SSC_DIR_MASK_PLAYBACK; 309 } else { 310 dir = 1; 311 dir_mask = SSC_DIR_MASK_CAPTURE; 312 } 313 314 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 315 SNDRV_PCM_HW_PARAM_RATE, 316 atmel_ssc_hw_rule_rate, 317 ssc_p, 318 SNDRV_PCM_HW_PARAM_FRAME_BITS, 319 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 320 if (ret < 0) { 321 dev_err(dai->dev, "Failed to specify rate rule: %d\n", ret); 322 return ret; 323 } 324 325 dma_params = &ssc_dma_params[pdev->id][dir]; 326 dma_params->ssc = ssc_p->ssc; 327 dma_params->substream = substream; 328 329 ssc_p->dma_params[dir] = dma_params; 330 331 snd_soc_dai_set_dma_data(dai, substream, dma_params); 332 333 spin_lock_irq(&ssc_p->lock); 334 if (ssc_p->dir_mask & dir_mask) { 335 spin_unlock_irq(&ssc_p->lock); 336 return -EBUSY; 337 } 338 ssc_p->dir_mask |= dir_mask; 339 spin_unlock_irq(&ssc_p->lock); 340 341 return 0; 342 } 343 344 /* 345 * Shutdown. Clear DMA parameters and shutdown the SSC if there 346 * are no other substreams open. 347 */ 348 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream, 349 struct snd_soc_dai *dai) 350 { 351 struct platform_device *pdev = to_platform_device(dai->dev); 352 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 353 struct atmel_pcm_dma_params *dma_params; 354 int dir, dir_mask; 355 356 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 357 dir = 0; 358 else 359 dir = 1; 360 361 dma_params = ssc_p->dma_params[dir]; 362 363 if (dma_params != NULL) { 364 dma_params->ssc = NULL; 365 dma_params->substream = NULL; 366 ssc_p->dma_params[dir] = NULL; 367 } 368 369 dir_mask = 1 << dir; 370 371 spin_lock_irq(&ssc_p->lock); 372 ssc_p->dir_mask &= ~dir_mask; 373 if (!ssc_p->dir_mask) { 374 if (ssc_p->initialized) { 375 free_irq(ssc_p->ssc->irq, ssc_p); 376 ssc_p->initialized = 0; 377 } 378 379 /* Reset the SSC */ 380 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); 381 /* Clear the SSC dividers */ 382 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0; 383 } 384 spin_unlock_irq(&ssc_p->lock); 385 386 /* Shutdown the SSC clock. */ 387 pr_debug("atmel_ssc_dai: Stopping clock\n"); 388 clk_disable(ssc_p->ssc->clk); 389 } 390 391 392 /* 393 * Record the DAI format for use in hw_params(). 394 */ 395 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai, 396 unsigned int fmt) 397 { 398 struct platform_device *pdev = to_platform_device(cpu_dai->dev); 399 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 400 401 ssc_p->daifmt = fmt; 402 return 0; 403 } 404 405 /* 406 * Record SSC clock dividers for use in hw_params(). 407 */ 408 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, 409 int div_id, int div) 410 { 411 struct platform_device *pdev = to_platform_device(cpu_dai->dev); 412 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 413 414 switch (div_id) { 415 case ATMEL_SSC_CMR_DIV: 416 /* 417 * The same master clock divider is used for both 418 * transmit and receive, so if a value has already 419 * been set, it must match this value. 420 */ 421 if (ssc_p->dir_mask != 422 (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE)) 423 ssc_p->cmr_div = div; 424 else if (ssc_p->cmr_div == 0) 425 ssc_p->cmr_div = div; 426 else 427 if (div != ssc_p->cmr_div) 428 return -EBUSY; 429 break; 430 431 case ATMEL_SSC_TCMR_PERIOD: 432 ssc_p->tcmr_period = div; 433 break; 434 435 case ATMEL_SSC_RCMR_PERIOD: 436 ssc_p->rcmr_period = div; 437 break; 438 439 default: 440 return -EINVAL; 441 } 442 443 return 0; 444 } 445 446 /* 447 * Configure the SSC. 448 */ 449 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream, 450 struct snd_pcm_hw_params *params, 451 struct snd_soc_dai *dai) 452 { 453 struct platform_device *pdev = to_platform_device(dai->dev); 454 int id = pdev->id; 455 struct atmel_ssc_info *ssc_p = &ssc_info[id]; 456 struct ssc_device *ssc = ssc_p->ssc; 457 struct atmel_pcm_dma_params *dma_params; 458 int dir, channels, bits; 459 u32 tfmr, rfmr, tcmr, rcmr; 460 int ret; 461 int fslen, fslen_ext; 462 463 /* 464 * Currently, there is only one set of dma params for 465 * each direction. If more are added, this code will 466 * have to be changed to select the proper set. 467 */ 468 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 469 dir = 0; 470 else 471 dir = 1; 472 473 dma_params = ssc_p->dma_params[dir]; 474 475 channels = params_channels(params); 476 477 /* 478 * Determine sample size in bits and the PDC increment. 479 */ 480 switch (params_format(params)) { 481 case SNDRV_PCM_FORMAT_S8: 482 bits = 8; 483 dma_params->pdc_xfer_size = 1; 484 break; 485 case SNDRV_PCM_FORMAT_S16_LE: 486 bits = 16; 487 dma_params->pdc_xfer_size = 2; 488 break; 489 case SNDRV_PCM_FORMAT_S24_LE: 490 bits = 24; 491 dma_params->pdc_xfer_size = 4; 492 break; 493 case SNDRV_PCM_FORMAT_S32_LE: 494 bits = 32; 495 dma_params->pdc_xfer_size = 4; 496 break; 497 default: 498 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format"); 499 return -EINVAL; 500 } 501 502 /* 503 * Compute SSC register settings. 504 */ 505 switch (ssc_p->daifmt 506 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) { 507 508 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS: 509 /* 510 * I2S format, SSC provides BCLK and LRC clocks. 511 * 512 * The SSC transmit and receive clocks are generated 513 * from the MCK divider, and the BCLK signal 514 * is output on the SSC TK line. 515 */ 516 517 if (bits > 16 && !ssc->pdata->has_fslen_ext) { 518 dev_err(dai->dev, 519 "sample size %d is too large for SSC device\n", 520 bits); 521 return -EINVAL; 522 } 523 524 fslen_ext = (bits - 1) / 16; 525 fslen = (bits - 1) % 16; 526 527 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) 528 | SSC_BF(RCMR_STTDLY, START_DELAY) 529 | SSC_BF(RCMR_START, SSC_START_FALLING_RF) 530 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 531 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 532 | SSC_BF(RCMR_CKS, SSC_CKS_DIV); 533 534 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext) 535 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 536 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) 537 | SSC_BF(RFMR_FSLEN, fslen) 538 | SSC_BF(RFMR_DATNB, (channels - 1)) 539 | SSC_BIT(RFMR_MSBF) 540 | SSC_BF(RFMR_LOOP, 0) 541 | SSC_BF(RFMR_DATLEN, (bits - 1)); 542 543 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) 544 | SSC_BF(TCMR_STTDLY, START_DELAY) 545 | SSC_BF(TCMR_START, SSC_START_FALLING_RF) 546 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) 547 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) 548 | SSC_BF(TCMR_CKS, SSC_CKS_DIV); 549 550 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext) 551 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 552 | SSC_BF(TFMR_FSDEN, 0) 553 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) 554 | SSC_BF(TFMR_FSLEN, fslen) 555 | SSC_BF(TFMR_DATNB, (channels - 1)) 556 | SSC_BIT(TFMR_MSBF) 557 | SSC_BF(TFMR_DATDEF, 0) 558 | SSC_BF(TFMR_DATLEN, (bits - 1)); 559 break; 560 561 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM: 562 /* I2S format, CODEC supplies BCLK and LRC clocks. */ 563 rcmr = SSC_BF(RCMR_PERIOD, 0) 564 | SSC_BF(RCMR_STTDLY, START_DELAY) 565 | SSC_BF(RCMR_START, SSC_START_FALLING_RF) 566 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 567 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 568 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? 569 SSC_CKS_PIN : SSC_CKS_CLOCK); 570 571 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 572 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) 573 | SSC_BF(RFMR_FSLEN, 0) 574 | SSC_BF(RFMR_DATNB, (channels - 1)) 575 | SSC_BIT(RFMR_MSBF) 576 | SSC_BF(RFMR_LOOP, 0) 577 | SSC_BF(RFMR_DATLEN, (bits - 1)); 578 579 tcmr = SSC_BF(TCMR_PERIOD, 0) 580 | SSC_BF(TCMR_STTDLY, START_DELAY) 581 | SSC_BF(TCMR_START, SSC_START_FALLING_RF) 582 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) 583 | SSC_BF(TCMR_CKO, SSC_CKO_NONE) 584 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ? 585 SSC_CKS_CLOCK : SSC_CKS_PIN); 586 587 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 588 | SSC_BF(TFMR_FSDEN, 0) 589 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) 590 | SSC_BF(TFMR_FSLEN, 0) 591 | SSC_BF(TFMR_DATNB, (channels - 1)) 592 | SSC_BIT(TFMR_MSBF) 593 | SSC_BF(TFMR_DATDEF, 0) 594 | SSC_BF(TFMR_DATLEN, (bits - 1)); 595 break; 596 597 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS: 598 /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */ 599 if (bits > 16 && !ssc->pdata->has_fslen_ext) { 600 dev_err(dai->dev, 601 "sample size %d is too large for SSC device\n", 602 bits); 603 return -EINVAL; 604 } 605 606 fslen_ext = (bits - 1) / 16; 607 fslen = (bits - 1) % 16; 608 609 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) 610 | SSC_BF(RCMR_STTDLY, START_DELAY) 611 | SSC_BF(RCMR_START, SSC_START_FALLING_RF) 612 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 613 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 614 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? 615 SSC_CKS_PIN : SSC_CKS_CLOCK); 616 617 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext) 618 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 619 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) 620 | SSC_BF(RFMR_FSLEN, fslen) 621 | SSC_BF(RFMR_DATNB, (channels - 1)) 622 | SSC_BIT(RFMR_MSBF) 623 | SSC_BF(RFMR_LOOP, 0) 624 | SSC_BF(RFMR_DATLEN, (bits - 1)); 625 626 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) 627 | SSC_BF(TCMR_STTDLY, START_DELAY) 628 | SSC_BF(TCMR_START, SSC_START_FALLING_RF) 629 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) 630 | SSC_BF(TCMR_CKO, SSC_CKO_NONE) 631 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ? 632 SSC_CKS_CLOCK : SSC_CKS_PIN); 633 634 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext) 635 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE) 636 | SSC_BF(TFMR_FSDEN, 0) 637 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) 638 | SSC_BF(TFMR_FSLEN, fslen) 639 | SSC_BF(TFMR_DATNB, (channels - 1)) 640 | SSC_BIT(TFMR_MSBF) 641 | SSC_BF(TFMR_DATDEF, 0) 642 | SSC_BF(TFMR_DATLEN, (bits - 1)); 643 break; 644 645 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS: 646 /* 647 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks. 648 * 649 * The SSC transmit and receive clocks are generated from the 650 * MCK divider, and the BCLK signal is output 651 * on the SSC TK line. 652 */ 653 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) 654 | SSC_BF(RCMR_STTDLY, 1) 655 | SSC_BF(RCMR_START, SSC_START_RISING_RF) 656 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 657 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 658 | SSC_BF(RCMR_CKS, SSC_CKS_DIV); 659 660 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 661 | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE) 662 | SSC_BF(RFMR_FSLEN, 0) 663 | SSC_BF(RFMR_DATNB, (channels - 1)) 664 | SSC_BIT(RFMR_MSBF) 665 | SSC_BF(RFMR_LOOP, 0) 666 | SSC_BF(RFMR_DATLEN, (bits - 1)); 667 668 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) 669 | SSC_BF(TCMR_STTDLY, 1) 670 | SSC_BF(TCMR_START, SSC_START_RISING_RF) 671 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) 672 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) 673 | SSC_BF(TCMR_CKS, SSC_CKS_DIV); 674 675 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 676 | SSC_BF(TFMR_FSDEN, 0) 677 | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE) 678 | SSC_BF(TFMR_FSLEN, 0) 679 | SSC_BF(TFMR_DATNB, (channels - 1)) 680 | SSC_BIT(TFMR_MSBF) 681 | SSC_BF(TFMR_DATDEF, 0) 682 | SSC_BF(TFMR_DATLEN, (bits - 1)); 683 break; 684 685 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM: 686 /* 687 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks. 688 * 689 * Data is transferred on first BCLK after LRC pulse rising 690 * edge.If stereo, the right channel data is contiguous with 691 * the left channel data. 692 */ 693 rcmr = SSC_BF(RCMR_PERIOD, 0) 694 | SSC_BF(RCMR_STTDLY, START_DELAY) 695 | SSC_BF(RCMR_START, SSC_START_RISING_RF) 696 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 697 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 698 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? 699 SSC_CKS_PIN : SSC_CKS_CLOCK); 700 701 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 702 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) 703 | SSC_BF(RFMR_FSLEN, 0) 704 | SSC_BF(RFMR_DATNB, (channels - 1)) 705 | SSC_BIT(RFMR_MSBF) 706 | SSC_BF(RFMR_LOOP, 0) 707 | SSC_BF(RFMR_DATLEN, (bits - 1)); 708 709 tcmr = SSC_BF(TCMR_PERIOD, 0) 710 | SSC_BF(TCMR_STTDLY, START_DELAY) 711 | SSC_BF(TCMR_START, SSC_START_RISING_RF) 712 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) 713 | SSC_BF(TCMR_CKO, SSC_CKO_NONE) 714 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? 715 SSC_CKS_CLOCK : SSC_CKS_PIN); 716 717 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 718 | SSC_BF(TFMR_FSDEN, 0) 719 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) 720 | SSC_BF(TFMR_FSLEN, 0) 721 | SSC_BF(TFMR_DATNB, (channels - 1)) 722 | SSC_BIT(TFMR_MSBF) 723 | SSC_BF(TFMR_DATDEF, 0) 724 | SSC_BF(TFMR_DATLEN, (bits - 1)); 725 break; 726 727 default: 728 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n", 729 ssc_p->daifmt); 730 return -EINVAL; 731 } 732 pr_debug("atmel_ssc_hw_params: " 733 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", 734 rcmr, rfmr, tcmr, tfmr); 735 736 if (!ssc_p->initialized) { 737 if (!ssc_p->ssc->pdata->use_dma) { 738 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0); 739 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0); 740 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0); 741 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0); 742 743 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0); 744 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0); 745 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0); 746 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0); 747 } 748 749 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0, 750 ssc_p->name, ssc_p); 751 if (ret < 0) { 752 printk(KERN_WARNING 753 "atmel_ssc_dai: request_irq failure\n"); 754 pr_debug("Atmel_ssc_dai: Stoping clock\n"); 755 clk_disable(ssc_p->ssc->clk); 756 return ret; 757 } 758 759 ssc_p->initialized = 1; 760 } 761 762 /* set SSC clock mode register */ 763 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div); 764 765 /* set receive clock mode and format */ 766 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr); 767 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr); 768 769 /* set transmit clock mode and format */ 770 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr); 771 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr); 772 773 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n"); 774 return 0; 775 } 776 777 778 static int atmel_ssc_prepare(struct snd_pcm_substream *substream, 779 struct snd_soc_dai *dai) 780 { 781 struct platform_device *pdev = to_platform_device(dai->dev); 782 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 783 struct atmel_pcm_dma_params *dma_params; 784 int dir; 785 786 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 787 dir = 0; 788 else 789 dir = 1; 790 791 dma_params = ssc_p->dma_params[dir]; 792 793 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); 794 ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error); 795 796 pr_debug("%s enabled SSC_SR=0x%08x\n", 797 dir ? "receive" : "transmit", 798 ssc_readl(ssc_p->ssc->regs, SR)); 799 return 0; 800 } 801 802 static int atmel_ssc_trigger(struct snd_pcm_substream *substream, 803 int cmd, struct snd_soc_dai *dai) 804 { 805 struct platform_device *pdev = to_platform_device(dai->dev); 806 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 807 struct atmel_pcm_dma_params *dma_params; 808 int dir; 809 810 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 811 dir = 0; 812 else 813 dir = 1; 814 815 dma_params = ssc_p->dma_params[dir]; 816 817 switch (cmd) { 818 case SNDRV_PCM_TRIGGER_START: 819 case SNDRV_PCM_TRIGGER_RESUME: 820 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 821 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable); 822 break; 823 default: 824 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); 825 break; 826 } 827 828 return 0; 829 } 830 831 #ifdef CONFIG_PM 832 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai) 833 { 834 struct atmel_ssc_info *ssc_p; 835 struct platform_device *pdev = to_platform_device(cpu_dai->dev); 836 837 if (!cpu_dai->active) 838 return 0; 839 840 ssc_p = &ssc_info[pdev->id]; 841 842 /* Save the status register before disabling transmit and receive */ 843 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR); 844 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS)); 845 846 /* Save the current interrupt mask, then disable unmasked interrupts */ 847 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR); 848 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr); 849 850 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR); 851 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR); 852 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR); 853 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR); 854 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR); 855 856 return 0; 857 } 858 859 860 861 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai) 862 { 863 struct atmel_ssc_info *ssc_p; 864 struct platform_device *pdev = to_platform_device(cpu_dai->dev); 865 u32 cr; 866 867 if (!cpu_dai->active) 868 return 0; 869 870 ssc_p = &ssc_info[pdev->id]; 871 872 /* restore SSC register settings */ 873 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr); 874 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr); 875 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr); 876 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr); 877 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr); 878 879 /* re-enable interrupts */ 880 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr); 881 882 /* Re-enable receive and transmit as appropriate */ 883 cr = 0; 884 cr |= 885 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0; 886 cr |= 887 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0; 888 ssc_writel(ssc_p->ssc->regs, CR, cr); 889 890 return 0; 891 } 892 #else /* CONFIG_PM */ 893 # define atmel_ssc_suspend NULL 894 # define atmel_ssc_resume NULL 895 #endif /* CONFIG_PM */ 896 897 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 898 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 899 900 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = { 901 .startup = atmel_ssc_startup, 902 .shutdown = atmel_ssc_shutdown, 903 .prepare = atmel_ssc_prepare, 904 .trigger = atmel_ssc_trigger, 905 .hw_params = atmel_ssc_hw_params, 906 .set_fmt = atmel_ssc_set_dai_fmt, 907 .set_clkdiv = atmel_ssc_set_dai_clkdiv, 908 }; 909 910 static struct snd_soc_dai_driver atmel_ssc_dai = { 911 .suspend = atmel_ssc_suspend, 912 .resume = atmel_ssc_resume, 913 .playback = { 914 .channels_min = 1, 915 .channels_max = 2, 916 .rates = SNDRV_PCM_RATE_CONTINUOUS, 917 .rate_min = 8000, 918 .rate_max = 384000, 919 .formats = ATMEL_SSC_FORMATS,}, 920 .capture = { 921 .channels_min = 1, 922 .channels_max = 2, 923 .rates = SNDRV_PCM_RATE_CONTINUOUS, 924 .rate_min = 8000, 925 .rate_max = 384000, 926 .formats = ATMEL_SSC_FORMATS,}, 927 .ops = &atmel_ssc_dai_ops, 928 }; 929 930 static const struct snd_soc_component_driver atmel_ssc_component = { 931 .name = "atmel-ssc", 932 }; 933 934 static int asoc_ssc_init(struct device *dev) 935 { 936 struct platform_device *pdev = to_platform_device(dev); 937 struct ssc_device *ssc = platform_get_drvdata(pdev); 938 int ret; 939 940 ret = snd_soc_register_component(dev, &atmel_ssc_component, 941 &atmel_ssc_dai, 1); 942 if (ret) { 943 dev_err(dev, "Could not register DAI: %d\n", ret); 944 goto err; 945 } 946 947 if (ssc->pdata->use_dma) 948 ret = atmel_pcm_dma_platform_register(dev); 949 else 950 ret = atmel_pcm_pdc_platform_register(dev); 951 952 if (ret) { 953 dev_err(dev, "Could not register PCM: %d\n", ret); 954 goto err_unregister_dai; 955 } 956 957 return 0; 958 959 err_unregister_dai: 960 snd_soc_unregister_component(dev); 961 err: 962 return ret; 963 } 964 965 static void asoc_ssc_exit(struct device *dev) 966 { 967 struct platform_device *pdev = to_platform_device(dev); 968 struct ssc_device *ssc = platform_get_drvdata(pdev); 969 970 if (ssc->pdata->use_dma) 971 atmel_pcm_dma_platform_unregister(dev); 972 else 973 atmel_pcm_pdc_platform_unregister(dev); 974 975 snd_soc_unregister_component(dev); 976 } 977 978 /** 979 * atmel_ssc_set_audio - Allocate the specified SSC for audio use. 980 */ 981 int atmel_ssc_set_audio(int ssc_id) 982 { 983 struct ssc_device *ssc; 984 int ret; 985 986 /* If we can grab the SSC briefly to parent the DAI device off it */ 987 ssc = ssc_request(ssc_id); 988 if (IS_ERR(ssc)) { 989 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n", 990 PTR_ERR(ssc)); 991 return PTR_ERR(ssc); 992 } else { 993 ssc_info[ssc_id].ssc = ssc; 994 } 995 996 ret = asoc_ssc_init(&ssc->pdev->dev); 997 998 return ret; 999 } 1000 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio); 1001 1002 void atmel_ssc_put_audio(int ssc_id) 1003 { 1004 struct ssc_device *ssc = ssc_info[ssc_id].ssc; 1005 1006 asoc_ssc_exit(&ssc->pdev->dev); 1007 ssc_free(ssc); 1008 } 1009 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio); 1010 1011 /* Module information */ 1012 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com"); 1013 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface"); 1014 MODULE_LICENSE("GPL"); 1015