1 /* 2 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver 3 * 4 * Copyright (C) 2005 SAN People 5 * Copyright (C) 2008 Atmel 6 * 7 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com> 8 * ATMEL CORP. 9 * 10 * Based on at91-ssc.c by 11 * Frank Mandarino <fmandarino@endrelia.com> 12 * Based on pxa2xx Platform drivers by 13 * Liam Girdwood <lrg@slimlogic.co.uk> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30 #include <linux/init.h> 31 #include <linux/module.h> 32 #include <linux/interrupt.h> 33 #include <linux/device.h> 34 #include <linux/delay.h> 35 #include <linux/clk.h> 36 #include <linux/atmel_pdc.h> 37 38 #include <linux/atmel-ssc.h> 39 #include <sound/core.h> 40 #include <sound/pcm.h> 41 #include <sound/pcm_params.h> 42 #include <sound/initval.h> 43 #include <sound/soc.h> 44 45 #include <mach/hardware.h> 46 47 #include "atmel-pcm.h" 48 #include "atmel_ssc_dai.h" 49 50 51 #define NUM_SSC_DEVICES 3 52 53 /* 54 * SSC PDC registers required by the PCM DMA engine. 55 */ 56 static struct atmel_pdc_regs pdc_tx_reg = { 57 .xpr = ATMEL_PDC_TPR, 58 .xcr = ATMEL_PDC_TCR, 59 .xnpr = ATMEL_PDC_TNPR, 60 .xncr = ATMEL_PDC_TNCR, 61 }; 62 63 static struct atmel_pdc_regs pdc_rx_reg = { 64 .xpr = ATMEL_PDC_RPR, 65 .xcr = ATMEL_PDC_RCR, 66 .xnpr = ATMEL_PDC_RNPR, 67 .xncr = ATMEL_PDC_RNCR, 68 }; 69 70 /* 71 * SSC & PDC status bits for transmit and receive. 72 */ 73 static struct atmel_ssc_mask ssc_tx_mask = { 74 .ssc_enable = SSC_BIT(CR_TXEN), 75 .ssc_disable = SSC_BIT(CR_TXDIS), 76 .ssc_endx = SSC_BIT(SR_ENDTX), 77 .ssc_endbuf = SSC_BIT(SR_TXBUFE), 78 .pdc_enable = ATMEL_PDC_TXTEN, 79 .pdc_disable = ATMEL_PDC_TXTDIS, 80 }; 81 82 static struct atmel_ssc_mask ssc_rx_mask = { 83 .ssc_enable = SSC_BIT(CR_RXEN), 84 .ssc_disable = SSC_BIT(CR_RXDIS), 85 .ssc_endx = SSC_BIT(SR_ENDRX), 86 .ssc_endbuf = SSC_BIT(SR_RXBUFF), 87 .pdc_enable = ATMEL_PDC_RXTEN, 88 .pdc_disable = ATMEL_PDC_RXTDIS, 89 }; 90 91 92 /* 93 * DMA parameters. 94 */ 95 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = { 96 {{ 97 .name = "SSC0 PCM out", 98 .pdc = &pdc_tx_reg, 99 .mask = &ssc_tx_mask, 100 }, 101 { 102 .name = "SSC0 PCM in", 103 .pdc = &pdc_rx_reg, 104 .mask = &ssc_rx_mask, 105 } }, 106 {{ 107 .name = "SSC1 PCM out", 108 .pdc = &pdc_tx_reg, 109 .mask = &ssc_tx_mask, 110 }, 111 { 112 .name = "SSC1 PCM in", 113 .pdc = &pdc_rx_reg, 114 .mask = &ssc_rx_mask, 115 } }, 116 {{ 117 .name = "SSC2 PCM out", 118 .pdc = &pdc_tx_reg, 119 .mask = &ssc_tx_mask, 120 }, 121 { 122 .name = "SSC2 PCM in", 123 .pdc = &pdc_rx_reg, 124 .mask = &ssc_rx_mask, 125 } }, 126 }; 127 128 129 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = { 130 { 131 .name = "ssc0", 132 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock), 133 .dir_mask = SSC_DIR_MASK_UNUSED, 134 .initialized = 0, 135 }, 136 { 137 .name = "ssc1", 138 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock), 139 .dir_mask = SSC_DIR_MASK_UNUSED, 140 .initialized = 0, 141 }, 142 { 143 .name = "ssc2", 144 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock), 145 .dir_mask = SSC_DIR_MASK_UNUSED, 146 .initialized = 0, 147 }, 148 }; 149 150 151 /* 152 * SSC interrupt handler. Passes PDC interrupts to the DMA 153 * interrupt handler in the PCM driver. 154 */ 155 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id) 156 { 157 struct atmel_ssc_info *ssc_p = dev_id; 158 struct atmel_pcm_dma_params *dma_params; 159 u32 ssc_sr; 160 u32 ssc_substream_mask; 161 int i; 162 163 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) 164 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); 165 166 /* 167 * Loop through the substreams attached to this SSC. If 168 * a DMA-related interrupt occurred on that substream, call 169 * the DMA interrupt handler function, if one has been 170 * registered in the dma_params structure by the PCM driver. 171 */ 172 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) { 173 dma_params = ssc_p->dma_params[i]; 174 175 if ((dma_params != NULL) && 176 (dma_params->dma_intr_handler != NULL)) { 177 ssc_substream_mask = (dma_params->mask->ssc_endx | 178 dma_params->mask->ssc_endbuf); 179 if (ssc_sr & ssc_substream_mask) { 180 dma_params->dma_intr_handler(ssc_sr, 181 dma_params-> 182 substream); 183 } 184 } 185 } 186 187 return IRQ_HANDLED; 188 } 189 190 191 /*-------------------------------------------------------------------------*\ 192 * DAI functions 193 \*-------------------------------------------------------------------------*/ 194 /* 195 * Startup. Only that one substream allowed in each direction. 196 */ 197 static int atmel_ssc_startup(struct snd_pcm_substream *substream, 198 struct snd_soc_dai *dai) 199 { 200 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 201 int dir_mask; 202 203 pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n", 204 ssc_readl(ssc_p->ssc->regs, SR)); 205 206 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 207 dir_mask = SSC_DIR_MASK_PLAYBACK; 208 else 209 dir_mask = SSC_DIR_MASK_CAPTURE; 210 211 spin_lock_irq(&ssc_p->lock); 212 if (ssc_p->dir_mask & dir_mask) { 213 spin_unlock_irq(&ssc_p->lock); 214 return -EBUSY; 215 } 216 ssc_p->dir_mask |= dir_mask; 217 spin_unlock_irq(&ssc_p->lock); 218 219 return 0; 220 } 221 222 /* 223 * Shutdown. Clear DMA parameters and shutdown the SSC if there 224 * are no other substreams open. 225 */ 226 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream, 227 struct snd_soc_dai *dai) 228 { 229 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 230 struct atmel_pcm_dma_params *dma_params; 231 int dir, dir_mask; 232 233 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 234 dir = 0; 235 else 236 dir = 1; 237 238 dma_params = ssc_p->dma_params[dir]; 239 240 if (dma_params != NULL) { 241 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); 242 pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n", 243 (dir ? "receive" : "transmit"), 244 ssc_readl(ssc_p->ssc->regs, SR)); 245 246 dma_params->ssc = NULL; 247 dma_params->substream = NULL; 248 ssc_p->dma_params[dir] = NULL; 249 } 250 251 dir_mask = 1 << dir; 252 253 spin_lock_irq(&ssc_p->lock); 254 ssc_p->dir_mask &= ~dir_mask; 255 if (!ssc_p->dir_mask) { 256 if (ssc_p->initialized) { 257 /* Shutdown the SSC clock. */ 258 pr_debug("atmel_ssc_dau: Stopping clock\n"); 259 clk_disable(ssc_p->ssc->clk); 260 261 free_irq(ssc_p->ssc->irq, ssc_p); 262 ssc_p->initialized = 0; 263 } 264 265 /* Reset the SSC */ 266 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); 267 /* Clear the SSC dividers */ 268 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0; 269 } 270 spin_unlock_irq(&ssc_p->lock); 271 } 272 273 274 /* 275 * Record the DAI format for use in hw_params(). 276 */ 277 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai, 278 unsigned int fmt) 279 { 280 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; 281 282 ssc_p->daifmt = fmt; 283 return 0; 284 } 285 286 /* 287 * Record SSC clock dividers for use in hw_params(). 288 */ 289 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, 290 int div_id, int div) 291 { 292 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; 293 294 switch (div_id) { 295 case ATMEL_SSC_CMR_DIV: 296 /* 297 * The same master clock divider is used for both 298 * transmit and receive, so if a value has already 299 * been set, it must match this value. 300 */ 301 if (ssc_p->cmr_div == 0) 302 ssc_p->cmr_div = div; 303 else 304 if (div != ssc_p->cmr_div) 305 return -EBUSY; 306 break; 307 308 case ATMEL_SSC_TCMR_PERIOD: 309 ssc_p->tcmr_period = div; 310 break; 311 312 case ATMEL_SSC_RCMR_PERIOD: 313 ssc_p->rcmr_period = div; 314 break; 315 316 default: 317 return -EINVAL; 318 } 319 320 return 0; 321 } 322 323 /* 324 * Configure the SSC. 325 */ 326 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream, 327 struct snd_pcm_hw_params *params, 328 struct snd_soc_dai *dai) 329 { 330 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 331 int id = dai->id; 332 struct atmel_ssc_info *ssc_p = &ssc_info[id]; 333 struct atmel_pcm_dma_params *dma_params; 334 int dir, channels, bits; 335 u32 tfmr, rfmr, tcmr, rcmr; 336 int start_event; 337 int ret; 338 339 /* 340 * Currently, there is only one set of dma params for 341 * each direction. If more are added, this code will 342 * have to be changed to select the proper set. 343 */ 344 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 345 dir = 0; 346 else 347 dir = 1; 348 349 dma_params = &ssc_dma_params[id][dir]; 350 dma_params->ssc = ssc_p->ssc; 351 dma_params->substream = substream; 352 353 ssc_p->dma_params[dir] = dma_params; 354 355 /* 356 * The snd_soc_pcm_stream->dma_data field is only used to communicate 357 * the appropriate DMA parameters to the pcm driver hw_params() 358 * function. It should not be used for other purposes 359 * as it is common to all substreams. 360 */ 361 snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_params); 362 363 channels = params_channels(params); 364 365 /* 366 * Determine sample size in bits and the PDC increment. 367 */ 368 switch (params_format(params)) { 369 case SNDRV_PCM_FORMAT_S8: 370 bits = 8; 371 dma_params->pdc_xfer_size = 1; 372 break; 373 case SNDRV_PCM_FORMAT_S16_LE: 374 bits = 16; 375 dma_params->pdc_xfer_size = 2; 376 break; 377 case SNDRV_PCM_FORMAT_S24_LE: 378 bits = 24; 379 dma_params->pdc_xfer_size = 4; 380 break; 381 case SNDRV_PCM_FORMAT_S32_LE: 382 bits = 32; 383 dma_params->pdc_xfer_size = 4; 384 break; 385 default: 386 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format"); 387 return -EINVAL; 388 } 389 390 /* 391 * The SSC only supports up to 16-bit samples in I2S format, due 392 * to the size of the Frame Mode Register FSLEN field. 393 */ 394 if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S 395 && bits > 16) { 396 printk(KERN_WARNING 397 "atmel_ssc_dai: sample size %d " 398 "is too large for I2S\n", bits); 399 return -EINVAL; 400 } 401 402 /* 403 * Compute SSC register settings. 404 */ 405 switch (ssc_p->daifmt 406 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) { 407 408 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS: 409 /* 410 * I2S format, SSC provides BCLK and LRC clocks. 411 * 412 * The SSC transmit and receive clocks are generated 413 * from the MCK divider, and the BCLK signal 414 * is output on the SSC TK line. 415 */ 416 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) 417 | SSC_BF(RCMR_STTDLY, START_DELAY) 418 | SSC_BF(RCMR_START, SSC_START_FALLING_RF) 419 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 420 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 421 | SSC_BF(RCMR_CKS, SSC_CKS_DIV); 422 423 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 424 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) 425 | SSC_BF(RFMR_FSLEN, (bits - 1)) 426 | SSC_BF(RFMR_DATNB, (channels - 1)) 427 | SSC_BIT(RFMR_MSBF) 428 | SSC_BF(RFMR_LOOP, 0) 429 | SSC_BF(RFMR_DATLEN, (bits - 1)); 430 431 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) 432 | SSC_BF(TCMR_STTDLY, START_DELAY) 433 | SSC_BF(TCMR_START, SSC_START_FALLING_RF) 434 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) 435 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) 436 | SSC_BF(TCMR_CKS, SSC_CKS_DIV); 437 438 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 439 | SSC_BF(TFMR_FSDEN, 0) 440 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) 441 | SSC_BF(TFMR_FSLEN, (bits - 1)) 442 | SSC_BF(TFMR_DATNB, (channels - 1)) 443 | SSC_BIT(TFMR_MSBF) 444 | SSC_BF(TFMR_DATDEF, 0) 445 | SSC_BF(TFMR_DATLEN, (bits - 1)); 446 break; 447 448 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM: 449 /* 450 * I2S format, CODEC supplies BCLK and LRC clocks. 451 * 452 * The SSC transmit clock is obtained from the BCLK signal on 453 * on the TK line, and the SSC receive clock is 454 * generated from the transmit clock. 455 * 456 * For single channel data, one sample is transferred 457 * on the falling edge of the LRC clock. 458 * For two channel data, one sample is 459 * transferred on both edges of the LRC clock. 460 */ 461 start_event = ((channels == 1) 462 ? SSC_START_FALLING_RF 463 : SSC_START_EDGE_RF); 464 465 rcmr = SSC_BF(RCMR_PERIOD, 0) 466 | SSC_BF(RCMR_STTDLY, START_DELAY) 467 | SSC_BF(RCMR_START, start_event) 468 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 469 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 470 | SSC_BF(RCMR_CKS, SSC_CKS_CLOCK); 471 472 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 473 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) 474 | SSC_BF(RFMR_FSLEN, 0) 475 | SSC_BF(RFMR_DATNB, 0) 476 | SSC_BIT(RFMR_MSBF) 477 | SSC_BF(RFMR_LOOP, 0) 478 | SSC_BF(RFMR_DATLEN, (bits - 1)); 479 480 tcmr = SSC_BF(TCMR_PERIOD, 0) 481 | SSC_BF(TCMR_STTDLY, START_DELAY) 482 | SSC_BF(TCMR_START, start_event) 483 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) 484 | SSC_BF(TCMR_CKO, SSC_CKO_NONE) 485 | SSC_BF(TCMR_CKS, SSC_CKS_PIN); 486 487 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 488 | SSC_BF(TFMR_FSDEN, 0) 489 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) 490 | SSC_BF(TFMR_FSLEN, 0) 491 | SSC_BF(TFMR_DATNB, 0) 492 | SSC_BIT(TFMR_MSBF) 493 | SSC_BF(TFMR_DATDEF, 0) 494 | SSC_BF(TFMR_DATLEN, (bits - 1)); 495 break; 496 497 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS: 498 /* 499 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks. 500 * 501 * The SSC transmit and receive clocks are generated from the 502 * MCK divider, and the BCLK signal is output 503 * on the SSC TK line. 504 */ 505 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) 506 | SSC_BF(RCMR_STTDLY, 1) 507 | SSC_BF(RCMR_START, SSC_START_RISING_RF) 508 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 509 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 510 | SSC_BF(RCMR_CKS, SSC_CKS_DIV); 511 512 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 513 | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE) 514 | SSC_BF(RFMR_FSLEN, 0) 515 | SSC_BF(RFMR_DATNB, (channels - 1)) 516 | SSC_BIT(RFMR_MSBF) 517 | SSC_BF(RFMR_LOOP, 0) 518 | SSC_BF(RFMR_DATLEN, (bits - 1)); 519 520 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) 521 | SSC_BF(TCMR_STTDLY, 1) 522 | SSC_BF(TCMR_START, SSC_START_RISING_RF) 523 | SSC_BF(TCMR_CKI, SSC_CKI_RISING) 524 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) 525 | SSC_BF(TCMR_CKS, SSC_CKS_DIV); 526 527 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 528 | SSC_BF(TFMR_FSDEN, 0) 529 | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE) 530 | SSC_BF(TFMR_FSLEN, 0) 531 | SSC_BF(TFMR_DATNB, (channels - 1)) 532 | SSC_BIT(TFMR_MSBF) 533 | SSC_BF(TFMR_DATDEF, 0) 534 | SSC_BF(TFMR_DATLEN, (bits - 1)); 535 break; 536 537 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM: 538 default: 539 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n", 540 ssc_p->daifmt); 541 return -EINVAL; 542 } 543 pr_debug("atmel_ssc_hw_params: " 544 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", 545 rcmr, rfmr, tcmr, tfmr); 546 547 if (!ssc_p->initialized) { 548 549 /* Enable PMC peripheral clock for this SSC */ 550 pr_debug("atmel_ssc_dai: Starting clock\n"); 551 clk_enable(ssc_p->ssc->clk); 552 553 /* Reset the SSC and its PDC registers */ 554 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); 555 556 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0); 557 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0); 558 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0); 559 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0); 560 561 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0); 562 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0); 563 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0); 564 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0); 565 566 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0, 567 ssc_p->name, ssc_p); 568 if (ret < 0) { 569 printk(KERN_WARNING 570 "atmel_ssc_dai: request_irq failure\n"); 571 pr_debug("Atmel_ssc_dai: Stoping clock\n"); 572 clk_disable(ssc_p->ssc->clk); 573 return ret; 574 } 575 576 ssc_p->initialized = 1; 577 } 578 579 /* set SSC clock mode register */ 580 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div); 581 582 /* set receive clock mode and format */ 583 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr); 584 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr); 585 586 /* set transmit clock mode and format */ 587 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr); 588 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr); 589 590 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n"); 591 return 0; 592 } 593 594 595 static int atmel_ssc_prepare(struct snd_pcm_substream *substream, 596 struct snd_soc_dai *dai) 597 { 598 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 599 struct atmel_pcm_dma_params *dma_params; 600 int dir; 601 602 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 603 dir = 0; 604 else 605 dir = 1; 606 607 dma_params = ssc_p->dma_params[dir]; 608 609 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable); 610 611 pr_debug("%s enabled SSC_SR=0x%08x\n", 612 dir ? "receive" : "transmit", 613 ssc_readl(ssc_p->ssc->regs, SR)); 614 return 0; 615 } 616 617 618 #ifdef CONFIG_PM 619 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai) 620 { 621 struct atmel_ssc_info *ssc_p; 622 623 if (!cpu_dai->active) 624 return 0; 625 626 ssc_p = &ssc_info[cpu_dai->id]; 627 628 /* Save the status register before disabling transmit and receive */ 629 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR); 630 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS)); 631 632 /* Save the current interrupt mask, then disable unmasked interrupts */ 633 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR); 634 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr); 635 636 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR); 637 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR); 638 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR); 639 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR); 640 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR); 641 642 return 0; 643 } 644 645 646 647 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai) 648 { 649 struct atmel_ssc_info *ssc_p; 650 u32 cr; 651 652 if (!cpu_dai->active) 653 return 0; 654 655 ssc_p = &ssc_info[cpu_dai->id]; 656 657 /* restore SSC register settings */ 658 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr); 659 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr); 660 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr); 661 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr); 662 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr); 663 664 /* re-enable interrupts */ 665 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr); 666 667 /* Re-enable receive and transmit as appropriate */ 668 cr = 0; 669 cr |= 670 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0; 671 cr |= 672 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0; 673 ssc_writel(ssc_p->ssc->regs, CR, cr); 674 675 return 0; 676 } 677 #else /* CONFIG_PM */ 678 # define atmel_ssc_suspend NULL 679 # define atmel_ssc_resume NULL 680 #endif /* CONFIG_PM */ 681 682 static int atmel_ssc_probe(struct snd_soc_dai *dai) 683 { 684 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 685 686 snd_soc_dai_set_drvdata(dai, ssc_p); 687 688 return 0; 689 } 690 691 #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000) 692 693 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 694 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 695 696 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = { 697 .startup = atmel_ssc_startup, 698 .shutdown = atmel_ssc_shutdown, 699 .prepare = atmel_ssc_prepare, 700 .hw_params = atmel_ssc_hw_params, 701 .set_fmt = atmel_ssc_set_dai_fmt, 702 .set_clkdiv = atmel_ssc_set_dai_clkdiv, 703 }; 704 705 static struct snd_soc_dai_driver atmel_ssc_dai = { 706 .probe = atmel_ssc_probe, 707 .suspend = atmel_ssc_suspend, 708 .resume = atmel_ssc_resume, 709 .playback = { 710 .channels_min = 1, 711 .channels_max = 2, 712 .rates = ATMEL_SSC_RATES, 713 .formats = ATMEL_SSC_FORMATS,}, 714 .capture = { 715 .channels_min = 1, 716 .channels_max = 2, 717 .rates = ATMEL_SSC_RATES, 718 .formats = ATMEL_SSC_FORMATS,}, 719 .ops = &atmel_ssc_dai_ops, 720 }; 721 722 static int asoc_ssc_init(struct device *dev) 723 { 724 struct platform_device *pdev = to_platform_device(dev); 725 struct ssc_device *ssc = platform_get_drvdata(pdev); 726 int ret; 727 728 ret = snd_soc_register_dai(dev, &atmel_ssc_dai); 729 if (ret) { 730 dev_err(dev, "Could not register DAI: %d\n", ret); 731 goto err; 732 } 733 734 if (ssc->pdata->use_dma) 735 ret = atmel_pcm_dma_platform_register(dev); 736 else 737 ret = atmel_pcm_pdc_platform_register(dev); 738 739 if (ret) { 740 dev_err(dev, "Could not register PCM: %d\n", ret); 741 goto err_unregister_dai; 742 }; 743 744 return 0; 745 746 err_unregister_dai: 747 snd_soc_unregister_dai(dev); 748 err: 749 return ret; 750 } 751 752 static void asoc_ssc_exit(struct device *dev) 753 { 754 struct platform_device *pdev = to_platform_device(dev); 755 struct ssc_device *ssc = platform_get_drvdata(pdev); 756 757 if (ssc->pdata->use_dma) 758 atmel_pcm_dma_platform_unregister(dev); 759 else 760 atmel_pcm_pdc_platform_unregister(dev); 761 762 snd_soc_unregister_dai(dev); 763 } 764 765 /** 766 * atmel_ssc_set_audio - Allocate the specified SSC for audio use. 767 */ 768 int atmel_ssc_set_audio(int ssc_id) 769 { 770 struct ssc_device *ssc; 771 int ret; 772 773 /* If we can grab the SSC briefly to parent the DAI device off it */ 774 ssc = ssc_request(ssc_id); 775 if (IS_ERR(ssc)) { 776 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n", 777 PTR_ERR(ssc)); 778 return PTR_ERR(ssc); 779 } else { 780 ssc_info[ssc_id].ssc = ssc; 781 } 782 783 ret = asoc_ssc_init(&ssc->pdev->dev); 784 785 return ret; 786 } 787 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio); 788 789 void atmel_ssc_put_audio(int ssc_id) 790 { 791 struct ssc_device *ssc = ssc_info[ssc_id].ssc; 792 793 ssc_free(ssc); 794 asoc_ssc_exit(&ssc->pdev->dev); 795 } 796 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio); 797 798 /* Module information */ 799 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com"); 800 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface"); 801 MODULE_LICENSE("GPL"); 802