1 /* 2 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver 3 * 4 * Copyright (C) 2005 SAN People 5 * Copyright (C) 2008 Atmel 6 * 7 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com> 8 * ATMEL CORP. 9 * 10 * Based on at91-ssc.c by 11 * Frank Mandarino <fmandarino@endrelia.com> 12 * Based on pxa2xx Platform drivers by 13 * Liam Girdwood <lrg@slimlogic.co.uk> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30 #include <linux/init.h> 31 #include <linux/module.h> 32 #include <linux/interrupt.h> 33 #include <linux/device.h> 34 #include <linux/delay.h> 35 #include <linux/clk.h> 36 #include <linux/atmel_pdc.h> 37 38 #include <linux/atmel-ssc.h> 39 #include <sound/core.h> 40 #include <sound/pcm.h> 41 #include <sound/pcm_params.h> 42 #include <sound/initval.h> 43 #include <sound/soc.h> 44 45 #include "atmel-pcm.h" 46 #include "atmel_ssc_dai.h" 47 48 49 #define NUM_SSC_DEVICES 3 50 51 /* 52 * SSC PDC registers required by the PCM DMA engine. 53 */ 54 static struct atmel_pdc_regs pdc_tx_reg = { 55 .xpr = ATMEL_PDC_TPR, 56 .xcr = ATMEL_PDC_TCR, 57 .xnpr = ATMEL_PDC_TNPR, 58 .xncr = ATMEL_PDC_TNCR, 59 }; 60 61 static struct atmel_pdc_regs pdc_rx_reg = { 62 .xpr = ATMEL_PDC_RPR, 63 .xcr = ATMEL_PDC_RCR, 64 .xnpr = ATMEL_PDC_RNPR, 65 .xncr = ATMEL_PDC_RNCR, 66 }; 67 68 /* 69 * SSC & PDC status bits for transmit and receive. 70 */ 71 static struct atmel_ssc_mask ssc_tx_mask = { 72 .ssc_enable = SSC_BIT(CR_TXEN), 73 .ssc_disable = SSC_BIT(CR_TXDIS), 74 .ssc_endx = SSC_BIT(SR_ENDTX), 75 .ssc_endbuf = SSC_BIT(SR_TXBUFE), 76 .ssc_error = SSC_BIT(SR_OVRUN), 77 .pdc_enable = ATMEL_PDC_TXTEN, 78 .pdc_disable = ATMEL_PDC_TXTDIS, 79 }; 80 81 static struct atmel_ssc_mask ssc_rx_mask = { 82 .ssc_enable = SSC_BIT(CR_RXEN), 83 .ssc_disable = SSC_BIT(CR_RXDIS), 84 .ssc_endx = SSC_BIT(SR_ENDRX), 85 .ssc_endbuf = SSC_BIT(SR_RXBUFF), 86 .ssc_error = SSC_BIT(SR_OVRUN), 87 .pdc_enable = ATMEL_PDC_RXTEN, 88 .pdc_disable = ATMEL_PDC_RXTDIS, 89 }; 90 91 92 /* 93 * DMA parameters. 94 */ 95 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = { 96 {{ 97 .name = "SSC0 PCM out", 98 .pdc = &pdc_tx_reg, 99 .mask = &ssc_tx_mask, 100 }, 101 { 102 .name = "SSC0 PCM in", 103 .pdc = &pdc_rx_reg, 104 .mask = &ssc_rx_mask, 105 } }, 106 {{ 107 .name = "SSC1 PCM out", 108 .pdc = &pdc_tx_reg, 109 .mask = &ssc_tx_mask, 110 }, 111 { 112 .name = "SSC1 PCM in", 113 .pdc = &pdc_rx_reg, 114 .mask = &ssc_rx_mask, 115 } }, 116 {{ 117 .name = "SSC2 PCM out", 118 .pdc = &pdc_tx_reg, 119 .mask = &ssc_tx_mask, 120 }, 121 { 122 .name = "SSC2 PCM in", 123 .pdc = &pdc_rx_reg, 124 .mask = &ssc_rx_mask, 125 } }, 126 }; 127 128 129 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = { 130 { 131 .name = "ssc0", 132 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock), 133 .dir_mask = SSC_DIR_MASK_UNUSED, 134 .initialized = 0, 135 }, 136 { 137 .name = "ssc1", 138 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock), 139 .dir_mask = SSC_DIR_MASK_UNUSED, 140 .initialized = 0, 141 }, 142 { 143 .name = "ssc2", 144 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock), 145 .dir_mask = SSC_DIR_MASK_UNUSED, 146 .initialized = 0, 147 }, 148 }; 149 150 151 /* 152 * SSC interrupt handler. Passes PDC interrupts to the DMA 153 * interrupt handler in the PCM driver. 154 */ 155 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id) 156 { 157 struct atmel_ssc_info *ssc_p = dev_id; 158 struct atmel_pcm_dma_params *dma_params; 159 u32 ssc_sr; 160 u32 ssc_substream_mask; 161 int i; 162 163 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) 164 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); 165 166 /* 167 * Loop through the substreams attached to this SSC. If 168 * a DMA-related interrupt occurred on that substream, call 169 * the DMA interrupt handler function, if one has been 170 * registered in the dma_params structure by the PCM driver. 171 */ 172 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) { 173 dma_params = ssc_p->dma_params[i]; 174 175 if ((dma_params != NULL) && 176 (dma_params->dma_intr_handler != NULL)) { 177 ssc_substream_mask = (dma_params->mask->ssc_endx | 178 dma_params->mask->ssc_endbuf); 179 if (ssc_sr & ssc_substream_mask) { 180 dma_params->dma_intr_handler(ssc_sr, 181 dma_params-> 182 substream); 183 } 184 } 185 } 186 187 return IRQ_HANDLED; 188 } 189 190 191 /*-------------------------------------------------------------------------*\ 192 * DAI functions 193 \*-------------------------------------------------------------------------*/ 194 /* 195 * Startup. Only that one substream allowed in each direction. 196 */ 197 static int atmel_ssc_startup(struct snd_pcm_substream *substream, 198 struct snd_soc_dai *dai) 199 { 200 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 201 struct atmel_pcm_dma_params *dma_params; 202 int dir, dir_mask; 203 204 pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n", 205 ssc_readl(ssc_p->ssc->regs, SR)); 206 207 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 208 dir = 0; 209 dir_mask = SSC_DIR_MASK_PLAYBACK; 210 } else { 211 dir = 1; 212 dir_mask = SSC_DIR_MASK_CAPTURE; 213 } 214 215 dma_params = &ssc_dma_params[dai->id][dir]; 216 dma_params->ssc = ssc_p->ssc; 217 dma_params->substream = substream; 218 219 ssc_p->dma_params[dir] = dma_params; 220 221 snd_soc_dai_set_dma_data(dai, substream, dma_params); 222 223 spin_lock_irq(&ssc_p->lock); 224 if (ssc_p->dir_mask & dir_mask) { 225 spin_unlock_irq(&ssc_p->lock); 226 return -EBUSY; 227 } 228 ssc_p->dir_mask |= dir_mask; 229 spin_unlock_irq(&ssc_p->lock); 230 231 return 0; 232 } 233 234 /* 235 * Shutdown. Clear DMA parameters and shutdown the SSC if there 236 * are no other substreams open. 237 */ 238 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream, 239 struct snd_soc_dai *dai) 240 { 241 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 242 struct atmel_pcm_dma_params *dma_params; 243 int dir, dir_mask; 244 245 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 246 dir = 0; 247 else 248 dir = 1; 249 250 dma_params = ssc_p->dma_params[dir]; 251 252 if (dma_params != NULL) { 253 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); 254 pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n", 255 (dir ? "receive" : "transmit"), 256 ssc_readl(ssc_p->ssc->regs, SR)); 257 258 dma_params->ssc = NULL; 259 dma_params->substream = NULL; 260 ssc_p->dma_params[dir] = NULL; 261 } 262 263 dir_mask = 1 << dir; 264 265 spin_lock_irq(&ssc_p->lock); 266 ssc_p->dir_mask &= ~dir_mask; 267 if (!ssc_p->dir_mask) { 268 if (ssc_p->initialized) { 269 /* Shutdown the SSC clock. */ 270 pr_debug("atmel_ssc_dau: Stopping clock\n"); 271 clk_disable(ssc_p->ssc->clk); 272 273 free_irq(ssc_p->ssc->irq, ssc_p); 274 ssc_p->initialized = 0; 275 } 276 277 /* Reset the SSC */ 278 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); 279 /* Clear the SSC dividers */ 280 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0; 281 } 282 spin_unlock_irq(&ssc_p->lock); 283 } 284 285 286 /* 287 * Record the DAI format for use in hw_params(). 288 */ 289 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai, 290 unsigned int fmt) 291 { 292 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; 293 294 ssc_p->daifmt = fmt; 295 return 0; 296 } 297 298 /* 299 * Record SSC clock dividers for use in hw_params(). 300 */ 301 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, 302 int div_id, int div) 303 { 304 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; 305 306 switch (div_id) { 307 case ATMEL_SSC_CMR_DIV: 308 /* 309 * The same master clock divider is used for both 310 * transmit and receive, so if a value has already 311 * been set, it must match this value. 312 */ 313 if (ssc_p->cmr_div == 0) 314 ssc_p->cmr_div = div; 315 else 316 if (div != ssc_p->cmr_div) 317 return -EBUSY; 318 break; 319 320 case ATMEL_SSC_TCMR_PERIOD: 321 ssc_p->tcmr_period = div; 322 break; 323 324 case ATMEL_SSC_RCMR_PERIOD: 325 ssc_p->rcmr_period = div; 326 break; 327 328 default: 329 return -EINVAL; 330 } 331 332 return 0; 333 } 334 335 /* 336 * Configure the SSC. 337 */ 338 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream, 339 struct snd_pcm_hw_params *params, 340 struct snd_soc_dai *dai) 341 { 342 int id = dai->id; 343 struct atmel_ssc_info *ssc_p = &ssc_info[id]; 344 struct atmel_pcm_dma_params *dma_params; 345 int dir, channels, bits; 346 u32 tfmr, rfmr, tcmr, rcmr; 347 int start_event; 348 int ret; 349 350 /* 351 * Currently, there is only one set of dma params for 352 * each direction. If more are added, this code will 353 * have to be changed to select the proper set. 354 */ 355 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 356 dir = 0; 357 else 358 dir = 1; 359 360 dma_params = ssc_p->dma_params[dir]; 361 362 channels = params_channels(params); 363 364 /* 365 * Determine sample size in bits and the PDC increment. 366 */ 367 switch (params_format(params)) { 368 case SNDRV_PCM_FORMAT_S8: 369 bits = 8; 370 dma_params->pdc_xfer_size = 1; 371 break; 372 case SNDRV_PCM_FORMAT_S16_LE: 373 bits = 16; 374 dma_params->pdc_xfer_size = 2; 375 break; 376 case SNDRV_PCM_FORMAT_S24_LE: 377 bits = 24; 378 dma_params->pdc_xfer_size = 4; 379 break; 380 case SNDRV_PCM_FORMAT_S32_LE: 381 bits = 32; 382 dma_params->pdc_xfer_size = 4; 383 break; 384 default: 385 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format"); 386 return -EINVAL; 387 } 388 389 /* 390 * The SSC only supports up to 16-bit samples in I2S format, due 391 * to the size of the Frame Mode Register FSLEN field. 392 */ 393 if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S 394 && bits > 16) { 395 printk(KERN_WARNING 396 "atmel_ssc_dai: sample size %d " 397 "is too large for I2S\n", bits); 398 return -EINVAL; 399 } 400 401 /* 402 * Compute SSC register settings. 403 */ 404 switch (ssc_p->daifmt 405 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) { 406 407 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS: 408 /* 409 * I2S format, SSC provides BCLK and LRC clocks. 410 * 411 * The SSC transmit and receive clocks are generated 412 * from the MCK divider, and the BCLK signal 413 * is output on the SSC TK line. 414 */ 415 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) 416 | SSC_BF(RCMR_STTDLY, START_DELAY) 417 | SSC_BF(RCMR_START, SSC_START_FALLING_RF) 418 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 419 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 420 | SSC_BF(RCMR_CKS, SSC_CKS_DIV); 421 422 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 423 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) 424 | SSC_BF(RFMR_FSLEN, (bits - 1)) 425 | SSC_BF(RFMR_DATNB, (channels - 1)) 426 | SSC_BIT(RFMR_MSBF) 427 | SSC_BF(RFMR_LOOP, 0) 428 | SSC_BF(RFMR_DATLEN, (bits - 1)); 429 430 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) 431 | SSC_BF(TCMR_STTDLY, START_DELAY) 432 | SSC_BF(TCMR_START, SSC_START_FALLING_RF) 433 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) 434 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) 435 | SSC_BF(TCMR_CKS, SSC_CKS_DIV); 436 437 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 438 | SSC_BF(TFMR_FSDEN, 0) 439 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) 440 | SSC_BF(TFMR_FSLEN, (bits - 1)) 441 | SSC_BF(TFMR_DATNB, (channels - 1)) 442 | SSC_BIT(TFMR_MSBF) 443 | SSC_BF(TFMR_DATDEF, 0) 444 | SSC_BF(TFMR_DATLEN, (bits - 1)); 445 break; 446 447 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM: 448 /* 449 * I2S format, CODEC supplies BCLK and LRC clocks. 450 * 451 * The SSC transmit clock is obtained from the BCLK signal on 452 * on the TK line, and the SSC receive clock is 453 * generated from the transmit clock. 454 * 455 * For single channel data, one sample is transferred 456 * on the falling edge of the LRC clock. 457 * For two channel data, one sample is 458 * transferred on both edges of the LRC clock. 459 */ 460 start_event = ((channels == 1) 461 ? SSC_START_FALLING_RF 462 : SSC_START_EDGE_RF); 463 464 rcmr = SSC_BF(RCMR_PERIOD, 0) 465 | SSC_BF(RCMR_STTDLY, START_DELAY) 466 | SSC_BF(RCMR_START, start_event) 467 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 468 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 469 | SSC_BF(RCMR_CKS, SSC_CKS_CLOCK); 470 471 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 472 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) 473 | SSC_BF(RFMR_FSLEN, 0) 474 | SSC_BF(RFMR_DATNB, 0) 475 | SSC_BIT(RFMR_MSBF) 476 | SSC_BF(RFMR_LOOP, 0) 477 | SSC_BF(RFMR_DATLEN, (bits - 1)); 478 479 tcmr = SSC_BF(TCMR_PERIOD, 0) 480 | SSC_BF(TCMR_STTDLY, START_DELAY) 481 | SSC_BF(TCMR_START, start_event) 482 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) 483 | SSC_BF(TCMR_CKO, SSC_CKO_NONE) 484 | SSC_BF(TCMR_CKS, SSC_CKS_PIN); 485 486 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 487 | SSC_BF(TFMR_FSDEN, 0) 488 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) 489 | SSC_BF(TFMR_FSLEN, 0) 490 | SSC_BF(TFMR_DATNB, 0) 491 | SSC_BIT(TFMR_MSBF) 492 | SSC_BF(TFMR_DATDEF, 0) 493 | SSC_BF(TFMR_DATLEN, (bits - 1)); 494 break; 495 496 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS: 497 /* 498 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks. 499 * 500 * The SSC transmit and receive clocks are generated from the 501 * MCK divider, and the BCLK signal is output 502 * on the SSC TK line. 503 */ 504 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) 505 | SSC_BF(RCMR_STTDLY, 1) 506 | SSC_BF(RCMR_START, SSC_START_RISING_RF) 507 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 508 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 509 | SSC_BF(RCMR_CKS, SSC_CKS_DIV); 510 511 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 512 | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE) 513 | SSC_BF(RFMR_FSLEN, 0) 514 | SSC_BF(RFMR_DATNB, (channels - 1)) 515 | SSC_BIT(RFMR_MSBF) 516 | SSC_BF(RFMR_LOOP, 0) 517 | SSC_BF(RFMR_DATLEN, (bits - 1)); 518 519 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) 520 | SSC_BF(TCMR_STTDLY, 1) 521 | SSC_BF(TCMR_START, SSC_START_RISING_RF) 522 | SSC_BF(TCMR_CKI, SSC_CKI_RISING) 523 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) 524 | SSC_BF(TCMR_CKS, SSC_CKS_DIV); 525 526 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 527 | SSC_BF(TFMR_FSDEN, 0) 528 | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE) 529 | SSC_BF(TFMR_FSLEN, 0) 530 | SSC_BF(TFMR_DATNB, (channels - 1)) 531 | SSC_BIT(TFMR_MSBF) 532 | SSC_BF(TFMR_DATDEF, 0) 533 | SSC_BF(TFMR_DATLEN, (bits - 1)); 534 break; 535 536 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM: 537 /* 538 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks. 539 * 540 * The SSC transmit clock is obtained from the BCLK signal on 541 * on the TK line, and the SSC receive clock is 542 * generated from the transmit clock. 543 * 544 * Data is transferred on first BCLK after LRC pulse rising 545 * edge.If stereo, the right channel data is contiguous with 546 * the left channel data. 547 */ 548 rcmr = SSC_BF(RCMR_PERIOD, 0) 549 | SSC_BF(RCMR_STTDLY, START_DELAY) 550 | SSC_BF(RCMR_START, SSC_START_RISING_RF) 551 | SSC_BF(RCMR_CKI, SSC_CKI_RISING) 552 | SSC_BF(RCMR_CKO, SSC_CKO_NONE) 553 | SSC_BF(RCMR_CKS, SSC_CKS_PIN); 554 555 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 556 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) 557 | SSC_BF(RFMR_FSLEN, 0) 558 | SSC_BF(RFMR_DATNB, (channels - 1)) 559 | SSC_BIT(RFMR_MSBF) 560 | SSC_BF(RFMR_LOOP, 0) 561 | SSC_BF(RFMR_DATLEN, (bits - 1)); 562 563 tcmr = SSC_BF(TCMR_PERIOD, 0) 564 | SSC_BF(TCMR_STTDLY, START_DELAY) 565 | SSC_BF(TCMR_START, SSC_START_RISING_RF) 566 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) 567 | SSC_BF(TCMR_CKO, SSC_CKO_NONE) 568 | SSC_BF(TCMR_CKS, SSC_CKS_PIN); 569 570 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) 571 | SSC_BF(TFMR_FSDEN, 0) 572 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) 573 | SSC_BF(TFMR_FSLEN, 0) 574 | SSC_BF(TFMR_DATNB, (channels - 1)) 575 | SSC_BIT(TFMR_MSBF) 576 | SSC_BF(TFMR_DATDEF, 0) 577 | SSC_BF(TFMR_DATLEN, (bits - 1)); 578 break; 579 580 default: 581 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n", 582 ssc_p->daifmt); 583 return -EINVAL; 584 } 585 pr_debug("atmel_ssc_hw_params: " 586 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", 587 rcmr, rfmr, tcmr, tfmr); 588 589 if (!ssc_p->initialized) { 590 591 /* Enable PMC peripheral clock for this SSC */ 592 pr_debug("atmel_ssc_dai: Starting clock\n"); 593 clk_enable(ssc_p->ssc->clk); 594 595 /* Reset the SSC and its PDC registers */ 596 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); 597 598 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0); 599 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0); 600 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0); 601 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0); 602 603 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0); 604 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0); 605 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0); 606 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0); 607 608 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0, 609 ssc_p->name, ssc_p); 610 if (ret < 0) { 611 printk(KERN_WARNING 612 "atmel_ssc_dai: request_irq failure\n"); 613 pr_debug("Atmel_ssc_dai: Stoping clock\n"); 614 clk_disable(ssc_p->ssc->clk); 615 return ret; 616 } 617 618 ssc_p->initialized = 1; 619 } 620 621 /* set SSC clock mode register */ 622 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div); 623 624 /* set receive clock mode and format */ 625 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr); 626 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr); 627 628 /* set transmit clock mode and format */ 629 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr); 630 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr); 631 632 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n"); 633 return 0; 634 } 635 636 637 static int atmel_ssc_prepare(struct snd_pcm_substream *substream, 638 struct snd_soc_dai *dai) 639 { 640 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 641 struct atmel_pcm_dma_params *dma_params; 642 int dir; 643 644 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 645 dir = 0; 646 else 647 dir = 1; 648 649 dma_params = ssc_p->dma_params[dir]; 650 651 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable); 652 ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error); 653 654 pr_debug("%s enabled SSC_SR=0x%08x\n", 655 dir ? "receive" : "transmit", 656 ssc_readl(ssc_p->ssc->regs, SR)); 657 return 0; 658 } 659 660 661 #ifdef CONFIG_PM 662 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai) 663 { 664 struct atmel_ssc_info *ssc_p; 665 666 if (!cpu_dai->active) 667 return 0; 668 669 ssc_p = &ssc_info[cpu_dai->id]; 670 671 /* Save the status register before disabling transmit and receive */ 672 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR); 673 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS)); 674 675 /* Save the current interrupt mask, then disable unmasked interrupts */ 676 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR); 677 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr); 678 679 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR); 680 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR); 681 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR); 682 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR); 683 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR); 684 685 return 0; 686 } 687 688 689 690 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai) 691 { 692 struct atmel_ssc_info *ssc_p; 693 u32 cr; 694 695 if (!cpu_dai->active) 696 return 0; 697 698 ssc_p = &ssc_info[cpu_dai->id]; 699 700 /* restore SSC register settings */ 701 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr); 702 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr); 703 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr); 704 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr); 705 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr); 706 707 /* re-enable interrupts */ 708 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr); 709 710 /* Re-enable receive and transmit as appropriate */ 711 cr = 0; 712 cr |= 713 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0; 714 cr |= 715 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0; 716 ssc_writel(ssc_p->ssc->regs, CR, cr); 717 718 return 0; 719 } 720 #else /* CONFIG_PM */ 721 # define atmel_ssc_suspend NULL 722 # define atmel_ssc_resume NULL 723 #endif /* CONFIG_PM */ 724 725 #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000) 726 727 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 728 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 729 730 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = { 731 .startup = atmel_ssc_startup, 732 .shutdown = atmel_ssc_shutdown, 733 .prepare = atmel_ssc_prepare, 734 .hw_params = atmel_ssc_hw_params, 735 .set_fmt = atmel_ssc_set_dai_fmt, 736 .set_clkdiv = atmel_ssc_set_dai_clkdiv, 737 }; 738 739 static struct snd_soc_dai_driver atmel_ssc_dai = { 740 .suspend = atmel_ssc_suspend, 741 .resume = atmel_ssc_resume, 742 .playback = { 743 .channels_min = 1, 744 .channels_max = 2, 745 .rates = ATMEL_SSC_RATES, 746 .formats = ATMEL_SSC_FORMATS,}, 747 .capture = { 748 .channels_min = 1, 749 .channels_max = 2, 750 .rates = ATMEL_SSC_RATES, 751 .formats = ATMEL_SSC_FORMATS,}, 752 .ops = &atmel_ssc_dai_ops, 753 }; 754 755 static const struct snd_soc_component_driver atmel_ssc_component = { 756 .name = "atmel-ssc", 757 }; 758 759 static int asoc_ssc_init(struct device *dev) 760 { 761 struct platform_device *pdev = to_platform_device(dev); 762 struct ssc_device *ssc = platform_get_drvdata(pdev); 763 int ret; 764 765 ret = snd_soc_register_component(dev, &atmel_ssc_component, 766 &atmel_ssc_dai, 1); 767 if (ret) { 768 dev_err(dev, "Could not register DAI: %d\n", ret); 769 goto err; 770 } 771 772 if (ssc->pdata->use_dma) 773 ret = atmel_pcm_dma_platform_register(dev); 774 else 775 ret = atmel_pcm_pdc_platform_register(dev); 776 777 if (ret) { 778 dev_err(dev, "Could not register PCM: %d\n", ret); 779 goto err_unregister_dai; 780 }; 781 782 return 0; 783 784 err_unregister_dai: 785 snd_soc_unregister_component(dev); 786 err: 787 return ret; 788 } 789 790 static void asoc_ssc_exit(struct device *dev) 791 { 792 struct platform_device *pdev = to_platform_device(dev); 793 struct ssc_device *ssc = platform_get_drvdata(pdev); 794 795 if (ssc->pdata->use_dma) 796 atmel_pcm_dma_platform_unregister(dev); 797 else 798 atmel_pcm_pdc_platform_unregister(dev); 799 800 snd_soc_unregister_component(dev); 801 } 802 803 /** 804 * atmel_ssc_set_audio - Allocate the specified SSC for audio use. 805 */ 806 int atmel_ssc_set_audio(int ssc_id) 807 { 808 struct ssc_device *ssc; 809 int ret; 810 811 /* If we can grab the SSC briefly to parent the DAI device off it */ 812 ssc = ssc_request(ssc_id); 813 if (IS_ERR(ssc)) { 814 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n", 815 PTR_ERR(ssc)); 816 return PTR_ERR(ssc); 817 } else { 818 ssc_info[ssc_id].ssc = ssc; 819 } 820 821 ret = asoc_ssc_init(&ssc->pdev->dev); 822 823 return ret; 824 } 825 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio); 826 827 void atmel_ssc_put_audio(int ssc_id) 828 { 829 struct ssc_device *ssc = ssc_info[ssc_id].ssc; 830 831 asoc_ssc_exit(&ssc->pdev->dev); 832 ssc_free(ssc); 833 } 834 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio); 835 836 /* Module information */ 837 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com"); 838 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface"); 839 MODULE_LICENSE("GPL"); 840