1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Atmel I2S controller 4 * 5 * Copyright (C) 2015 Atmel Corporation 6 * 7 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com> 8 */ 9 10 #include <linux/init.h> 11 #include <linux/module.h> 12 #include <linux/device.h> 13 #include <linux/slab.h> 14 #include <linux/delay.h> 15 #include <linux/io.h> 16 #include <linux/clk.h> 17 #include <linux/mfd/syscon.h> 18 19 #include <sound/core.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/initval.h> 23 #include <sound/soc.h> 24 #include <sound/dmaengine_pcm.h> 25 26 #define ATMEL_I2SC_MAX_TDM_CHANNELS 8 27 28 /* 29 * ---- I2S Controller Register map ---- 30 */ 31 #define ATMEL_I2SC_CR 0x0000 /* Control Register */ 32 #define ATMEL_I2SC_MR 0x0004 /* Mode Register */ 33 #define ATMEL_I2SC_SR 0x0008 /* Status Register */ 34 #define ATMEL_I2SC_SCR 0x000c /* Status Clear Register */ 35 #define ATMEL_I2SC_SSR 0x0010 /* Status Set Register */ 36 #define ATMEL_I2SC_IER 0x0014 /* Interrupt Enable Register */ 37 #define ATMEL_I2SC_IDR 0x0018 /* Interrupt Disable Register */ 38 #define ATMEL_I2SC_IMR 0x001c /* Interrupt Mask Register */ 39 #define ATMEL_I2SC_RHR 0x0020 /* Receiver Holding Register */ 40 #define ATMEL_I2SC_THR 0x0024 /* Transmitter Holding Register */ 41 #define ATMEL_I2SC_VERSION 0x0028 /* Version Register */ 42 43 /* 44 * ---- Control Register (Write-only) ---- 45 */ 46 #define ATMEL_I2SC_CR_RXEN BIT(0) /* Receiver Enable */ 47 #define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */ 48 #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */ 49 #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */ 50 #define ATMEL_I2SC_CR_TXEN BIT(4) /* Transmitter Enable */ 51 #define ATMEL_I2SC_CR_TXDIS BIT(5) /* Transmitter Disable */ 52 #define ATMEL_I2SC_CR_SWRST BIT(7) /* Software Reset */ 53 54 /* 55 * ---- Mode Register (Read/Write) ---- 56 */ 57 #define ATMEL_I2SC_MR_MODE_MASK GENMASK(0, 0) 58 #define ATMEL_I2SC_MR_MODE_SLAVE (0 << 0) 59 #define ATMEL_I2SC_MR_MODE_MASTER (1 << 0) 60 61 #define ATMEL_I2SC_MR_DATALENGTH_MASK GENMASK(4, 2) 62 #define ATMEL_I2SC_MR_DATALENGTH_32_BITS (0 << 2) 63 #define ATMEL_I2SC_MR_DATALENGTH_24_BITS (1 << 2) 64 #define ATMEL_I2SC_MR_DATALENGTH_20_BITS (2 << 2) 65 #define ATMEL_I2SC_MR_DATALENGTH_18_BITS (3 << 2) 66 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS (4 << 2) 67 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT (5 << 2) 68 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS (6 << 2) 69 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT (7 << 2) 70 71 #define ATMEL_I2SC_MR_FORMAT_MASK GENMASK(7, 6) 72 #define ATMEL_I2SC_MR_FORMAT_I2S (0 << 6) 73 #define ATMEL_I2SC_MR_FORMAT_LJ (1 << 6) /* Left Justified */ 74 #define ATMEL_I2SC_MR_FORMAT_TDM (2 << 6) 75 #define ATMEL_I2SC_MR_FORMAT_TDMLJ (3 << 6) 76 77 /* Left audio samples duplicated to right audio channel */ 78 #define ATMEL_I2SC_MR_RXMONO BIT(8) 79 80 /* Receiver uses one DMA channel ... */ 81 #define ATMEL_I2SC_MR_RXDMA_MASK GENMASK(9, 9) 82 #define ATMEL_I2SC_MR_RXDMA_SINGLE (0 << 9) /* for all audio channels */ 83 #define ATMEL_I2SC_MR_RXDMA_MULTIPLE (1 << 9) /* per audio channel */ 84 85 /* I2SDO output of I2SC is internally connected to I2SDI input */ 86 #define ATMEL_I2SC_MR_RXLOOP BIT(10) 87 88 /* Left audio samples duplicated to right audio channel */ 89 #define ATMEL_I2SC_MR_TXMONO BIT(12) 90 91 /* Transmitter uses one DMA channel ... */ 92 #define ATMEL_I2SC_MR_TXDMA_MASK GENMASK(13, 13) 93 #define ATMEL_I2SC_MR_TXDMA_SINGLE (0 << 13) /* for all audio channels */ 94 #define ATMEL_I2SC_MR_TXDME_MULTIPLE (1 << 13) /* per audio channel */ 95 96 /* x sample transmitted when underrun */ 97 #define ATMEL_I2SC_MR_TXSAME_MASK GENMASK(14, 14) 98 #define ATMEL_I2SC_MR_TXSAME_ZERO (0 << 14) /* Zero sample */ 99 #define ATMEL_I2SC_MR_TXSAME_PREVIOUS (1 << 14) /* Previous sample */ 100 101 /* Audio Clock to I2SC Master Clock ratio */ 102 #define ATMEL_I2SC_MR_IMCKDIV_MASK GENMASK(21, 16) 103 #define ATMEL_I2SC_MR_IMCKDIV(div) \ 104 (((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK) 105 106 /* Master Clock to fs ratio */ 107 #define ATMEL_I2SC_MR_IMCKFS_MASK GENMASK(29, 24) 108 #define ATMEL_I2SC_MR_IMCKFS(fs) \ 109 (((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK) 110 111 /* Master Clock mode */ 112 #define ATMEL_I2SC_MR_IMCKMODE_MASK GENMASK(30, 30) 113 /* 0: No master clock generated (selected clock drives I2SCK pin) */ 114 #define ATMEL_I2SC_MR_IMCKMODE_I2SCK (0 << 30) 115 /* 1: master clock generated (internally generated clock drives I2SMCK pin) */ 116 #define ATMEL_I2SC_MR_IMCKMODE_I2SMCK (1 << 30) 117 118 /* Slot Width */ 119 /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */ 120 /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */ 121 #define ATMEL_I2SC_MR_IWS BIT(31) 122 123 /* 124 * ---- Status Registers ---- 125 */ 126 #define ATMEL_I2SC_SR_RXEN BIT(0) /* Receiver Enabled */ 127 #define ATMEL_I2SC_SR_RXRDY BIT(1) /* Receive Ready */ 128 #define ATMEL_I2SC_SR_RXOR BIT(2) /* Receive Overrun */ 129 130 #define ATMEL_I2SC_SR_TXEN BIT(4) /* Transmitter Enabled */ 131 #define ATMEL_I2SC_SR_TXRDY BIT(5) /* Transmit Ready */ 132 #define ATMEL_I2SC_SR_TXUR BIT(6) /* Transmit Underrun */ 133 134 /* Receive Overrun Channel */ 135 #define ATMEL_I2SC_SR_RXORCH_MASK GENMASK(15, 8) 136 #define ATMEL_I2SC_SR_RXORCH(ch) (1 << (((ch) & 0x7) + 8)) 137 138 /* Transmit Underrun Channel */ 139 #define ATMEL_I2SC_SR_TXURCH_MASK GENMASK(27, 20) 140 #define ATMEL_I2SC_SR_TXURCH(ch) (1 << (((ch) & 0x7) + 20)) 141 142 /* 143 * ---- Interrupt Enable/Disable/Mask Registers ---- 144 */ 145 #define ATMEL_I2SC_INT_RXRDY ATMEL_I2SC_SR_RXRDY 146 #define ATMEL_I2SC_INT_RXOR ATMEL_I2SC_SR_RXOR 147 #define ATMEL_I2SC_INT_TXRDY ATMEL_I2SC_SR_TXRDY 148 #define ATMEL_I2SC_INT_TXUR ATMEL_I2SC_SR_TXUR 149 150 static const struct regmap_config atmel_i2s_regmap_config = { 151 .reg_bits = 32, 152 .reg_stride = 4, 153 .val_bits = 32, 154 .max_register = ATMEL_I2SC_VERSION, 155 }; 156 157 struct atmel_i2s_gck_param { 158 int fs; 159 unsigned long mck; 160 int imckdiv; 161 int imckfs; 162 }; 163 164 #define I2S_MCK_12M288 12288000UL 165 #define I2S_MCK_11M2896 11289600UL 166 167 /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */ 168 static const struct atmel_i2s_gck_param gck_params[] = { 169 /* mck = 12.288MHz */ 170 { 8000, I2S_MCK_12M288, 0, 47}, /* mck = 1536 fs */ 171 { 16000, I2S_MCK_12M288, 1, 47}, /* mck = 768 fs */ 172 { 24000, I2S_MCK_12M288, 3, 63}, /* mck = 512 fs */ 173 { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */ 174 { 48000, I2S_MCK_12M288, 7, 63}, /* mck = 256 fs */ 175 { 64000, I2S_MCK_12M288, 7, 47}, /* mck = 192 fs */ 176 { 96000, I2S_MCK_12M288, 7, 31}, /* mck = 128 fs */ 177 {192000, I2S_MCK_12M288, 7, 15}, /* mck = 64 fs */ 178 179 /* mck = 11.2896MHz */ 180 { 11025, I2S_MCK_11M2896, 1, 63}, /* mck = 1024 fs */ 181 { 22050, I2S_MCK_11M2896, 3, 63}, /* mck = 512 fs */ 182 { 44100, I2S_MCK_11M2896, 7, 63}, /* mck = 256 fs */ 183 { 88200, I2S_MCK_11M2896, 7, 31}, /* mck = 128 fs */ 184 {176400, I2S_MCK_11M2896, 7, 15}, /* mck = 64 fs */ 185 }; 186 187 struct atmel_i2s_dev; 188 189 struct atmel_i2s_caps { 190 int (*mck_init)(struct atmel_i2s_dev *, struct device_node *np); 191 }; 192 193 struct atmel_i2s_dev { 194 struct device *dev; 195 struct regmap *regmap; 196 struct clk *pclk; 197 struct clk *gclk; 198 struct snd_dmaengine_dai_dma_data playback; 199 struct snd_dmaengine_dai_dma_data capture; 200 unsigned int fmt; 201 const struct atmel_i2s_gck_param *gck_param; 202 const struct atmel_i2s_caps *caps; 203 int clk_use_no; 204 }; 205 206 static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id) 207 { 208 struct atmel_i2s_dev *dev = dev_id; 209 unsigned int sr, imr, pending, ch, mask; 210 irqreturn_t ret = IRQ_NONE; 211 212 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr); 213 regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr); 214 pending = sr & imr; 215 216 if (!pending) 217 return IRQ_NONE; 218 219 if (pending & ATMEL_I2SC_INT_RXOR) { 220 mask = ATMEL_I2SC_SR_RXOR; 221 222 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) { 223 if (sr & ATMEL_I2SC_SR_RXORCH(ch)) { 224 mask |= ATMEL_I2SC_SR_RXORCH(ch); 225 dev_err(dev->dev, 226 "RX overrun on channel %d\n", ch); 227 } 228 } 229 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask); 230 ret = IRQ_HANDLED; 231 } 232 233 if (pending & ATMEL_I2SC_INT_TXUR) { 234 mask = ATMEL_I2SC_SR_TXUR; 235 236 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) { 237 if (sr & ATMEL_I2SC_SR_TXURCH(ch)) { 238 mask |= ATMEL_I2SC_SR_TXURCH(ch); 239 dev_err(dev->dev, 240 "TX underrun on channel %d\n", ch); 241 } 242 } 243 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask); 244 ret = IRQ_HANDLED; 245 } 246 247 return ret; 248 } 249 250 #define ATMEL_I2S_RATES SNDRV_PCM_RATE_8000_192000 251 252 #define ATMEL_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 253 SNDRV_PCM_FMTBIT_S16_LE | \ 254 SNDRV_PCM_FMTBIT_S18_3LE | \ 255 SNDRV_PCM_FMTBIT_S20_3LE | \ 256 SNDRV_PCM_FMTBIT_S24_3LE | \ 257 SNDRV_PCM_FMTBIT_S24_LE | \ 258 SNDRV_PCM_FMTBIT_S32_LE) 259 260 static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 261 { 262 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 263 264 dev->fmt = fmt; 265 return 0; 266 } 267 268 static int atmel_i2s_prepare(struct snd_pcm_substream *substream, 269 struct snd_soc_dai *dai) 270 { 271 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 272 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 273 unsigned int rhr, sr = 0; 274 275 if (is_playback) { 276 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr); 277 if (sr & ATMEL_I2SC_SR_RXRDY) { 278 /* 279 * The RX Ready flag should not be set. However if here, 280 * we flush (read) the Receive Holding Register to start 281 * from a clean state. 282 */ 283 dev_dbg(dev->dev, "RXRDY is set\n"); 284 regmap_read(dev->regmap, ATMEL_I2SC_RHR, &rhr); 285 } 286 } 287 288 return 0; 289 } 290 291 static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs) 292 { 293 int i, best; 294 295 if (!dev->gclk) { 296 dev_err(dev->dev, "cannot generate the I2S Master Clock\n"); 297 return -EINVAL; 298 } 299 300 /* 301 * Find the best possible settings to generate the I2S Master Clock 302 * from the PLL Audio. 303 */ 304 dev->gck_param = NULL; 305 best = INT_MAX; 306 for (i = 0; i < ARRAY_SIZE(gck_params); ++i) { 307 const struct atmel_i2s_gck_param *gck_param = &gck_params[i]; 308 int val = abs(fs - gck_param->fs); 309 310 if (val < best) { 311 best = val; 312 dev->gck_param = gck_param; 313 } 314 } 315 316 return 0; 317 } 318 319 static int atmel_i2s_hw_params(struct snd_pcm_substream *substream, 320 struct snd_pcm_hw_params *params, 321 struct snd_soc_dai *dai) 322 { 323 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 324 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 325 unsigned int mr = 0, mr_mask; 326 int ret; 327 328 mr_mask = ATMEL_I2SC_MR_FORMAT_MASK | ATMEL_I2SC_MR_MODE_MASK | 329 ATMEL_I2SC_MR_DATALENGTH_MASK; 330 if (is_playback) 331 mr_mask |= ATMEL_I2SC_MR_TXMONO; 332 else 333 mr_mask |= ATMEL_I2SC_MR_RXMONO; 334 335 switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 336 case SND_SOC_DAIFMT_I2S: 337 mr |= ATMEL_I2SC_MR_FORMAT_I2S; 338 break; 339 340 default: 341 dev_err(dev->dev, "unsupported bus format\n"); 342 return -EINVAL; 343 } 344 345 switch (dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 346 case SND_SOC_DAIFMT_CBC_CFC: 347 /* codec is slave, so cpu is master */ 348 mr |= ATMEL_I2SC_MR_MODE_MASTER; 349 ret = atmel_i2s_get_gck_param(dev, params_rate(params)); 350 if (ret) 351 return ret; 352 break; 353 354 case SND_SOC_DAIFMT_CBP_CFP: 355 /* codec is master, so cpu is slave */ 356 mr |= ATMEL_I2SC_MR_MODE_SLAVE; 357 dev->gck_param = NULL; 358 break; 359 360 default: 361 dev_err(dev->dev, "unsupported master/slave mode\n"); 362 return -EINVAL; 363 } 364 365 switch (params_channels(params)) { 366 case 1: 367 if (is_playback) 368 mr |= ATMEL_I2SC_MR_TXMONO; 369 else 370 mr |= ATMEL_I2SC_MR_RXMONO; 371 break; 372 case 2: 373 break; 374 default: 375 dev_err(dev->dev, "unsupported number of audio channels\n"); 376 return -EINVAL; 377 } 378 379 switch (params_format(params)) { 380 case SNDRV_PCM_FORMAT_S8: 381 mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS; 382 break; 383 384 case SNDRV_PCM_FORMAT_S16_LE: 385 mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS; 386 break; 387 388 case SNDRV_PCM_FORMAT_S18_3LE: 389 mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS; 390 break; 391 392 case SNDRV_PCM_FORMAT_S20_3LE: 393 mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS; 394 break; 395 396 case SNDRV_PCM_FORMAT_S24_3LE: 397 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS | ATMEL_I2SC_MR_IWS; 398 break; 399 400 case SNDRV_PCM_FORMAT_S24_LE: 401 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS; 402 break; 403 404 case SNDRV_PCM_FORMAT_S32_LE: 405 mr |= ATMEL_I2SC_MR_DATALENGTH_32_BITS; 406 break; 407 408 default: 409 dev_err(dev->dev, "unsupported size/endianness for audio samples\n"); 410 return -EINVAL; 411 } 412 413 return regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr); 414 } 415 416 static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev, 417 bool enabled) 418 { 419 unsigned int mr, mr_mask; 420 unsigned long gclk_rate; 421 int ret; 422 423 mr = 0; 424 mr_mask = (ATMEL_I2SC_MR_IMCKDIV_MASK | 425 ATMEL_I2SC_MR_IMCKFS_MASK | 426 ATMEL_I2SC_MR_IMCKMODE_MASK); 427 428 if (!enabled) { 429 /* Disable the I2S Master Clock generator. */ 430 ret = regmap_write(dev->regmap, ATMEL_I2SC_CR, 431 ATMEL_I2SC_CR_CKDIS); 432 if (ret) 433 return ret; 434 435 /* Reset the I2S Master Clock generator settings. */ 436 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, 437 mr_mask, mr); 438 if (ret) 439 return ret; 440 441 /* Disable/unprepare the PMC generated clock. */ 442 clk_disable_unprepare(dev->gclk); 443 444 return 0; 445 } 446 447 if (!dev->gck_param) 448 return -EINVAL; 449 450 gclk_rate = dev->gck_param->mck * (dev->gck_param->imckdiv + 1); 451 452 ret = clk_set_rate(dev->gclk, gclk_rate); 453 if (ret) 454 return ret; 455 456 ret = clk_prepare_enable(dev->gclk); 457 if (ret) 458 return ret; 459 460 /* Update the Mode Register to generate the I2S Master Clock. */ 461 mr |= ATMEL_I2SC_MR_IMCKDIV(dev->gck_param->imckdiv); 462 mr |= ATMEL_I2SC_MR_IMCKFS(dev->gck_param->imckfs); 463 mr |= ATMEL_I2SC_MR_IMCKMODE_I2SMCK; 464 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr); 465 if (ret) 466 return ret; 467 468 /* Finally enable the I2S Master Clock generator. */ 469 return regmap_write(dev->regmap, ATMEL_I2SC_CR, 470 ATMEL_I2SC_CR_CKEN); 471 } 472 473 static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 474 struct snd_soc_dai *dai) 475 { 476 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 477 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 478 bool is_master, mck_enabled; 479 unsigned int cr, mr; 480 int err; 481 482 switch (cmd) { 483 case SNDRV_PCM_TRIGGER_START: 484 case SNDRV_PCM_TRIGGER_RESUME: 485 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 486 cr = is_playback ? ATMEL_I2SC_CR_TXEN : ATMEL_I2SC_CR_RXEN; 487 mck_enabled = true; 488 break; 489 case SNDRV_PCM_TRIGGER_STOP: 490 case SNDRV_PCM_TRIGGER_SUSPEND: 491 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 492 cr = is_playback ? ATMEL_I2SC_CR_TXDIS : ATMEL_I2SC_CR_RXDIS; 493 mck_enabled = false; 494 break; 495 default: 496 return -EINVAL; 497 } 498 499 /* Read the Mode Register to retrieve the master/slave state. */ 500 err = regmap_read(dev->regmap, ATMEL_I2SC_MR, &mr); 501 if (err) 502 return err; 503 is_master = (mr & ATMEL_I2SC_MR_MODE_MASK) == ATMEL_I2SC_MR_MODE_MASTER; 504 505 /* If master starts, enable the audio clock. */ 506 if (is_master && mck_enabled) { 507 if (!dev->clk_use_no) { 508 err = atmel_i2s_switch_mck_generator(dev, true); 509 if (err) 510 return err; 511 } 512 dev->clk_use_no++; 513 } 514 515 err = regmap_write(dev->regmap, ATMEL_I2SC_CR, cr); 516 if (err) 517 return err; 518 519 /* If master stops, disable the audio clock. */ 520 if (is_master && !mck_enabled) { 521 if (dev->clk_use_no == 1) { 522 err = atmel_i2s_switch_mck_generator(dev, false); 523 if (err) 524 return err; 525 } 526 dev->clk_use_no--; 527 } 528 529 return err; 530 } 531 532 static const struct snd_soc_dai_ops atmel_i2s_dai_ops = { 533 .prepare = atmel_i2s_prepare, 534 .trigger = atmel_i2s_trigger, 535 .hw_params = atmel_i2s_hw_params, 536 .set_fmt = atmel_i2s_set_dai_fmt, 537 }; 538 539 static int atmel_i2s_dai_probe(struct snd_soc_dai *dai) 540 { 541 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 542 543 snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture); 544 return 0; 545 } 546 547 static struct snd_soc_dai_driver atmel_i2s_dai = { 548 .probe = atmel_i2s_dai_probe, 549 .playback = { 550 .channels_min = 1, 551 .channels_max = 2, 552 .rates = ATMEL_I2S_RATES, 553 .formats = ATMEL_I2S_FORMATS, 554 }, 555 .capture = { 556 .channels_min = 1, 557 .channels_max = 2, 558 .rates = ATMEL_I2S_RATES, 559 .formats = ATMEL_I2S_FORMATS, 560 }, 561 .ops = &atmel_i2s_dai_ops, 562 .symmetric_rate = 1, 563 .symmetric_sample_bits = 1, 564 }; 565 566 static const struct snd_soc_component_driver atmel_i2s_component = { 567 .name = "atmel-i2s", 568 }; 569 570 static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev, 571 struct device_node *np) 572 { 573 struct clk *muxclk; 574 int err; 575 576 if (!dev->gclk) 577 return 0; 578 579 /* muxclk is optional, so we return error for probe defer only */ 580 muxclk = devm_clk_get(dev->dev, "muxclk"); 581 if (IS_ERR(muxclk)) { 582 err = PTR_ERR(muxclk); 583 if (err == -EPROBE_DEFER) 584 return -EPROBE_DEFER; 585 dev_dbg(dev->dev, 586 "failed to get the I2S clock control: %d\n", err); 587 return 0; 588 } 589 590 return clk_set_parent(muxclk, dev->gclk); 591 } 592 593 static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = { 594 .mck_init = atmel_i2s_sama5d2_mck_init, 595 }; 596 597 static const struct of_device_id atmel_i2s_dt_ids[] = { 598 { 599 .compatible = "atmel,sama5d2-i2s", 600 .data = (void *)&atmel_i2s_sama5d2_caps, 601 }, 602 603 { /* sentinel */ } 604 }; 605 606 MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids); 607 608 static int atmel_i2s_probe(struct platform_device *pdev) 609 { 610 struct device_node *np = pdev->dev.of_node; 611 const struct of_device_id *match; 612 struct atmel_i2s_dev *dev; 613 struct resource *mem; 614 struct regmap *regmap; 615 void __iomem *base; 616 int irq; 617 int err; 618 unsigned int pcm_flags = 0; 619 unsigned int version; 620 621 /* Get memory for driver data. */ 622 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 623 if (!dev) 624 return -ENOMEM; 625 626 /* Get hardware capabilities. */ 627 match = of_match_node(atmel_i2s_dt_ids, np); 628 if (match) 629 dev->caps = match->data; 630 631 /* Map I/O registers. */ 632 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 633 if (IS_ERR(base)) 634 return PTR_ERR(base); 635 636 regmap = devm_regmap_init_mmio(&pdev->dev, base, 637 &atmel_i2s_regmap_config); 638 if (IS_ERR(regmap)) 639 return PTR_ERR(regmap); 640 641 /* Request IRQ. */ 642 irq = platform_get_irq(pdev, 0); 643 if (irq < 0) 644 return irq; 645 646 err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0, 647 dev_name(&pdev->dev), dev); 648 if (err) 649 return err; 650 651 /* Get the peripheral clock. */ 652 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 653 if (IS_ERR(dev->pclk)) { 654 err = PTR_ERR(dev->pclk); 655 dev_err(&pdev->dev, 656 "failed to get the peripheral clock: %d\n", err); 657 return err; 658 } 659 660 /* Get audio clock to generate the I2S Master Clock (I2S_MCK) */ 661 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 662 if (IS_ERR(dev->gclk)) { 663 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER) 664 return -EPROBE_DEFER; 665 /* Master Mode not supported */ 666 dev->gclk = NULL; 667 } 668 dev->dev = &pdev->dev; 669 dev->regmap = regmap; 670 platform_set_drvdata(pdev, dev); 671 672 /* Do hardware specific settings to initialize I2S_MCK generator */ 673 if (dev->caps && dev->caps->mck_init) { 674 err = dev->caps->mck_init(dev, np); 675 if (err) 676 return err; 677 } 678 679 /* Enable the peripheral clock. */ 680 err = clk_prepare_enable(dev->pclk); 681 if (err) 682 return err; 683 684 /* Get IP version. */ 685 regmap_read(dev->regmap, ATMEL_I2SC_VERSION, &version); 686 dev_info(&pdev->dev, "hw version: %#x\n", version); 687 688 /* Enable error interrupts. */ 689 regmap_write(dev->regmap, ATMEL_I2SC_IER, 690 ATMEL_I2SC_INT_RXOR | ATMEL_I2SC_INT_TXUR); 691 692 err = devm_snd_soc_register_component(&pdev->dev, 693 &atmel_i2s_component, 694 &atmel_i2s_dai, 1); 695 if (err) { 696 dev_err(&pdev->dev, "failed to register DAI: %d\n", err); 697 clk_disable_unprepare(dev->pclk); 698 return err; 699 } 700 701 /* Prepare DMA config. */ 702 dev->playback.addr = (dma_addr_t)mem->start + ATMEL_I2SC_THR; 703 dev->playback.maxburst = 1; 704 dev->capture.addr = (dma_addr_t)mem->start + ATMEL_I2SC_RHR; 705 dev->capture.maxburst = 1; 706 707 if (of_property_match_string(np, "dma-names", "rx-tx") == 0) 708 pcm_flags |= SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX; 709 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, pcm_flags); 710 if (err) { 711 dev_err(&pdev->dev, "failed to register PCM: %d\n", err); 712 clk_disable_unprepare(dev->pclk); 713 return err; 714 } 715 716 return 0; 717 } 718 719 static int atmel_i2s_remove(struct platform_device *pdev) 720 { 721 struct atmel_i2s_dev *dev = platform_get_drvdata(pdev); 722 723 clk_disable_unprepare(dev->pclk); 724 725 return 0; 726 } 727 728 static struct platform_driver atmel_i2s_driver = { 729 .driver = { 730 .name = "atmel_i2s", 731 .of_match_table = of_match_ptr(atmel_i2s_dt_ids), 732 }, 733 .probe = atmel_i2s_probe, 734 .remove = atmel_i2s_remove, 735 }; 736 module_platform_driver(atmel_i2s_driver); 737 738 MODULE_DESCRIPTION("Atmel I2S Controller driver"); 739 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>"); 740 MODULE_LICENSE("GPL v2"); 741