1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ACP 6.x Register Documentation 4 * 5 * Copyright 2021 Advanced Micro Devices, Inc. 6 */ 7 8 #ifndef _acp6x_OFFSET_HEADER 9 #define _acp6x_OFFSET_HEADER 10 11 /* Registers from ACP_DMA block */ 12 #define ACP_DMA_CNTL_0 0x1240000 13 #define ACP_DMA_CNTL_1 0x1240004 14 #define ACP_DMA_CNTL_2 0x1240008 15 #define ACP_DMA_CNTL_3 0x124000C 16 #define ACP_DMA_CNTL_4 0x1240010 17 #define ACP_DMA_CNTL_5 0x1240014 18 #define ACP_DMA_CNTL_6 0x1240018 19 #define ACP_DMA_CNTL_7 0x124001C 20 #define ACP_DMA_DSCR_STRT_IDX_0 0x1240020 21 #define ACP_DMA_DSCR_STRT_IDX_1 0x1240024 22 #define ACP_DMA_DSCR_STRT_IDX_2 0x1240028 23 #define ACP_DMA_DSCR_STRT_IDX_3 0x124002C 24 #define ACP_DMA_DSCR_STRT_IDX_4 0x1240030 25 #define ACP_DMA_DSCR_STRT_IDX_5 0x1240034 26 #define ACP_DMA_DSCR_STRT_IDX_6 0x1240038 27 #define ACP_DMA_DSCR_STRT_IDX_7 0x124003C 28 #define ACP_DMA_DSCR_CNT_0 0x1240040 29 #define ACP_DMA_DSCR_CNT_1 0x1240044 30 #define ACP_DMA_DSCR_CNT_2 0x1240048 31 #define ACP_DMA_DSCR_CNT_3 0x124004C 32 #define ACP_DMA_DSCR_CNT_4 0x1240050 33 #define ACP_DMA_DSCR_CNT_5 0x1240054 34 #define ACP_DMA_DSCR_CNT_6 0x1240058 35 #define ACP_DMA_DSCR_CNT_7 0x124005C 36 #define ACP_DMA_PRIO_0 0x1240060 37 #define ACP_DMA_PRIO_1 0x1240064 38 #define ACP_DMA_PRIO_2 0x1240068 39 #define ACP_DMA_PRIO_3 0x124006C 40 #define ACP_DMA_PRIO_4 0x1240070 41 #define ACP_DMA_PRIO_5 0x1240074 42 #define ACP_DMA_PRIO_6 0x1240078 43 #define ACP_DMA_PRIO_7 0x124007C 44 #define ACP_DMA_CUR_DSCR_0 0x1240080 45 #define ACP_DMA_CUR_DSCR_1 0x1240084 46 #define ACP_DMA_CUR_DSCR_2 0x1240088 47 #define ACP_DMA_CUR_DSCR_3 0x124008C 48 #define ACP_DMA_CUR_DSCR_4 0x1240090 49 #define ACP_DMA_CUR_DSCR_5 0x1240094 50 #define ACP_DMA_CUR_DSCR_6 0x1240098 51 #define ACP_DMA_CUR_DSCR_7 0x124009C 52 #define ACP_DMA_CUR_TRANS_CNT_0 0x12400A0 53 #define ACP_DMA_CUR_TRANS_CNT_1 0x12400A4 54 #define ACP_DMA_CUR_TRANS_CNT_2 0x12400A8 55 #define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC 56 #define ACP_DMA_CUR_TRANS_CNT_4 0x12400B0 57 #define ACP_DMA_CUR_TRANS_CNT_5 0x12400B4 58 #define ACP_DMA_CUR_TRANS_CNT_6 0x12400B8 59 #define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC 60 #define ACP_DMA_ERR_STS_0 0x12400C0 61 #define ACP_DMA_ERR_STS_1 0x12400C4 62 #define ACP_DMA_ERR_STS_2 0x12400C8 63 #define ACP_DMA_ERR_STS_3 0x12400CC 64 #define ACP_DMA_ERR_STS_4 0x12400D0 65 #define ACP_DMA_ERR_STS_5 0x12400D4 66 #define ACP_DMA_ERR_STS_6 0x12400D8 67 #define ACP_DMA_ERR_STS_7 0x12400DC 68 #define ACP_DMA_DESC_BASE_ADDR 0x12400E0 69 #define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4 70 #define ACP_DMA_CH_STS 0x12400E8 71 #define ACP_DMA_CH_GROUP 0x12400EC 72 #define ACP_DMA_CH_RST_STS 0x12400F0 73 74 /* Registers from ACP_AXI2AXIATU block */ 75 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C00 76 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C04 77 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C08 78 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C 79 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C10 80 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C14 81 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C18 82 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C 83 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C20 84 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C24 85 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C28 86 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C 87 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C30 88 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C34 89 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C38 90 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C 91 #define ACPAXI2AXI_ATU_CTRL 0x1240C40 92 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x1240C44 93 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x1240C48 94 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x1240C4C 95 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x1240C50 96 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x1240C54 97 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x1240C58 98 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x1240C5C 99 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x1240C60 100 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x1240C64 101 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x1240C68 102 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x1240C6C 103 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x1240C70 104 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x1240C74 105 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x1240C78 106 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x1240C7C 107 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x1240C80 108 109 /* Registers from ACP_CLKRST block */ 110 #define ACP_SOFT_RESET 0x1241000 111 #define ACP_CONTROL 0x1241004 112 #define ACP_STATUS 0x1241008 113 #define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010 114 #define ACP_ZSC_DSP_CTRL 0x1241014 115 #define ACP_ZSC_STS 0x1241018 116 #define ACP_PGFSM_CONTROL 0x1241024 117 #define ACP_PGFSM_STATUS 0x1241028 118 #define ACP_CLKMUX_SEL 0x124102C 119 120 /* Registers from ACP_AON block */ 121 #define ACP_PME_EN 0x1241400 122 #define ACP_DEVICE_STATE 0x1241404 123 #define AZ_DEVICE_STATE 0x1241408 124 #define ACP_PIN_CONFIG 0x1241440 125 #define ACP_PAD_PULLUP_CTRL 0x1241444 126 #define ACP_PAD_PULLDOWN_CTRL 0x1241448 127 #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x124144C 128 #define ACP_PAD_SCHMEN_CTRL 0x1241450 129 #define ACP_SW_PAD_KEEPER_EN 0x1241454 130 #define ACP_SW_WAKE_EN 0x1241458 131 #define ACP_I2S_WAKE_EN 0x124145C 132 #define ACP_SW1_WAKE_EN 0x1241460 133 134 /* Registers from ACP_P1_MISC block */ 135 #define ACP_EXTERNAL_INTR_ENB 0x1241A00 136 #define ACP_EXTERNAL_INTR_CNTL 0x1241A04 137 #define ACP_EXTERNAL_INTR_CNTL1 0x1241A08 138 #define ACP_EXTERNAL_INTR_STAT 0x1241A0C 139 #define ACP_EXTERNAL_INTR_STAT1 0x1241A10 140 #define ACP_ERROR_STATUS 0x1241A4C 141 #define ACP_P1_SW_I2S_ERROR_REASON 0x1241A50 142 #define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x1241A6C 143 #define ACP_P1_SW_I2S_TX_DMA_POS 0x1241A70 144 #define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x1241A74 145 #define ACP_P1_SW_I2S_RX_DMA_POS 0x1241A78 146 #define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x1241A7C 147 #define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x1241A80 148 #define ACP_SCRATCH_REG_BASE_ADDR 0x1241A84 149 #define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x1241A88 150 #define ACP_P1_SW_BT_TX_DMA_POS 0x1241A8C 151 #define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x1241A90 152 #define ACP_P1_SW_HS_TX_DMA_POS 0x1241A94 153 #define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x1241A98 154 #define ACP_P1_SW_BT_RX_DMA_POS 0x1241A9C 155 #define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x1241AA0 156 #define ACP_P1_SW_HS_RX_DMA_POS 0x1241AA4 157 158 /* Registers from ACP_AUDIO_BUFFERS block */ 159 #define ACP_I2S_RX_RINGBUFADDR 0x1242000 160 #define ACP_I2S_RX_RINGBUFSIZE 0x1242004 161 #define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008 162 #define ACP_I2S_RX_FIFOADDR 0x124200C 163 #define ACP_I2S_RX_FIFOSIZE 0x1242010 164 #define ACP_I2S_RX_DMA_SIZE 0x1242014 165 #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018 166 #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C 167 #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020 168 #define ACP_I2S_TX_RINGBUFADDR 0x1242024 169 #define ACP_I2S_TX_RINGBUFSIZE 0x1242028 170 #define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C 171 #define ACP_I2S_TX_FIFOADDR 0x1242030 172 #define ACP_I2S_TX_FIFOSIZE 0x1242034 173 #define ACP_I2S_TX_DMA_SIZE 0x1242038 174 #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C 175 #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040 176 #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044 177 #define ACP_BT_RX_RINGBUFADDR 0x1242048 178 #define ACP_BT_RX_RINGBUFSIZE 0x124204C 179 #define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050 180 #define ACP_BT_RX_FIFOADDR 0x1242054 181 #define ACP_BT_RX_FIFOSIZE 0x1242058 182 #define ACP_BT_RX_DMA_SIZE 0x124205C 183 #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060 184 #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064 185 #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068 186 #define ACP_BT_TX_RINGBUFADDR 0x124206C 187 #define ACP_BT_TX_RINGBUFSIZE 0x1242070 188 #define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074 189 #define ACP_BT_TX_FIFOADDR 0x1242078 190 #define ACP_BT_TX_FIFOSIZE 0x124207C 191 #define ACP_BT_TX_DMA_SIZE 0x1242080 192 #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084 193 #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088 194 #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C 195 #define ACP_HS_RX_RINGBUFADDR 0x1242090 196 #define ACP_HS_RX_RINGBUFSIZE 0x1242094 197 #define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098 198 #define ACP_HS_RX_FIFOADDR 0x124209C 199 #define ACP_HS_RX_FIFOSIZE 0x12420A0 200 #define ACP_HS_RX_DMA_SIZE 0x12420A4 201 #define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8 202 #define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC 203 #define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0 204 #define ACP_HS_TX_RINGBUFADDR 0x12420B4 205 #define ACP_HS_TX_RINGBUFSIZE 0x12420B8 206 #define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC 207 #define ACP_HS_TX_FIFOADDR 0x12420C0 208 #define ACP_HS_TX_FIFOSIZE 0x12420C4 209 #define ACP_HS_TX_DMA_SIZE 0x12420C8 210 #define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC 211 #define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0 212 #define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4 213 214 /* Registers from ACP_I2S_TDM block */ 215 #define ACP_I2STDM_IER 0x1242400 216 #define ACP_I2STDM_IRER 0x1242404 217 #define ACP_I2STDM_RXFRMT 0x1242408 218 #define ACP_I2STDM_ITER 0x124240C 219 #define ACP_I2STDM_TXFRMT 0x1242410 220 #define ACP_I2STDM0_MSTRCLKGEN 0x1242414 221 #define ACP_I2STDM1_MSTRCLKGEN 0x1242418 222 #define ACP_I2STDM2_MSTRCLKGEN 0x124241C 223 #define ACP_I2STDM_REFCLKGEN 0x1242420 224 225 /* Registers from ACP_BT_TDM block */ 226 #define ACP_BTTDM_IER 0x1242800 227 #define ACP_BTTDM_IRER 0x1242804 228 #define ACP_BTTDM_RXFRMT 0x1242808 229 #define ACP_BTTDM_ITER 0x124280C 230 #define ACP_BTTDM_TXFRMT 0x1242810 231 #define ACP_HSTDM_IER 0x1242814 232 #define ACP_HSTDM_IRER 0x1242818 233 #define ACP_HSTDM_RXFRMT 0x124281C 234 #define ACP_HSTDM_ITER 0x1242820 235 #define ACP_HSTDM_TXFRMT 0x1242824 236 237 /* Registers from ACP_WOV block */ 238 #define ACP_WOV_PDM_ENABLE 0x1242C04 239 #define ACP_WOV_PDM_DMA_ENABLE 0x1242C08 240 #define ACP_WOV_RX_RINGBUFADDR 0x1242C0C 241 #define ACP_WOV_RX_RINGBUFSIZE 0x1242C10 242 #define ACP_WOV_RX_LINKPOSITIONCNTR 0x1242C14 243 #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x1242C18 244 #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x1242C1C 245 #define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x1242C20 246 #define ACP_WOV_PDM_FIFO_FLUSH 0x1242C24 247 #define ACP_WOV_PDM_NO_OF_CHANNELS 0x1242C28 248 #define ACP_WOV_PDM_DECIMATION_FACTOR 0x1242C2C 249 #define ACP_WOV_PDM_VAD_CTRL 0x1242C30 250 #define ACP_WOV_WAKE 0x1242C54 251 #define ACP_WOV_BUFFER_STATUS 0x1242C58 252 #define ACP_WOV_MISC_CTRL 0x1242C5C 253 #define ACP_WOV_CLK_CTRL 0x1242C60 254 #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x1242C64 255 #define ACP_WOV_ERROR_STATUS_REGISTER 0x1242C68 256 #define ACP_PDM_CLKDIV 0x1242C6C 257 258 /* Registers from ACP_P1_AUDIO_BUFFERS block */ 259 #define ACP_P1_I2S_RX_RINGBUFADDR 0x1243A00 260 #define ACP_P1_I2S_RX_RINGBUFSIZE 0x1243A04 261 #define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x1243A08 262 #define ACP_P1_I2S_RX_FIFOADDR 0x1243A0C 263 #define ACP_P1_I2S_RX_FIFOSIZE 0x1243A10 264 #define ACP_P1_I2S_RX_DMA_SIZE 0x1243A14 265 #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1243A18 266 #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x1243A1C 267 #define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x1243A20 268 #define ACP_P1_I2S_TX_RINGBUFADDR 0x1243A24 269 #define ACP_P1_I2S_TX_RINGBUFSIZE 0x1243A28 270 #define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x1243A2C 271 #define ACP_P1_I2S_TX_FIFOADDR 0x1243A30 272 #define ACP_P1_I2S_TX_FIFOSIZE 0x1243A34 273 #define ACP_P1_I2S_TX_DMA_SIZE 0x1243A38 274 #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C 275 #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1243A40 276 #define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x1243A44 277 #define ACP_P1_BT_RX_RINGBUFADDR 0x1243A48 278 #define ACP_P1_BT_RX_RINGBUFSIZE 0x1243A4C 279 #define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x1243A50 280 #define ACP_P1_BT_RX_FIFOADDR 0x1243A54 281 #define ACP_P1_BT_RX_FIFOSIZE 0x1243A58 282 #define ACP_P1_BT_RX_DMA_SIZE 0x1243A5C 283 #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1243A60 284 #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x1243A64 285 #define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x1243A68 286 #define ACP_P1_BT_TX_RINGBUFADDR 0x1243A6C 287 #define ACP_P1_BT_TX_RINGBUFSIZE 0x1243A70 288 #define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x1243A74 289 #define ACP_P1_BT_TX_FIFOADDR 0x1243A78 290 #define ACP_P1_BT_TX_FIFOSIZE 0x1243A7C 291 #define ACP_P1_BT_TX_DMA_SIZE 0x1243A80 292 #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1243A84 293 #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x1243A88 294 #define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x1243A8C 295 #define ACP_P1_HS_RX_RINGBUFADDR 0x1243A90 296 #define ACP_P1_HS_RX_RINGBUFSIZE 0x1243A94 297 #define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x1243A98 298 #define ACP_P1_HS_RX_FIFOADDR 0x1243A9C 299 #define ACP_P1_HS_RX_FIFOSIZE 0x1243AA0 300 #define ACP_P1_HS_RX_DMA_SIZE 0x1243AA4 301 #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x1243AA8 302 #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x1243AAC 303 #define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x1243AB0 304 #define ACP_P1_HS_TX_RINGBUFADDR 0x1243AB4 305 #define ACP_P1_HS_TX_RINGBUFSIZE 0x1243AB8 306 #define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x1243ABC 307 #define ACP_P1_HS_TX_FIFOADDR 0x1243AC0 308 #define ACP_P1_HS_TX_FIFOSIZE 0x1243AC4 309 #define ACP_P1_HS_TX_DMA_SIZE 0x1243AC8 310 #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x1243ACC 311 #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x1243AD0 312 #define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x1243AD4 313 314 /* Registers from ACP_SCRATCH block */ 315 #define ACP_SCRATCH_REG_0 0x1250000 316 #define ACP_SCRATCH_REG_1 0x1250004 317 #define ACP_SCRATCH_REG_2 0x1250008 318 #define ACP_SCRATCH_REG_3 0x125000C 319 #define ACP_SCRATCH_REG_4 0x1250010 320 #define ACP_SCRATCH_REG_5 0x1250014 321 #define ACP_SCRATCH_REG_6 0x1250018 322 #define ACP_SCRATCH_REG_7 0x125001C 323 #define ACP_SCRATCH_REG_8 0x1250020 324 #define ACP_SCRATCH_REG_9 0x1250024 325 #define ACP_SCRATCH_REG_10 0x1250028 326 #define ACP_SCRATCH_REG_11 0x125002C 327 #define ACP_SCRATCH_REG_12 0x1250030 328 #define ACP_SCRATCH_REG_13 0x1250034 329 #define ACP_SCRATCH_REG_14 0x1250038 330 #define ACP_SCRATCH_REG_15 0x125003C 331 #define ACP_SCRATCH_REG_16 0x1250040 332 #define ACP_SCRATCH_REG_17 0x1250044 333 #define ACP_SCRATCH_REG_18 0x1250048 334 #define ACP_SCRATCH_REG_19 0x125004C 335 #define ACP_SCRATCH_REG_20 0x1250050 336 #define ACP_SCRATCH_REG_21 0x1250054 337 #define ACP_SCRATCH_REG_22 0x1250058 338 #define ACP_SCRATCH_REG_23 0x125005C 339 #define ACP_SCRATCH_REG_24 0x1250060 340 #define ACP_SCRATCH_REG_25 0x1250064 341 #define ACP_SCRATCH_REG_26 0x1250068 342 #define ACP_SCRATCH_REG_27 0x125006C 343 #define ACP_SCRATCH_REG_28 0x1250070 344 #define ACP_SCRATCH_REG_29 0x1250074 345 #define ACP_SCRATCH_REG_30 0x1250078 346 #define ACP_SCRATCH_REG_31 0x125007C 347 #define ACP_SCRATCH_REG_32 0x1250080 348 #define ACP_SCRATCH_REG_33 0x1250084 349 #define ACP_SCRATCH_REG_34 0x1250088 350 #define ACP_SCRATCH_REG_35 0x125008C 351 #define ACP_SCRATCH_REG_36 0x1250090 352 #define ACP_SCRATCH_REG_37 0x1250094 353 #define ACP_SCRATCH_REG_38 0x1250098 354 #define ACP_SCRATCH_REG_39 0x125009C 355 #define ACP_SCRATCH_REG_40 0x12500A0 356 #define ACP_SCRATCH_REG_41 0x12500A4 357 #define ACP_SCRATCH_REG_42 0x12500A8 358 #define ACP_SCRATCH_REG_43 0x12500AC 359 #define ACP_SCRATCH_REG_44 0x12500B0 360 #define ACP_SCRATCH_REG_45 0x12500B4 361 #define ACP_SCRATCH_REG_46 0x12500B8 362 #define ACP_SCRATCH_REG_47 0x12500BC 363 #define ACP_SCRATCH_REG_48 0x12500C0 364 #define ACP_SCRATCH_REG_49 0x12500C4 365 #define ACP_SCRATCH_REG_50 0x12500C8 366 #define ACP_SCRATCH_REG_51 0x12500CC 367 #define ACP_SCRATCH_REG_52 0x12500D0 368 #define ACP_SCRATCH_REG_53 0x12500D4 369 #define ACP_SCRATCH_REG_54 0x12500D8 370 #define ACP_SCRATCH_REG_55 0x12500DC 371 #define ACP_SCRATCH_REG_56 0x12500E0 372 #define ACP_SCRATCH_REG_57 0x12500E4 373 #define ACP_SCRATCH_REG_58 0x12500E8 374 #define ACP_SCRATCH_REG_59 0x12500EC 375 #define ACP_SCRATCH_REG_60 0x12500F0 376 #define ACP_SCRATCH_REG_61 0x12500F4 377 #define ACP_SCRATCH_REG_62 0x12500F8 378 #define ACP_SCRATCH_REG_63 0x12500FC 379 #define ACP_SCRATCH_REG_64 0x1250100 380 #define ACP_SCRATCH_REG_65 0x1250104 381 #define ACP_SCRATCH_REG_66 0x1250108 382 #define ACP_SCRATCH_REG_67 0x125010C 383 #define ACP_SCRATCH_REG_68 0x1250110 384 #define ACP_SCRATCH_REG_69 0x1250114 385 #define ACP_SCRATCH_REG_70 0x1250118 386 #define ACP_SCRATCH_REG_71 0x125011C 387 #define ACP_SCRATCH_REG_72 0x1250120 388 #define ACP_SCRATCH_REG_73 0x1250124 389 #define ACP_SCRATCH_REG_74 0x1250128 390 #define ACP_SCRATCH_REG_75 0x125012C 391 #define ACP_SCRATCH_REG_76 0x1250130 392 #define ACP_SCRATCH_REG_77 0x1250134 393 #define ACP_SCRATCH_REG_78 0x1250138 394 #define ACP_SCRATCH_REG_79 0x125013C 395 #define ACP_SCRATCH_REG_80 0x1250140 396 #define ACP_SCRATCH_REG_81 0x1250144 397 #define ACP_SCRATCH_REG_82 0x1250148 398 #define ACP_SCRATCH_REG_83 0x125014C 399 #define ACP_SCRATCH_REG_84 0x1250150 400 #define ACP_SCRATCH_REG_85 0x1250154 401 #define ACP_SCRATCH_REG_86 0x1250158 402 #define ACP_SCRATCH_REG_87 0x125015C 403 #define ACP_SCRATCH_REG_88 0x1250160 404 #define ACP_SCRATCH_REG_89 0x1250164 405 #define ACP_SCRATCH_REG_90 0x1250168 406 #define ACP_SCRATCH_REG_91 0x125016C 407 #define ACP_SCRATCH_REG_92 0x1250170 408 #define ACP_SCRATCH_REG_93 0x1250174 409 #define ACP_SCRATCH_REG_94 0x1250178 410 #define ACP_SCRATCH_REG_95 0x125017C 411 #define ACP_SCRATCH_REG_96 0x1250180 412 #define ACP_SCRATCH_REG_97 0x1250184 413 #define ACP_SCRATCH_REG_98 0x1250188 414 #define ACP_SCRATCH_REG_99 0x125018C 415 #define ACP_SCRATCH_REG_100 0x1250190 416 #define ACP_SCRATCH_REG_101 0x1250194 417 #define ACP_SCRATCH_REG_102 0x1250198 418 #define ACP_SCRATCH_REG_103 0x125019C 419 #define ACP_SCRATCH_REG_104 0x12501A0 420 #define ACP_SCRATCH_REG_105 0x12501A4 421 #define ACP_SCRATCH_REG_106 0x12501A8 422 #define ACP_SCRATCH_REG_107 0x12501AC 423 #define ACP_SCRATCH_REG_108 0x12501B0 424 #define ACP_SCRATCH_REG_109 0x12501B4 425 #define ACP_SCRATCH_REG_110 0x12501B8 426 #define ACP_SCRATCH_REG_111 0x12501BC 427 #define ACP_SCRATCH_REG_112 0x12501C0 428 #define ACP_SCRATCH_REG_113 0x12501C4 429 #define ACP_SCRATCH_REG_114 0x12501C8 430 #define ACP_SCRATCH_REG_115 0x12501CC 431 #define ACP_SCRATCH_REG_116 0x12501D0 432 #define ACP_SCRATCH_REG_117 0x12501D4 433 #define ACP_SCRATCH_REG_118 0x12501D8 434 #define ACP_SCRATCH_REG_119 0x12501DC 435 #define ACP_SCRATCH_REG_120 0x12501E0 436 #define ACP_SCRATCH_REG_121 0x12501E4 437 #define ACP_SCRATCH_REG_122 0x12501E8 438 #define ACP_SCRATCH_REG_123 0x12501EC 439 #define ACP_SCRATCH_REG_124 0x12501F0 440 #define ACP_SCRATCH_REG_125 0x12501F4 441 #define ACP_SCRATCH_REG_126 0x12501F8 442 #define ACP_SCRATCH_REG_127 0x12501FC 443 #define ACP_SCRATCH_REG_128 0x1250200 444 #endif 445